經濟部中央標窣局員工消費合作杜印裝 ^1282 A7 B7 五、發明説明（/ ) ㈠技術領域 本發明是有關於在半導體基底【substrate】上的積體 電路，特別是與靜態隨機存取記憶體【SRAM】中的薄膜電晶 體【TFT】製作歐姆接觸【ohmic contact】有關。 (二)發明背景 隨機存取記憶體(RAM)在電子工業中廣泛地被使用在數 位系統中的資料貯存’如電腦之類。隨機存取記憶體的主要 型態有動態隨機存取記憶體（dram)及靜態隨機存取記憶體 (SRAM) 〇—個DRAM的記憶元（cell)中結合一個電晶體 和一個電容器，將訊號以電荷方式貯存於電容器中。一般而 言，DRAM的速度較SRAM慢，且需定期補充電荷以維持電 容器中的電荷，但一般認爲製造單位DRAM訊號儲存位元比 SRAM者便宜。另一方面，在SRAM記憶元中通常結合六個 電晶體，其功能如同靜態門閂式電路（static latch circuit)或搖擺式電路（flip circuit)，不需要補充， 其速度也比DRAM快很多。由於速度關係，SRAM很理想做 爲緩衝記憶體，以提高系統的動作表現。 典型的【六-電晶體電路】如圖一所示，圖一只顯示多記 憶元中的一個行列（array) 〇近年的趨勢是用一個P-通道 薄膜電晶體作爲Pi和P2電晶體來製造CMOS SRAM，以 縮小記憶體的尺寸和降低晶方（chip)的製造成本。如 T.Okazawa，U.S. Pat. No. 4.980.732 揭露一個具有較低 截止電流（off current)的TFT製作方法。此篇專利中， 通道的場效電晶體汲極是由閘極補償（off set)而減少電 流，簡單地說，SRAM記憶元的功能如下：（參考圖一）加 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0><297公釐） ct^— 警 i (請先閲讀背面之注意事項再填寫本頁) 訂_ )線· 經濟部中央標隼局員工消費合作社印製 3^1282 ^ Α7 ____ ____ Β7 五、發明説明（二·） 一閘電壓於字元線（word line)上而開啓傳導電晶體 (pass transistor) WNi和WN2的開關，此電壓是加在， 介於兩對電晶體Pi，m及P2，N2之間的節點Qi和Q2 上，而從位元線（bit line) BU和BL2的讀取環（read cycle)當中決定SRAM門閂的狀態；在寫入環（write cycle)中，位元線間的電壓引入可開啓門閂的電位，也因 此改變代表0和1的二進位貯存資料。 然而，在SRAM記憶元的製造當中，每對CMOS P-通道 和N-通道場效電晶體之間的節點仏和Q2必須與閘極G2 和山有良好的電性接觸，如圖一所示。很不性地，以習知 技藝在半導體基底（semiconductor substrate)上建構P— 通道TFT時，會發生一些製程問題，使得SRAM的動作表 現和穩定性受到限制。 這些問題可藉傳統習知技藝製造P-型TFT而揭露並瞭 解，如圖二至圖五所示，爲簡化討論，圖中只顯示在基底上 建構SRAM記憶元的結構，其他的電路元（circuit elements)，如WNi，WN2場效電晶體（FET)、由第一複 晶矽層所形成的字元線及由第二複晶矽層所形成的位元線等 在圖二至圖五中並未顯示。 當基底【10】上已完成字元線和位元線之後，在字元線 和位元線行列之中則形成具有P-通道TFTs的SRAM記憶 元門閃電路。參考圖二，TFT閘極Gi和G2的圖案是由N+ 摻雜的第三複晶矽層【14】形成，此時薄閘氧化層【16】沉 積於閘極之上，如圖二所示；繼續藉光阻圖案和鈾刻，在第 二閘極G2上形成一接觸窗（參考圖三），第四複晶矽層 (請先聞讀背面之注意事項再填寫本頁) -c^. 訂_ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） A7 B7 ^11282 五、發明説明（彡） 【18】再沉積並將之圖案化，在山閘極上方及接處觸到G2 閘極上形成TFT通道層【18】，如圖四所示，此時層次 【18】以P型雜質植入於光阻圖形中形成F通道的源極 (source)及汲極（drain)區，同時形成TFT汲極的電性 連線，即接到G2閘極的接點Qi (參考圖一）。圖五所示有 第二絕緣層【22】沉積於SRAM結構上，並且在層次【22】 製作第二接觸窗作爲第一層金屬封塞（Plug)之用，此金屬 封塞通常由阻隔金屬，如鎢（W)，來形成，後序沉積並圖 案化第一金屬層【26】，形成SRAM積體電路中內部連線 (interconnection)的第一層。雖圖中顯示金屬接觸位於 G2閘接觸旁之可見之處，但必須瞭解，金屬封塞是形成於 基底上需電性接觸的任何位置。 在習知結構及製程中有些考量點會降低SRAM的動作表 現及可靠度，如在蝕刻接觸窗【2】時，光阻是直接接觸閘 氧化層，會導入污染物，如鈉（sodium)於氧化層中而造成 元件特性的不穩定。另一嚴重問題是在接觸窗【2】中，摻 雜複晶矽層【14】及【18】之間以堆疊（stacked)接觸方 式形成P+/N+接面（junction)，雖摻雜濃度高，此接面 仍有二極體（diode)的特性，使得當SRAM記億元切換至 相反狀態時會降低導通電流（on current)，而理想上以低 電阻歐姆接觸爲佳。 因此，在半導體工業中對SRAM的薄膜電晶體製作及其 他積體電路的結構及製程的改善有強烈需求，以解決上述問 題，並能能符合成本效益。 (三)發明的簡要說明 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 訂The Ministry of Economic Affairs, Central Standardization Bureau, Employee Consumer Cooperation Du Printing ^ 1282 A7 B7 V. Description of the invention (/) (1) Technical Field The present invention relates to an integrated circuit on a semiconductor substrate [substrate], especially with static random access The thin film transistor [TFT] in the memory [SRAM] is related to the ohmic contact [ohmic contact]. (2) Background of the invention Random access memory (RAM) is widely used in the electronics industry for data storage in digital systems, such as computers. The main types of random access memory are dynamic random access memory (dram) and static random access memory (SRAM). A DRAM memory cell (cell) combines a transistor and a capacitor to connect the signal It is stored in the capacitor as a charge. Generally speaking, the speed of DRAM is slower than that of SRAM, and it is necessary to replenish the charge regularly to maintain the charge in the capacitor. However, it is generally considered that the manufacturing unit DRAM signal storage bit is cheaper than that of SRAM. On the other hand, six transistors are usually incorporated in SRAM memory cells. Their functions are like static latch circuits or flip circuits, and they do not need to be supplemented. They are also much faster than DRAM. Due to the speed relationship, SRAM is ideal as a buffer memory to improve the performance of the system. A typical [six-transistor circuit] is shown in Fig. 1, which shows an array of multiple memory cells. The trend in recent years is to use a P-channel thin film transistor as Pi and P2 transistors to manufacture CMOS SRAM to reduce the size of the memory and reduce the manufacturing cost of the chip. For example, T. Okazawa, U.S. Pat. No. 4.980.732 discloses a method for manufacturing a TFT with a lower off current. In this patent, the field-effect transistor drain of the channel is reduced by the gate compensation (off set) to reduce the current. Simply put, the function of the SRAM memory cell is as follows: (refer to Figure 1) plus the paper size is applicable to the Chinese national standard (CNS) A4 specification (2 丨 0 > < 297mm) ct ^ — 警 i (Please read the precautions on the back and then fill out this page) Order_) Line · Printed by the Employee Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs 3 ^ 1282 ^ Α7 ____ ____ Β7 5. Description of the invention (2 ·) A gate voltage is applied to the word line to turn on the switches of the conductive transistors WNi and WN2. This voltage is added to At the nodes Qi and Q2 between the two pairs of transistors Pi, m and P2, N2, the state of the SRAM latch is determined from the read cycle of the bit line BU and BL2; In the write cycle, the voltage between the bit lines introduces a potential that can open the latch, thus changing the binary storage data representing 0 and 1. However, in the manufacture of SRAM memory cells, the nodes between each pair of CMOS P-channel and N-channel field effect transistors and Q2 must have good electrical contact with the gate G2 and the mountain, as shown in Figure 1 . Very poorly, when using conventional techniques to construct P-channel TFTs on a semiconductor substrate, some process problems may occur, which limits the performance and stability of the SRAM. These problems can be revealed and understood through the manufacturing of P-type TFTs by traditional techniques. As shown in Figures 2 to 5, to simplify the discussion, the figure only shows the structure of the SRAM memory cell built on the substrate, and other circuit elements ( circuit elements), such as WNi, WN2 field effect transistors (FETs), word lines formed by the first polycrystalline silicon layer and bit lines formed by the second polycrystalline silicon layer, etc. are shown in Figures 2 to 5 Is not shown in. After the word lines and bit lines have been completed on the substrate [10], SRAM memory gate flash circuits with P-channel TFTs are formed in the word line and bit line rows and columns. Referring to FIG. 2, the pattern of the TFT gates Gi and G2 is formed by a N + doped third polycrystalline silicon layer [14], at which time a thin gate oxide layer [16] is deposited on the gate, as shown in FIG. 2 ; Continue to use the photoresist pattern and uranium engraving to form a contact window on the second gate G2 (refer to Figure 3), the fourth polycrystalline silicon layer (please read the precautions on the back before filling this page) -c ^ . Order _ This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) A7 B7 ^ 11282 V. Description of invention (彡) [18] Redeposit and pattern it, above and at the junction of the mountain gate Touch the G2 gate to form the TFT channel layer [18], as shown in Figure 4, at this time the layer [18] is implanted with P-type impurities in the photoresist pattern to form the source and drain of the F channel ) Area, at the same time form the electrical connection of the TFT drain, which is connected to the contact Qi of the G2 gate (refer to Figure 1). As shown in Figure 5, a second insulating layer [22] is deposited on the SRAM structure, and a second contact window is formed at the level [22] as the first layer of metal plug (Plug). This metal plug is usually made of a barrier metal , Such as tungsten (W), is formed, and then the first metal layer is deposited and patterned [26], forming the first layer of interconnection in the SRAM integrated circuit. Although the figure shows that the metal contact is visible next to the G2 gate contact, it must be understood that the metal plug is formed anywhere on the substrate that requires electrical contact. Some considerations in the conventional structure and process will reduce the performance and reliability of the SRAM. For example, when etching the contact window [2], the photoresist directly contacts the gate oxide layer and will introduce contaminants such as sodium. In the oxide layer, the device characteristics are unstable. Another serious problem is that in the contact window [2], a P + / N + junction is formed in a stacked contact between the doped polycrystalline silicon layers [14] and [18], although the doping concentration is high This junction still has the characteristics of a diode, so that when the SRAM is switched to the opposite state, the on current will be reduced. Ideally, a low resistance ohmic contact is preferred. Therefore, there is a strong demand in the semiconductor industry for the improvement of the structure and manufacturing process of SRAM thin film transistors and other integrated circuits in order to solve the above problems and be cost-effective. (3) Brief description of the invention This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) (please read the precautions on the back before filling this page)
•-Q 經濟部中央標準局員工消費合作社印裝 經濟部中央標準局員工消費合作社印製 A7 _____B7 五、發明説明（々：） 本發明主要目的在提出一個在具有薄膜電晶體的SRAM 元件中可同時形成低電阻歐姆P+/N+堆疊式接觸及金屬接 觸的製程’可藉提高導通電流及比而改善SRAM 的動作表現。 本發明另一目的在提出一較少光罩組來改善低電阻歐姆 P+/M+堆疊式接觸窗及金屬接觸窗的製程，即提供一個具成 本效益的生產製造程序。 與本發明目的一致的是上述一個在SRAU記憶元中嶄新 封塞結構的製作方法。此方法藉合倂製程步驟，同時形成堆 疊式接觸及金屬接觸；製程步驟起始於P-型（硼，B)摻雜 單晶半導體基底的提供，基底表面並有元件區及電性絕緣場 氧化（FOX)區，在元件區有由第一複晶矽層形成閘極及內 部連接的字元線（word line)，形成具源極與汲極區的N-通道場效電晶體（即傳導電晶體）；接著第二層r摻雜複 晶矽層圖案在每個傳導電晶體（pass transistor)上接觸 源/汲極區之一，此時在SRAM每個記憶元的第一絕緣層上 已形成二個P-通道薄膜電晶體。此電晶體的形成是藉沉積 第二複晶矽層，以N-型雜質，如砷（As)或磷（P)，摻雜使 成爲N+，再圖案化形成二個P-通道薄膜電晶體的鬧極；其 次，第二絕緣層沉積於閘極上作爲閘氧化層，再沉積淡 摻雜非晶矽層於閘氧化層之上，並以P—型雜質，如硼（B) 植入，在電極邊形成TFT源/汲極區。在形成二個TFT區 域的上方，此非晶砂層被光阻保護避免P-型植入，而閘極 上方的非晶矽層則是P+植入摻雜；藉光罩圖案及蝕刻’在 每個具P+源/汲的閘極部份形成N-淡摻雜FET矽通道。 (請先閱讀背面之注意事項再填寫本頁) -G 裝. 訂 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） A7 ^1282 B7 五、發明説明（f) ---------0装—— *- (請先閱讀背面之注意事項再填寫本頁) 每個TFT的P+傳導矽層甚至延伸至其他TFT閘極部份， 也提供一個堆疊式接觸的形成方法，連接一個TFT的汲極· 到另一個TFT的閘極。堆疊式接觸窗及金屬接觸窗是將1T 摻雜非晶矽層圖案化及蝕刻同時形成。繼續沉積第三絕緣層 並以非等向性蝕刻開接觸窗於非晶矽層上之P+摻雜部份； 另外，在非晶矽層之開闊區（被触刻區）的第二絕緣層（閘 氧化層）則被飩刻到N+摻雜的第三複晶矽層的表面。以上 的光罩和蝕刻同時用以形成連接到元件區的金屬接觸窗，作 爲內部的電性連接。因此，只用一層光罩，即可減少習知技 藝的光罩層數。開接觸窗之後沉積一耐熱金屬（refractory metal)，如鎢（W)，再回蝕刻（etch back)至第三絕緣 層表面形成金屬封塞（plug)，當沉積一金屬，如鋁 (A1)，並圖案化之後，此時的SRAM已完成內部連線的第 一金屬佈線層，而在堆疊式接觸窗中的金屬封塞連接PVN+ 接面形成低阻値歐姆接觸。 (四)圖示的簡要說明 將以下圖例說明與圖結合硏讀時，本發明的目的與其他 優點將可更加淸楚且具體。 經濟部中央樣準局員工消費合作社印製 圖一是一習知技藝六-電晶體SRAM記憶元的電性圖。 圖二至圖五是一習知技藝SRAM記憶元部份的剖面圖’其中 包含一個反向【reverse】P—通道薄膜電晶體【TFT】及 一有P+/N+接面的傳統P+/N+堆疊式接觸窗。 圖六至圖九是一 SRAM記憶元部份的剖面圖’其中包含本發 明同時形成阻値歐姆堆疊式接觸窗及金屬接觸窗 的P-通道薄膜電晶體。 本紙張尺度逋用中國國家標準（CNS ) Μ規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（/ ) (五)發明的詳細說明 本發明是有關於在具p-通道薄膜電晶體的SRAM上改進 堆疊式接觸窗的形成並且結合二層光罩步驟同時形成金屬接 觸窗；然而，應淸楚瞭解此方法中的技藝也可應用於在不同 傳導摻雜型態的摻雜矽層中需求低阻値歐姆堆疊式接觸之 P-通道薄膜電晶體的其他積體電路上。 爲更瞭解本發明嶄新封塞結構的製作，以下簡要說明 SRAM記憶元的製作。圖六至九的剖面圖中並未顯示完整 SRAM記憶元’但圖一的電性圖則描述了元件基元（device elements) ° SRAM 是在半導體基底（semiconductor substrate)上形成，如在P-摻雜單晶矽基底。元件區的 开：^成是作爲N-通道傳導電晶體（pass transistor)的行列 (array)。圖一中描述了靜態隨機存取記憶體記憶元 (SRAM cell)的二個電晶體WN!和WN2。基本上，元件區 間的電性絕緣是在元件區週圍以選擇性氧化法形成，如使用 矽的傳統區域性氧化製程（LOCOS);傳導電晶體是藉在元 件區長一閘氧化層並使用已圖案化的第一複晶矽層作爲場效 電晶體閘極（gate electrode)和字元線（word line)而 成。鄰近閘極的源/汲極區經離子植入，且閘極與形成位元 線的第二複晶矽層之間有電性絕緣層，（二個位元線BU 和BL2描述於圖一）此位元線是接於傳導電晶體的二個源 /汲極區之一，電晶體的另一個源/汲極區則接於SRAM門 閂電路的節點Qi和Q2，此門閂電路是由CMOS FET元件 組成，包含二個P-通道薄膜電晶體Pi、P2 ;二個具閘極 Gi、G2的通道傳導電晶體Νι、N2，如圖一所描述。此 本紙張又度適用中國國家榡準（CNS ) A4规格（210X297公釐） ---------〇裝— > 祕 (請先《讀背面之注意事項再填寫本頁) •ax 經濟部中央樣準局員工消費合作社印製 S11282 A7 ^_ B7 五、發明说明（y) &、N2電晶體的閘極也可視爲驅動電晶體的閘極，是由第一 複晶矽層形成作爲傳導電晶體的閘極。第二複晶矽層則怍爲 驅動電晶體仏、N2的源極接地平面，提供Vss接地’如 圖一所示。 圖六至圖九的實施例詳細描述本發明中P_通道薄膜電晶 體的形成，嶄新封塞結構及SRAM門閂電路部份金屬接觸的 製作方法。 首先參考圖六’剖面圖顯示在SRAM記憶元區的P- W 基底【10】、一個尸通道薄膜電晶體Pi及第二個薄膜電 晶體閘極G2部份，在基底【1〇】右邊也顯示元件區中將製 作接觸到基底的金屬接觸。爲簡化圖示，在基底部份的元件 並未顯示。在基底【10】上藉前述區域性氧化製程 (LOCOS)製程方法形成第一絕緣層作爲薄膜電晶體的電性 絕緣，從圖六開始將描述具嶄新封塞製程的P_通道薄膜電 晶體製作方法。 仍參考圖六，在基底【10】上沉積第三複晶矽層 【14】，以傳統微影技術及電漿蝕刻法圖案化形成二個薄膜 電晶體的閘極G!和G2 ;由第三複晶矽層形成的閘極與由第 一複晶矽層形成的閘極以堆疊方式接觸，複晶矽層【14】則 以低壓化學氣相沉積（LPCVD)爲佳，如使用含矽甲烷 (silane，SiH4)爲反應氣體，且期望厚度在300〜 1500A，繼以離子植入法（i〇n implantation)摻雜N_型 雜質’如砷（As75)或憐（P31)。當然，複晶矽層【14】在 CVD沉積時也可同時加入雜質，如磷化氫（PH3)，摻雜濃 度期望在 1.0E18〜1.0E20atom/cm3。 (請先聞讀背面之注意事項再填寫本頁) ---------------ο —^ϋ HI ml 訂----- 本紙張尺度適用中國國家梂準（CNS )人4规格（21〇χ29?公嫠） 經濟部中央榇準局員Η消費合作杜印装 A7 ____B7 五、發明説明（57) 此時，複晶矽層【14】以傳統微影技術及非等向性電獎 蝕刻法定義出二個薄膜電晶體的閘極Q和02，如圖六所 示；良好的非等向性電漿蝕刻可選擇活性離子蝕刻機 (reactive ion etcher, RIE)，其使用含氯（Ci)及攜帶 用氣體，如氬氣（Ar)的混合氣體。 圖六也顯示第二絕緣層【16】沉積於由複晶矽層【14】 形成的閘極Gi和G2之上，層次【16】是作爲薄膜電晶體 的閘氧化層，沉積可使用高溫(〜800°C) LPCVD系統並使用 二氯矽甲烷（SiH2Cl2)及一氧化二氮（N20)的混合氣體； 此氧化層相當薄，期望厚度在50〜500A。 圖六也顯示一相當薄的非晶矽層【18】沉積於閘氧化層 【16】之上，作爲薄膜電晶體的通道層；此非晶矽層的沉積 可使用低溫CVD來達成，而一般使用含矽甲烷（SiH4)或 多氫矽化物，如矽乙烷（Si2H6)混合物的LPCVD，使用溫 度在450〜560°C ;期望厚度在50〜800A。基本上，此非 晶矽層【18】是以型雜質摻雜，如砷（As)或磷（P) 使成淡摻雜（light doped)，可防止當P-通道薄膜電晶體 處於非導通狀態（off)時造成反轉（inversion)，同時也 提供TFT FET通道與源/汲區之間的P+/N+接面；N-摻雜 可以砷（As75)或磷（PW離子植入完成，摻雜濃度期望在 1.0Ε16〜1.0Ε18 at〇m/cm3〇 本發明有一優點是如圖三習知技藝，在TFT閘氧化層 的接觸窗尙未形成，完全除去閘氧化層曝露於光阻下的機 會，如眾周知光阻中的鈉（Na)會污染閘氧化層，當電路啓 動時會造成電性的不穩定。 ---------f -' (請先閲讀背面之注意事項再填寫本頁) 訂 本紙張尺度逋用中國國家揉準（CNS ) Α4规格（210X297公釐）• -Q Printed by the Ministry of Economy Central Standards Bureau Employee Consumer Cooperative Printed by the Ministry of Economic Affairs Central Standards Bureau Employee Consumer Cooperative A7 _____B7 V. Description of the invention (々 :) The main purpose of the present invention is to propose an SRAM device with thin film transistors The process of simultaneously forming low-resistance ohmic P + / N + stacked contacts and metal contacts can improve the performance of SRAM by increasing the on-current and ratio. Another object of the present invention is to propose a fewer mask set to improve the process of low resistance ohmic P + / M + stacked contact windows and metal contact windows, that is, to provide a cost-effective manufacturing process. Consistent with the object of the present invention is the above-mentioned method for making a brand-new sealing structure in the SRAU memory cell. This method combines the process steps to form stacked contacts and metal contacts at the same time; the process steps start with the provision of a P-type (boron, B) doped single crystal semiconductor substrate, which has device regions and electrically insulating fields on the surface Oxidation (FOX) region, in the device region, there is a gate formed by the first polycrystalline silicon layer and a word line connected internally to form an N-channel field effect transistor with source and drain regions (ie Conductive transistors); then the second layer of r-doped polycrystalline silicon layer pattern contacts one of the source / drain regions on each conductive transistor (pass transistor) at this time in the first insulating layer of each memory cell of the SRAM Two P-channel thin film transistors have been formed. This transistor is formed by depositing a second polycrystalline silicon layer, doped with N-type impurities, such as arsenic (As) or phosphorus (P), to become N +, and then patterned to form two P-channel thin film transistors Second, the second insulating layer is deposited on the gate as a gate oxide layer, and then a lightly doped amorphous silicon layer is deposited on the gate oxide layer, and implanted with P-type impurities, such as boron (B), A TFT source / drain region is formed on the electrode side. Above the formation of the two TFT regions, this amorphous sand layer is protected by photoresist to avoid P-type implantation, and the amorphous silicon layer above the gate is doped with P + implantation; A gate part with P + source / drain forms an N-lightly doped FET silicon channel. (Please read the precautions on the back before filling in this page) -G pack. The size of the bound paper is in accordance with Chinese National Standard (CNS) Α4 specification (210Χ297mm) A7 ^ 1282 B7 V. Invention description (f) ---- ----- 0 装 —— *-(Please read the precautions on the back before filling in this page) The P + conductive silicon layer of each TFT even extends to other TFT gate parts, and also provides a stacked contact formation Method, connect the drain of one TFT to the gate of another TFT. The stacked contact window and the metal contact window are simultaneously formed by patterning and etching the 1T doped amorphous silicon layer. Continue to deposit the third insulating layer and anisotropically etch the contact window on the P + doped part of the amorphous silicon layer; In addition, the second insulating layer in the open area (the area being touched) of the amorphous silicon layer (Gate oxide layer) is engraved on the surface of the N + doped third polysilicon layer. The above photomask and etching are simultaneously used to form a metal contact window connected to the element area as an internal electrical connection. Therefore, only one layer of mask can be used to reduce the number of mask layers of conventional technology. After opening the contact window, deposit a refractory metal, such as tungsten (W), and then etch back to the surface of the third insulating layer to form a metal plug. When depositing a metal, such as aluminum (A1) After the patterning, the SRAM at this time has completed the first metal wiring layer of the internal wiring, and the metal plug in the stacked contact window is connected to the PVN + junction to form a low resistance ohmic contact. (4) Brief description of the figures When the following legends and figures are read together, the purpose and other advantages of the present invention will be more clear and specific. Printed by the Employee Consumer Cooperative of the Central Prototype Bureau of the Ministry of Economic Affairs. Figure 1 is an electrical diagram of a conventional six-transistor SRAM memory cell. Figures 2 to 5 are cross-sectional views of a conventional SRAM memory cell, which includes a reverse [reverse] P-channel thin film transistor [TFT] and a traditional P + / N + stack with a P + / N + junction Contact window. Figures 6 to 9 are cross-sectional views of a portion of a SRAM memory cell, which includes P-channel thin film transistors of the present invention that simultaneously form resistive ohmic stacked contacts and metal contacts. This paper scale is printed in Chinese National Standard (CNS) M specifications (210X297mm) A7 B7 printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention (/) (5) Detailed description of the invention Improving the formation of stacked contact windows on SRAMs with p-channel thin film transistors and combining two-layer photomask steps to simultaneously form metal contact windows; however, it should be understood that the technique in this method can also be applied to different conductive doping Low-resistance ohmic stacked contact P-channel thin film transistors are required for other integrated circuits in the type of doped silicon layer. In order to better understand the production of the new sealing structure of the present invention, the following briefly describes the production of SRAM memory cells. The cross-sectional diagrams in Figures 6 to 9 do not show the complete SRAM memory cell ', but the electrical diagram in Figure 1 describes the device elements (device elements) ° SRAM is formed on a semiconductor substrate (semiconductor substrate), such as P- Doped single crystal silicon substrate. Opening of the element area: This is an array of N-channel pass transistors. Figure 1 depicts the two transistors WN! And WN2 of the SRAM cell. Basically, the electrical insulation in the device area is formed around the device area by selective oxidation, such as the traditional local oxidation process (LOCOS) using silicon; the conductive transistor is a long gate oxide layer in the device area and uses the The patterned first polycrystalline silicon layer is formed as a field effect gate electrode and a word line. The source / drain regions adjacent to the gate are ion implanted, and there is an electrical insulating layer between the gate and the second polysilicon layer forming the bit line, (the two bit lines BU and BL2 are described in FIG. 1 ) This bit line is connected to one of the two source / drain regions of the conductive transistor, and the other source / drain region of the transistor is connected to the nodes Qi and Q2 of the SRAM latch circuit. This latch circuit is made of CMOS The FET device is composed of two P-channel thin film transistors Pi and P2; two channel conduction transistors N1 and N2 with gates Gi and G2, as described in FIG. This paper is again applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) --------- 〇 装 — > Secret (please first read the precautions on the back side and then fill out this page) • ax Printed S11282 A7 ^ _ B7 by the Employees ’Consumer Cooperative of the Central Prototype Bureau of the Ministry of Economic Affairs V. Description of Invention (y) & The gate of the N2 transistor can also be regarded as the gate of the driving transistor, which is made of the first polycrystalline silicon The layer forms a gate that acts as a conductive transistor. The second polysilicon layer serves as the source ground plane for driving transistors N2 and N2, providing Vss grounding 'as shown in Figure 1. The embodiments of FIGS. 6 to 9 describe in detail the formation of the P_channel thin film transistor in the present invention, the brand-new sealing structure and the manufacturing method of the metal contacts of the SRAM latch circuit. First, refer to Figure 6 'cross-sectional view showing the P-W substrate [10] in the SRAM memory cell area, a cadaver channel thin film transistor Pi and the second thin film transistor gate G2, on the right of the substrate [1〇] In the display element area, metal contacts to the substrate will be made. To simplify the illustration, the components on the base are not shown. The first insulating layer is formed on the substrate [10] by the aforementioned local oxidation process (LOCOS) process method as the electrical insulation of the thin film transistor. The fabrication of P_channel thin film transistor with a new sealing process will be described starting from FIG. 6. method. Still referring to FIG. 6, a third polycrystalline silicon layer [14] is deposited on the substrate [10], and the gate electrodes G! And G2 of two thin film transistors are patterned by traditional lithography and plasma etching methods; The gate formed by the triple polycrystalline silicon layer is in contact with the gate formed by the first polycrystalline silicon layer in a stacked manner. The polycrystalline silicon layer [14] is preferably low pressure chemical vapor deposition (LPCVD), such as the use of silicon Methane (silane, SiH4) is a reactive gas, and the desired thickness is 300 ~ 1500A, followed by ion implantation (i〇n implantation) doped with N_-type impurities' such as arsenic (As75) or phosphorus (P31). Of course, the polycrystalline silicon layer [14] can also be added with impurities such as phosphine (PH3) during CVD deposition. The doping concentration is expected to be 1.0E18 ~ 1.0E20 atom / cm3. (Please read the precautions on the back before filling out this page) --------------- ο — ^ ϋ HI ml Order ----- This paper size is applicable to the Chinese National Standard ( CNS) People 4 specifications (21〇 × 29? Gonghu) Member of the Central Bureau of Economics of the Ministry of Economic Affairs HM Consumer Cooperation Du Printed A7 ____B7 V. Description of the invention (57) At this time, the polycrystalline silicon layer [14] is based on traditional lithography technology and The anisotropic electric award etching method defines the gate electrodes Q and 02 of two thin film transistors, as shown in Figure 6; good anisotropic plasma etching can choose reactive ion etcher (RIE) It uses a mixed gas containing chlorine (Ci) and a carrier gas, such as argon (Ar). Figure 6 also shows that the second insulating layer [16] is deposited on the gates Gi and G2 formed by the polycrystalline silicon layer [14]. The layer [16] is a gate oxide layer of thin film transistors, which can be deposited at high temperature ( ~ 800 ° C) The LPCVD system uses a mixed gas of dichlorosilane (SiH2Cl2) and nitrous oxide (N20); this oxide layer is quite thin, and the expected thickness is 50 ~ 500A. Figure 6 also shows that a relatively thin amorphous silicon layer [18] is deposited on the gate oxide layer [16] as a channel layer of the thin film transistor; the deposition of this amorphous silicon layer can be achieved using low temperature CVD, which is generally Use LPCVD containing a mixture of silicon methane (SiH4) or polyhydrogen silicide, such as silane (Si2H6), at a temperature of 450 ~ 560 ° C; the desired thickness is 50 ~ 800A. Basically, this amorphous silicon layer [18] is doped with type impurities, such as arsenic (As) or phosphorous (P), to make it lightly doped (light doped), which can prevent the P-channel thin film transistor from being non-conductive Inversion is caused when the state is off, and it also provides the P + / N + junction between the TFT FET channel and the source / drain region; N-doping can be done with arsenic (As75) or phosphorus (PW ion implantation, The doping concentration is expected to be 1.0E16 ~ 1.0E18 at〇m / cm3. One advantage of the present invention is that as shown in FIG. 3, the contact window of the TFT gate oxide layer is not formed, and the gate oxide layer is completely removed and exposed to the photoresist. Opportunity, for example, it is well known that sodium (Na) in the photoresist will contaminate the gate oxide layer, which will cause electrical instability when the circuit is started. --------- f-'(Please read the back side first Please pay attention to this page and then fill out this page) The size of the paper used is in accordance with China National Standard (CNS) Α4 specification (210X297mm)
Sii A7 B7 五、發明説明（1) 仍參考圖六，此時在非晶矽層18跨過閘極部份製作植 •入光阻圖案，在圖一標示爲18’，繼以P-型雜質，如硼11 【B11】進行離子植入；此離子植入不僅形成P+通道薄膜電 晶體的源/汲極摻雜區，也在基底上提供一傳導層；圖六中 植入光罩只顯市具聞極Gi的薄膜電晶體，剖面圖中閘極 G2並未顯示通道區，因此有P+的層次【18】延伸至閘極 G2之上。基本上’層次【18】於離子植入後摻雜濃度期望 在 1.0E18〜1.0E20 atom/cm3。 參考圖七，顯示製程的下一步驟，使用光阻光罩(未顯 示)及電獎蝕刻，將非晶矽層【18】圖案化定義出P+傳導 區，此圖案化的步驟也定義出TFT閘極上方的通道寬度。 圖七也同時顯示閘極Gi上方的通道層18’，P+傳導區的 圖案也延伸到另一 TFT閘極G2部份。本發明有一重點是 同時形成在閘極&上方從層次【18】到閘氧化【16】的接 觸窗，此蝕刻期望以有選擇性及非等向性等特性的活性離子 蝕刻機來完成’可使用含氯（Ci)或二氟二氯甲烷 (CF2C12)及一攜帶氣體，如氬氣（Ar)等混合氣體。 接著沉積第三絕緣層【22】於層次【18】圖案之上’如 圖七所示，此絕緣層期望用低流動性玻璃以提供表面平坦化 的層次效應（leveling effect) ’層次【22】可使用低壓 化學氣相沉積（LPCVD)反應器’藉分解TEOS同時加入氫 化磷（PH3)和二硼化六氫（賊6)以形成BPTEOS »此玻璃 繼續於800〜900°C下退火（annealing) 15〜60分鐘。 此層也作爲鈉（Na)污染隔離層。 參考圖九，嶄新的封塞結構可藉金屬層24均勻沉積充 本紙浓尺度適用中國國家揲準（CNS)Α4規格（2丨0X297公羞） (請先閲讀背面之注意事項再填寫本頁) η裝. 、1Τ 經濟部中央橾準局員工消費合作杜印製 ^11282 A7 B7 經濟部中央揉隼局員工消费合作社印製 五、發明説明（/p ) 塡於接觸窗【6】和【7】中，可在接觸窗【6】完成P+和 N+的電性連接，也同時在接觸窗七中形成與其他元件端之 間的電性連接，此金屬層再被回蝕刻（etch back)，形成 傳導封塞【24】間的電性絕緣，如圖九所示，此傳導封塞是 耐熱金屬，如鎢（W)的結合；其功能是作爲金屬在接觸窗 中穿透到基底的阻隔層（barrier layer)。鎢的沉積可有 多種方法，如CVD、物理蒸鍍、源鍍或其他類似方法，但以 CVD方法，將六氟化鎢（wf6 )分解來完成爲佳；圖九顯示 SRAM完成到第—金屬層（26)，其中金屬鋁層（26)可藉 沉積金屬鋁並以微影技術及電漿蝕刻將鋁層圖案化以形成第 一金屬層的內部連線。 爲簡化本發明的說明，圓六至圖九只顯示從具閛極 之TFT的汲極（圖中的節點Ql)到第二個TFT的閘極& 之間的電性連接。然而，在製程中也同時製作從第二個TFT 的汲極到第一個TFT的閘極G!之間的電性連接。二者電 性連接均使用金屬封塞，經由堆疊式接觸窗連接層次【18】 和【14】，形成P+和N+接面的結合，並且提供一低電阻 歐姆接觸，很明顯改善圖二至圖五中習知技藝的堆疊式接 觸。 當本發明由此能具體地描述時，藉本技藝的一些技術可 瞭解各種形式及細節的改變都是可達成的，而無需與本發明 的精神和架構刻意分離。例如，雖然具體說明是可改善 SRAM電路的堆疊式接觸，但也可被瞭解到在其他半導體積 體電路需要在P+和N+間的矽層有低阻値者甚至須要金屬 接觸到基底的其它元件時，這些改善的歐姆接觸都可製作應 (請先閲讀背面之注意事項再填寫本頁}Sii A7 B7 V. Description of the invention (1) Still referring to FIG. 6, at this time, an implanted photoresist pattern is made on the amorphous silicon layer 18 across the gate part, marked 18 ′ in FIG. 1, followed by the P-type Impurities such as boron 11 [B11] are used for ion implantation; this ion implantation not only forms the source / drain doped region of the P + channel thin film transistor, but also provides a conductive layer on the substrate; In the thin film transistor with the Gi electrode in Xianshi, the gate G2 in the cross-sectional view does not show the channel area, so there is a P + level [18] that extends above the gate G2. Basically, the level [18] after ion implantation is expected to have a doping concentration of 1.0E18 ~ 1.0E20 atom / cm3. Referring to Figure 7, the next step of the process is shown. Using a photoresist mask (not shown) and electric award etching, the amorphous silicon layer [18] is patterned to define the P + conductive region. This patterning step also defines the TFT The width of the channel above the gate. Fig. 7 also shows the channel layer 18 'above the gate Gi, and the pattern of the P + conductive region also extends to another TFT gate G2. An important point of the present invention is to simultaneously form a contact window from level [18] to gate oxidation [16] above the gate & this etching is expected to be completed by an active ion etching machine with selective and anisotropic characteristics. A mixed gas containing chlorine (Ci) or difluorodichloromethane (CF2C12) and a carrier gas such as argon (Ar) can be used. Then deposit a third insulating layer [22] on top of the layer [18] pattern. As shown in Figure 7, this insulating layer is expected to use low-fluidity glass to provide a leveling effect on the surface planarization. Level [22] A low-pressure chemical vapor deposition (LPCVD) reactor can be used to form BPTEOS by decomposing TEOS and adding phosphorus hydride (PH3) and hexahydrogen diboride (thief 6) at the same time. The glass continues to anneal at 800 ~ 900 ° C (annealing ) 15 ~ 60 minutes. This layer also acts as a sodium (Na) contamination barrier. With reference to Figure 9, the new sealing structure can be deposited uniformly by the metal layer 24. The thick scale of the paper is suitable for the Chinese National Standard (CNS) Α4 specifications (2 丨 0X297) (please read the precautions on the back and fill in this page) η 装., 1T Printed by the Consumer Cooperation of the Central Central Bureau of Economics of the Ministry of Economic Affairs ^ 11282 A7 B7 Printed by the Consumer Cooperative of the Central Falcon Bureau of the Ministry of Economic Affairs Fifth, the invention description (/ p) at the contact window [6] and [7 】 In the contact window [6], the electrical connection between P + and N + can be completed. At the same time, the electrical connection between the contact window 7 and other device ends is formed. This metal layer is then etched back. Forming the electrical insulation between the conductive seals [24], as shown in Figure 9, this conductive seal is a combination of heat-resistant metal, such as tungsten (W); its function is to act as a barrier for the metal to penetrate the substrate in the contact window Layer (barrier layer). There are various methods for the deposition of tungsten, such as CVD, physical evaporation, source plating or other similar methods, but it is better to decompose tungsten hexafluoride (wf6) by CVD method; Figure 9 shows the completion of SRAM to the first metal The layer (26), wherein the metal aluminum layer (26) can be deposited by metal aluminum and patterned by photolithography and plasma etching to form the interconnection of the first metal layer. In order to simplify the description of the present invention, circle 6 to figure 9 only show the electrical connection from the drain of the TFT with a gate electrode (node Q1 in the figure) to the gate & of the second TFT. However, the electrical connection from the drain of the second TFT to the gate G! Of the first TFT is also made during the process. Both electrical connections are made of metal plugs, which connect the layers [18] and [14] via stacked contact windows to form a combination of P + and N + junctions, and provide a low-resistance ohmic contact, which is obviously improved. The stacking contact of the learned skills of the fifth school. When the present invention can be described in detail in this way, it can be understood that various forms and details of changes can be achieved by some techniques of the present technology without intentionally separating from the spirit and architecture of the present invention. For example, although the specific description can improve the stacked contact of the SRAM circuit, it can also be understood that in other semiconductor integrated circuits, the silicon layer between P + and N + needs to have a low resistance value, and even requires metal to contact other elements of the substrate At this time, these improved ohmic contacts can be made (please read the notes on the back before filling this page)
—C 裝- 、11 本紙垠又度適用中國國家榡準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印裝 Μ Β7 五、發明説明（// ) 用。 (請先閱讀背面之注意事項再填寫本頁) -裝- 訂 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）—C 装 － 、 11 This paper is also applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). Printed and printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs Μ Β7. Invention description (//). (Please read the precautions on the back before filling out this page)-Binding-Order This paper size is applicable to China National Standard (CNS) A4 specification (210X297mm)