經濟部中央標準局員工消费合作社印製 3 切 478 Λ7 B7 五、發明説明（） 1 於 1988 年H.Kawahara 等人發表於 J.Electrochem·Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 3 cut 478 Λ7 B7 5. Description of the invention () 1 Published in 1988 by H. Kawahara et al. In J. Electrochem ·
Soc·第135卷第8期第2013-16頁，揭示一種可於50 °C 下低溫成長氧化珍(S i 02)的液相沈積（y>D, 1 iquid phase deposition)方法，該方法榮獲美國專利第5,〇73,408號 5 。此技術原本係應用於成長破璃基板之羡塍，以阻止破璃 内钠離子向外癀散，避免其破壤成長於上方之液晶平面顯 示器（LCD，liquid crystal display)。此液相沈穡（LPD) 方辱之饞點在於設儀簡單、製作價格便宜、低溫下進行製 備以及成長良好品質良好之氧化矽薄後，具有選擇性沈積 10 之能力。 傳統之複晶矽及複晶矽鍺薄繾電晶體之製迭，如T.J.Soc · Vol. 135, No. 8, page 2013-16, discloses a liquid phase deposition (y > D, 1 iquid phase deposition) method that can grow at a low temperature at 50 ° C (S i 02) US Patent No. 5, 〇73,408 5. This technology was originally applied to the growth of broken glass substrates to prevent the sodium ions in the broken glass from scattering outwards and to prevent it from growing above the liquid crystal display (LCD). This liquid phase sedimentation (LPD) recipe is due to its simple design, low manufacturing cost, low temperature preparation, and good growth of good quality silicon oxide thin, with the ability to selectively deposit 10%. Traditional polycrystalline silicon and polycrystalline silicon germanium thin-film transistors, such as T.J.
King 等人於1990 年IEDM Teeh.Dig.第253-256 I所揭示 ，係以低壓化學氟相沉積(LPCVD,l〇w pressure chemical 15 vapor deposition)系絃先於低温狀態下沉穑一層非晶矽 薄腹，再經過24〜72小時長時間之退火(a簡eal)處理使 其结晶成複晶矽。此方法咴母费時，不僅提高生產成本且 產品内沉猜許·多熱量，再則一般之低懕化學氣相沉積（ LPCVD)系统之成長室潔淨度較差*故所成長之複晶矽及複 20 晶矽鍺薄腹的品質無法與超高真空化學氣相沉積(UHV/CVD, ultrahigh vacuum chemical vapor deposition)系統所 成長的薄腹相較。雖然亦可利用雷射退火(annea 1)處理之 方法於低溫下使非晶矽結晶成複晶矽，然兩以該方法所製 24 作之複晶矽薄踱電晶艎即使具有良好之特性，但其整體之 2 nn tn ml nn m m n n^— m m· 一 I tm n^i n^i 'tn (請先閱讀.背面之注意事項再填窍本頁) 本紙張尺度逋用中國國家標率（CNS ) A4规格（2丨0 κ 2们公釐） 3^〇47s Λ7 B7 五、發明説明（） 均勻性及量產之可行性方面尚有待進一步克服，所以雷射 退火方式至目前爲止亦非無if可擊之方法。此外尚可利用 一種新近發表之催化劑(catalyzer)輔助法以成長複晶梦 ，其係以金屬絲置於冷壁(cold wall)成長室將晶片加熱 至成長溫度，以傳統之低壓化犖氣相沉穡（LPCVD)系統即 可成長複晶矽，而不必經由退火處理之方法。 10 本發明中利用超高真空化奪氣相沉積細V/CVD)直接 於550 以下溫度成長出複晶矽及複晶矽鍺薄貘，並以化 學機械研磨（CMP)系統改善複晶矽及複晶矽鍺薄膜表面之 平坦度。 15 本發明之主要目的係提供一種新顆之製備複晶矽n 晶矽鍺薄後電晶體方法，該方法可於低溢及低麵預算j (thermal budget)簏程造出特性·良好·之複晶珍及複晶竣备 薄腹電晶髏，且於製程中不需經過任何退火（anneal)處 理。 ---------1.-裝------訂------f 外 (請先閱讀背面之注意事項再填寫本I) 經濟部中央樣準局貝工消费合作社印製 20 24 繭式説明： 圖一本發明“一種製備薄臟電晶髗方法”之製程 圖二原子力顯歡镜照片 (atomic force microscopy) (a)爲抛光前 （b)爲抛光後 本紙張尺度逍用中國國家棣率（CNS > A4规格（2丨0X297公釐} 五、發明説明（ 5 10 15 Λ7 B7 圖三薄臌電晶艟的特性比較 W) P通道 1. Vd=-0.1V 抛光前 2. Vd=-5.0V 抛光前 3. Vd=-0.1V 拋光後 4. Vd=-5.0V 抛光後 (Β) η通追 1. Vd= 0.1V拋光前 2. Vd= 5.0V抛光前 3. Vd= 0.1V抛光後 4. Vd= 5.0V拋光後 nn ........ n Jm In -i— {請先閱讀^:面之注意事項再填寫太頁) 經濟部中央標準局貝工消費合作社印聚 20 24 圖號説明 1—介電基板 2____通道材質 21·…通造表面 3.. ..閘極介電層 4.. ..閘極 41.. ..氧化矽層 42.. ..隔離層 5 ----n+或P +區 6 ____絶緣介電層 7.. ..接觸區 4 .訂 u 本紙張尺度適用中國國家標準（CNS ) Α4規格（2丨Ο X 25»7公釐） A7 B7 經濟部中央#率局貝工消费合作社印製 五、發明説明（） 1 爲使贵審查委灵能對本發明故術手段及其功效能夠 更加明睐，茲佐以圈式並烊細説明如后： 雖然一般超高真空化季氣相沉積細V/CVW能於5501 5 以下的低溫成長出複晶矽及複晶矽鍺薄腹而不需經過任何 退欠（anneal )處理，且由於其製程中極低之背景蜃力 及極潔淨之成長環境，故所成長之複晶矽及複晶矽鍺薄蔽 亦1具有較低之缺：陷密度。然而該薄蓰之表面平坦度 (morphology )仍然較差，所以不適合運用於製造頂閘極 1〇 (top sate)之薄蓰電晶艟。本發明“一種製耩薄胰電晶體 方法”係運用超高真空化學氣相沉積（UHV/CVD)系統和化 學機械研磨法（chemical mechanical polishing.CMP)系 紋，既採用極低之背景壓力及極潔淨成長蠓境，以成長擁 有較低緃陷密度之複晶矽及複晶矽鍺薄暖，再以化學機械 15 研磨(CMF)系紋改善其表面平坦度，因而獲得表面平坦度 良好適用於製造議閘極(top gate〉，特性良好之複晶衫及 複晶矽鍺薄腹電晶髏。 本發明“一種製備薄璇電晶艟方法”如圖一（a)所示 20 ，首先在一般絶緣的介電基板（1)上以趣高真空化學氣相 沉積（UHV/CVD)系統沉精一廣複晶矽或複品矽鍺薄籤作爲 通追材質⑵，蓋以化學輾械研磨法_抛光其表面使通 道表面之粗輪度降低，接著定義元件之區域後於抛光的通 24 造表面(21)形成一閘極介電層(3)，再於閘極介電層⑶上 5 I — 裝— I 訂 n (請先閲讀背面之注$項再填寫本頁) 本紙張尺度適用中«_家榡率（CNS ) A4规格（210X297公釐） 五、發明説明（） 經濟部中央標準扃貝工消费合作社印製 1 以趁高真空化舉氣相诞積(UHV /CVW系舰藏積一麝氰晶發 或複晶矽错薄蘸作爲鬮極材質並尨義出閉接⑷，再以n-塑滲雜(n-type doping)或p-盤渗雜(p-type dopi塊)镍明 極與源極、级極形成n+或P+區⑸，然後藏積一絶錄介電 5 廣（6)並定義接觸口 •最後鏈金屬並；I：巍_麵與躁極、汲 極之接觸區(7)。 本發明“一種製镛薄腠f義艙方法”亦可如騙一 〇>) 所示，首先在一般絶線的介電基板（1)上以超高真空化學 10 氣相沉裱（UHV/CVD)系統沉稜一旛複晶矽戚複A矽鍺螓嶷 作爲通道村質（2) *並以化犖扇槭研磨法(CMP)抛光其表面 使通道表面之粗輪度降低，接著皮義元件之廉域攙齡挑光 的通道表面（21)形成一閘極介鬌層(3)，籌務蘭極命電赝 ⑶上以超高真空化學氣相沉棟iUHV/CVD)系觫菰轎一層高 15 濃度滲雜之Π+或p+複晶矽成褪A摩諸薄漢雜爲麟癱材質益 定義出閘極⑷，接著低溢沉轤一層曩雜矽機)戴獻均向（ an isotrop ic)電搫缺刻後形成明雜镅壁之麟錄看 ，42)，再以趄高真空化學氣相露輪«V/CI驗系鎗遘擇性 成長(selective grmrth) 高瀘農渗雜之逢化形（recess) 20 株極、汲極，以形成n+或p+蘿⑸，然瘓现義一饞籬介電 層（6)益定義揍觸口，最後鏞金屬並定義摘__嫌極、汲 極之接觸區(7)。 24 上迷以超高真空化學氣相_積(11VZCTW系鎗舲低激 (請先閱讀背面之注意事項再填寫本頁) 裝. 訂 本紙張尺度適用中國.國家標準（〇阳）八4规格<210父297公釐） 經濟部中央標準局貝工消费合作社印製 310478 五、發明説明（） 1 下沉積一複晶矽或複晶矽鍺薄藏作爲通道材質（2)，此通 道之材質可爲單層或多層之结構。本發明“一種製儀薄膜 電晶體方法”係運用超高真空化學氣相沉積（UHV/CVD)系 統配合化學機械研磨法（CMP〉系統，以抛光所成長之複晶 5 矽及複晶矽鍺薄胰*降低通造表面之粗糙度。然而本發明 亦可採取超高真空化學氣相沉積(UHV /CVD)系統方法搭配 合其它研磨故巧，例如研磨前輔以電漿缺刺可改善作爲通 追之複晶矽及複晶矽鍺薄暖通造表面研磨後之均勻性。 10 本發明定義元件區域（active「egion)後於抛光的通 道表面（21)形成一閘極介電層⑶，此閘極之可運 用如氧化矽(Si〇2)、氮化矽(Si3N4)或三氧化j：^l2〇3) 、氮氧化矽或其它可作爲閘極命電層之材質，氧化、 氣化、沉積、濺鍍等方法形成介電層。 15 本發明定義元件匾域（active region)以及間極⑷ 係以超高真空化學氣相沉積（UHV /CVD)系統於低溢下沉 積複晶矽或複晶矽鍺薄後作爲材質，並以ft方式進行蝕 刻定義。運用離子佈植（i〇n implant)、電漿滲雜(plasma 20 doping)、雷射輔助離子滲雜（laser assisted ion doping )或氣態滲雜（gas source doping)故術形成閘極與源極 、汲極之n+或p+區⑸；此/或p+區亦可利用選擇性成長（ selective growth)輔以同時（in situ)參雜之故術形成。 24 7 本紙張尺度適用中國國家揉準（CMS ) A4规格（210X2^7公釐） ---------ί 裝— (請先閱讀背面之注意事項再填艿本頁) 丁 -a 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（） 1 依照本發明“一種製備薄臟電晶體方法”所製儒作爲 通道材質之複晶矽或複晶矽鍺薄廒經原子力顯歡鏡(atomic force microscopy)照片如圖二所示，發現(a)抛光前其表 面平均粗鞭度(roughness)爲9.0 nm，⑸抛光後其表面 5 平均粗輪度(roughness)爲3.6 nm。且所製儀之薄暖電晶 艎之P通道及η通道薄瑗電属艙的特性，如fi三所示，其通 道寬長比W/L= 100徵米/10敬米。 爲使本發明之目的、方法及優點能更明顯地説明，以 10 下特舉實施例作蛘細具殖之陳迷，但不以其内容限制本發 明之範圔。 實施例一 15 於6501下以趣高真空化學氣相沉裱(UHV/CVD)系紋 於玻璃或二氧化矽基屑上沉積一庸1〇〇〜3〇〇隨之複晶矽 ⑵並經化學機械研磨法(CMP)研磨振光成50〜200 run 〇 以電漿灶刻將複晶碎灶_成元件區（active region〉 20 ，以低於600”#下溪度成長1〇〜50 μ的氧化矽（Si0z) 作閘極介電層。再以趄高真空化學氣相沉積（UHV / CVD) 於650 1〇下成長一層100-500 run之複晶矽。以電漿铖刻 定義出閘極*而以離子佈植（ion implant)後以高於500"0 24 下使閘極與源極、没極形成n+區或p+區。於200〜400t下 本紙張尺度適用中國國家槺率（CNS〉A4规格（210X29?公釐） -裝------訂------f w (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作杜印裝 五、發明説明（） 1 以電漿輔助化學氣相沉積一層200^-500 nm之氧化矽作介 電層。 烛刻出接觸口，鍍金屬並再蝕刻出閘極與源極、现極 之接觸區。 5 實施例二 以低於650 °C下以超高真空化學氣相沉積(UHV/CVD)系 統於玻璃或二氧化矽基層上沉積一層100〜300 mn之複晶 1〇 矽⑵並經化學機械研磨法(CMP)研磨抛光成50〜200 nm。 以電衆独刻將複A碎独刻成元件區（act ive reg ion) ，以低於600X3以下温度成長10〜50 nm的氧化碎（s i 〇2 ) 作閘極介電層。再以超高真空化學氣相沉積（UHV/CVD)以 15 低於6501下成長100〜500 rim之複晶矽。以電漿紬刻出 閘極，接著以低溫沉積一層氧化妙再經非均向性(recess) 電漿灶刻後形成閘極侧壁之隔離層（spacer)，再以超高真 空化學氣相沉積（UHV/CVD)系統選揮性成長（selective growth)出高浪度滲雜之退化形（recess)源極、沒極，以 20 形成n+或p+區，於200〜400°C下以電槳輔助化學氣相沉積 一層200^500 nm之氧化矽作介電層。 蝕刻出接觸口，鍍金屬並再蝕刻出閘極與騄極、没極 24 之接觸區。 9 --------{ ·裝------訂------^ ^ (請先聞讀背面之注意事項再填巧本1) 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐）King et al., 1990, IEDM Teeh. Dig. No. 253-256 I disclosed that the low-pressure chemical fluorine phase deposition (LPCVD, lww pressure chemical 15 vapor deposition) string was deposited before the low temperature state. The thin silicon abdomen is then crystallized into polycrystalline silicon after a long 24 to 72 hours of annealing (a simple eal) treatment. This method is time-consuming, not only increases production costs but also increases the amount of heat in the product, and the growth chamber of the general low-pressure chemical vapor deposition (LPCVD) system is poor in cleanliness *. Therefore, the grown polycrystalline silicon and The quality of the thin-web of Si-20 Ge cannot be compared with the thin-web developed by ultra-high vacuum chemical vapor deposition (UHV / CVD, ultrahigh vacuum chemical vapor deposition) system. Although the method of laser annealing (annea 1) can also be used to crystallize amorphous silicon into polycrystalline silicon at low temperature, the two thin polycrystalline silicon crystals made by this method even have good characteristics. , But its overall 2 nn tn ml nn mmnn ^ — mm · one I tm n ^ in ^ i 'tn (please read first. Note on the back and then fill in this page) This paper scale uses the Chinese national standard ( CNS) A4 specification (2 丨 0 κ 2 mm) 3 ^ 〇47s Λ7 B7 V. Description of the invention () The uniformity and the feasibility of mass production have yet to be further overcome, so the laser annealing method has not been so far There is no way to attack. In addition, a newly published catalyst-assisted method can be used to grow the compound crystal dream. It is to place the metal wire in a cold wall growth chamber to heat the wafer to the growth temperature, and use the traditional low pressure to reduce the gas phase. Shen LP (LPCVD) system can grow polycrystalline silicon without annealing. 10 In the present invention, ultra-high vacuum chemical vapor deposition fine V / CVD is used to directly grow polycrystalline silicon and polycrystalline silicon germanium thin tapir at a temperature below 550, and use chemical mechanical polishing (CMP) system to improve polycrystalline silicon and The flatness of the surface of the polycrystalline silicon germanium film. 15 The main purpose of the present invention is to provide a new method for preparing polycrystalline silicon n-crystalline silicon germanium thin post transistors, which can produce characteristics in a low overflow and low area budget (thermal budget) process Fujingzhen and Fujing have completed thin-bellied electric crystal skeletons and do not need to undergo any annealing treatment during the manufacturing process. --------- 1.-installed ----- ordered ----- f outside (please read the precautions on the back before filling in this I) Ministry of Economic Affairs Central Bureau of Standards and Peanut Consumption Printed by Cooperative Society 20 24 Description of cocoon type: Figure 1 Process diagram of the present invention "a method for preparing thin and dirty electric crystals" Two atomic force microscopy photos (a) before polishing (b) after polishing Paper-scale ease of use China national rate (CNS > A4 specification (2 丨 0X297mm) V. Description of the invention (5 10 15 Λ7 B7 Figure 3 Comparison of the characteristics of thin electro-transparent crystal W) P channel 1. Vd =- 0.1V before polishing 2. Vd = -5.0V before polishing 3. Vd = -0.1V after polishing 4. Vd = -5.0V after polishing (B) η through chase 1. Vd = 0.1V before polishing 2. Vd = 5.0 V before polishing 3. Vd = 0.1V after polishing 4. Vd = 5.0V after polishing nn ........ n Jm In -i— (please read ^: the precautions before filling in the page) Economy Ministry of Central Standards Bureau Beigong Consumer Cooperative Printed Poly 20 24 Description of Drawing Number 1—Dielectric Substrate 2____ Channel Material 21 ·… General Surface 3 ... Gate Dielectric Layer 4 ... Gate 41 .. .. silicon oxide layer 42 ... isolation layer 5-n + or P + region 6 ____ insulating dielectric layer 7 ... contact region 4. u This paper scale is applicable to the Chinese National Standard (CNS) Α4 specification (2 丨 Ο X 25 »7mm) A7 B7 Printed by the Central Bureau of the Ministry of Economic Affairs # Rate Bureau Beigong Consumer Cooperatives 5. Description of invention () 1 For your review committee Psionic energy can be more obvious for the tricks and effects of the present invention. Zuo Zuo uses a circle and explains in detail as follows: Although the general ultra-high vacuum seasoning vapor deposition fine V / CVW can grow at a low temperature below 5501 5 Polycrystalline silicon and polycrystalline silicon germanium thin belly without any anneal treatment, and because of the extremely low background vigour and extremely clean growth environment in the process, the grown polycrystalline silicon and polycrystalline The SiGe thin mask also has a lower defect: sink density. However, the thin morphology of the thin morphology is still poor, so it is not suitable for the manufacture of top gate 10 thin thyristor crystal stern. The "a method for making thin pancreas transistors" of the present invention uses the ultra-high vacuum chemical vapor deposition (UHV / CVD) system and chemical mechanical polishing (CMP) system lines, both using extremely low background pressure and Extremely clean growth environment, with growth support Polycrystalline silicon and polycrystalline silicon germanium with low sink density are thin and warm, and then chemical mechanical 15 grinding (CMF) lines are used to improve the surface flatness, so the surface flatness is good. It is suitable for manufacturing top gates. , The compound crystal shirt with good characteristics and thin crystal silicon germanium compound crystal skeleton. The "a method for preparing thin Xuan electric crystal capsules" of the present invention is shown in Fig. 1 (a). First, a high-vacuum chemical vapor deposition (UHV / CVD) system is used to concentrate on a generally insulating dielectric substrate (1) Yiguang compound crystal silicon or compound silicon germanium thin label is used as the follow-up material ⑵, and the cover is chemically polished by polishing. The surface is polished to reduce the roughness of the channel surface, and then the area of the component is defined. A gate dielectric layer (3) is formed on the surface (21), and then on the gate dielectric layer ⑶ 5 I — 装 — I Order n (please read the $ item on the back and then fill in this page) This paper size is applicable Chinese «_Home 戡 Rate (CNS) A4 specification (210X297 mm) V. Description of the invention () Printed by the Central Standard of the Ministry of Economic Affairs of the Beigong Consumer Cooperatives 1 to take advantage of the high vacuum to generate gas (UHV / CVW series ships) Deposit a musk cyanide crystal or polycrystalline silicon with a thin dip as the electrode material and define the closure ⑷, and then use n-type doping (n-type doping) or p-type doping (p-type dopi (Block) Nickel Ming electrode forms n + or P + area with source electrode and grade electrode ⑸, then accumulates an absolute recording dielectric 5 (6) and defines the contact port • The last chain metal merges; I: Wei_plane and The contact area (7) of the pole and the drain pole. The present invention "a method of making a thin yam-fed compartment" can also be as shown in 計 一 >>, first on a generally insulated dielectric substrate (1) Ultra High Vacuum Chemistry 10 Vapor-phase deposition (UHV / CVD) system Shen Ling Yipuan polycrystalline silicon Qi Fu A silicon germanium carbamide is used as a channel quality (2) * and polished by chemical maple grinding method (CMP) The surface reduces the roughness of the surface of the channel, and then the channel surface (21) of the cheap area of the Piyi component forms a gate dielectric layer (3), which is super high on the planning electrode. Vacuum chemical vapor deposition (iUHV / CVD) is a layer of high concentration 15 ++ p + polycrystalline silicon in the first layer of 賫 菰 軰, which has been dissipated. A Mozhu thin Han complex is defined as a material for Lin paralysis. Shen Shi 1st layer of mixed silicon machine) Dai Xianjun (an isotrop ic) electrocuts the engraving and forms the wall of the Ming Zhe americium wall, 42), and then uses the high-vacuum chemical vapor dew wheel «V / CI test system gun 遘Selective growth (selective grmrth) Gao Lunong infiltrated recurrence (recess) 20 strain poles, dip poles, to form n + or p + Luo ⑸, then paralyze the current meaning of a dielectric layer (6) Yi definition strike Mouth, last yong Genus and define hook __ too polar, the drain contact region (7). 24 The fan uses ultra-high vacuum chemical vapor_products (11VZCTW series guns are low-excited (please read the precautions on the back and then fill out this page) for installation. The size of this paper is applicable to China. National Standard (〇 阳) 84 specifications < 210 father, 297 mm) Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 310478 V. Description of the invention () 1 A polycrystalline silicon or polycrystalline silicon germanium thin deposit is deposited as a channel material (2). The material can be single-layer or multi-layer structure. The "a method for manufacturing thin film transistors" of the present invention uses an ultra-high vacuum chemical vapor deposition (UHV / CVD) system combined with a chemical mechanical polishing method (CMP> system) to polish the grown polycrystalline silicon 5 and polycrystalline silicon germanium Thin pancreas * reduces the roughness of the general surface. However, the present invention can also use the ultra-high vacuum chemical vapor deposition (UHV / CVD) system method in combination with other grinding tricks, such as supplementing with plasma puncture before grinding can improve the The uniformity of the surface of the polycrystalline silicon and polycrystalline silicon germanium thin heating and ventilation through grinding after grinding. 10 The present invention defines an active area (eg "element") and forms a gate dielectric layer (21) on the polished channel surface (21) , The gate can be used as silicon oxide (Si〇2), silicon nitride (Si3N4) or trioxide j: ^ l2〇3), silicon oxynitride or other materials that can be used as the gate life layer, oxidation, The dielectric layer is formed by gasification, deposition, sputtering, etc. 15 The present invention defines the active region and interelectrode ⑷ of the device. The ultra-high vacuum chemical vapor deposition (UHV / CVD) system is used to deposit the complex Crystal silicon or polycrystalline silicon germanium is thin as a material and etched in ft mode Defined by using ion implantation (plasma doping), laser assisted ion doping (laser assisted ion doping) or gas source doping (gas source doping) N + or p + area with source and drain ⑸; this / or p + area can also be formed by selective growth supplemented by in situ miscellaneous techniques. 24 7 This paper size is suitable for Chinese countries Kneading (CMS) A4 specification (210X2 ^ 7mm) --------- ί Packing — (please read the notes on the back before filling this page) Ding-a Employee Consumption of Central Bureau of Standards, Ministry of Economic Affairs Printed by cooperatives A7 B7 V. Description of the invention (1) According to the invention "a method of preparing thin dirty transistors" made of crystalline crystalline silicon or polycrystalline silicon germanium thin channels as atomic material microscopy ) The photo is shown in Figure 2. It is found that (a) the average roughness of the surface before polishing is 9.0 nm, ⑸ the average roughness of the surface after polishing is 3.6 nm, and the thickness of the instrument is thin The characteristics of the P-channel and η-channel thin sub-electric compartments of the warm electric crystal, as shown in fi III, the channels Length ratio W / L = 100 levy meters / 10 Jingmi. In order to make the purpose, method and advantages of the present invention more obvious, the following ten specific examples are used as the mystery of the worms, but not The content limits the scope of the present invention. Embodiment 1 15 At 6501, a high vacuum chemical vapor deposition (UHV / CVD) pattern is deposited on glass or silicon dioxide-based chips to deposit 100-300. Following this, the polycrystalline silicon ⑵ is polished by chemical mechanical polishing (CMP) to 50 ~ 200 run. The polycrystalline broken stove is etched into a component area (active region> 20, less than 600 "by plasma stove). # The silicon oxide (Si0z) grown in Xiaxidu is 10-50 μm as the gate dielectric layer. Then, a layer of 100-500 run of polycrystalline silicon is grown under high vacuum chemical vapor deposition (UHV / CVD) at 650-10. The gate electrode * is defined by plasma engraving and the ion implantation (ion implant) is used to form an n + region or p + region with the source electrode and the non-electrode electrode above 500 " 0 24. Under 200 ~ 400t, this paper scale is applicable to China ’s national rate (CNS> A4 specification (210X29? Mm) -installed ------ ordered ------ fw (please read the notes on the back before filling in This page) Employee's consumer cooperation with the Central Bureau of Standards of the Ministry of Economic Affairs, Du Printing. V. Description of the invention () 1 A plasma-assisted chemical vapor deposition of a layer of silicon oxide of 200 ^ -500 nm is used as the dielectric layer. Metal and then etch out the contact area of the gate, source and current electrode. 5 Example 2 The ultra-high vacuum chemical vapor deposition (UHV / CVD) system is used on the glass or silicon dioxide base layer below 650 ° C Deposit a layer of 100 ~ 300 mn of polycrystalline 10 silicon ⑵ and polish to 50 ~ 200 nm by chemical mechanical polishing (CMP). The complex A is broken into the element area (act ive reg ion) ， Oxide fragments (si 〇2) grown at a temperature below 600X3 below 10 ~ 50 nm are used as the gate dielectric layer. And then grown under ultra-high vacuum chemical vapor deposition (UHV / CVD) at 15 below 6501 100 ~ Polycrystalline silicon of 500 rim. The gate electrode is engraved with plasma, and then a layer of oxide is deposited at low temperature and then shaped by the anisotropic (recess) plasma stove The spacers on the sidewalls of the gates are then selectively grown by ultra-high vacuum chemical vapor deposition (UHV / CVD) system to produce high-wave infiltrated recessed source and no-recess sources , Forming n + or p + regions with 20, and using a paddle-assisted chemical vapor deposition of 200 ^ 500 nm silicon oxide as the dielectric layer at 200 ~ 400 ° C. The contact openings are etched, the metal is plated and the gate is etched Contact area with 騄 极 、 无极 24. 9 -------- {· Install ------ Order ------ ^ ^ (Please read the notes on the back before filling This 1) This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm)