CN100485890C - Method for manufacturing thin film electricity crystal and method for changing non-crystal inlay to multi-crystal inlay or single-crystal inlay - Google Patents
Method for manufacturing thin film electricity crystal and method for changing non-crystal inlay to multi-crystal inlay or single-crystal inlay Download PDFInfo
- Publication number
- CN100485890C CN100485890C CNB2005100992084A CN200510099208A CN100485890C CN 100485890 C CN100485890 C CN 100485890C CN B2005100992084 A CNB2005100992084 A CN B2005100992084A CN 200510099208 A CN200510099208 A CN 200510099208A CN 100485890 C CN100485890 C CN 100485890C
- Authority
- CN
- China
- Prior art keywords
- layer
- single crystalline
- amorphous
- substrate
- polycrystalline
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
This invention provides one film transistor process method, which comprises the following steps: forming one buffer layer onto baseboard and one first single transistor layer onto buffer layer; then forming one non-crystal layer onto first single crystal layer and converting the layer into one crystal layer by one annealing method; the crystal layer is of one compound layer or second layer then forming one gate medium layer and then forming one gate electrode on medium layer.
Description
[technical field]
The invention relates to a kind of manufacture method of membrane transistor, the manufacture method of the particularly relevant membrane transistor that is applicable to LCD and amorphous layer is converted to the method for polycrystalline layer or single crystalline layer.
[background technology]
Present membrane transistor LCD (thin film transistor-liquid crystaldisplay, TFT-LCD) technology is divided into two kinds, and one is traditional amorphous silicon membrane electric crystal, and another is the compound crystal silicon membrane transistor.Since the electronics translational speed of compound crystal silicon membrane transistor be 10 times to 100 times of the amorphous silicon membrane electric crystal between.Therefore, the TFT-LCD industry has taken up to study and develop, with the drive circuit as picture element (pixel) switch element and LCD periphery of compound crystal silicon membrane transistor.
Low temperature compound crystal silicon (lowtemperature polysilicon, LTPS) processing procedure are adopted in the making of above-mentioned compound crystal silicon membrane transistor usually.So-called LTPS processing procedure is to utilize quasi-molecule laser annealing to handle that (excimer laser annealing ELA) makes original amorphous silicon membrane be transformed into the compound crystal silicon structure.
Yet, by traditional quasi-molecule laser annealing technology with amorphous silicon crystallization and the output energy process window that forms compound crystal silicon is very narrow again.Existing excimer laser energy time stability is not good, though equipment can be suppressed at the energy change of (peak to peak) between spike and spike below 15% at present, if yet when irradiation energy change occurs, can cause substrate locality energy height difference.This energy changing can cause compound crystal silicon thin film crystallization particle diameter, and great changes will take place, and the membrane transistor characteristic is produced harmful effect.
[summary of the invention]
Therefore, according to above-mentioned problem, a purpose of the present invention can increase excimer laser energy process window for a kind of manufacture method of membrane transistor is provided, and can be by directly increasing the restriction that the excimer laser energy range overcomes board.
Another object of the present invention converts amorphous layer the method for polycrystalline layer or single crystalline layer to for providing a kind of, and it can obtain uniform compound crystal silicon or monocrystalline silicon thin film.
The invention provides a kind of manufacture method of membrane transistor.At first, form a resilient coating on substrate, and form one first single crystalline layer on resilient coating., form an amorphous layer in first single crystalline layer on,, convert amorphous layer to a crystallizing layer with a laser anneal method thereafter.This crystallizing layer is a polycrystalline layer or second single crystalline layer; Then, form a brake-pole dielectric layer on polycrystalline layer.Follow-up, form a gate electrode on brake-pole dielectric layer.
The present invention also provides a kind of and converts amorphous layer the method for polycrystalline layer or single crystalline layer to, it is characterized in that: comprise the steps:
One substrate is provided; Form a resilient coating on this substrate; Form one first single crystalline layer on this resilient coating; Form an amorphous layer on this single crystalline layer; And, convert this amorphous layer to a crystallizing layer with a laser anneal method, wherein this crystallizing layer is to be one second single crystalline layer or a polycrystalline layer.
[description of drawings]
1A figure～the 1H figure illustrates one embodiment of the invention to make membrane transistor TFT flow chart.
[embodiment]
Below will describe in detail as reference of the present invention, and example is accompanied by graphic explanation with embodiment.In graphic or description, similar or identical part is to use identical figure number.In graphic, the shape of embodiment or thickness can enlarge, to simplify or convenient the sign.The part of element will illustrate with description in graphic.Apprehensiblely be that the element that does not illustrate or describe can have the various forms of haveing the knack of known to this skill people.In addition, when narration one deck is when being positioned at a substrate or another layer and going up, this layer can be located immediately on substrate or another layer, or intermediary layer can also be arranged therebetween.
Figure 1A～Fig. 1 H illustrates one embodiment of the invention to make membrane transistor TFT flow chart.Please refer to Figure 1A, a substrate 100 at first is provided.This substrate 100 can be a glass substrate, is preferably a glass with lower alkali content substrate or an alkali-free glass substrate.Deposit a resilient coating 102 in substrate 100 on thereafter.Resilient coating 102 can be the dielectric layer formed of silica, silicon nitride or silicon oxynitride for example.Next, form single crystalline layer 104 on resilient coating 102, shown in Figure 1B.Single crystalline layer 104 can be a monocrystalline silicon, and its formation method can be molecular beam epitaxy (Molecular beamepitaxy), atomic layer brilliant (Atomic layer epitaxy) of heap of stone, gas phase brilliant (Vapor phase epitaxy) of heap of stone or liquid built crystalline substance modes such as (Liquid phase epitaxy) form.The preferably, single crystalline layer 104 is to be the monocrystalline silicon thin film of a thickness between 20 dusts～200 dusts.
Next, please refer to Fig. 1 C, form an amorphous layer 106 on single crystalline layer 104.Amorphous layer 106 can be an amorphous silicon.The preferably, amorphous layer 106 is to be an amorphous silicon, and its thickness is the design alternative of considering for according to product demand or processing procedure.The deposition process of amorphous layer 106 can strengthen chemical vapour deposition technique PECVD, atomic layer deposition method APCVD or similar technology for Low Pressure Chemical Vapor Deposition LPCVD, aumospheric pressure cvd method APCVD, electricity slurry.In preferable enforcement example, amorphous layer 106 is can adopt the lower electricity slurry of process temperatures to strengthen chemical vapour deposition technique (PECVD) to form.
, please refer to Fig. 1 D, amorphous layer 106 is annealed, and make amorphous layer 106 be converted to the crystallizing layer 106 of polycrystalline layer or single crystalline layer for example " with laser beam annealing 108 (for example quasi-molecule laser annealing, ELA, Excimer laser anneal) thereafter.
Tradition quasi-molecule laser annealing technology is with amorphous silicon crystallization and the output energy process window that forms compound crystal silicon is that very narrow reason is in the recrystallized amorphous silicon process again, the amorphous silicon that needs one deck not have to melt is used as crystal seed (seed), and known techniques can't effectively provide this crystal seed that does not melt, and the crystal grain that causes amorphous silicon to form compound crystal silicon diminishes.The reason that the crystal grain that causes amorphous silicon to form compound crystal silicon diminishes has two: (1) if laser energy is crossed when hanging down, the amorphous silicon that can melt fully concentrates on the top layer, and bottom then presents the semi-molten state.Silicon wafer particle diameter during therefore with low-yield crystallization is less and also have portion of amorphous silicon and be entrained in wherein.(2),,, cause homogeneous nucleation from all directions, and the compound crystal silicon crystal grain of crystallization is less owing to there is not the guiding of silicon seed because amorphous silicon presents the state of fusing fully if when laser energy is too high.Because these two reasons make the energy process window of traditional quasi-molecule laser annealing very little.
In one example of the present invention, before deposition of amorphous silicon 106, deposition one deck monocrystalline silicon thin film 104 is as crystal seed earlier.Because the height that the fusing point of monocrystalline silicon (1686 ℃) is more next than amorphous silicon fusing point (1273 ℃), so the present invention can improve excimer laser output energy at least about 15%.According to (energy (E)=specific heat (S) * quality (M) * temperature difference (Δ T)), generally speaking laser radiation generation instantaneous temperature is about 1400 ℃, when increasing energy 15%, the moment high temperature that produces is about 1600 ℃, therefore when arriving monocrystalline silicon thin film 104 via thermal diffusion, temperature is less than 1600 ℃, do not allow monocrystalline silicon 104 fusings and can not make, and makes amorphous silicon 106 recrystallize into crystallizing layer 106 into for example polycrystalline layer or single crystalline layer by monocrystalline silicon 104 crystal seeds ".So just can overcome the output energy unsteadiness influence that crystallization is again caused to amorphous silicon of quasi-molecule laser annealing ELA board.
Next, please refer to Fig. 1 E,, form brake-pole dielectric layer 110 and gate electrode layer 112 in regular turn in crystallizing layer 106 with general little shadow and engraving method " on.Brake-pole dielectric layer 110 can be formed by for example silica, silicon nitride or silicon oxynitride.Gate electrode layer 112 can be a single metal layer, a bimetal structure or polymetal crust.Above-mentioned structure can be selected from following group: W, WN
x, Ti, TiW
x, TiN
x, Ta, TaN
x, Mo, Al, Cu and similar material.The deposition process of any kenel (including but not limited to chemical vapour deposition technique CVD, physical vaporous deposition PVD, evaporation, plating, sputter, reaction sputter (reactive co-sputtering) or above-mentioned combination altogether) can be in order to form this metal level.
After forming gate structure, lightly mixed drain area (LDD), dielectric gap wall and source/drain regions can known techniques form.For instance, shown in the 1F～1H figure, at first, please refer to Fig. 1 F, carry out a light dope ion disposing process with variety classes impurity, implant impurity is in crystallizing layer 106 " in, to form light doping section (light doped region, LDD) 114.The border of light doping section 114 is the sidewalls that approximately are registered to gate structure.The energy of light dope ion disposing process is reducible between 1～100Kev, and its doping is approximately between 1 * 10
13～1 * 10
15Ions/cm
2Afterwards, deposit and dry ecthing procedure, form clearance wall 116 with sidewall along gate structure.Clearance wall 116 can be formed by following material: the alternating layer of silicon nitride layer, silicon oxide layer, silicon oxynitride layer, silicon nitride layer and silicon oxide layer or above-mentioned combination.Afterwards, carries out a heavy doping ion cloth and plant, and gate clearance wall 116 is to be made for cover curtain, plant multiple impurity to crystallizing layer 106 with cloth " in, source/drain regions 118 formed.The border of source/drain regions 118 is the exterior side wall that approximately are registered to the gate clearance wall respectively.Heavy doping ion cloth is planted the energy of processing procedure approximately between 1～100Kev, and doping is approximately between 5 * 10
13～1 * 10
16Ions/cm
2
Therefore, according to the foregoing description, the present invention has following advantage at least:
(1) mode forms in compound crystal silicon or the monocrystalline silicon process thus, and it is about more than 15% to increase excimer laser energy process window significantly.
(2) according to the method for the embodiment of the invention, can be by bottom monocrystalline silicon as crystal seed, via the quasi-molecule laser annealing technology amorphous silicon is recrystallized into again and be monocrystalline silicon or compound crystal silicon, so electronics mobility (Electron mobility) can increase significantly, and can solve the low temperature compound crystal silicon because panel size increased back (〉 at 15 o'clock), the shortcoming that the electronics mobility can't satisfy.In addition, according to the method for the embodiment of the invention, it can promote outside the electronics mobility of membrane transistor element, and can shorten the time that tradition is used molecular beam epitaxy deposition monocrystalline silicon.
Though the present invention discloses as above with preferred embodiment, so it is not in order to limiting the present invention, anyly has the knack of this skill person, and a little change and the retouching done all should belong to protection scope of the present invention.
[symbol description]
100～substrate; 102～cushion;
104～single crystalline layer; 106～amorphous layer;
106 "～crystallizing layer; The annealing of 108～laser beam;
110～brake-pole dielectric layer; 112～gate electrode layer;
114～light doping section; 116～clearance wall;
118～source/drain regions.
Claims (15)
1. the manufacture method of a membrane transistor is characterized in that: comprise the steps:
One substrate is provided;
Form a resilient coating on this substrate;
Form one first single crystalline layer on this resilient coating;
Form an amorphous layer on this first single crystalline layer;
With a laser anneal method, convert this amorphous layer to a crystallizing layer;
Form a brake-pole dielectric layer on this crystallizing layer; And
Form a gate electrode on this brake-pole dielectric layer,
Wherein this crystallizing layer is to be one second single crystalline layer or a polycrystalline layer, and this laser annealing is to adopt an excimer laser to shine in this amorphous surface, and the instantaneous temperature that produces in this amorphous surface is 1400～1600 ℃.
2. the manufacture method of membrane transistor as claimed in claim 1 is characterized in that: also comprise:
With this gate electrode is the cover curtain, carries out an ion disposing process, forms light doping section in this substrate;
Form a clearance wall in this gate electrode and this brake-pole dielectric layer sidewall; And
With this gate electrode and this clearance wall is the cover curtain, carries out an ion disposing process, forms source/drain regions in this substrate.
3. the manufacture method of membrane transistor as claimed in claim 1 is characterized in that: this amorphous layer is to produce the melting state, and this first single crystalline layer does not produce the melting state as yet.
4. the manufacture method of membrane transistor as claimed in claim 1, it is characterized in that: this first single crystalline layer is a monocrystalline silicon.
5. the manufacture method of membrane transistor as claimed in claim 1, it is characterized in that: this amorphous layer is an amorphous silicon, and this polycrystalline layer or second single crystalline layer are compound crystal silicon or monocrystalline silicon.
The manufacture method of 6 membrane transistors as claimed in claim 1 is characterized in that: the thickness of this first single crystalline layer is between 20 dusts～200 dusts.
7. the manufacture method of membrane transistor as claimed in claim 1 is characterized in that: this first single crystalline layer is to adopt molecular beam epitaxy, atomic layer brilliant, gas phase crystalline substance of heap of stone of heap of stone or liquid built is brilliant forms.
8. the manufacture method of membrane transistor as claimed in claim 1, it is characterized in that: this substrate is a glass substrate.
9. one kind converts amorphous layer the method for polycrystalline layer or single crystalline layer to, it is characterized in that: comprise the steps:
One substrate is provided;
Form a resilient coating on this substrate;
Form one first single crystalline layer on this resilient coating;
Form an amorphous layer on this first single crystalline layer; And
With a laser anneal method, convert this amorphous layer to a crystallizing layer,
Wherein this crystallizing layer is to be one second single crystalline layer or a polycrystalline layer, and this laser annealing is to adopt an excimer laser to shine in this amorphous surface, and the instantaneous temperature that produces in this amorphous surface is 1400～1600 ℃.
10. as claimed in claim 9ly convert amorphous layer the method for polycrystalline layer or single crystalline layer to, it is characterized in that: this amorphous layer is to produce the melting state, and this first single crystalline layer does not produce the melting state as yet.
11. as claimed in claim 9ly convert amorphous layer the method for polycrystalline layer or single crystalline layer to, it is characterized in that: this first single crystalline layer is a monocrystalline silicon.
12. as claimed in claim 9ly convert amorphous layer the method for polycrystalline layer or single crystalline layer to, it is characterized in that: this amorphous layer is an amorphous silicon, and this polycrystalline layer or second single crystalline layer are compound crystal silicon or monocrystalline silicon.
13. as claimed in claim 9ly convert amorphous layer the method for polycrystalline layer or single crystalline layer to, it is characterized in that: the thickness of this first single crystalline layer is between 20 dusts～200 dusts.
14. as claimed in claim 9ly convert amorphous layer the method for polycrystalline layer or single crystalline layer to, it is characterized in that: this first single crystalline layer is to adopt molecular beam epitaxy, atomic layer brilliant, gas phase crystalline substance of heap of stone of heap of stone or liquid built is brilliant forms.
15. as claimed in claim 9ly convert amorphous layer the method for polycrystalline layer or single crystalline layer to, it is characterized in that: this substrate is a glass substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100992084A CN100485890C (en) | 2005-09-09 | 2005-09-09 | Method for manufacturing thin film electricity crystal and method for changing non-crystal inlay to multi-crystal inlay or single-crystal inlay |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100992084A CN100485890C (en) | 2005-09-09 | 2005-09-09 | Method for manufacturing thin film electricity crystal and method for changing non-crystal inlay to multi-crystal inlay or single-crystal inlay |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1929101A CN1929101A (en) | 2007-03-14 |
| CN100485890C true CN100485890C (en) | 2009-05-06 |
Family
ID=37858996
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100992084A Active CN100485890C (en) | 2005-09-09 | 2005-09-09 | Method for manufacturing thin film electricity crystal and method for changing non-crystal inlay to multi-crystal inlay or single-crystal inlay |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100485890C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103715269B (en) * | 2013-12-31 | 2015-06-03 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate and display device |
| CN109801973B (en) * | 2018-09-25 | 2021-01-26 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method thereof, array substrate and display device |
-
2005
- 2005-09-09 CN CNB2005100992084A patent/CN100485890C/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN1929101A (en) | 2007-03-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Yamamoto | Technological innovation of thin-Film transistors: technology development, history, and future | |
| US5965904A (en) | Semiconductor device comprising silicon semiconductor layer | |
| JPH07140454A (en) | Manufacture of glass panel for silicon device | |
| CN100356506C (en) | Crystal mask, amorphous silicon crystallization method and method of manufacturing array base plate using same | |
| TW316999B (en) | ||
| Kim et al. | Polycrystalline Si films formed by Al-induced crystallization (AIC) with and without Al oxides at Al/a-Si interface | |
| US20020090772A1 (en) | Method for manufacturing semiconductor lamination, method for manufacturing lamination, semiconductor device, and electronic equipment | |
| US6326226B1 (en) | Method of crystallizing an amorphous film | |
| CN100485890C (en) | Method for manufacturing thin film electricity crystal and method for changing non-crystal inlay to multi-crystal inlay or single-crystal inlay | |
| TWI260747B (en) | A method for forming a thin film transistor, and a method for transforming an amorphous layer into a poly crystal layer of a single crystal layer | |
| Mudgal et al. | Communication—CMOS thin-film transistors via Xe flash-lamp crystallization of patterned amorphous Si | |
| JPH0422120A (en) | Thin film semiconductor device | |
| JP3924828B2 (en) | Method for manufacturing crystalline semiconductor film and method for manufacturing thin film transistor | |
| US6818319B2 (en) | Diffusion barrier multi-layer structure for thin film transistor liquid crystal displays and process for fabricating thereof | |
| KR100307397B1 (en) | Method of producing a thin film transistor of which a microcrystalline silicon film is deposited on a glass substrate by using fluorite or cerium oxide seed layer | |
| KR100518922B1 (en) | Formation method of crystalline film and manufacturing method of thin film electronic device | |
| CN1316770A (en) | Process for preparing polysilicon film | |
| JP2002246606A (en) | Method for fabricating thin film transistor | |
| US20040106244A1 (en) | Method of crystallizing amorphous silicon and device fabricated using the same | |
| KR100222913B1 (en) | Process for forming polycrystalline silicon | |
| Higashi et al. | Technological Innovation of Thin-Film Transistors: Technology Development, History, and Future | |
| CN108231794A (en) | Preparation method, the array substrate of array substrate | |
| KR20040036761A (en) | Method of silicon deposition using of hdp-cvd | |
| Song et al. | A fabrication method for reduction of silicide contamination in polycrystalline-silicon thin-film transistors | |
| JPH07142405A (en) | Polycrstalline semiconductor film and deposition thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: YOUDA PHOTOELECTRIC CO., LTD. Free format text: FORMER OWNER: GUANGHUI ELECTRONIC CO., LTD. Effective date: 20080215 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20080215 Address after: Hsinchu, Taiwan, China Applicant after: AU Optronics Corporation Address before: China Taiwan Taoyuan County Applicant before: Guanghui Electronic Co., Ltd. |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |