TW309657B - - Google Patents

Description

Ministry of Economic Affairs, Central Standardization Bureau, Consumer Cooperative Du Printing 309657 A7 B7 V. Description of the invention (1) [Detailed description of the invention] The present invention relates to a multi-bit semiconductor memory with multiple-digit data. [Conventional Technology] In the semiconductor memory digital system with DRAM (Dynamic Random Access Memory), etc., in order to increase the data transfer speed, the following features are applied. The first feature is that the semiconductor memory is multi-bit type. The multi-bit (X 2n) semiconductor billion system is generally composed of 2η (η is a natural number) data input and output at the same time. The second feature is that it synchronizes the high-frequency external clock output from the CPU (Central Processing Unit) to input and output data. In such a clock-synchronized semiconductor memory (SDRAM, RDRAM, etc.), the higher the external clock frequency, the higher the continuous data output and the higher the data transfer speed. The third feature is that a plurality of banks are installed in one semiconductor memory (memory chip). The plural district libraries have the same elements, and each of the plural district libraries can be constructed by independently outputting data. Thus, the time to access the original data can be shortened, and the data transmission speed can be improved. FIG. 3 is a schematic diagram showing the chip layout of the conventional semiconductor memory. This semiconductor billion system has the above three characteristics. On one memory chip 10, configure 4 zone libraries 1 1 _ 0 ~ This paper scale is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297 mm), one bucket-II-;!--ΛΙ ( I —l · * < nn taxi ----(please read the notes on the back before filling this page)

, 1T 309657 b7 309657 b7 Printed by the Employee Consumer Cooperative of the Central Bureau of Economic Development of the Ministry of Economic Affairs Five'Instructions for Invention (2) 1 1 — 3 Each zone library 1 1-〇 ~ 1 1 to 3 forms a memory array controller, a memory array controller, and forms a row decoder, a column decoder, a DQ buffer (called a buffer in the input and output section of the zone library), etc. Peripheral circuit. In addition, on one memory chip 10, the configuration data input and output range is 12. When data input / output circuits (I / O), such as 16-bit (2-byte) data are input and output simultaneously in the data input / output range L2, 16 input / output circuits are formed. In the district library 1 1-0 ~ 1 1 to 3, configure the data bus 1 3. The child material bus 13 is a data path between the district library 1 1 1 0 ~ 1 1 — 3 and the data input / output range 12. The data bus 13 is configured such that when 16-bit (2-byte) data is input and output at the same time, 16-bit data is transmitted. The input and output operations of the above-mentioned semiconductor memory data are performed as follows. First, select one of the four district libraries 11-10 to 11-3. In the selected one area library, perform the access operation with 100 million grids according to the address signal '. Select and output the 2 n-bit (for example, 16 bit (2 byte)) data from one area library . This 2 " bit data is directed to the data input / output range 1 2 ’through the data bus 1 3 and is output from the data input / output range 12 to the outside of the semiconductor memory (memory chip). [Problems to be solved by the invention] The above-mentioned semiconductor memory must be reviewed because it occupies the standard size of the paper and is suitable for financial projects® (CNS) Λ4 present (210X 297 public voices) , --- γ '* clothing ------, 玎 ------- f (please read the precautions on the back before filling this page) -I "-3〇9657 A7 ----- -B7 V. Description of the invention (3) According to the ratio of the full range of data bus i 3 on 1 billion chip. That is, the range of the data bus 13 is made as small as possible, and the chip area can be reduced. However, as the number of bits that are input and output is increased at the same time, the range of the data bus increases. That is, in the past, the structure of semiconductor memory has shifted from 16-bit type (X16)-32-bit type (x32)-64-bit (X64) 'to multi-bit type, the chip area range will be Increase the disadvantages. v / The present invention is to solve the above shortcomings. The purpose is in a multi-bit type, one-clock synchronous type, and block-type semiconductor memory, without increasing the chip volume, can increase the data transfer speed. [Means for Solving the Problem] In order to achieve the above object, the semiconductor memory system of the present invention includes a memory wafer and a plurality of banks arranged on the memory wafer. Each of the foregoing plural bank is independent of each other, and performs the reading operation of the plural digit data or the writing operation of the plural digit data. Printing and Burning of the Cooperative Society for Employee Capital Consumption of the Central Lizhun Bureau of the Ministry of Economic Affairs

Hi mr »I— 1 m in n In —— ^ ϋ I HI 一 —r. / J- ', (please read the precautions on the back before filling in this page) The above-mentioned plural district library system has plural middle districts Library. The aforementioned middle blocks are composed of two small blocks composed of a self-recorded billion grid array, a sense amplifier arranged between the two small blocks, and character lines, data lines and rows arranged on the memory grid array Select the line. The aforementioned middle blocks are arranged in the row direction in which the row selection line and the data line pair extend. The small blocks are arranged in the column direction. The aforementioned plural district libraries are arranged at the two ends in the aforementioned column direction. The paper standard is applicable to the Chinese National Standard (CNS) Λ4 specification (2ΙΟΧ2 () 7 公 «) A7 B7 309657 V. The invention description (4) , With a column decoder connected to at least one of the aforementioned column selection lines. The plurality of bank areas are arranged at one of the two end portions of the word line in the extending column direction, and are arranged one by one in each of the center bank areas. The column decoder is connected to the word line. Each of the plural bank is arranged in the other DQ buffer in the two ends in the row direction. Each of the plural blocks is arranged at the other of the two end portions in the row direction, and has a grid array controller that controls the reading operation of the plural bit data or the writing operation of the plural bit data. The semiconductor memory system of the present invention is equipped with a data input / output range configured on the memory chip to perform data input / output of the complex number, and is set in common with the bank of the complex number, extending in the row direction to be the complex The data bus of the path of the aforementioned complex digital data between the library and the aforementioned data input / output range. The plurality of district libraries are provided between the two small blocks constituting each of the blocks, extending in the row direction, connected to the local DQ line pair of the sense amplifier, and extending on the middle block In the column direction, the entire DQ line pair connecting the block DQ line pair and the buffer is provided. The semiconductor billion memory system of the present invention includes a memory and a plurality of main area libraries arranged on the billion memory chip. Each of the aforementioned plural primary area libraries is composed of plural secondary area libraries. Each of the aforementioned plural sub-blocks performs reading of plural-digit data or writing of plural-digit data independently of each other. Each of the aforementioned sub-regional reservoir systems has a plurality of middle blocks. The aforementioned middle blocks are the paper standards applicable to the Chinese National Standard (CNS) Λ4 specification (210X297 mm) ~ " --- Λ --- * ---- ^., Iyi ------ order ------ Fei (please read the precautions on the back before filling this page) Printed by the Central Standards Bureau of the Ministry of Economic Affairs, printed by the Central Standards Bureau of the Ministry of Economic Affairs, printed by the Consumers Cooperative of the Ministry of Economics ^^ 9657 A7 B7 _________ 5. Description of the invention (5) Two small blocks composed of a self-recording array and a sense amplifier arranged between the two small blocks, and character lines, data lines and row selection lines arranged on the memory array . The aforementioned middle blocks are arranged in the row direction in which the row selection line and the data pair extend. The small blocks are arranged in the column direction. Each of the plural sub-region libraries is arranged at one of the two ends in the column direction, and is connected to at least one column decoder of the column selection line. Each of the plural sub-region libraries has one of two end portions arranged in the row direction of the extended word line, one for each middle block, and connected to the row decoder of the word line. Each of the plural sub-region libraries is equipped with the other DQ buffer arranged in the two ends of the column direction. The aforementioned plural sub-region libraries are equipped with the other one arranged in the two ends of the row direction. On the other hand, a grid array controller that controls the reading operation of the aforementioned complex bit data or the writing operation of the aforementioned bit data. The semiconductor memory device of the present invention has a data input / output range configured on the aforementioned memory chip to perform the data input / output of the plural digits, and is set in common in all the sub-region libraries constituting the plural main block More than two sub-zone libraries extend in the aforementioned row direction, and a complex data bus is formed by the aforementioned plural-digit data path between the aforementioned sub-zone library and the aforementioned data input / output range. The plural sub-region libraries are provided between the two small blocks constituting each of the middle blocks, extending in the row direction, connected to the local DQ line pair of the sense amplifier, and on the middle block Extend the size of the paper mentioned above and apply to the Chinese National Standard (CNS) Λ4 present grid (210X297mm) --- Λ --- ^ ---- ^ Shiyi ------ order- (please read the back page first Matters needing attention and then fill out this page)-Printed by the Central Standard Falcon Bureau Beigong Consumer Cooperative of the Ministry of Economic Affairs 11 This paper scale is applicable to the China National Standard (CNS) Λ4 specifications (210Χ297 male seams) A7 B7 V. Invention description (6)

In the column direction, the block D Q line pair and the overall D Q line pair of the buffer are connected. The semiconductor billion system with the test circuit of the present invention has a memory cell array composed of plural blocks, and a billion cell in a block of η (η is a natural number of 2 or more) among the aforementioned plural blocks, Block writing means for writing n-bit data at the same time, and a register for holding the aforementioned n-bit data written in the aforementioned n-block in advance "The test circuit of the present invention is provided in the test mode, Simultaneously write the n-bit data held in the register in the memory cell array, and write / read through the test mode for reading the n-bit data of the memory cell Means, and the n-bit data held in the temporary memory and the test mode writing / reading means, compare the n-bit data read from the memory cell, and determine the semiconductor memory based on the comparison result "Yi-Yi-Yang", a 1-bit data comparison method that displays the result of the "Yi-Yu" and the 1-bit data output from the above-mentioned comparison method are output for testing to the outside of the semiconductor memoryCircuit. The test circuit of the present invention is provided with a latch means for holding the n-bit data showing the comparison result of the comparison means, and when the good result is bad, the n-bit data of the latch means is provided in order The switching means of the aforementioned test output circuit. The semiconductor memory system with the test circuit of the present invention is an η-bit type semiconductor memory device that simultaneously outputs and imports η-bit data. The aforementioned semiconductor memory system has η output pads used in the normal operation mode- Ί —! Λ ----------- Shimin-I-IIITI —-'· " 、 \ έ (Please read the precautions on the back before filling out this page) Employee of Loss of Standards Bureau, Ministry of Economic Affairs Printed by the consumer cooperative ^ A7 B7 5. Description of the invention (7) 'The test output circuit of the test circuit of the present invention is connected to one of the n output pads. The data transmission system of the present invention has a plurality of blocks that are extended in the column direction and each block is self-arranged with two switch arrays composed of a matrix of plural switches, and a row direction adjacent to the aforementioned two switch arrays One of the two ends is arranged to select the row decoder for the row of the two switch arrays, and the local DQ line arranged between the two switch arrays, extending in the row direction, and connected to each The plural switches of the switch array make the data lead to the data lines of the aforementioned local DQ lines. In addition, the data transmission system of the present invention has an extended arrangement in the row direction on the block, one end is connected to the entire DQ of the local DQ line, and two ends in the row direction adjacent to the complex block One of the two parts is arranged to select the column decoder of the row of the switch array of the complex block, and the other of the two ends adjacent to the row direction of the complex block is arranged to be connected to the overall DQ At the other end of the line, data input and output circuits that perform data input and output are executed. [Embodiment of the Invention] Hereinafter, the semiconductor memory of the present invention, the test circuit, and the data transmission system will be described in detail with reference to the drawings. Fig. 1 shows a wafer layout of the semiconductor memory of the first reference example of the present invention. Figure 2 shows in detail the layout in a district library of Figure 1. In this reference example, a 16-bit (X 1 6) semiconductor memory that can output 16-bit data at the same time will be explained. * The paper size is suitable for China National Standard (CNS) Λ4 present format ( 210X; W mm) ~ / ϋ-Λ ---, 丨 丨 Yiyi—I (please read the precautions on the back and then fill out this page) Order --- Printed by the Ministry of Economic Affairs Central Standardization Bureau Unemployment Consumer Cooperative 309657 ΑΊ Β7 V. Description of the invention (8) On one billion chip 10, 4 area libraries 11_0 ~ 1 1-3 are arranged. Each zone library 1 1 10 ~ 13 in the formation of 100 million grid array CAL, CAR, § billion grid array controller CA c 'and. Row decoding ^ RD, column decoder CD0, CD1' DQ buffer (called area Kuker I / O buffer) D 〇 and other peripheral circuits. The 100 million grid array in one district library is divided into 4 middle blocks BLa, BLb, BLc, BLd. In addition, each middle block system is divided into two small blocks CAL and CAR. Therefore, the memory cell array in one bank consists of 8 blocks. The line decoder RD is set in each of the four Ning special blocks BLa, BLb, B L c and B L d, and one is set for each. The row decoder RD selects any one of the two small blocks CAL and CAR according to the row address signal, and selects one row (character line 1 7) from the plural rows in the selected one block (character line 1 7) 0 column decoding CD0 and CD1 are installed in one zone library. The column decoders C D 〇, C D 1 select one or a plurality of columns of four hundred million grid arrays of four middle blocks BLa, BLb, BLc, and BLd according to the address signals of each column. That is, when the selected column selection line 15 ~ 〇, 1 5-1 is selected via the column decoders CD0, CD1, the column selection switch 16 connected to the specified column selection line 1 5-〇 '1 5-1 shows In the open state, the data of 1 data line 1 4 or the data of multiple data line pairs 1 4 pass through the sense amplifier SA and the data line pair (hereinafter referred to as this data line pair d Q line pair 'and data line pair 1 4 To distinguish), import DQ buffer DQ. The size of this paper is suitable for China National Standard Falcon (CNS) Λ4 present grid (210 × 297 male elk) I / Bu I.-11 -II-fcf I— I ΙΊ Shishi-. I (Please read the precautions on the back before filling in This page) Order --- A7 B7 Printed by the Consumer Labor Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (9) 1 1 In this reference example, one column decoder selects two columns to form 0 1 I this At this time, there are 2 column decoders, so each of the middle blocks BL a »1 1 1 BL b, BLC, BL d * 4-bit data input and output 0 ie * white 1 I please 1 I 1 block library, Exporting and importing 16-bit (2-byte) data 0 This 1 6 first-read 1 I 1-byte data is transferred to the repository through the data bus 1 3 1 1 1 Γ έ | of 1 0 One of 11 -3 9 and the data input / output range 1 2 〇 Note Γ Chapter 1 Sense amplifier SA and column selection switch 1 6 series Add 1 to the entry of the memory grid array 1 and each of the blocks BL a, BL b > BLCBL d is placed between the small blocks CALCAR of the 4-page 100 million grid array 0 1 row decoder RD and DQ The buffer DQ will record a 100 million grid array 1 1 CAL, CAR is placed in the center to face each other. Column decoding 1 1 device C D0 is configured with 4 middle blocks BL a BL b BLCB set the direction of 1 1 L d , That is, one of the two ends arranged in the column direction (the direction in which the data line pair or column selection line extends 1 I)-the side column decoder CD 0 is arranged in the other of the two ends 1 1 1 0 1 1 The grid array controller CAC is adjacent to the column decoder RD and is configured. 1 0 The grid array controller CAC performs the data input and output operations in the bank 1 1 Control 0 1 I after the DQ buffer DQ)-Normal While > is configured as Select the zone library 1 I zone library selector SEL. 1 1 Λ The data is guided to the DQ line pair 1 8 through the data line pair 1 4 The sense amplifier SA and the row selection 1 1 Switch 16, the DQ line pair 1 8 is in each block of the memory cell array BL a »BL b» BLC t BL d 1 1 »Arranged in the small CALCAR space of the 100 million grid array 〇1 1 This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) -IX-303657 A7 B7 Employee's Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs, Employee Cooperative V. Description of the invention (10) 1 | Therefore »The data is via the DQ line pair 1 8» Orthogonal to the 4 middle blocks BL a of the 1 billion array > BL b 1 BL c, BL d side 1 1 moves in the direction of the row direction C character line extending), via / -— V 1 I please 1 1 DQ buffer DQ > Area library output Reading 1 I Reading 1 (the data bus in all 4 districts 1 3 is located on the back of district 11 Γ | No. 1 — 0, 1 1 -1 and block 1 1 — 2 1 1 — 3 Note about the 100 million grid array. The block BL a > BL b • BL <? The item is in the 1 I direction, that is, extended in the row direction. The data bus 1 3 is presented as a library 1 1-fill in the% I 0 11-3 and the data input and output range 1 2 data input and output path page 1 1 of 0 1 1 In this reference example »It is a 16-bit (2-byte) data output 1 | The input can be configured at the same time 9 Order 1 Data input range 1 2 In the M simultaneous 16-bit (2 bit Element 1 1 I group) data input and output to form 16 I / O circuits (I / 0) 1 1 1, J The above-mentioned semiconductor memory data input and output operations are performed as follows: 1 I first pass the area Library selector SEL »Choose from 4 district libraries 1 1-1 I 0 11 — 3 — one library ， According to the 1 J address signal, the access operation is recorded in billions of squares. 〇1 1 Data output (reading) t 2 n bits' For example, 16 bits (112 bytes)) Via DQ line pair 1 8-from the selected 1 1 1 zone library output * 2 from the zone library output [metadata is directed to the data input and output range 1 2 1 and 1 1 through row 1 3 . From the data input into the standard 1 1 This paper scale is applicable to the Chinese National Standard Falcon (CNS) A4 specification (210X297 mm) -β-A7 B7 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of Invention (11) 1 | Circumstance 1 2 When outputting to the semiconductor memory (billion memory chip) 0 1 1 Data input (writing) »2 n bits (eg. L 3 bits (1 12 bytes)) Through data input / output range 1 2, data sink 1 I stream row 1 3 »Input to the 1 selected library ○ Input to 1 selected library Please read 2 " of 1 I library The data of the element is read through the DQ line L 8 and the back of the sense amplifier \ \ ISA 9 Attention to the memory cell of the memory cell array. 1 | * | V The above-mentioned semiconductor chip memory chip layout> has the following Disadvantages 〇 Matters 1 | The first information is filled in 1 I There are 4 districts 1 1 0 1 1 3 Material assembler assembly row 1 3 It is arranged through the central part of the 100 million chip 1 0, extended on page 1 1 Row direction (the direction in which the data line pair or row selection line extends) 0 At this time, half 1 1 The bit type of the conductor memory is proportional to the number of simultaneous input and output bits 1 | The number of data bus 1 3 increases Increase the range of the data bus 13 1 range 9 1 1 I For example > 16-bit (X 16) semiconductor memory time 1 1 I The data bus 1 3 needs to send 16 bits The wiring of the number of divided data is also the same as 1 1 ground 3 2 bit type (X 3 2) The data bus of the semiconductor memory unit 1 row 1 3 is the wiring that needs to transmit 3 2 bit data 0 1 1 2nd »1 in the block BL a BL d located in each zone library The IDQ line pair 1 8 9 is only arranged in the small block CAL% 1 of the mega-array. The CAR 9 is only extended in the direction (the direction in which the character line is extended) P this 1 1 when »Proportion in the white one block The number of bits output increases the number of DQ line pairs 1 1 1 8 t Increases the range of DQ line pairs 1 8 〇1 1 For example »In a middle block of y, 4 bits of raw material input and output 1 At 1 o'clock, the DQ wire pair 1 8 series requires wiring that can transmit 4 digits of data. 1 1 This paper standard is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 0X297mm) Employee consumption cooperation of the Central Standards Bureau of the Ministry of Economic Affairs. Du printed A7 B7 _ V. Description of the invention (12) Similarly, when 8-bit data is input and output in a middle block, the DQ line pair 18 series needs to be able to transmit 8-bit points The number of data lines 3 billion, in the interior area, one of the two end portions in the row direction, the row decoder arranged RD, arranged on the other DQ buffer DQ. At this time, the column decoder CD 0 is arranged in one of the two ends in the column direction in the bank, and the column decoder CD 1 is arranged in the other of the two ends. In addition, the grid array controller CAC is arranged across one of the two end portions in the row direction across the four middle blocks BLa, BLb, BLc, and BLd. Therefore, the column decoder R D and the grid array controller CAC are co-located

Since V is placed at one of the two ends in the row direction, the arrangement and wiring of the components constituting the row decoder RD and the grid array controller CAC are complicated. Fig. 3 shows a wafer layout of a semiconductor memory according to a second reference example of the present invention. Figure 4 shows in detail the layout in the one-zone library of Figure 3. In this reference example, a 32-bit (X 3 2) semiconductor memory device capable of simultaneously outputting 32-bit data will be explained. On a memory chip 10, 4 area libraries 1 1 are arranged. — 0〜 1 1 — 3. In each zone library 1 1 — 0 to 1 1 — 3, a scalar grid array CAL, CAR, a scalar grid array controller CAC, and row decoders RD, column decoders CDO, CD1, DQ buffer (called a zone library) are formed I / O buffer) DQ and other peripheral circuits. The memory grid array in one district library is divided into 4 middle blocks B La, BLb, BLc, BLd. In addition, each middle block is divided into 2 small areas. The paper scale is applicable to the Chinese National Standard Rate (CNS) Λ4 specification (210X 297 mm) ~-* / L-II—-I Λί ^^ 1 tli 0-I- —4 I--i--!--»! I Ge * T (Please read the precautions on the back before filling in this I) Coffee 657 A7 B7 V. Description of invention (u) Block CAL, CAR. Therefore, the 100 million grid array in a district library is composed of 8 blocks. The row decoder RD is set in each of the four middle blocks BLa, BLb 'BLc, BLd, and each one is set. * The row decoder RD selects any of the two small blocks CAL and CAR based on the row address signal One 'and one row (character line 1 7) is selected from the plural rows in the block of one selection ° Column decoder CD 〇 ~ CD 3 is set in a block of 4 ° Column decoder CD 0 ~ CD 3 is to select one or a plurality of columns of four hundred million grid arrays of four middle blocks BLa, BLb, BLc, and BLd according to the address signals of each column. That is, when the predetermined column selection lines 15-0, 15-1 are selected via the column decoders CD 0 ~ CD 3, the column selection switch 16 connected to the predetermined column selection lines 15-0 ~ 15-3 is turned on, The data of one data line pair 14 or the data of multiple data line pairs 14 is passed through the sense amplifier SA and the data line pair (hereinafter referred to as this data line pair is a DQ line pair, which is different from the data line pair 14), and imported into DQ Buffer DQ. Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs \ / In this reference example, one column decoder is selected to constitute two columns. At this time, because there are 4 column decoders, 8 bits of data are output from the middle blocks B La, BLb, BLc, BLd. That is, from one zone library, 32-bit (4-byte) data is output. This 32-byte data is passed through the data bus 13 to one of the district libraries 1 1-0 ~ 1 1-3, and the data is exported to and input from 12 rooms. The sense amplifier SA and the row selection switch 16 are in the memory cell array ~ / b ~ (please read the precautions on the back and then fill out this page) This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm ) A 7 B7 printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of the invention (14) In the middle blocks BLa, BLb, BLc and BLd, they are arranged between the small blocks CAL and CAR of the memory grid array. The row decoders R D and D Q buffers D Q place the memory cell arrays CAL and CAR in the center and configure them to face each other. The column decoder CDO is arranged in the direction of the four middle blocks BLa, BLb, BLc, B L_d, that is, it is arranged on one of the two ends of the column direction (the direction in which the data line pair or column selection line extends), The column decoder CDO is arranged at the other of the two ends. The grid array controller CAC is arranged adjacent to the column decoder Rd. The grid array controller CAC controls the data input and output in the library. After the DQ buffer DQ, generally speaking, it is configured to select the bank selector SEL of the bank. The data is directed to DQ line pair 18 through data line pair 14, sense amplifier SA and column selection switch 16. The DQ line pair 18 is located in the middle blocks BLa, BLb, BLc, and BLd of the memory grid array, and is arranged between the small blocks CAL and CAR of the memory grid array. Therefore, the data is shifted to the row direction (the direction in which the character line extends) through the DQ line pair 18, which is orthogonal to the direction of the four middle blocks BLa, BLb, BLc, and BLd of the megapixel array. , Via DQ buffer DQ, output from the zone library. The data bus 13 in the 4 district libraries is arranged between the district library 1 1-0, 11-1 and the block 11-2, 11-3, and the blocks BLa, BLb, BLc in the billion grid array , The square paper size configured by BLd is applicable to the Chinese National Standard (CNS) A4 (2 丨 0> < 297mm) -η- · 7 pack n order (please read the precautions on the back before filling this page ) A7 Ministry of Economic Affairs Central Standards Bureau employee elimination cooperation ^ B7 V. Description of the invention (15) 1 has been extended in the direction of the row 〇 data bus 1 3 is the district library 1 1 — 0 1 1 0 1 1 3 and Data input / output range 1 2 Data input / output path 1 1 | In this reference example »Let the 32-bit semiconductor memory be > 刖 提 的 / -— S Please read 1 1 I Therefore y data Bus 1 3 is based on 32-bit (4-byte) data input and read back 1 \ I access can be formed simultaneously by the 1 of 9 I Γ meaning I data input range 1 2 middle »same Perform 3 2 bit (4 bit items 1 I group) data input / output »Form 3 2 input / output circuits (I / 0) and fill in this — ^ 4 Ά 0 page 1 IV, the above semiconductor ruZ · memory The data input / output action of the volume is as follows: 1 I for 0 1 I First, choose from 4 district libraries 1 1-1 order 1 0 1 1-3 through district library selector SEL-choose one of the district banks 0 In a bank, according to the 1 1 address signal, the access operation is recorded in billions of grids. When the data is output (read)> 2 η bits (for example, ί 2! Bit [1 1 4 bytes )) The data through the DQ line pair 1 8 the selected 1 1. Γ block output 0 0 block output 2 η bit data is through the data bus 1 I row 1 3 »leads to the data input and output range 1 2 1 and white data output input range 1 I range 1 2 output to semiconductor FU2 . Memory limb (100 million chip) External 0 1 1 1 When data is input (written) 1 2 η bit (for example 2 2! Bit < 1 1 4 byte)) The data is output through the data Input range 1 2 Data sink 1 1 Stream bank 1 3 I Input to the selected 1 bank 0 2 N-bit data input to the selected 1 1 1 bank is via DQ line] ε 丨 和 感Test Amplifier 1 1 SA »Memory cell in memory cell array 〇1 1 The scale of this paper is applicable to China National Standard (CNS) A4 specification (210X 297 public green)

It Printed by the Ministry of Economy, Central Falcon Bureau Employee Association 3_57 Λ7 B7 V. Description of the invention (16) The above-mentioned semiconductor memory chip layout has the semiconductor memory of the first reference example shown in FIGS. 2 and 3. The same disadvantages of chip layout. That is, first, the bit type of semiconductor memory, which is proportional to the number of simultaneous input and output bits, the number of data buses 13 increases, increasing the range of data buses 13. The second 2 'ratio is the number of bits output by the blocks in each zone library, increasing the number of DQ line pairs 18 and increasing the range of DQ line pairs 18. Third, the column decoder RD and the grid array controller CAC are arranged together at one of the two ends in the row direction, so the arrangement and wiring of elements constituting the row decoder RD and the grid array controller CAC are complicated. In the reference example, two column decoders are arranged at the two ends of each column direction, so the arrangement and wiring of the elements constituting the column decoders CD 0 to CD 3 are complicated. ^^ FIG. 5 is a schematic diagram showing the position of the semiconductor memory bank and the position of the data bus in the first reference example of FIG. 1 and FIG. 2. The range on the billion chip 10 is mainly occupied by the library 11-0 ~ 11-3 and the data input / output range (I / O) 12. The data input / output range 12 is one of the four edges adjacent to the billion chip 10, that is, one of the two edges adjacent to the column direction. The memory cell array in the bank is composed of a plurality of small blocks arranged in the column direction, and a middle block is formed by two small blocks. Within each small block, it is arranged in a character line extending in the row direction, and a data line and a column selection line extending in the column direction (the direction in which the small blocks are arranged). The D Q line pair 18 is tied between two small blocks, extending in the row direction. 2 I: 1 ---! | 4—-.-Nr -—- II-n (Please read the precautions on the back before filling out this page) Xun --- This paper scale is applicable to China National Standard (CNS) Λ4 Cash (210X2 * ^ mm)-Called-Ministry of Economic Affairs Central Standards Bureau employee consumption cooperation Du Yin t A7 B7 V. Description of invention (π) DQ line pairs between small blocks 1 8 series only exists to transmit 4 bits The number of data. / Material bus 13 is arranged in the zone library 1 1-0, 1 1-1 and zone library 1 1-2, 1 1-3, extended in the column direction. Data bus 13 is a system in which 16-bit (2-byte) data can be transmitted and constituted. FIG. 6 is a modification of the chip layout of the semiconductor memory cell of the first reference example in FIGS. 1 and 2. FIG. 7 shows in detail the layout of the semiconductor memory chip of FIG. 6.

The chip layout of Xy7 is compared with the chip layout of Figures 1 and 2, and differs in the following points. First, make one district library (main district library) composed of two sub-blocks. That is, the main zone library 1 1 — 0 is composed of the secondary zone library 1 1 — 0 — # 0, 1 1 — 0_ # 1, the main zone library 1 1 — 1 is composed of the secondary zone library 1 1 -1 — # 0 , 11 — 1 — # 1, the main zone library 11 — 2 is from the secondary zone library 1 1 — 2 — # 0, 1 1 2- # 1, the main zone library 1 1 — 3 is from the secondary zone Library 1 1 — 3 — # 0, 1 1 — 3- # 1. Sub-zone library 11 — 0 — # 0, 11 — 0-# 1 are selected through the zone library selection circuit at the same time. Sub-zone library 1 1 — 0-# 0, 1 1 — 0-# 1 When selected, the remaining zone library is not selected. Similarly, for example, when the sub-zone library 1 1 — 1 one # 0 and 1 1_1 one # 1 are selected, the remaining zone libraries are not selected. In addition, through 4 sub-district libraries 1 1 — 〇 — # 0 '1 1 — 1 A paper standard is applicable to the Chinese National Standard Falcon (CNS) A4 specification (210X 297 mm) ~ ... »1 — ^ ϋ ft W— I — ^ ilk (Please read the precautions on the back before filling out this page) Order --- _β57 A7 Β7 Printed by the Central Bureau of Standards of the Ministry of Economic Affairs, only the Consumers F Cooperative. V. Description of the invention ------ ~ | # 0 > 1 1 one 2 — # 0) 1 1 — 3 one # 0 constitutes a group »Jing 1 I consists of 4 sub-zones 1 1 one 0 — # 1 I 1 1 — 1 — # 1 1 1 — 1 1 2 — # 1 > 1 1 one 3 one # 1 constitutes a group 0 1 1 that is y in the secondary library 1 1 — 0 — # 0 1 1 1 — 1 — # 0 »1 ---- V Please 1 1 1 — 2 — # 0 > 1 1 — 3 — # 0 Simultaneously perform 8-bit reading on the back 1 side Γ 1 data input and output ◆ in the secondary area Library 1 1 — 0 one # 1 »1 1 — 1 of Note 1 # 1 > 1 1 one 2 — # 1» 1 1 — 3 one # 1 Simultaneously entering items in the group 1 1 line of 8-bit data Lose Fill in and out again and then fill in this 1 Ί. 2nd page of 8-bit (1 byte) in a sub-zone library, Sw- 1 1 Data input and output location constitute 〇 1 1 Sub-zone library layout system and diagram 1 and Figure 2 when comparing the library layout 1 1 The decoder CD is that only one is the difference. Because in this example, 1 is ordered in a sub-region library for 8-bit data output »Column decoding! 1 CD exists-only 0, but the column decoder CD is the same as the semiconductor memory of Figure 1 and 1 1 I Figure 2 * Select 2 columns in each middle area of the memory cell array 1 I Block BL a »BL b» BLC »BL d middle> Execution 2 1 I bit data output I / O volume 1 I Memory cell array CAL, CAR column decoder in the secondary library 1 IRDDQ line pair 1 8 The layout of the DQ and DQ buffer is the same as that of Figures 1 and 1 1 Figure 2 The layout in the body area library is the same. 1 The third data input / output circuit (I / 0) 1 2 a 1 2 b is 1 1 in the center of the billion chip 1 0. The length is increased in the row direction. Configuration 9 1 1 The data bus 1 3 a is allocated in the sub-zone library 1 1 -0 one- # 0 1 1 1 1 1 — # 0 1 1 — 2 — # 0 9 1 1 — 3 — # 0 ______ ^ 1 1 The scale of this paper is applicable to the Chinese National Standard (CNS) Λ4 is now available (210X297 public) f-II / Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A7 ______B7 V. Invention description (19) Placed in the data output Into both sides of the circuit 1 2 a, the data bus 1 3 b is in the sub-zone library 11-0 — # 1, 11 — 1 — # 1, 11 — 2 — # 1 '11 — 3-# 1 , Configured on both sides of the data input and output circuit 1 2 b. The data buses 13a and 13b are located between the sub-zones, extend in the row direction, and are connected to the data input / output circuits 12a and 12b in the central data section of the memory chip 10. The data bus 13a, 13b can be configured to transmit 8-bit data. In such a semiconductor memory of the chip layout, for example, when the sub-region library 11 — 〇- # 〇, 1 1 — 〇- # 1 is selected , In the sub-region library 1 ΙΟ _ # 0 and the data input and output circuit 1 2 a, through the data bus 1 3 a '8-bit data reception, in the sub-region library 1 1 — 〇_ # 1 and data output Into the circuit 1 2 b, through the data bus 1 3 b 'to receive and receive 8-bit data. ^ 3 8 shows a modification of the layout of the semiconductor memory chip in the first reference example shown in FIGS. 1 and 2. FIG. 9 shows the chip layout of the semiconductor memory of FIG. 8 in detail. This chip layout is different from the chip layout of FIGS. 1 and 2 in the following points. The first 1 'order that a district library (main district library) is composed of two sub-blocks. That is, the main zone library 1 1-0 is composed of the sub zone library 1 1 — 0 — # 0, 1 1-0 — # 1, and the main zone library 1 1_1 is from the sub zone library 1 1 — 1 — # 0, The main area library 11-2 is composed of the auxiliary area library 1 1 — 2 — # 0,1 1-2- # 1, the paper size of the main area is applicable to China National Standard (CNS) A4 specifications (210X297 PC) I! --- ί-IV— --- ^-* Cloth II. I I-…! I.-— ^ 1 (please read the precautions on the back before filling in this page) -2 ^ ·-309657 a? B7 The Ministry of Economic Affairs Central Bureau of Standardization and Employee's Cooperation in the Disposal of Funds for Printing V. Description of Inventions (20) Library 1 1 — 3 is composed of the sub-zone library 1 1 one 3 — # 0,1 1 — 3- # 1. The sub-zone library 1 1 — 〇 — # 〇 ’1 i-o-ti is selected through the zone library selection circuit at the same time. Sub-zone library 1 1 — 〇 — # 〇, 1 1 — 0 — # 1 When selected, the remaining zone library is not selected. Similarly, for example, when the sub-zone library 1 1 — 1 — # 〇 ′ 1 i — l— # 1 is selected, the remaining zone library is not selected. In addition, through four sub-zone libraries 11 one, 11 one 1 one # 0, 11-2 — # 0 '11 — 3 ~ constitute a group, through four sub-zone libraries 11 one 0 — # 1' # 1, 11 1 2 — # 1, 11-3 — # 1 form a group. In other words, 8-bit data input and output are simultaneously performed in the sub-zone library 11 1 0- # 〇, 11 1 1- # 0, 1 1 — 2 — # 0, 1 1-3 — # ◦ In the sub-zone library 1 1 — 0 — # 1, 1 1 — 1 — # 1, 11-2 — # 1, 11_3 ~ # 1, 8-bit data input and output are performed simultaneously. Second, in a sub-zone library, 8-bit (1-byte) data input and output are constructed. When the layout of the secondary bank is compared with the layout of the bank of Figs. 1 and 2, the column decoder CD has only one difference. This is because, in this example, there is only one column decoder CD to output 8-bit data in a sub-region library. However, the column decoder CD is the same as the semiconductor memory of FIG. 1 and FIG. 2, select two columns, and execute in the blocks BLa, BLb, BLc, and BLd of the memory grid (please read first The weeping matters on the back are to be filled out in the form of \\ 〇. The size of the paper is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297mm) (21) The input and output of 2-bit data. The layout of the memory cell array CAL, CAR, column decoder RD, DQ line pair 18 and DQ buffer DQ in the sub-zone library is the same as the semiconductor memory of FIGS. 1 and 2. The layout in the body area library is the same. Third, the data bus 1 3 a is in the auxiliary area library 1 1-0-〇, 11- 1- # 〇, 11-2- # 0, 11-3- # 〇 In the group, they are arranged to extend in the column direction, and the data bus 1 3 b is connected to the I! Zone I library 11 — 〇 — # 1, 11 — 1 — # 1 '11_2 — # 1' 11 — 3 — # 1 之In the group, it is arranged to extend in the column direction. That is, the data bus 13a is located between the sub-zones, and the data output from the end arranged in the column direction is input to the circuit 1 2 a extends in the column direction, the data bus 1 3 b is located in the secondary area, and the data input and output circuit 1 2 b is extended in the column direction from the end arranged in the column direction. Also, the data bus 1 3 a, 1 3 b is composed of data that can be transmitted with 8 bits each. In such a semiconductor memory of the chip layout, for example, when selecting the sub-region library 1 1 — 0 — # 〇, 1 1 — 〇- # 1, the sub District library 1 Ι ο — # 0 and the data wheel access circuit i 2 a, through the data bus 1 3 a, 8-bit data is received and received from the subsidiary district library 1 1 — 〇— # 1 and the data input and output circuit Between 1 and 2 b, 8-bit data is received and received through the data bus 1 3 b. • 1 〇 shows the chip layout of the semiconductor memory of the first embodiment of the present invention. FIG. 1 1 shows in detail FIG. 1 0 The layout of the paper in one of the districts is in the paper size suitable for the financial home (CNS) Λ4 present grid (2U) 'X Gongkang)' — '-21} .- (please read the precautions on the back before filling in this page) " Subscription A7 B7 309657 V. Description of the invention (22) In this embodiment, for the i 6-bit type that can simultaneously output 16-bit data X 1 6) 'of the semiconductor memory will be described. Four bank libraries 1 1 to 1 1 to 3 are arranged on one billion wafer 10. Each zone library 1 1 10 ~ 1 work-3 in the form of a memory grid array CAL, CAR, memory grid array controller CAC, and row decoder RD, column decoder CD〇, CD1, DQ buffer (called area The input / output buffer of the library) peripheral circuits such as DQ. The memory cell array in one district library is divided into 4 middle blocks B L a ′ BLb, BLc, BLd. Also, each middle block is divided into two small blocks, CAL and CAR. Therefore, the memory cell array in the 1 bank is composed of 8 blocks. The row decoder RD is provided in each of the four middle blocks BLa'BLb'BLc, BLd, and one each. The row decoder RD selects any one of the two small blocks CAL and CAR according to the row address signal, and selects one row from the plural rows in the selected one block (character line 17) The selection of the small blocks of the grid array is performed on either of the two word lines 19a and 19b by applying a high voltage. For example, when a high voltage is applied to the word line 19 a, the switch 20 a is turned on, and the small block CAL is selected. At this time, due to the low voltage applied to the word line 19b, the switch 20b is turned off, and the small block CAR is not selected. The column decoders CD0 and CD1 are installed in one zone library. The column decoders CD 0 and CD 1 are based on the address signals of each column, and select one of the paper standards for the Chinese National Standard (CNS) Λ4 specification (210X2W mm) _-n, / 1 —ί--·- -J * κ 1-«: —---__ I m T -J Ge-a (please read the precautions on the back before filling in this page) Ministry of Economic Affairs Bian Zhuren Zheng Gong Consumer Cooperative Indica A7 B7 Ministry of Economic Affairs Printed by the Central Consumer Service Cooperative Staff V. Description of invention (23) 1 or the plural 4 mid-blocks BL a, BL b, BLC * BL d 1 1 1 For example, through the column decoder CD 1 »select xsg The two column selection switches 1 6 connected to the column selection lines 1 5 and 1 1 1 in the column selection line 1 5 are turned on, and the 1 1 state is read first. Then, the two data lines connected to the two column selection switches 16 are backed by 1 1 1 to 14. The 2-bit data is selected by the sense amplifier SA and the column selection fjm. Output to data line pair (f below makes this data line symmetrical. Item 1 I and then 1 DQ line pair, which is different from data line pair 1 4) 18 a 〇 fill in this frame I in this example »1 row decoding The device selects 2 columns to form a 1 1 〇 At this time, due to the presence of 2 column decoders, the 9 blocks in each block BL a 9 B 1 [L b, BL c BL d »output 4-bit data 〇Is a white 1 I area library, input and output 16-bit (2-byte) data 〇1 Order 1 sense amplifier SA and row selection switch 16 are in the 1 1 I middle area of the memory cell array Block BL a 'BL b BL (: BL d is arranged in a small block CALCAR of 1 1 billion grid array. 1 1 The decoder RD and the grid array controller CAC enable the memory grid array f CAL, CAR to be placed opposite each other in the center. That is, the row 1 1 The decoder RD is configured with 4 middle blocks BL a, BL b 1 The direction of IBL c * BL d is arranged in the row direction (the direction of the word line 1 7 9 1 I 1 9 a, 19 b extension). One of the two sides 1 1 The array controller CAC is arranged in The other side of the two ends 〇1 1 grid array controller CAC is to control the data input and output actions 1 1 in the library. 1 1 column decoder CD 0 t CD 1 is configured with 4 Middle block 1 1 This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) f ~ 2b-A7 B7 309657 V. Description of the invention (24) The direction of BLa, BLb, BLc, BLd, which is configured in One of the two ends of the column direction (the direction in which the data line pair or column selection line extends) "(Please read the precautions on the back first (Fill in this page) The two column decoders CD 0 and CD 1 divide the columns of the C D 0 and C D 1 in the billion-element array into two rows and arrange them in the row direction. The DQ buffer DQ is matched to the other side of the two ends in the column direction (the direction in which the data line pair or the column selection line extends), that is, CD 1 and the DQ buffer DQ are ordered in billion grid array CAL, CAR Holding it in the center, they are arranged to face each other. After the DQ buffer DQ, generally speaking, the bank selector SEL configured to select the bank »The data is guided to the local DQ line pair 18a after the data line pair 14, the sense amplifier SA and the column selection switch 16» The local DQ line pair 18a is in the middle blocks BLa, BLb, BLc, BLd of the billion grid array, and is arranged in the small blocks CAL, CAR of the billion grid array. v / Therefore, the local DQ line pair 18 a extends in the row direction (the direction in which the word line extends). In addition, the data line pair (the following makes this data line symmetrical overall DQ line pair, which is different from the data line pair 1 4) 1 8 b is placed on the small block CAL, CAR of the memory grid array, and is arranged in the direction of the extended column * overall DQ line One end of the pair 18b is connected to the local DQ line pair 18a via the switch 21, and the other end is connected to the DQ buffer DQ. The opening and closing of the switch 2 1 is controlled by the control signal C Ο N. The paper size is applicable to the Chinese National Standard (CNS) Λ4 specification (210X2 ^ 7 Gongqing) A7 B7 309657 5. The invention description (25) system. (Please read the precautions on the back before filling in this page) The data bus 13 in 4 district libraries is located in the district library 11 — 0 ′ 1 1-1 and block 1 1 1-2, 1 1-3 , Extending in the column direction. The data bus 13 is the data input / output path between the data base 1 1 — 0 ~ 1 1 — 3 and the data input / output range 12. In this embodiment, the premise is that a 16-bit semiconductor memory is used. The 'data bus 13 is a 16-bit (2-byte) data input and output that can be constructed simultaneously. The data input / output range 12 is arranged on one side of the two ends of the memory chip 10 in the traveling direction. In the data input range 1 2, for 16-bit (2-byte) data input and output at the same time, 16 input / output circuits (I / 0) are formed. The data input and output operations of the semiconductor memory described above are performed as follows. First, select one zone library from four zone libraries 1 1 to 10 1 to 3 via the zone library selector SEL. In the selected one bank, the memory cell is accessed according to the @address signal. When outputting (reading) the printed disaster data of the Employee Consumer Cooperative of the Central Sample Agency of the Ministry of Economic Affairs, the 2n-bit (eg 16-bit (2-byte)) data passes through the local DQ line pair 18 a and the overall DQ Line pair 18b is output from the selected bank. The t 2 n-bit data output from the library is guided to the data output area 12 through the data bus 13 and output from the data input / output range 12 to the outside of the semiconductor memory (memory chip). When inputting (writing) data, 2 " bits (for example, 16 bits (this · paper standard applies to China National Standard (CNS) Λ4 present grid (210Χ 297mm)-^^ 9657 A7 B7 Ministry of Economic Affairs Printed by Zhongshang Standard Bureau Beigongxiao #Cooperative V. Description of the invention (26 2 bytes)) The data is input into the range 1 2 through the data input and output data bus 1 3 > input to the selected 1 library. The data of 2 " bits input to the selected one bank is through the local DQ line 1 3 a, the overall DQ line pair 1 8 and the sense amplifier SA, and the memory cell of 100 million grid is recorded. The chip layout of the semiconductor memory has the following features. 0 1st-The grid array controller CAC and the column decoder RD make the memory grid array CAL * CAR placed in the center, opposite to each other in the row direction. The decoders C DO, CD 1 and DQ buffer DQ make the memory cell array CAL • CAR centered on each other To the end of the column direction is configured. That is, the grid array controller CAC, row decoder RD column decoder CD0, CD 1 and DQ buffer DQ are connected to the memory grid array CAL, CAR Configuration. Therefore, it is easy to configure the components or wiring of the grid array controller CAC, row decoder RD, column decoder C D0 CD 1 and DQ buffer DQ. 2nd In the library, set the extension in the row direction The local DQ line pair 1 8 a, and the overall DQ line pair set to extend in the column direction 1 £ t), the data is formed from the input and output ground of the column direction end of the bank 0. That is, let the DQ buffer DQ » It can be set at the end in the column direction of the bank, so that the first feature described above can be achieved. Also, as in the conventional embodiment, the number of bits that are input / output in 1 middle block of the memory cell array is 4 bit time • Allocation in small block CA L > This paper scale is applicable to China ’s National Standard Rate (CNS) Λ4 specification (21 ox297 mm) 1 8 a, it is set on the CD 0 side of the column decoder 2 bits, and only 2 bit points on the CD 1 side of the column decoder. This series of decoders CDO, CD 1 is adjacent to the memory cell array and is arranged in the row direction. Also, the output of the data is performed at the end of the column direction of the library. Therefore, the local DQ line pair 18 a makes the necessary range change Hour 'Specifically, in order to configure the DQ line pair, only one and a half of the reference examples in FIGS. 1 and 2 are required. In addition, the overall D Q line 18 b is the number of 16-bit data transfers required in the zone 1 library when 4-bit data is input and output in a middle block. However, the overall DQ line pair 18b is configured in the CAL grid array CAL, so there is no need to newly configure the range of the overall DQ line pair 18 b for CAR. Third, the data bus 13 is located in the district library 1 1-0, 1 1-2 and the district library 11-1, 11-3, extended in the row direction. This is because the DQ buffer DQ in the bank is arranged at one of the two ends in the column direction. As a result, the design of the configuration of the bank and the data input and output circuits can reduce the wiring of the data bus 13 and reduce the range of the data bus 13 that the memory chip 10 occupies. xyi 1 2 shows an example of the configuration of the switches 16 and 21 which constitute the semiconductor memory of FIGS. 10 and 11. The column selection switch 16 is composed of N-channel type MOS transistors N1'N2. The gates of MOS transistors N1'N2 are connected to this paper. The Chinese standard (CNS) Λ4 specification (210 X 297 mm) is applicable. L ^ n In 1-ti I---T ... . -I— ^^ 1 · I 1 In Tlv (please read the notes on the back before filling in this page) V. Description of the invention (statement) A7 B7 line selection line printed by the Consumer Cooperative of the China National Standard Falcon Bureau 1 5 * Source • One side of the drain range 9 is connected to the sense amplifier SA > Source • The other side of the drain range »is connected to the local DQ line pair DQ 〇V 'Figure 1 3 is shown in Figure 1 0 And the configuration example 0 of the column decoder of the semiconductor memory of FIG. 1 In this example »the column decoder CD 0 is used to describe 0 column address signal A 0 A 1 0 is input to the column decoder CD 0 0 column address signal A 0 «" • Ο- / A 7 is a pre-decoder (NAND circuit) 2 3 — 1 > 2 3 — 2 2 3 — N of any — the output signal of the pre-decoder The bit is% L (low) ¥ > The output signal level of all remaining predecoders is% Η (high). The column address signal A 8 A 1 0 makes the decoder 2 4 — 1 > 2 4 1 2 2 4 — any of Μ—the output level of the decoder is% L (low) 0 I makes the output signal level of all remaining decoders be Η (high) 〇 predecoder 2 3 — 1, 2 3 — 2 '2 3 — Ν The output signal is input to the block 2 5 — 1 t 2 5 — 2 »2 5 — Ν Decoder 2 4 — 1' 2 4 — 2 2 4 one The output signal of N is input to block 2 5 — 1 »2 5 — 2 > 2 5 — Ν 〇Ν 0 R circuit 2 6 0 j 2 6 — 1 2 6 — 7 middle > input predecoder 2 3 — 1, 2 3-2 '2 3 — N output signal and decoder 2 4 — 1 2 4 — 2 > 2 4 — M output signal 〇 For example 1 predecoder 2 3-1 output signal level For L 9 decoder 2 4-1 of When the level of the output signal is L 0 t only the level of the output signal of the Ν 0 R circuit 2 6 — 0 is present, and all remaining II ........ I .....-*-*- —II -'- I —.1--II ^ 1 (Please read the precautions on the back before filling in this page) The paper size is far from the Chinese National Standard (CNS) Λ4 specification (210X2W celebration) 309657 Α7 Β7 5. Description of the invention (29) The output signal level of the NOR circuit is * L. NOR circuit 26 — 0, 26 — 1, output of ~ 26-7 (please read the precautions on the back before filling in this page) The signal is during the period when the level of the control signal L is 〃, through the conversion room 27 — 0, 27-1, ~ 27-7, input to the latch circuit 28-0, 28-1, ~ 28_7. The output signal of the latch circuit 28-0, 28-1, ~ 28-7 is during the period of the level of the control signal T, via the AND gate 29-0, 29-1, ~ 29-7, for column selection Line 15. For example, when the output signal level of the predecoder 23-1 is, and the output signal level of the decoder 2 4-1 is iLf, only the level of one of the column selection lines 15 is CSL0,! ! ', The level of all remaining column selection lines is t L 〃. The column selection open relationship connected to the column selection line of * H ^ level is turned on. BW is a block write signal. The level of the block write signal BW is in the normal mode, and it appears as "H" in the block write mode. That is, in the block writing mode, the level of the output signals of all decoders 24-1, 24-2, 2-4-M does not need to be addressed according to the column address signal A 8 ~ employees of the Central Standard Falconry Bureau of the Ministry of Economic Affairs # Cooperative society printed A 1 0 and presented, L '. Therefore, for example, when the level of the output signal of the predecoder 23-1 is t L #, all the levels of the eight column selection lines C S L 〇 ~ CSL 7 controlled by the block 25-1 are 'H'. The column selection open relationship connecting the column selection lines of the level is turned on. Thus, data can be written in block units. V // Figure 1 4 shows the blocks of the semiconductor memory of Figure 1 and Figure 1 1. The paper size is applicable to the Chinese National Standard (CNS) Λ4 specification (2 丨 0 X 297 mm)-A7 B7 Central Standard of the Ministry of Economic Affairs Printed by Falcon Staff Consumer Cooperative V. Description of the invention (30 1 I composition of the selection circuit S Ε L) 1 The block selection circuit SEL is connected to the DQ hopper DQ and the 1 1 data bus 13 through the transfer gate Τ 0 1 t T 0 2 »T 1 1 9 / -— V 1 I please 1 IT 1 2, Τ 2 1, Τ 2 2, Τ 3 1 T 3 2 to make up 0 turn to read 1 I read 1 J switch Τ0 1 丁 0 2, Τ1 1 9 Τ1 2 »T2 1, T2 2 back 1 1 of 1) T 3 1 Τ 3 2 is composed of N channel type MO S transistor and P channel intention 1 type M It is composed of OS transistors. Item 1 is filled with ~ 1 again in block 1 1-0, and the block selection circuit S Ε L is input with writing Έ 1 block selection signal BNK 0, / BNK 0, which constitutes the switching gate 'W, 1 T 0 1, Input 1 1 block selection signal B Ν Κ 0 to the gate of the N channel type M 0 S transistor of T 0 2 to form the input of the gate of the P 1 1 channel type M 0 S transistor of the switching gate T 0 1 TO 2 Block selection signal / order 1 B Ν Κ 0 〇1 I is also in block 1 1-1 in block selection circuit SEL 1 1 I »Input block selection signal Β Ν Κ 1 / BNK 1 〇 in the area In block 1 1 1 4-2, input block selection information Γ B Ν Κ 2 1 / Β Ν Κ 2 in block selection circuit S Ε L, in block selection 1 1 in block 1 1-3 Circuit S Ε L * Input block selection signal BNK 3 / BNK 3 1 1 | Block selection signal Β Ν Κ 〇Β Ν K 3 is any-the level of which is 1 1 * Η Continue, All the remaining levels are% L ψ 〇1 1 I For example, when the block 1 1-0 is selected, the level of the block selection signal BNK 0 1 1 1 is H. Although, the block selection signal B NK 1 * B Ν K 2 The level of 1 1 B Ν Κ 3 is' L #. At this time, only the DQ of block 1 1-〇 is 1 1 This paper size is applicable to the Chinese National Standard (CNS) Λ4 specification (210X 297 mm) -33 Α7 Β7 309657 V. Description of invention (31) The punch DQ is connected Data bus 1 3 'Block 1 1 1 1' 1 1-2, 11-3 DQ buffer DQ is 13 cut from the data bus (please read the precautions on the back before filling in this page) The data is received only in blocks 1 1-10 and the data is output to and from the circuit 12. 15 shows the structure of the data input / output circuit 12 of the semiconductor memory shown in FIGS. 10 and 11. In this example, a data input / output circuit that performs 1-bit data output is described. That is, for example, in a 16-bit type (X 16) semiconductor memory, the data input / output circuit in this example 16 submissions are required. This data input / output circuit is mainly composed of a data sense amplifier DBSA MP, a data bus write buffer DBWBF, an output latch circuit 30, an output circuit 31, and an output buffer 32. The data writing buffer D BWB F is used when writing data. The control signal NW is input to the synchronous inverter cI1, and the control signal is printed by the Consumer Labor Cooperative of the Central Standards Bureau of the Ministry of Economy. ^ WX is input to the synchronous inverter CI 2, CI 5. During data writing in the normal operation mode, the level of the control signal NW is present, and the synchronous inverter C I 1 is activated. In addition, the level of the control signal w X is input data (writing data) RWDm (m is 0, 1... Or 5) during the period of ^ Η ^ through the synchronous inverter CI 1, latch The lock circuit LA and the synchronous inverters CI 2 and CI 5 lead to the data bus 13. This data is entered into the selection area library via the data bus 1 3. The control signal BW is input to the synchronous inverter c I 3, and the block is written in the paper standard paper (CNS) 2 丨 () χ 297 Gongqing) --- Printed by the Staff Consumer Cooperative of the Central Standardization Bureau of the Ministry of Economic Affairs ^ A7 B7 V. Description of invention (32) In the data writing mode, the level of the control signal BW is presented, and the synchronous inverter c I 3 is activated. In addition, the level of the control signal WX is during the period of H ", and the color temporary data CRm (m is 0, 1, ..., or 5) is passed through the synchronous inverter CI 3, the latch circuit LA, and the synchronization Inverter CI 2, CI 5 'leads to data bus 1 3. This data is entered into the selection area via the data bus 13. The color temporary data C Rm is supplied from the color register. In the color register, in the block writing mode, data patterns are simultaneously written in a plurality of memory cells. The color register is generally equipped with a portrait memory, so that the data of the predetermined pattern can be recorded in a number of hundreds of millions of grids and used for writing at the same time. The content of the color register (data case) is changed by changing the data mode of the color register. The control signal TW is input to the synchronous inverter C I 4. During the writing of the test mode data, the level of the control signal TW is presented! ·! ', While activating the synchronous inverter C I 4. In addition, the level of the control signal WX is in the period of 'Η #, the output signal of the exclusive OR circuit EX is guided to the synchronous inverter CI 4, the latch circuit LA and the synchronous inverters CI 2, CI 5 to The data bus 1 3. This data is input into the selection area library through the data bus 13. In the exclusive OR circuit EX, input color temporary data / CRm and data R W D 〇. That is, in this example, the data pattern used in the test mode can be constructed from the color register. The test circuit for the semiconductor memory used in this embodiment will be described later. The standard of this paper is the general Chinese National Standard (CNS) Λ4 specification (210X297mm) ------------ ^ IIi-- (please read the precautions on the back before filling this page)

* tT-A7 B7 Ministry of Economics and Trademark Hayabusa Consumers Co., Ltd. Printed V. Description of Invention (33) ^ The data bus sense amplifier DBS AMP is used when reading data. The data bus sense amplifier D B S AMP is an N-channel type operational amplifier S AN and a P-channel type operational amplifier SAp. The data bus sense amplifier D B S AMP is activated when the level of the active signal RENBL is present, and is inactive when the level of the active signal RENBL is present. When the level of the active signal RENBL is L, the synchronous inverter C I 6 is inactive, and the data bus sense amplifier SAMP is cut off from the read and write data line RWD. Reading and writing data line RWD line presents the path of output data (reading data), while presenting the path of input data (writing data), precharged transistor PR is output data RWDm (m system 〇, engineering ... or 5) It is output to the RWD line of the read and write data, and the level of the RWD line of the read and write data is shown as η for charging. When the output data rWd m is output from the data bus sense amplifier D AMP, the output data RWDm is output through the output lock circuit 3 〇 and input to the output circuit 3 1 ^ The output W lock circuit 3 0 is output through the reset signal / r 5 Reset. The synchronization signal QST is input to the output circuit 31. That is, the output data (which is 0 1 ... or 5) is output from the output circuit 31 in synchronization with the synchronization signal q s T, and is output to the outside of the memory chip through the output buffer 32. .——_ ^ Road 3 3 and exclusive NOR circuit 3 4 are in the test mode ^ Zhang scale 2 ⑴X condition public celebration)-(please read the precautions on the back before filling this page) •-I 1 ϊ II-»1. .74

* ST A7 B7 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs

V. Description of the invention (34) 1 Type I is a part of the test circuit used 〇1 I Ν AND circuit 3 3 in »Input and output latch Λ / 1> Output of the lock circuit 3 0 1 1 | Data and test signal e D 丁〇In the test mode, the test signal 1 I asks 1 R e DT level is Η • Exclusive 0 R circuit 3 4 in 9 first read 1 I read 1 1 input N AND circuit 3 3 output signal and color temporary Information / 1 fCR on the back of I I m 0 exclusive 0 R circuit 3 4 series output shows the test result is possible or not to pay attention 1 thing 1 output signal m TRD m (m series 0 1…… or 5) and then fill in 1 -J rm Figure 16 shows the overall AS of the circuit used to display the test page 1 of the semiconductor memory of the present invention. The structure is shown in Figure 16 where t corresponds to Figure 1 5 data>-^ 1 The components of the input and output circuits are the same as those attached to the attached symbols in Figure 1 1 1 Symbol 0 1 1 This test circuit is made of 3 2 bit type (X 3 2) The test of the semiconductor memory module is ^ ·-刖 提 〇1 I The test circuit of this embodiment is a white NAND circuit 3 3 exclusive 1 1 I 0 R circuit 3 4, the test switching circuit 1 0 0 and the test output Circuit 1 1 2 0 0 constitutes 〇k > 1 test mode 1 test signal Re e DT level is% Η ¥ 〇 row 1 1 other 0 R circuit 3 4 output signal TRD m (m is 0 1…… Or 1 | 3 1) It is input to the test switching circuit 1 0 0 0 J Test switching circuit 1 0 0 »Input and display the measurement result 3 2 1 1 J bit data 〇 Test switching circuit 1 0 0 system Make this 32-bit data 1 I sequence (serial) output to Trial output circuit 2 0 0 〇II Trial output circuit 2 0 0 Make the level of the control signal TQST is II Η • When »is activated. At this time the level of the control signal QST is II This paper standard is applicable to China_Home Standard (CNS) A4 specification (2 丨 0X297mm) A7 B7 Printed by the consumer cooperation of the Central Standards Bureau of the Ministry of Economy V. Invention description (35) 1 | L The output circuit 3 1 used in the normal mode is non-activated 〇1 1 FIG. 17 shows the details of the test circuit 1 1 used in the semiconductor memory device of the present invention. 1 is shown in FIG. 7> For nftr, the structure of the data input and output circuit according to FIG. 1 5 is 1 | In the composition requirements »As shown in the picture above, the attached characters are the same. First read 1 | Read I 〇 背} ιέ I The test circuit for this test is a 3 2 bit type ( X 3 2) The test of the semiconductor memory I body is W. Reminder 0 Item 1 I in the color register 35 5 billion data with a predetermined pattern (refill 4.0, 1 9 0 〇 color only The content (pattern) of the register 3 5 is changed on page 1 1 in the pattern change mode through the output of the control signal Z. Ο 1 1 Exclusive 0 R The data input to the color register 3 5 in the circuit EX / 1 ICR 0 / CR 1-/ CR 3] L and input data RWD C) Order! 0 Input data RWD 0 Level is a L / f Can also be 'Η ^ 亦 1 1 | Available 0 1 1 For example »Input data RWD When the level of 0 is L / r, 1 cell array 1 1 0 0% ff data input 9 cell array 1 L data input »W 1 cell array 2 Η data input 1 cell array 3 1 L input ff 1 I data 1 I is in all grid arrays 0 3 1 is normal White IJ Array 0 output data ＞ 1 Array 1 output L tt 1 1 J data, Grid array 2 output Η data > Grid array 3 1 output 1 1 L ^ data 〇1 1 At this time ♦ Exclusive 0 R The output signal TRD m of the circuit 3 4 is all 1 1 presents' L 〇1 1 This paper scale is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297 mm) Employee Consumer Cooperative of Central Central Bureau of Economic Affairs印 ^ 309657 A7 B7 5. Description of the invention (36) The output signal TRDm of the exclusive OR circuit 34 is output to the memory chip as the determination signal DQ0 through the test mode switching circuit 1 0 0 and the test mode output circuit 2 0 0 '. In the test mode switching circuit 1 0 0, the judgment test result is yes (the grid array is normal) or not (the grid array is abnormal). When the grid array is normal, the level of the output signal TRDm of the exclusive OR circuit 34 is all presented, and the output signal of the L " level is output from the test mode switching circuit 100, and the test result is determined to be OK. On the one hand, when the grid array is abnormal, the output signal TRDm level of the OR circuit 34, which receives the output data of the abnormal grid array, is presented as ^. At this time, the output signal level of the test mode switching circuit 100 is H, and the test result is determined to be bad. When the test result is not possible, investigate which of the grid arrays 0 to 32 is abnormal. This investigation is based on the latch circuit LATCH0 ~ 3 1 and the output signal of the latch exclusive OR circuit 34, so that the latch data is sequentially read in series. According to such a test circuit, when the data of the color register 35 is tested using semiconductor memory, when the test result is bad, it will show which is the signal of the grid array. The signal of 100 million grids is bad. Structure> Therefore, in the test circuit of this embodiment, the structure of the test circuit itself becomes simple, and only one test pad (terminal) used for testing is sufficient, which can contribute to the memory chip. Reduce or reduce costs. The scale of this paper is applicable to the Chinese national standard falcon (CNS) Λ4 present grid (210X297 gong) ---- „---.--- j < ------ IT ------ f I ( Please read the precautions on the back and then fill out this page) A7 B7 printed by κΜ Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (37) 'y Figure 1 8 shows the test mode switching circuit 1 0 0 of Figure 17 An example of the structure. The exclusive NOR unit 36 checks whether there are defective parts in the grid array 0 to 31. The exclusive NOR unit 36 comes from the exclusive OR circuit EX-ORO, EX-ORi, ~ EX-OR30 and synchronous inversion It consists of CI7. The output signals TRD0 ~ TRD31 are input to the exclusive OR circuits EX-OR0, EX-OR1, ~ EX-OR30. When the output signal TRD0 ~ TRD3 1 are all 'L 〃, the exclusive OR circuit EX — The level of the output signal of OR3 0 is 0. When the level of the control signal / SRCH is 〃, the synchronous inverter CI 7 is activated. At this time, the output signal Re DRD showing the test result is output from the synchronous inverter CI7. When the levels of signals TRD0 ~ TRD3 1 are all #, the output signal Re DRD level is, Η '. That is, the signal showing the test result is acceptable, since Try the output from the output circuit. When the level of at least one of the output signals TRD0 ~ TRD 3 1 is' H ", the output signal ReDRD level is displayed. That is, the test result is displayed as an impossible signal, and it is output from the test output circuit. The switch circuit part 37 is the one where the grid array is defective when the test result is not possible, which is a specific bad grid array. The switch circuit part 37 is a self-switching gate TG〇, TG1, ~ This paper standard is applicable to China ’s national standard rate ( CNS) Λ4 present grid (210X 297 male seam 1 ~ '-Dou〇- ----.------ ^ -clothing -------- order ------ f) (Please read first (Notes on the back and then fill in this page) A7 B7 Central Government Bureau of Economic Affairs Employee Consumer Cooperation Du Printed Goods 5. Description of the Invention (38) 1 | TG 3 1 and synchronous inverter CI 8 are formed 0 Each switching gate TG 0 1 1 > TG 1 > TG 3 1 is composed of N channel type M 〇S transistor and P channel 1 1 type M 0 S transistor. Shift gate TG 0 > TG 1 »I | You please 1 Opening and closing of TG 3 1 The selector 3 8 is controlled first 1 I read 1 system 0 back 1- | The serial selector 3 8 is activated when the level of the control signal Pfla No. SRC Η is Η Note that f is activated »Same 3 steps as the clock signal CLK output control signal Q 0 9 Item 1 | Q 1 Q 1 0 Control signal Q 0 Q 1 ~ Q ί i] Fill in the L ▲ One is the Η level and all the remaining is the L JT level 〇Η page S___ 1 1 The control signal of the level is switched to the sequence Q 0 to Q 3 1 (serial) 1 1 is exchanged for the data RD 0 TRD 1 TRD 3 1 is the sequence 1 I (serial) via the synchronous inverter CI 8 is output. The synchronous inverter CI 8 is activated when the level of the control signal SRC Η is 1 1 I Η can be activated at the moment. 1 1 J 'Figure 1 9 and Figure 2 0 show the invention in the test Operation of semiconductor memory 1 1 〇k 1 recovery • In the test mode, check whether there is a defect in the grid array of the semiconductor memory flsz · 1 1 Check whether there is a defect ○ Serial search • Check in the test mode 1 I Defect of a certain complex grid array There is a grid array 0 1 J / RE decides that the line address signal Qr ^ is placed in the eye of the semiconductor memory when it is 1 1 0. That is »/ RE when the level is% L When the line address signal is placed in a half 1 conductor memory body 0 1 1 / CE determines the time when the column address signal is placed in the semiconductor memory 1 1 0 0 9 9 / CE level is L continued when the column address signal is set to half 1 1 This paper standard is applicable to Chinese national standards (CNS) Λ4 specification (210 /: 2 ^ 7mm)-4 / _ A7 B7 Ministry of Economic Affairs Central Standard Twin Bureau Employee Elimination # Cooperation Du Yin Disaster V. Description of the Invention (39) 1 I Conductor Billion Body 〇1 1 Remedy • The test mode is eg / CE level When it is L sound> Let 1 1 test signal TEST level be set to L ground to execute 〇 / ---- 1 I please 1 1 serial search • Test mode is for example / CE level is L read first 1 | Read 1 1 Let the level of the test signal DEST be set to% Η to be executed acoustically on the back \ 1 of 1 〇 Note I 1 v / FIG. 2 1 is a semiconductor showing the second embodiment of the present invention Memory still item 1 Filling the chip layout 〇 Writing 2 Έ 1 This embodiment describes a 3 1 bit type (X 3 2) semiconductor memory that can simultaneously input and output 3 2 bit data. 〇 1 1 in- Memory chip 1 0 is equipped with 4 banks 1 1 — 0 1 1 1 1 1 3 0 Banks 1 1 — 0 1 1-3 form a 100 million grid order 1 column CALCAR memory grid array controller CAC and row decoding 1 I device RD column decoder CD 0 CD 3 DQ buffer (called I / O buffer of zone library 1 1) DQ etc. The peripheral circuit 〇1 1 1 The memory cell array in the bank is divided into 4 middle blocks BL a > 1 BL b BL c BL d «and each middle block is divided into 2 small 1 1 blocks CAL »CAR 〇 Therefore, the memory cell array in one bank is 1 1 composed of 8 blocks 〇1 row decoder RD is in each of the 4 middle blocks BL a BL b 9 1 BLC» BL d Set 1 〇 line decoder RD is based on the line 1 1 f address signal »Select any one of the two small blocks CAL, CAR 1 1 and white select one of the plural lines in the block select 1 line (word Yuan line) 〇1 1 column decoder CD 0 CD 1 is tied to a district library Set four 〇1 1 paper standards for China National Falcon (CNS) Α4 specifications (210X297 mm)-309657 A7 B7 M printed by the Employee Consumer Cooperative of the Central Bureau of Standards, Ministry of Economy V. Description of invention (40) Column decoder CD 0 block BL a, BL plural column. For example, the connection to the two columns via the selection line of the column is output to the local D y embodiment. At this time, due to the existence of 4 BL b, BL c 1 bank, output sense amplifiers BL a, BL b small block CAL column decoder R CAL-CAR column decoder RD (BL c, BL d direction) 2 The end is placed under the control of the two end grid arrays. Column decoders CBL a · BL b ~ CD 3 select one of the middle zone b, BLc, BLd or the column decoder CD 0 according to the signal of each column address, when selecting the column selection line, connect two The row selection switch is in the on state 9 Then, the two data line pairs of the self-selection switch and the 2-bit data Q line pair 1 8 a. One column decoder selects two columns to form a column decoder, and outputs 8-bit data from each middle block BLa ', BLd. That is, the 32-bit (4-byte) data and row selection are related to each block in the memory grid, BLc and BLd, and are arranged between the memory grid array and CAR. D and the grid array controller CAC make the memory grid array centrally located and configured to face each other. That is, in the direction in which the four blocks BLa 'BLb' are arranged, that is, in the row direction (one side of the portion where the word line extends, the grid array controller CAC is the other side in the matching portion. The data input and output actions D 0 ~ CD 3 in the library are arranged in the direction of the 4 middle blocks, BLc and BLd, that is, they are arranged in the row (please read the precautions on the back before filling this page)

J The standard format of the paper is applicable to the Chinese National Standard (CNS) Λ4 present grid (210/21 factory t) Α7 Β7 Printed by the Central Standards Bureau of the Ministry of Economic Affairs Section Cooperative Fifth, the invention description (41) I 1 direction (data line The direction of the extension of the pair or column selection line) is one of the two ends 1 1 1 square side 〇1 1 4 column decoders CD 0 CD 3 will be responsible for each column decoder 1 I please 1 | CD 0 CD 3 The column of the memory grid array is divided into 4 points *. It is arranged in the row first read I | read 1 direction 〇 back delta | 1 DQ buffer DQ is allocated to the column direction (data line pair or column selection line means decoder 1 extension direction ) The other side of the 2 ends. That is, fill in the column and fill in 1 «« Ji, CD 0 CD 3 and DQ buffer DQ make the memory cell array CAL copybook »CAR in the center» opposite each other 1) The data is sent through the data line pair sense amplifier and the row selection switch 1 1 »Guided to the local DQ line pair 1 8 a 〇 The local DQ line pair 1 8 a is in 1 1 Each middle block BL a BL b BLCBL d of the Yige array is arranged in the small block CALCAR of the Yige array. The local DQ line pair 1 8 a is extended in the row direction (character line 1 1 | The direction of extension) 0 1 1 and the overall data line pair 1 8 b is arranged in the extended column direction on the small block of the memory grid array 1 CALCAR 0 The overall DQ line pair 1 1 1 8 b-the end is through the switch 2 1 Connected to the local DQ line pair 1 1 1 8 a The other end is connected to the DQ buffer DQ 1 1 A total of 4 data bank data bus 1 3 is configured in the bank 1 1 1 1 J — 0 1 1 — 1 and block 1 1 — 2 1 1 — 3 extend from column 1 1 Direction 0 The data bus 1 3 is the district library 1 1 — 0 1 1 — 3 and the capital 1 1 The data input / output path between the data input and output range 1 2 Ο 1 1 In this embodiment »Let 3 2 bit type The semi-conductor of the semiconductor is > ·-刖 提 1 1 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 ϋχπ7mm). -44-A7 B7 309657 V. Invention description (42) Therefore, The data bus 13 is composed of 32-bit (4-byte) data input and output that can be constructed simultaneously. "Memory chip 1 0 in the circumference 1 2 for input, forming a row of 3 2 simultaneously. The output data input / output range 12 is configured on one side of the two ends. The data input range 32 is a 2-bit (4-byte) data input / output circuit (I / 0). The data input and output operations of the semiconductor memory described in y are carried out as follows. First, through the bank selector SEL 'from 4 bank 1 1 — 0 (please read the precautions on the back before filling this page) 1 1 — Select a zone library in 3. In the selected 1 zone library, the memory cell is accessed according to the address signal. When the data is output (read), 32 data are paired via the local DQ line for 1 8 a and the whole zone is selected. Output. From the zone library to the data through the data bus 1 3, leading to the data input and output range 12 output to the semiconductor department. Du Yindi, Staff Consumption Cooperation, Central Bureau of Standards, Ministry of Economic Affairs

Bits (4 bits of DQ line pair 1 output 3 2 bits input and output range of 1 billion body (memory bit (4 bit data bus 1 selected one bank, 100 million grid of the entire DQ line In the following, there are the following decoder RD group), the capital 8 b, the metadata is 2, and it is from the chip) outside group)) 3, the input 3 2 bit pairs 1 8 and characteristics. When inputting (writing) the memory data, 32 data will be input / output range 1 2 through the data to the selected one bank. The data input to this selector is through the local DQ line 18 a sense amplifier SA, which is recorded in the memory grid. The chip layout of the above semiconductor memory is the first. The grid controller CAC and the original paper are suitable for China. Standard (CNS) 8.4 specifications (2 ΙΟ X 297 mm) A7 B7 printed by the consumer cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs V. Invention description (43) Grid grid CAL, CAR is placed in the center, facing each other in the direction of travel At the end. In addition, the column decoders CD0 to CD3 and the DQ buffer DQ are the mega-array CAL and CAR, which are placed in the center and arranged opposite to each other in the column direction. That is, the grid array controller CAC 'row decoder RD, column decoder CD-0 ~ CD3, and DQ buffer DQ are all connected to one side of the memory grid array CAL, CAR. Therefore, it is possible to easily arrange and wire the components constituting the lattice array controller CAC, the row decoder RD, the column decoders CDO to CD3, and the DQ buffer DQ. Second, in the district library: set up a local DQ line pair 18a that extends in the row direction, and set an overall DQ line pair 18b that extends in the column direction, and the data is constructed from the input and output grounds in the column direction end of the library . That is, the DQ buffer DQ can be provided at the end in the column direction of the bank, so that the first feature described above can be realized. Moreover, as in this embodiment, when the number of bits to be input and output in a middle block of the memory cell array is 8 bits, the local DQ line pair 1 8 a arranged between the small blocks CAL and CAR is A 2-bit minute is provided on the CD 0 side of the column decoder, and similarly, only a 2-bit minute is provided on each of the column decoders C D 1 to CD 3 side. This series of decoders CD 〇 ~ CD 3 is adjacent to the memory grid array and is arranged in the row direction, and the output of the data is carried out at the end of the column direction of the bank. Therefore, the necessary range is reduced for the local DQ line pair 18a. The standard of this paper is applicable to the China Lai Family Standard (CNS format (2_297 Gongqing) _ ~ -private- ------- l · --- 1 clothing ------ order ------ ^ (Please read the precautions on the back before filling out this page) A7 B7 Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs V. Description of Invention (44) In addition, the overall DQ line 1 8b is in a middle block. When the 8-bit data is input and output, only the number of 32-bit data transmission is needed in the library of area 1. However, the overall DQ line pair 1 8 b is configured on the memory cell array CAL, CAR. The new setting configures the range of the overall DQ line pair 1 8 b. Third, the data bus 1 3 is located in the zone library 1 1 — 0, 1 1 — 2 and the zone library 11 — 1, 11 — 3, extending in the row direction Configuration. This is the reason that the DQ buffer DQ in the zone library is arranged in one of the two ends in the column direction. As a result, the design of the arrangement of the zone library and the data input and output circuits can reduce the data bus 1 3 The structured wiring can be narrowed to the range of the data bus 13 occupied by the memory chip 10. 2 2 is a schematic diagram showing the location of the bank of the semiconductor memory constituting the first embodiment of FIG. 10 and The location of the material bus. The range on the memory chip 10 is mainly occupied by the library 1 1 10 ~ 1 1 _3 and the data input and output range (I / O) 12. The data input and output range 1 2 is adjacent to the billion One of the four sides of chip 10, that is, one of the two sides adjacent to the column direction is arranged. The memory cell array in the bank is composed of a plurality of small blocks arranged in the column direction, and passes through two small blocks It constitutes a middle block. Within each small block, it is arranged in a character line extending in the row direction, and a data line and a column selection line extending in the column direction (the direction in which the small blocks are arranged). DQ line pair 18 Between 2 small blocks' extension in the row direction. The DQ line pair 18 between 2 small blocks can only transmit 4-bit data -η- This paper size is suitable for the Chinese National Standard (CNS) Λ4 of this paper. (210X 297 Gong) (Please read the precautions on the back before filling in this page) 1 " Order * Τ— n J— * 309657 A7 B7 5. Description of the invention (45 number data bus 1 3 series is arranged in the district library 1 1 — 〇, 1 1_1 and the district library 11 — 2 ′ 11 — 3, extending in the row direction. Data bus 1 3 The 16-bit (2-byte) data can be transmitted to be formed. 2 3 is the first modification of the semiconductor memory device shown in FIGS. 10 and 22. The characteristics of this modification are arranged on the memory chip 10 The two sides' each set area library 1 3 a, 1 3 b ° That is, the memory chip 1 makes the data input and output circuit (I / 0) 1 2 the central part, and the data input and output circuit 1 2 11-0 11 3 and the range on the data bus 0 are mainly occupied by the library 11-10 ~ 11-3 and the data input / output range (I / O) 12. Data 2 is placed in the central part of the 100 million chip 10, in the column (please read the precautions on the back and then fill out this page). The Ministry of Economic Affairs, Central Standard Falcon Bureau, employee cooperation, du printing, I / O range 1 direction change long. The structure within the library, and via, is arranged in the overall DQ direction of the extension line and the column selection line. In addition, the situation is in the column direction. Through the switch mutual data convergence memory array is composed of a plurality of small blocks arranged in the row direction 2 small blocks to form a middle block. The character lines in the row direction in each small block, and the data extending in the column direction. The line pair 1 8 a is between 2 small blocks' extended in the row side DQ line pair 1 8 b is in the billion grid array The upper extension DQ wire pair 18 a and the local DQ wire pair 18 b are connected. Row 1 3 a is configured in the district warehouse 1 1 10 and district warehouse 1 1 This paper standard is applicable to the Chinese hoarding standard (CNS) eight 4 clam (210X2SH male t)-you-A7 B7 employees of the Central Standardization Bureau of the Ministry of Economic Affairs Consumer cooperation it printed back 5. Description of the invention (46) 1-1 extended in the row direction t connected to the data input and output circuit 1 2 〇 The same 1 1 W, the data bus 1 3 b is located in the district library 1 1- 2 and the library 1 1 1 1-3 extended in the row direction »Connected to the data input and output circuit 1 2 1 1 I 〇 data bus 1 3 a I 1 3 b order 16 bits (2 bytes) Please read first 1 1 I data can be transmitted to form 0 read back and 1 \ jM 2 4 is shown in detail in the wafer layout of the semiconductor memory shown in Figure 2 1 Note 1 Bureau 1 Thinking 1 I Re 1 | Each The layout in the area library is the same as that of each ΤΓΓ m library in the semiconductor memory of Fig. 10. Same page 0 '«« wV 1 | \ β 2 5 shows the first modified example of the semiconductor memory of Figure 2 1 1 1 1 The characteristics of this modified example are the data input and output circuit (I / 0) 1 2 1 1 Order | Arranged in the central part of the memory chip 1 0 »and on both sides of the data input and output circuit 1 2 1 1 Set up the library 1 1 — 0 1 1 — 3 and the data bus 1 1 1 3 a 1 3 b 〇1 1 means the range on the memory chip 1 0 is mainly composed of the library 1 1 — 0 | 1 1 — 3 and the data input / output range (I / 0) 1 2 occupied 0 data 1 I input / output range 1 2 system configuration The central part of Yu Jiyi wafer 1 0 »Yu Lifang 1 1 I direction lengthening 〇1 1 Zone library 1 1 — 0 1 1 — 1 is arranged in the data input / output range 1 1 1 2 — Side zone library 1 1 One 2 1 1 — 3 is configured on the other side of the data output • 1 1 into the range 1 2 The grid array is composed of a plurality of small blocks 1 | arranged in the column direction, and 1 medium block is formed by 2 small blocks. 1 Within each small block 1 1 paper standard Tongzhou National Standard (CNS) Λ4 (210X 297 gongs) Cooperation with the Central Bureau of Standards of the Ministry of Economic Affairs, M Industry and Consumers, Du Yin crack A7 _ B7 V. Description of invention (47) 'Configured on the character line extended in the row direction, and the data line extended in the column direction and Column selection line. The overall D Q line pair 1 8 a is tied between 2 small blocks, extending in the row direction. In addition, the local DQ line pair 18 b is tied to the grid array and extends in the column direction. The overall DQ line pair 18 a and the local DQ line pair 18 b are connected to each other via a switch. The data bus 1 3 a is arranged between the zone library 1 1 -10 and the zone library 1 1-1 * extended in the column direction and connected to the data input / output circuit 12. In the same way, the data bus 13b is arranged between the bank 1 1-2 and the bank 1 1-3, extending in the row direction, and connected to the data input / output circuit 1 2. The data bus 13a, 13b is composed of 32-bit (4-byte) data that can be transmitted. The layout in each bank is the same as the layout in each bank of the semiconductor memory of FIG. 22. This chip layout is different from the chip layouts of Fig. 10 and Fig. 2 in the following points. First, make one district library (main district library) composed of two sub-blocks. That is, the 'main zone library 1 1 — 0 is composed of the sub-zone library 1 1 — 10 — # 〇, 1 1 — 0 — # 1 constitutes the' main zone library 1 1 — 1 is composed of the sub-zone library 1 1 -l- # 0, 1 1 — 1- # 1, the main zone library 1 1 — 2 is composed of the secondary zone library 1 1 2 — # 〇, 1 1 — 2 — # 1, the main zone library 1 1 ~ 3 system It is composed of the sub-zone library 1 1 — 3- # 〇, 1 1 — 3- # 1. The sub-zone library 1 1 — 0 — # 〇, 1 1 — 〇 — # 1 is the standard of the Laijia standard (CNS) Λ4 " Ιϋ (2H) x297 public slow through the zone library paper standard-~ t〇- (please (Read the notes on the back before filling this page)

J-* δ 309657 Λ7 B7 V. Description of the invention (48) The selection circuit, in cooperation with # 1 by the district bank of the district bank 1 — 0 — the Central Standard Falconry Bureau of the Ministry of Economic Affairs Μ 工 消 f cooperation du printing such as deputy, residual and # 1. The group sub-region library # 0, the data sink, the data input sub-device CD, one sub-c, and the sub-RD, DQ of the semiconductor block B data are selected at the time of the layout. Sub-zone library 1 1 — 0 — # 0, 1 1 When selected, the remaining zone library is not selected》 Similarly, 1 — i— # 〇, 11 — 1 — # 1 is selected when it is selected》 Via 4 sub-zone libraries 1 1 0 * 11 The library system is connected to the data bus 0 * 11 1 to form a group, and the group library system of this group is connected to -0- # 0 '11-0--1 — # 1 composition 1 group, this 13a. Similarly, through 4-2- # l, 11-3- 1 1-3-# stream row 1 2, when entering and leaving the regional library, there is a memory La in the regional library, which is exported to the local D in the regional library Punch D is almost the same as 3, with a capital of 3b. 1 sub-composition. The layout system has only one, and it can be entered in the same way. In the B L b area library, 8-bit (1-byte) is performed, which is not 8-bit as shown in Figure 10. However, select 2, and the layout of the C Q line pair 1 8 a Q of the B L c in memory grid array is the same as the figure. When comparing the layout of the data input and output circuits, the column decoding is the same. Because, in this example, the output of the data, the column decoder, the column decoder CD and the row in Figure 10 are in the memory grid array. In each of the BLd's, the 2-bit AL, CAR, column decoder overall DQ line pair 1 8 b and 1 0 in the semiconductor memory area library / Ο (please read the precautions on the back before filling this page ) -¾ The size of the paper is suitable; the two families of the 2nd family are on the 100 million chip--r ^ Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs t A7 B7 V. Description of the invention (49) 10 The central part of the 10, extending in the direction of the column The data bus I 3 a is located on one side of the data input / output circuit 1 2 and is commonly located in the secondary area library II — 0 — # 0 '1 1-0-# 1, 1 1-1-# 0 '1 1 — 1 — # 1 group of data bus 1 3 b is on the other side of the data input and output circuit 12 and is commonly set in the sub-zone library 1 1 — 2 — # 0, 11-2- # 1, 11-3- # 1, 11-3_ # 0. The data bus 1 3 a, 1 3 b is located between the sub-zones and extends in the direction of the column. It is connected to the central part of the memory chip 10 and the data input / output circuit 12 . The bus bars 13a and 13b can be configured to transmit 16-bit data each. In the semiconductor memory of such a chip layout, for example, the sub-zone library 1 1 -〇- # 〇, 1 1 — 〇- # 1 At the time, between the sub-zone library 1 Ι Ο — # 0 and the data output and input circuit 12 through the data bus 1 3 · a '8-bit data reception, similarly in the sub-zone library 1 1 1 〇- # 1 and data input and output circuit 12 through the data bus 1 3 a, 8-bit data reception. ^ Figure 2 8 shows the second modification of the semiconductor memory chip of the second embodiment of Figure 21 Example. This chip layout is different from the chip layout of Figure 21 in the following points. The first 1 'makes 1 zone library (main zone library) composed of 2 sub-blocks. That is, the main zone library 1 1 — 〇 is from the sub-zone library〗 1 _ 〇 一 # 〇, 1 1 1 0_ # 1, the main zone library 1 1-1 is from the sub zone library 1 1 — 1 — # 0, 1 1 — 1- # 1 is composed of the main zone library 1 1-2 series. The paper size is applicable to the Chinese National Standard (CNS) Λ4 present grid (210Χ 297 Gong Chu) (please read the precautions on the back before filling this page). 1 order The central banner of the Ministry of Economic Affairs. The cooperation of industrial and consumer cooperation Du Yinju A7 B7 5. Description of the invention (5〇) From the sub-district library 1 1 — 2 — # 〇, 1 1 1- 2- # 1, the main district library 1 1 — 3 is composed of the sub-zone library 1 1 — 3- # 0, 1 1 — 3 — # 1. Sub-zone library 1 1 — 0 one # 〇 ′ 1 1-0 — # 1 is selected through the zone library selection circuit at the same time. Sub-zone library 1 1 — 0 — # 〇, 1 1 — 0 — # 1 When selected, the remaining zone library is not selected. Similarly, for example, when the sub-zone library 1 1 — 1_ # 〇 '1 1 — 1_ # 1 is selected, the remaining zone library is not selected. In addition, via 4 sub-zone libraries 1 1 — 0 — # 0, 1 1 — 0 — # 1, 11 — 1 — # 0 '11 — 1- # 1 form a group, and the zone library of this group is connected to Data bus 1 3 a. Similarly, via 4 sub-regional libraries 11 — 2 — # 〇, 11-2 — # 1, 11 — 3 — # 0, 1 1—3-# 1 form a group, and the group library of this group is connected to Data bus 1 3 b. Second, in a sub-zone library, the 16-bit (2-byte) data input and output structure is composed. When the layout of the sub-zone library is compared with the layout of the zone library in Figure 21, the column decoder CD Only one is the difference. That is, the layout of the sub-zone library is the same as the layout of FIG. This is because, in this example, there is only one column decoder CD in order to output 8-bit data in a secondary bank. However, the column decoder CD is the same as the semiconductor memory of FIG. 21, selects two columns, and executes 4-bit data in each block BLa, BLb, BLc, BL d Import and export. The standard of this paper is applicable to the Chinese National Standard (CNS) Λ4 specification (210Χ 297 male)---·: Γ- — ^ 1 — I- I! I one---II (please read the precautions on the back and fill in this amaranth first ) Order-['3-A7 __ B7 V. Description of the invention (51) Billion grid array c AL, CAR, column decoder RD' local DQ line pair 18a, overall DQ line pair 18b and DQ buffer The layout of the device DQ is almost the same as the layout in the semiconductor memory bank of Figure 10. Third, the data input / output circuit (I / O) 12 is located in the central part of the 100 million chip 10 and is arranged to extend in the column direction. The data bus 1 3 a is on the side of the data input / output circuit 12. Commonly located in the sub-zone library 11-〇- # 〇. 11-0- # 1 & 11-1- # 〇 > 1 1 — 1 1 # 1 in the group data bus 1 3 b is in the data input and output The other side of the circuit 1 2 is commonly set in the sub-zone library 1 1-2-# 0, 11-2- # 1, 11-3- # 0, 11-3- # 1. The data buses 1 3 a and 1 3 b are located between the sub-zones, and are extended in the column direction to the data input / output circuit 12 in the central part of the billion chip 10. The data buses 1 3 a and 1 3 b are composed of data that can transmit 32 bits each. The Ministry of Economic Affairs Central Standard Falcon Bureau Employee Consumer Cooperative is printed in the semiconductor memory of such a wafer layout, for example, when selecting the sub-zone library 1 1-0 — # 〇 '1 1-0 — # 1, in the sub-zone library 1 Ιο -Between # 0 and the data input and output circuit 12 through the data bus 1 3 a, 8-bit data is received and received in the same way in the secondary area library 1 1 1 0_ # 1 and the data output and input circuit 12 between Data bus 1 3 a, receiving 16-bit data》 2 8 shows the first modification of the semiconductor memory chip of the first embodiment shown in FIGS. 10 and 22 2》 FIG. 30 shows in detail Figure 29 shows the chip layout of the semiconductor memory. -tii-I: nn — ^ nn .n ^ (Please read the precautions on the back before filling in this 1) This paper scale is applicable to the Chinese National Standard (CNS) Λ4 specification (210 > < 297 public health) A7 B7 308657 V. DESCRIPTION OF THE INVENTION (52) This chip layout is different from the chip layouts of FIGS. 10 and 22 in the following points. HI 'I _-«I--I---· 1-nf I (please read the precautions on the back before filling out this page) Article 1, make 1 district library (main district library) from 2 subsidiary districts Block composition. That is, the main zone library 1 1-0 is composed of the sub-zone library 1 1 1 〇 一 # 〇, 1 1 — 〇 — # 1, the main zone library 1 1-1 is from the sub-zone library 1 1 — 1 — # 0, 1 1 1- # 1 constitutes the 'main area library 11 1 2 series from the secondary area library 1 1 — 2 — # 0, 1 1 constitutes the primary area library 1 1 3 from the secondary area library 1 1 one 3 one, 1 1 one 3 — # 1. The sub-zone library 1 1-0-# 〇 '1 1-0-# 1 is selected through the zone library selection circuit at the same time. Sub-zone library 1 丨 ―〇 — # 0,1 1 —0 — # 1When selected, the remaining zone library is not selected. Similarly, for example, when the sub-zone library 1 1-1 — # 〇, 1 1 — 1_ # 1 is selected, the remaining zone library is not selected. The Ministry of Economic Affairs Central Standardization Bureau®: Cooperative Du Printing Co., Ltd. Printed again, through 4 sub-district libraries 1 1 — 0 — # 〇, 1 Gongyi 1 — # 0, 11-2 — # 0, 11 — 3 — # 1 Make up a group 'The district library is connected to the data input / output circuit 12a through the data bus 13a, 13b. Similarly, through 4 sub-regional libraries 1 1 — 〇- # 1, 1 1-1-# 1, 1 1-2-# 1 '11-3- # 1 constitute a group, the group of this group It is connected to the data input / output circuit 1 2 b through the data bus 1 3 C and 1 3 d. \ ySecond, 8-bit (1-byte) data input and output are formed in a sub-region library. The layout of the sub-regional library is compared with the layout of the regional library in Figure 10, and the paper size of the decoded code is applicable to the Chinese National Standard Falcon (CNS) Λ4 尭 格 (210X297 鳌). Install A7 ________B7__ V. Description of the invention (53) The device c D is that only one is its difference. This is because, in this example, there is only one column decoder CD to output 8-bit data in a sub-region library. However, the column decoder CD selects two columns in the same way as the semiconductor memory of FIG. 21, and executes 2-bit data in each of the blocks BLa, BLb, BLc, and BLd in the memory grid array. Import and export. The layout of the memory grid array CAL, CAR, column decoder RD, local DQ line pair 18a, overall DQ line pair 18b and DQ buffer DQ in the sub-region library is the same as the layout in the semiconductor memory region library of FIG. 10 It's almost the same. Third, the data input / output circuit (I / O) 12a '12b is arranged on the memory chip 10 and is extended in the column direction. The data bus 13a, 13b is provided on both sides of the data input / output circuit 12a. The bus bars 1 3 c, 1 3 d are provided on both sides of the data input / output circuit 1 2 b. The data bus bars 1 3 a are commonly provided in the sub-zone library 1 1 1 0 ~ # 〇 '11 — 1 — # 0, 11 一 1 一 # 0. The data bus 13b is commonly located in the sub-district 1 1 — 2 — # 0, 1 1 — 3 — # 〇, the data bus 1 3 c is commonly located in the sub-division 1 1 — 〇 — # 1, 1 1 —1 — # 1, the data bus 1 3 d is set in the sub-zone library 1 1 _ 2_ # 1, 11-3- # 1. The data bus 1 3 a and 1 3 b are connected between the sub-zones, extending in the column direction, and connected to the data input and output circuit 1 2 a. Similarly, the data bus 1 3 c and 1 3 d are connected to each sub Between the warehouses, the direction of the row is extended, and even the size of this paper is applicable to China National Standard (CNS) Λ4 ^ 格 （21 () Χ297mm) 7 / ~~-^^^ 1 111 I m ^ i .... .... I in — ^ n one V (please read the precautions on the back before filling in this page) A7 __B7_ 5. Description of the invention (54) Connected to the data input / output circuit 12b, the data bus 13a ~ 13d can be Each 8-bit data is transmitted. . In the semiconductor memory with such a chip layout, for example, when the sub-zone library 1 1-0 — # 0 '1 is selected, between the sub-zone library 1 Ι ο — # 0 and the data output and input circuit 1 2 a, via the data bus Row 1 3 a is for receiving 8-bit data, the sub-zone library 1 1 — 〇— and the data output and input circuit 1 2 b, through the data bus 1 3 c for 8-bit data receiving. That is, in a 16-bit semiconductor memory, the data bus 1 3 a ~ 1 3 d can be constructed by wiring that can transmit 8-bit data. The data bus on the memory chip can be made The range becomes smaller. Fig. 3 1 shows a third modification of the semiconductor billion wafer of the second embodiment of Fig. 2 1. Fig. 30 shows the chip layout of the semiconductor memory of Fig. 29 in detail. This chip layout is different from the chip layout of FIG. 21 in that it differs in the following points. The first 1 'order that a district library (main district library) is composed of two sub-blocks. Central Standards Bureau of the Ministry of Economic Affairs, M Industry and Consumer Cooperatives, I --- i. Ii 1 n ^ p j--II-! I (please read the precautions on the back before filling out this page), that is, the main zone library 1 1 1 0 It is composed of the deputy zone library 1, 1 1 — 0 — # 1. The main zone library 1 1 — 1 is composed of the deputy zone library 1 1 — 1 — # 〇, 11_1_ # 1. It is composed of the secondary district library 1 1 — 2 — # 〇 ,; [1_2_ # 1, the primary district library 1 1 — 3 is composed of the secondary district library 1 i — 3 — # 〇, 1 1. Sub-zone library 1 1 — 〇_ # 〇 '1 1 — 〇_ # 1 is based on the size of the zone library paper and is applicable to the Chinese National Standard (CNS) Λ4 specification (2 丨 0χ247 common edge) spoon A7 B7 3〇9657 V. Description of the invention (55) Select the circuit and select it at the same time> Sub-zone library 1 1 — 0 — # 〇, 1 1 _ 0 _ # 1 When the selected zone library is selected, the remaining zone library is not selected. Similarly, for example, the sub-zone library 1 1 — 1 — # 〇 ,; [When selected, the remaining zone library does not select β, and through the 4 sub-zone libraries 1 1 — 〇 — # 〇, 1 1_1_ # 0 , 11 — 2 — # 0, 11 — 3_ # 〇 constitutes a group of workers, and the district library of this group is connected to the data input / output circuit 1 2 a through the data bus 13a, 13 b. Similarly, through 4 sub-zone libraries 1 1 — 〇- # 1 '11 一 1- # 1, 11-2- # 1, 11-3- # 1 form a group, the group library of this group is through data The bus bars 1 3 c and 13 d are connected to the data input / output circuit 12 b. The second 2 'is composed of a 16-bit (2-byte) data input and output in a sub-region library. When the layout of the sub-zone library is compared with the layout of the zone library in Fig. 21, the column decoder CD has two differences. That is, the layout of the sub-zone library is the same as the layout of the zone library of FIG. Because, in this example, in a sub-region library, in order to carry out 16-bit; ^ data output, there are only two column decoder CD. However, the row decoder CD is the same as the semiconductor memory of FIG. 21, and selects two rows to execute 4-bit data in each of the blocks BLa, BL b-BL c, and BL d The input and output of the sub-area library: the layout of the billion grid array CAL, CAR, column decoder RD, local DQ line pair 18a, overall DQ line pair 18b, and DQ buffer DQ are as shown in the semiconductor record of FIG. 10. The cloth in the library of the body area (please read the precautions on the back and fill in this page).-,-· Printed by the Liji Ministry of Central Bureau of Industry and Commerce Cooperative Society. The paper size is applicable to the Chinese National Standard (CNS) Λ4 Present case (2 丨 0X 297mm) A7 B7 309657 5. The description of the invention (5δ) is almost the same. (Please read the precautions on the back and then fill out this page) Article 3, data input and output circuit (I / O) 12a and 12b are arranged on the billion-element chip 10 and are extended in the column direction. The data buses 13a and 13b are located on both sides of the data input and output circuit 12a. The data buses 13c and 13d It is located on both sides of the data input / output circuit 1 2 b. \ ^ Material bus 1 3 a is commonly located in the sub-zone library 1 1 — 〇— # 〇 ， 1 1 一 1 — # 0. The data bus 1 3b is commonly located in the sub-zone library 11-2-# 0,11 — 3 — # 0, the data bus 13c is commonly located in the sub-zone library 11 — 0- # 1 ， 11 — 1 一 # 1, data bus 1 3d is commonly located in the secondary area library 11 — 2 — # 1,11 一 3-# 1. The data bus 1 3 a, 1 3 b is in each sub Between the warehouses, it extends in the column direction and connects to the data input / output circuit 1 2 a. Similarly, the data bus 1 3 c and 1 3 d are connected between the warehouses of each sub-area, extend in the row direction, and connect to the data input and output. Circuit 1 2b, data bus 1 3 a ~ 1 3 d can be composed of 16-bit data .. Central Bureau of Standards of the Ministry of Economic Affairs Printed in the semiconductor memory of such a chip layout. , For example, when selecting the sub-zone library 1 1-0 — # 0, 1 1 — 〇- # 1, between the sub-zone library 1 1 — 0-# 0 and the data output and input circuit 1 2 a, via the data bus 13a, To receive and receive 16-bit data, the sub-zone library 11 — 〇 — # 1 and the data output and input circuit 1 2 b, through the data bus 1 3 c, to receive and receive 16-bit data. That is, at 3 2 bits In the semiconductor memory, the data sheet format of the data bus is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297 g) A7 B7 5. Description of the invention (57) 13 a ~ 13d is the number of 16-bit data that can be sent via Fu The wiring can be structured to reduce the range of the data bus on the 100 million chip. The third is a fourth modification of the semiconductor memory chip of the first embodiment shown in FIGS. 10 and 22. FIG. 3 3 shows the chip layout of the semiconductor memory of FIG. 32 in detail. This chip layout is different from the chip layout of FIG. 10 and FIG. 2 in the following points. The first 1 'order that a district library (main district library) is composed of two sub-blocks. That is, the main area library 1 1 — 0 is composed of the auxiliary area library 1 1-0 — # 0, 1 1 — 0 — # 1, the main area library 1 1 — 1 is composed of the auxiliary area library 1 1 — 1 — # Composed of 0, 11-1 and # 1, the main zone library 11 and 2 are from the secondary zone library 1 1-2 — # 0, 1 1 and 2- # 1, the main zone library 1 1 and 3 are from the secondary zone District library 1 1 — 3 — # 0, 1 1 — 3 — # 1. Sub-zone library 1 1 — 〇 — # 〇, 1 1 — 〇- # 1 is selected through the zone library selection circuit at the same time. When the secondary bank 1 1 — 〇 — # 〇, 1 1 _ 0 — # 1 is selected, the remaining bank is not selected. Similarly, for example, when the sub-zone library 1 1-1 — # 〇, 1 1 — 1 — # 1 is selected, the remaining zone library is not selected ”again” via 4 sub-zone libraries 1 1-0 — # 〇 ， 11 — 1 一 # 0 '11 — 2 — # 0,11 — 3-# 0 form a group, and the district library of this group is connected to the data input / output circuit 12 via the data bus 1 3 a »Similarly , Through 4 sub-district libraries 1 1 10 — # 1, 1 1 The paper size is applicable to the Chinese National Standard (CNS) Λ4 specification (210X 297 mm) ------: --- ^ Cloth—I ( Please read the precautions on the back before filling in this page) Order the Ministry of Economic Affairs Central Standards Bureau employee consumer cooperatives to print and gather the Ministry of Economics Central Standards Bureau Mgong Consumer Cooperatives Indigenous A7 ________ B7 5. Invention Instructions (58) One 1 One # 1 11 — 2-# 1, 11 — 3_ # 1 form a group. The district library of this group is connected to the data input / output circuit 1 2 via the data bus 1 3 b. 'No. 2' is composed of 8-bit (1-byte) data in and out of a sub-region library. When the layout of the secondary bank is compared with the layout of the bank in Figure 10, only one column decoder CD is the difference. Because, in this example, in order to output 8-bit data in a sub-region library, there is only one column decoder CD. However, the column decoder CD is the same as the semiconductor memory device of FIG. 10, selects two columns, and executes 2-bit data in each block BLa'BLb, BLc, BLd of the memory cell array. I / O; the layout of the mega-array CAL, CAR, column decoder RD, local DQ line pair 18a, overall DQ line pair 18b and DQ buffer DQ in the sub-region library is the same as the semiconductor memory area of FIG. 10 The layout in the library is almost the same. "Third, the data input and output circuit (I / O) 12 is on the memory chip 10, which is arranged to extend in the column direction. The data bus 1 3 a and 1 3 b are designed. On both sides of the data input and output circuit 12. The data bus 1 3a is set in the sub-zone library 1 1 — 0-# 0, 1 1 — 1 — # 0 * 11 — 2 — # 0, 11 — 3 — # 0. The data bus 1 3 b is commonly located in the sub-zone library 1 1-# 1,, 11 1 2 — # 1, 11-3- # 1. The data bus 1 3 a and 1 3 b are located between the depots of each sub-district 'n-I-I-I-IJ Ά — I --- II Ding — · 4,-° (please read the notes on the back first Please fill in this page for details) This paper scale is applicable to the Chinese National Standard (CNS) Α4 specification (210X 297mm)-έ /-309657 5. Description of invention (59) Direction extension, connected to the data input and output circuit 12. The data buses 1 3 a and 13 b are composed of 8-bit data. . In the semiconductor memory with such a chip layout, for example, when the sub-zone library 1 1-0- # 0, 1 1-0 — # 1 is selected, between the sub-zone library 1 ίο — # 0 and the data output and input circuit 1 2 Through the data bus 13a, the 8-bit data is received, the secondary library 11-0 — # 1 and the data output and input circuit 12 between the data bus 1 3b, the 8-bit data is received. That is, in a 16-bit semiconductor memory, the data bus 13a, 13b can be formed by wiring that can send 8-bit data, which can make the data bus on the 100 million chip The range becomes smaller. > 3 4 shows a fourth modification of the semiconductor memory chip of the second embodiment shown in FIG. 21. Fig. 30 shows the detailed layout of the semiconductor memory device of Fig. 29. The chip layout is different from the chip layout of FIG. 21 in that it differs in the following points. The first 1 'order that a district library (main district library) is composed of two sub-blocks. Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling in this page) Liang P 'Main Zone Library 1 1 — 〇 is from the Deputy Zone Library 1 1-0 — # 〇, 1 1 — 0 — Constituted by # 1, the main zone library 1 1_1 is composed of the secondary zone library 1 1 — 1 — # 〇, 11 — 1 — # 1, the main zone library 11_2 is composed of the secondary zone library 1 1 — 2- # 0, 1 1 — 2 — # 1, the main zone library 1 1 — 3 is composed of the secondary zone library 1 1 3-# 〇, 1 1 3-# 1. Deputy Yaoku 1 1 — 〇 — # 〇, 1 1 — 〇 一 # 1 is applicable to the Chinese national standard (CNS) Λ4 present grid (210X297 mm) through the regional library paper scale-309657 at __B7__ (6〇) Select the circuit and select it at the same time. Sub-zone library 1 1 — 〇 一 # 〇, 1 1 — 0 — # 1 is selected, the remaining zone library is not selected. Similarly, for example, when the sub-zone library 1 1— · 1 one # 0, 1 1—1— # 1 is selected, the remaining zone library is not selected. In addition, via 4 sub-zone libraries 11—0— # 0, 11—1—1 # 0, 11-2- # 0, 11—3— # 0 form a group, and the zone library of this group is via the data bus 1 3 a, connected to the data input and output circuit 1 2. Similarly, through 4 sub-regional libraries 1 1 1 0_ # 1, 1 1 — 1 — # 1, 11 — 2 — # 1, 11 — 3_ # 1 form a group, the group library of this group is via data convergence Row 1 3 b, connected to the data input and output circuit 1 2. Second, in a sub-region library, 16-bit (2-byte) data input and output structure. When the layout of the sub-zone library is compared with the layout of the zone library in Fig. 21, the column decoder CD has two differences. That is, the layout of the secondary library is the same as the layout of the library in FIG. Because, in this example, in a deputy district library, in order to carry out 16-bit (please read the precautions on the back before filling in this I). The land is the same two-body code in the E-store system D-leading C half-device 1 solution 2 column diagram 'and the C feeder code for the output D

b L. B in ’out 3 out L of the B material block in the middle of the block area 4 rows of everyone in the Jml ft. grid, billion in the record d in L

Unpack the columns, 2 is L but B

C

D R 畐 歹 bR · grid 1 within the Q of the memory line D library department 8 a device code and solution b column 8, 1 R to A line c Q, D L body A integer

Inner District Body Billion Records Half of the Body IX IX Figures and Department of Layout QD Device Relief QD Falcon Bakers Guoguo No. 1 Middle School | General Ruler I Sheets of Paper I Books I Ligong 7 9 2 Central Bureau of Standards, Ministry of Economic Affairs Printed by employees' consumer cooperatives Α7 Β7 5. The layout of the invention description (61) is almost the same. V / 7 No. 3 'Data input and output circuit (I / 0) 1 2 is on the memory chip 1 〇' extended in the column direction, the data bus 1 3 a, 1 3 b is set in the data input and output circuit 1 2 on both sides. The data bus 1 3 a is set in the sub-zone library 1 1 — 〇 — # 〇 '1 1-1-# 0, 1 1-2-# 0, 1 1-3-# 0, the data bus 13b is Commonly located in the sub-zone library 11-〇_ # 1, 11-2- # 1, 11-3- # 1. The data buses 1 3 a and 1 3 b are connected between the sub-zones, and are extended in the column direction to the data input / output circuit 12. The data buses 1 3 a and 1 3 b are each composed of 16 bits of data. In the semiconductor memory with such a chip layout, for example, when the sub-region library 1 1 — 〇- # 〇, 1 1 — 〇 — # 1 is selected, between the sub-region library 1 ίο-# 0 and the data output and input circuit 1 2 , Through the data bus 1 3 a, to receive 16-bit data, the sub-zone library 1 1_〇- # 1 and the data input and output circuit 12 between, through the data bus 1 3 b, 16-bit data Acceptance. That is, in a 32-bit semiconductor memory, the data bus 1 3 a, 1 3 b can be formed by wiring that can send 16-bit data, which can make the data on the memory chip The scope of the bus becomes smaller "x / ia 3 5 shows the data transmission system of the present invention. η (η is plural) blocks BLO ~ BLn are constructed from the same elements * Blocks B L 〇 ~ B L η are arranged to extend in the column direction. Block B L 〇 is taken as an example, and the configuration will be described. This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X2 ^ 7 Gongqing) -Correct- --------; --- ^ --- (Please read the precautions on the back before filling this page )

, tT The Ministry of Economic Affairs Central Standards Bureau employee consumer cooperatives printed this paper standard is applicable to the Chinese National Standard (CNS) Λ4 specifications (210X 297 mm) A7 _B7______ Five 'invention description (62) Block BL 0 is configured in the column direction Two switch arrays 41a, 41b. The switch arrays 41a'41b are self-arranged matrix-like complex switches (MOS transistors) 46a'46b. The β-row decoder 4 2a is adjacent to the two ends in the column direction of the switch array 4 1a One is configured. The row decoder 4 2 b is arranged adjacent to one of the two ends in the column direction of the switch array 4 1 b. One end of the word lines 44a, 44b is connected to the column decoders 42a, 42b, and the word lines 44a, 44b are connected to the control terminals (gates) of the plural switches 46a, 46b which are also in the column. The column decoder 43 is arranged adjacent to one of the two ends in the column direction of the switch array 4 1 a. One end of the column selection line 49 is connected to the column decoder 43. The registers 47a and 47b and the column selection switches 48a and 48b are arranged between the two switch arrays 41a and 41b. One end of the data lines 45a, 45b is connected to the registers 47a, 47b and the column selection switches 48a, 48b, and the data lines 45a, 45b are connected to the output ends of the plural switches 4 6a, 4 6 b which both belong to the column ( Jiji). The column selection line 49 is connected to the column selection switches 48a, 48b. The data is applied to the input (source) of the complex switches 4 6 a and 4 6 b. The local DQ lines 5 0-0 are arranged between the two switch arrays 4 1 a and 41 b and extend in the row direction. The local DQ lines 50-0 are connected to the registers 47a and 47b and the column selection switches 48a and 48b. --IL---L, --- 1 --- (please read the precautions on the back before filling in this page) Order ^ 09657 A7 B7 Central China Bureau of Economic Affairs Employee's consumer cooperation du printing 5. Invention description (63) 1 | The overall DQ line 5 1 — 0 is arranged on the switch array of n blocks BL 0 1 1 BL η> extended in the column direction. The end of the overall DQ line 5 1 — 1 1 0 is connected to the local DQ Line 5 0--3 'Overall DQ line 1 I Please 1 | 5 1 — 0 The other end is connected to the data input / output circuit (I / 0) First 1 1 Read 1 5 2 〇Back! I Road 1 Data output Incoming power 5 2 is adjacent to one of the two ends in the row direction of η blocks BL 0 * BL η to be placed 0 items and then 1 i I The characteristics of the above data transmission system are filled in η blocks BL 0 BL η When Ben-4 is extended in the column direction, for example, the data page output by the white block BL 0 BL η ^ — '1 1 is passed The overall DQ line 5 1-0 1 1 5 1-η on the array 4 1 a 4 1 b »Import data I / O circuit 5 2 〇1 | That is, the data output from the block B L 0 BL η is collected in Adjacent to the two ends in the column direction of the blocks BL 0 ~ B L η 1 1 | 1 of the configured data input and output circuit 5 2 while the data input 1 1 input and output circuit 5 2 External output to LS 1 1 3 6 is shown in the configuration of the memory fia · system of the present invention. 0 1 Here, an example of a memory 1 1 body system using a semiconductor memory of f 1 circle 1 circle 3 4 Explanation 〇1 1 1 0 is a billion-element chip. 4 The configuration of the memory chip 10 is the same as the configuration of one semiconductor memory 1 i selected from the semiconductor memories described in [S3 FIG. 1 1 FIG. 3 4 Set 0 1 1 I Memory chip 10 in 1 to form a memory grid array 5 1 Read • Write 1 1 circuit 5 2, input circuit 5 3 output circuit 5 4, synchronous circuit 5 5 1 1 and clock buffer 5 6 〇1 1 The paper standard is applicable to China National Standard (CNS) A4 specification (2 丨 OX 297 Mm) A7 B7 Employee's consumption cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs Du Printed Fifth, invention description (64) 1 ICPU 5 8 series output clock signal CK 〇 clock signal CK for 1 1 to memory chip Pulse signal OtL · Wt CLK 〇In the memory chip 1 1 1 0 Internal clock signal CLK is for reading and writing circuit 5 2 1 | Read and write please 1 | 0 fetching • Erlu 5 2 is synchronized internally The clock signal CLK moves first. Read 1 | Read 1 as 9. Back I. The clock signal No. 1 CK and the internal clock signal CLK are shifted by the same attention. 1 circuit matter 1 step 5 5 t remove 0 synchronization circuit 5 5 series output internal clock signal item and then 1 K filled with JC 0 part clock signal CK f is supplied to input circuit 5 3 and output script 〆, -1 circuit 5 4 0 input circuit 5 3 and output circuit 5 4 are synchronized Internally, V__ «1 1 pulse signal CK t action 0 1 1 I / 0 bus 5 7 is connected to memory chip 1 0 and CPU chip 1 1 5 8 0 The data is transferred to memory via I / 〇 bus 5 7 Chip order I 1 0 and CPU chip 5 8 0 1 1 I [Effects of the invention] 1 1 1 Try as described above »The semiconductor memory according to the present invention and the test circuit and data transmission system will produce the following effects 〇1 1 Set up multiple zone libraries »Set up local DQ lines extending in the row direction between the small blocks of the memory cell array 1 1 in each zone library The overall DQ line 0 extending in the column direction on the grid array, and then the input and output 1 materials are carried out through the local DQ line and the overall DQ line. Intermittently constitute 〇1 1 1 With such a configuration *, make the memory cell controller and row 1 1 decoder column decoder% DQ buffer 9 in each zone library adjacent to 1 1 paper wave of each memory cell array The standard is applicable to the Chinese National Standard (CNS) A4 (210X297mm) 0 Α7 Β7 S09657 V. Description of the invention (65) Because of the configuration on one side, it is a multi-bit type, clock synchronization type, regional library type semiconductor record In the 100 million body, the data transfer speed can be improved without increasing the chip surface area.

V shows the chip layout of the semiconductor memory according to the first reference example of the present invention. \ / 【Figure 2】 Detailed display of the chip layout in the district library of Figure 1. \ / 【Figure 3】 Show the second reference example of the present invention, the layout of the semiconductor memory chip

[Figure 4] Detailed display of the chip layout in the district library of FIG. ^ ^ [Figure 5] A simplified display of the chip layout of FIG. 1 "Printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 4: Figure 6] 1 Wafer layout diagram of a modification of the reference example. 4 Figure 7] The chip layout of Figure 6 is shown in detail. I " [FIG. 8] A chip layout diagram showing a modification of the first reference example in FIG. 1. Figure 9] The scale of this paper is applicable to the Chinese standard (CNS) Λ4 present grid (2 丨 0Χ 297mm)-flavor-A7 B7 5. Description of the invention (66) Detailed display of the wafer layout of Figure 8. v / [Figure 1 0] shows the chip layout of the semiconductor memory according to the first embodiment of the present invention. v / 【Figure 11】 Detailed display of the chip layout in the district library of Figure 10. V [Figure 1 2] shows an example of the switch configuration shown in Figure 11. 7 [Figure 1 3] A diagram showing an example of the configuration of a column decoder. v [Figure 14] An example of the structure of the display area library selection circuit. 17 [Figure 15] A diagram showing an example of the structure of the data input / output circuit. 1 / [Figure 16] Shows the main part of the structure of the test circuit. 7 [Figure 1 7] Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. b {Figure 18] A diagram showing an example of the configuration of the test switching circuit.

VyC Figure 1 9] Display the signal waveform in test mode. Figure 2 0] Display the signal waveform in test mode. This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (21〇X297 mm) (please read the notes on the back before filling this page)-^-A7 B7 Printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Description (67) 1 I vyt rgi Figure 2 1] 1 1 shows the chip layout of the semiconductor memory according to the second embodiment of the invention 1 1 Figure ο 1 I [A Please 1 Figure 2 2] Read 1 1 Read 1 Overview Show the chip layout of Figure 1 0. Back to the first Figure 2 3] i | Show the first modification of the chip layout of Figure 2 2 Figure 0 Matters 1 1 ”\ χ Figure 2 4] Fill in this 1 Detailed display Figure 2 3 Layout of the chip 〇 page Sw · * 1 1 ν [Figure 2 5] 1 1 shows the first modification of the chip layout of Figure 2 1 Figure 0 i | \ Λ Figure 2 6] Order I shows the chip of Figure 2 2 Layout 2nd Modification Figure 0 1 1 I VI mrr Figure 2 7] 1 1 | Detailed display of the chip layout of Figure 2 6 ΓΒΠ Figure 〇1 1 \ Λ ΓΒΊ Figure 2 8] 1 shows the second modification of the chip layout of Figure 2 1 Example ΓΒΠ Figure 〇1 1 '> [Figure 2 9] 1 I shows the third modification of the chip layout of Figure 2 2 IWI Figure 〇1 | Figure 3 0] 1 1% shows the chip layout of Figure 2 9 in detail 9 1 1 α ΓΈΓΤ Figure 3 1] 1 1 shows the third modification of the chip layout of Figure 2 1 囵 〇1 1 Figure 3 2] 1 1

This paper scale is applicable to the Chinese National Standard (CNS) Λ4 specification (210X 297mm) A-ΊΟ-A7 S09657 Five'Invention Description (68) B7 The layout of the chip shown in Figure 2 2 printed by the Staff Consumer Cooperative of the Central Bureau of Standards The fourth modification example. α · ... Fig. 3 3] Detailed display of the wafer layout of Fig. 3.2. [Fig. 3 4] A fourth variation of the wafer layout of Fig. 2 1 is displayed. □ sa 圚 3 5] shows the data transmission system of the present invention 1 M.I Figure 0 1 Figure 3 6 shows the memory system of the present invention 0 y Figure 3 7] shows the layout diagram of the past semiconductor memory wafers. [Explanation of symbols] 1 0 Memory chip 1 1 — 0 11 — 3 — — Area library (main area library) 1 1 — 0 — # 0, 11 — 0 — # 1 1 1 1-3-# 0 1 1 — 3-# 1: Sub-zone library 1 2 1 2 a * 12b-data input / output (I / 0) range 1 3 1 3 a ~ 13d-data bus 1 4 data line pair 1 5 9 1 5 -0 ~ 1 5 — 3-: Column selection line 1 6 Column selection switch 1 7) 1 9 a, 19b __; Character line I 1 —- ^ 1.---—-I —1, ^! 1 ----- I.---I (please read the precautions on the back before filling in this page) 18 -----: DQ line applies to Chinese paper standard (CNS) Λ4 specification (210X297mm) for this paper standard_ u Central Ministry of Economic Affairs Bureau of Standards and Staff Consumer Cooperation Du Yinjia A7 B7 V. Description of the invention (69) 18a -----: partial DQ line pair 18b -----: overall DQ line pair 2 0a, 20b, '21 switch 2 2- ----: control line 23- 1 ~ 23- N--: pre-decoder 24- 1 ~ 24- MU decoder 25- 1 ~ 25-1 ^-: block 2 6-0 ～ 2 6 — 7 ---: NOR circuit 27 — 0 to 27-7, T〇1, T〇2, T11, T12, T21, T22, T31, T32, TG0 ~ TG3 1--: changeover gate 2 8 — 0 ~ 2 8-7 ---: latch circuit 2 9 — 0 ~ 2 9 — 7 ---: AND circuit 3 0 -----: output latch circuit 3 1 -----: output circuit 3 2 -----: output buffer 3 3 -----: NAND circuit 3 4 --- -: Exclusive OR circuit 3 5 -----: Color register 3 6 -----: Exclusive NOR circuit 3 7 -----: Switch circuit section 3 8 -----: Serial Selector 4 1 a, 4 1 b ---: switch array 42a, 42b ---: line decoder This paper scale is applicable to China National Standard (CNS) A4 specification (210X297 public t) _ p _ ---- ^ --- κ I--f 'clothing-- (Please read the notes on the back before filling this page)

, 1T S09657 V. Description of invention (70) A7 B7 Printed by the Employee Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs 4 3 = Column decoder 4 4 a> 4 4 b-: Character line 4 5 a »4 5 b- : Data line 4 6 ai 4 6 b--• switch 4 7 a »4 7 b-: register 4 8 a> 4 8 b-: column selection switch 4 9 = column selection line 5 0 — 0 5 0-~ η ---: Local DQ line pair 5 1 — 0 5 1--η ---: Overall DQ line pair 1 0 0: Test switching circuit 2 0 0: Test output circuit CAL »CAR-- : Memory grid array (Small block: CAC grid array controller RD row decoder CD 0 c D 3-: Column decoder DQDQ buffer BL a BL d-: Middle block SEL--Block selector SA sense Sense amplifier N 1 N 4 one-one: N channel Μ 0 S transistor DBSAMP • —: data bus sense amplifier DB w BF one-: data bus write buffer CI 1 CI 7-: synchronous inversion Device LA latch circuit (please read the precautions on the back before filling this page) The Zhang scale applies the Chinese National Standard (CNS) A4 specification (210X 297mm)-3〇9β57 V. Description of invention (Ή) EX -----: Exclusive 〇R circuit ---- ^ --- i- --〆 \ ------ Subscribe ------- ξ I (Please read the precautions on the back before filling in this page) The paper standard printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs is applicable to the Chinese national standard (CNS) A4 specification (2l〇X 297mm) -lr-

Claims (1)

309657 B8 C8 D8 VI. Patent application No. 85112087 Patent application Chinese application Patent scope amendment Amended in April 1986 (Please read the precautions on the back before filling this page) 1 · A semiconductor memory, its characteristics It is equipped with a memory chip, and a plurality of libraries arranged on the memory chip, and a data input and output range arranged on the memory chip to perform data input and output of a plurality of digits, and are commonly provided in the plurality of regions, extended by The row direction is the data bus that presents the data path of the complex number between the aforementioned plural bank and the aforementioned data input / output range. The aforementioned plural bank is composed of a self-memory array and is arranged in the row direction 2 small blocks, the sense amplifiers arranged between the two small blocks and the character lines arranged on the memory cell array, and the data lines 'column selection lines' are arranged in the plural middle blocks in the column direction, And at least one of the two ends arranged in the column direction is 'a column decoder connected to at least one of the column selection lines' One of the two ends of the above-mentioned row direction printed and arranged by the Central Bureau of Standards 'Staff Consumer Cooperative' is set in each of the above-mentioned middle blocks, and a row decoder connected to the plural of the above-mentioned character lines > The other of the two ends in the row direction 'in each of the middle blocks, one complex DQ buffer is provided' and one of the two ends in the row direction 'control the complex bits The operation of reading the data and the writing of the aforementioned plural digits of paper. The paper standard is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) 309657 as B8 · C8 ___ D8 6. The grid array for patent application The controller is composed of (please read the precautions on the back before filling in this page) and the above-mentioned complex number banks are independent of each other, and perform the above-mentioned plural-digit data reading operation or the aforementioned plural-digit data writing operation To be composed. 2. The semiconductor memory according to item 1 of the patent application scope, wherein each of the plurality of bank libraries is provided with a bank library selection circuit arranged on the other of the two ends in the row direction, and the bank library selection circuit is When reading the plural data or writing the plural data, the one of the plural banks is connected to the data bus, and the remaining banks are removed from the data bus. Cut off. 3. The semiconductor f5 memory body as claimed in item 1 of the patent scope, wherein the plural bank of the plural numbers exists in the row direction, and there are two in the row direction, and four in the row direction. Printed by the Employees ’Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 4 · For example, the semiconductor memory of item 1 of the patent scope, where 'is located between the two small blocks and has a DQ pair that extends in the aforementioned row direction, and the aforementioned DQ pair The sense amplifier and the DQ buffer are connected to each other. 5. The semiconductor memory as claimed in item 1 of the scope of patent application is arranged between the two small blocks and has a row selection switch connected to the row selection line. 6. The semiconductor memory according to item 1 of the patent application scope "wherein" the aforementioned data input / output range is arranged at one of the two end portions in the row direction of the billion chip. This paper scale is applicable to the Chinese National Standard Falcon (CNS) A4 specification (210X297 mm). 309657 C8 printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. ____ D8 VI. Patent application scope 7 · If applying for patent scope item 1 In a semiconductor memory, the data input / output range includes a complex data input / output circuit for simultaneously inputting and inputting the complex data. 8. The semiconductor memory according to item 1 of the patent application scope, wherein the data bus is located at the center of the billion chip and extends in the row direction, and the plural bank is arranged in the foregoing of the data bus Both sides of the direction of travel. 9. The semiconductor memory as claimed in item 1 of the patent scope, wherein, when each of the plural bank has a plural row decoder, the two row selection lines adjacent to each other of the row selection lines pass through different row decoders Take control. 1 〇. As claimed in the first patent scope of semiconductor memory, wherein the row decoder selects any one of the two small blocks mentioned above and from the character line of the selected small block, select 1 Character line. 1 1. A semiconductor memory, which is characterized by having a memory chip 100 million and a plurality of sub-region libraries arranged on the memory chip, and a memory bank arranged on the memory chip, which is used to perform data input and output of plural bits The range of data input and output is common to two or more sub-zones in all the sub-zones that constitute the aforementioned plural main zone library, extending in the column direction, and presenting the aforementioned plural primary zone library ’s secondary zone library and the aforementioned The complex data bus of the data path of the complex number between the data input and output ranges, and the secondary area library of the complex number is composed of a self-recorded billion grid array, arranged in the two small blocks in the row direction, and arranged in the aforesaid The sense amplifiers and their configuration between the two small blocks (please read the precautions on the back before filling in this 1) Binding, Ordering, — This paper size is applicable to China National Standards (CNS) Α4 specifications (2 丨 Ο X 297 C) -3-A8 B8 C8 · D8 printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 6. The patent line applies to the character line, data line, row selection line, and the A plurality of middle blocks in the column direction, at least one of two end portions arranged in the column direction, a column decoder connected to at least one of the column selection lines, and two arranged in the row direction One of the end portions, one for each of the aforementioned middle blocks, connected to the plural row decoder of the word line > and the other of the two end portions arranged in the aforementioned row direction, in each of the aforementioned Each block is provided with a complex DQ buffer and one of the two ends arranged in the row direction to control the read operation of the complex bit data and the write operation of the complex bit data The grid array controller is composed of the complex sub-regions that are independent of each other, and are configured to perform the data reading operation of the complex digits or the data writing operation of the complex digits. 1 2. The semiconductor memory as claimed in item 11 of the patent application, wherein each of the plural secondary bank is equipped with the bank select circuit arranged on the other of the two ends in the row direction, the bank The selection circuit selects two or more sub-region libraries out of all the sub-region libraries constituting the above-mentioned main block when performing the above-mentioned plural-digit data reading or the above-mentioned plural-digit data writing operations. The selected secondary library is connected to the aforementioned data bus, so that the unselected secondary library is cut off from the aforementioned data bus. Β 1 3. For the semiconductor memory of patent application item 12, the paper size is applicable to China National Standard (CNS) Μ Specification (210x297mm) (Please read the precautions on the back before filling in this page) Binding · Order 309657 A8 B8 C8 D8 々 In the scope of patent application, output in the sub-block selected above The incoming data is between the aforementioned selected sub-library and the aforementioned data input / output range through different aforementioned data busses. (Please read the precautions on the back and then fill out this page) 1 4. If the patent application is in the scope of item 11 of the semiconductor memory device, which is arranged between the two small blocks mentioned above, with the DQ line extending in the direction of the line Yes, the DQ line pair connects the sense amplifier and the DQ buffer to each other. 15. The semiconductor memory as claimed in item 11 of the patent scope, which is arranged between the two small blocks and has a column selection switch connected to the column selection line. 16. As stated in the patent application scope item 11 of the semiconductor memory module, where the number of the secondary sub-zones constituting the main bank of each complex number is η, the data input / output range has the order Η times of the data of the complex digits, and the complex data that is output at the same time is output to and from the circuit. Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. 7. For example, the semiconductor memory of item 11 of the scope of patent application, where 'the aforementioned plural sub-region libraries that constitute the aforementioned plural main-region libraries, have plural row decoding At the time of the decoder, the two adjacent column selection lines among the column selection lines are controlled by different column decoders. 18. The semiconductor memory as claimed in item 11 of the patent scope, in which the aforementioned row decoder selects any one of the aforementioned two small blocks, and selects 1 from the character line of the selected small block Character line. 1 9. As for the semiconductor memory according to item 11 of the patent application scope, where the aforementioned data input / output range is in the central part of the aforementioned memory chip, the Chinese National Standard Falcon (CNS) A4 specification (210X 297 %) -5-________ D8 VI. Scope of patent application The aforementioned line direction is configured to be longer. 2 0. The semiconductor memory as claimed in item x 9 of the patent scope, in which the aforementioned data bus is on both sides of the aforementioned row direction of the aforementioned data input / output range, each extending in the aforementioned row direction. 2 1. The semiconductor memory as claimed in item 2 of the patent scope, where the 'major bank of the plural bank is composed of the secondary bank of the plural bank is arranged on both sides of the row direction of the data bus. 2 2 · Semiconductor memory as claimed in item 21 of the patent scope, where 'the plural sub-region libraries constituting the plural main-region library exist in the row direction, and there are 2 in the column direction, a total of 8 Person. 2 3 · Semiconductor memory as claimed in item 11 of the scope of patent application, where 'the aforementioned data input / output range is arranged at one of the two ends in the aforementioned row direction of the aforementioned billion chip' 2 4 · if applying for a patent The semiconductor memory device according to item 23 of the scope, wherein the data bus is located on one side of the row direction of the data input / output range, each extending in the row direction. Du Printed by the Ministry of Economic Affairs, Central Bureau of Standards and Staff Consumer Cooperation (please read the precautions on the back and then fill out this page) 2 5 · If you are applying for the patent scope item 24 of the semiconductor record, which constitutes The aforementioned secondary bank is arranged on both sides of the aforementioned data bus in the aforementioned row direction. 2 6. The semiconductor memory as claimed in item 25 of the patent scope, wherein the plurality of sub-region libraries constituting the plurality of main-region libraries exist in the row direction, and there are 2 in the column direction. Person. 2.7. A kind of semiconductor memory 'characteristics of having a billion-memory chip, and a plurality of memory banks arranged on the aforementioned memory chip' and the paper-based paper size arranged on the aforementioned memory chip are applicable to the Chinese National Standard (CNS) A4 specification (210X 297mm> ABCD Ministry of Economic Affairs Central Standards Bureau Staff Consumer Cooperative Printed and Patented Scope Films are data input and output ranges that perform multiple-digit data input and output, and are shared with the aforementioned multiple district libraries, extended in the list Direction, the data bus that presents the data path of the complex number between the aforementioned plural bank and the aforementioned data input / output range, the aforementioned plural bank is composed of a self-memory array, and is arranged in the row direction 2 A small block, a sense amplifier arranged between the two small blocks, and a character line, a data line, and a row selection line arranged on the memory cell array are arranged in a plurality of middle blocks in the row direction, and At least one of the two ends arranged in the column direction, connected to at least one of the column selection lines, and the column decoder arranged in the row direction One of the two ends is provided with one in each of the above-mentioned blocks, a row decoder connected to the plural of the word lines, and a DQ buffer disposed on the other of the two ends in the column direction , And the other of the two end portions arranged in the row direction 'is composed of a grid array controller which controls the reading operation of the plural-digit data and the resource operation of the plural-digit data, and each of the plural district libraries , It is independent of each other 'to carry out the data reading operation of the aforementioned complex digits or the data writing of the aforementioned complex digits. "In the above, each of the plural districts mentioned above, the paper standard uses the Chinese National Standard (CNS) Α4 specifications (210X297 mm) ------ ^-{装 ------ 定 (Please first Read the precautions on the back and then fill out this page) A8 B8 C8 D8 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy VI. Patent Application Scope 1 1 Equipped with each configuration. W-Describe block Describe 2 small blocks Interval 1 1 Longer than ^ r- The line direction is connected to, /. Describe the local DQ line pair of the sense amplifier 1 1 I and the overall DQ line pair connected to the aforementioned buffer. Please read 1 1 I 2 9 ♦ If Please refer to the number 28 of the patent scope of the semiconductor memory device, which is read back 1 1 1 »More equipped with the attention to the configuration of the description of the local DQ line pair and the description of the overall DQ line pair 1 Switcher between 1 1 Item 1 I then 1 3 0 If you want to ask for the semiconductor memory of item 2 9 of the patent scope> It fills in the package I. The relationship is made up of N-channel MOS transistors. Page 1 1 3 1 If you want to connect The semiconductor memory 9 of the patent scope No. 2 7 is provided with 1 I I. The plural bank is arranged at the two ends 1 in the row direction of the row I. The other- * bank selection circuit 1 I Department of Library Selection Circuit Perform the reading of the data of the plural digits 1 1 and the writing of the data of the plural digits. W · Describe the plural area 1 1 A block in the block is connected to the narration data bus Residual area library white> 刖 1 The data bus is cut off by 0 Ί 3 2 If the semiconductor scope of the patent scope item 2 7 is claimed, ηΛζ., 1 of which constitutes the arbitrarily complex number of arbitraries are described in the narration There are 2 in the row direction. ·-刖 1 \ There are 2 in the column direction. There are 4 in total. 1 1 3 3 * If you want to apply for the semiconductor record of the patent scope item 2 7 of which 1 1 i Between the two small blocks 9 There is a column selection switch connected to the column selection line 1 1 〇1 1 3 4 • If the patent of the patent scope item 2 7 of the semiconductor memory is in 1 I. W- The range of data input and output is configured in Before said memories of said wafer Column 1 a wave-scale paper suitable China National Standard (CNS) A4 size (210X297 mm) 3〇9β57 il C8, D8 six patent applications two end portions in the range of one of those directions. 3 5. The semiconductor memory as claimed in item 27 of the patent scope, wherein the data input range is in the central part of the memory chip and extends in the row direction. 36. The semiconductor memory as claimed in item 27 of the patent scope, in which the aforementioned data input / output range is a complex data output / input circuit for simultaneously outputting / inputting the aforementioned plural digit data. 37. The semiconductor memory as claimed in item 27 of the patent scope, wherein the data bus is located at the central part of the memory chip and extends in the row direction, and the plural bank is arranged in the data bus Those on both sides of the aforementioned row direction. 3 8. The semiconductor memory device as claimed in item 27 of the patent scope, wherein, when each of the complex bank includes a complex column decoder, the complex column decoder is arranged in the row direction to control the decoding of the complex column The groups of the aforementioned selection lines of the device are completely separated from each other. Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling in this page) 3 9. For example, the semiconductor memory of item 27 of the patent scope, where the aforementioned line decoder selects the aforementioned two Any one of the small blocks of the small block, and one character line is selected from the character lines of the selected small block. 4 〇. The semiconductor memory according to item 2 7 of the patent scope, wherein the at least one column decoder has the function of selecting one of the column selection lines and the second of the column selection lines The function of more than one row selection line, the two functions are switched by the control signal. 4 1. A semiconductor memory device, which is characterized by a memory chip 'and a main area library composed of a plurality of secondary area libraries arranged on the aforementioned memory chip' and the size of this paper is in accordance with China National Standards (CNS) .Vt specifications (210X297 Mm) _ Q _ A8 B8, C8 D8 printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 6. The scope of patent application is configured on the aforementioned memory chip, and the data input and output range for performing data input and output of multiple digits, and common settings The two or more sub-regions of all the sub-regions constituting the aforementioned plural main-region library are extended in the column direction, presenting the aforementioned plural digits between the aforementioned plural-primary library and the data input / output range The plural data bus of the data path of the element, the aforementioned secondary bank of each plural, is composed of a self-memory array, arranged in the two small blocks in the column direction, and the sense amplifier arranged between the two small blocks. And the character lines, data lines, and row selection lines arranged on the memory cell array are arranged in the plural middle blocks in the row direction, and 2 arranged in the row direction One of the two ends is a column decoder connected to at least one of the column selection lines, and one of the two ends arranged in the row direction is provided with one in each of the middle blocks and connected to the word The complex row decoder of the element line and the complex DQ buffer arranged on the other of the two ends in the column direction, and the other one arranged on the other of the two ends in the row direction, control the complex bits The data reading operation and the complex array data writing operation are constituted by a grid array controller, and the complex secondary libraries are independent of each other, and perform the complex data reading operation or the complex The digital data is written to constitute the action. 4 2. For the semiconductor memory device with the scope of patent application item 41, the standard of this paper is in accordance with Chinese National Standard (CNS > Λ4 present format (210X297mm) (please read the notes on the back and fill in this page) Binding · Order 10-Printed by ABCD Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 6. Patent Application Scope 1 I in y Each of the multiple sub-divisions of the library 1 1 is equipped with the configuration of each > /. Between the aforementioned two cell frf blocks 1 1, extending in the direction of the description line > Local DQ 1 1 connected to the description amplifier 1 Please 1 I line pair ϊ Read 1 1 and the block in the description » Extend to -1 Describing the column direction> Connect the Describing Partial Read Back 1 IDQ line pair and Describing the overall DQ line pair of the DQ Buffer Attention 1 4 3 • For example, please apply for the patent scope item 4 2 semiconductor Memory 115. Its matters are more 1 1 1 more Equipped with, \ j. Fill out the switch between the local wire pair and the overall DQ wire pair. 0 Page 1 1 4 4-If you want to apply for the patent scope item 4 3 of the semiconductor memory 100 9 1 1 The aforementioned open relationship is made up of N-channel MOS transistors. I 1 4 5 If the semiconductor memory of the patent scope item 41 is applied for, please refer to Item I for the description of the plural! I library It is configured in the .u /. The two ends of the column direction I 1 I of the other side of the IBS. Library selection circuit 1 1 I The above-mentioned library selection circuit is used to perform the reading of the data of the complex number 1 Select the two or more sub-region libraries of all the sub-region libraries that constitute the main block of the multi-digit number in the action of writing the multiple-digit data write operation. This option is selected. Describe the sub-repositories that are not selected in the data bus 1 The above data bus is cut off. 1 I 4 6 • If you want to apply for the semiconductor memory of the patent scope item 4 5 1 1 I I input and output data in the sub-blocks selected above through different 1 1 ,, Λ Describing the data bus> going to and from the aforementioned sub-repository and .Λ, /. Describing the data input 1 1 between the in and out ranges 〇1 1 4 7 * If the patent scope is claimed to be the 4th Item 1 of the semiconductor memory t 1 1 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) Printed by the Employees ’Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 309657 B8 D8 Between the two small blocks, there is a column selection switch connected to the column selection line. 4 8. The semiconductor memory as claimed in item 41 of the patent scope, in which, when the number of the secondary sub-banks constituting the main bank of each complex number is η, the data input / output range has the above-mentioned complex Η times the data of the digital data, and the complex data that is output at the same time is output to and from the circuit. 4 9. The semiconductor memory as claimed in item 41 of the patent scope, in which each of the plurality of sub-region banks constituting the above-mentioned main bank of plural numbers has a row decoder of plural numbers, the decoder of the row of plural numbers is Arranged in the row direction, the groups of the column selection lines that control the plural column decoders are completely separated from each other. 50. The semiconductor memory as claimed in item 41 of the patent scope, wherein the row decoder selects any one of the two small blocks and selects 1 from the character line of the selected small block "Character line" 5 1. The semiconductor memory as claimed in item 41 of the patent scope, wherein the data input / output range is located in the central part of the memory chip and is arranged to be longer in the row direction. 5 2. The semiconductor memory as claimed in item 51 of the patent scope, wherein the data bus is on both sides of the row direction of the data input / output range, each extending in the row direction. 53. The semiconductor memory as claimed in item 52 of the patent application scope, wherein the plural primary bank constituting the plural bank is arranged on both sides of the row direction of the data bus. (Please read the precautions on the back before filling in this page) This paper scale is applicable to China National Standard · (CNS) Λ4 specification (210Χ297mm) 12-6. Patent application scope 5 4 · If applying for patent scope item 5 3 The semiconductor memory device, in which the plural sub-region libraries that make up the plural main-region library exist in the row direction, and there are two in the column direction, a total of eight. (Please read the note on the back first Please fill in this page for details) 5 5. For the semiconductor memory of claim 41, the data input / output range is one of the two ends in the row direction of the memory chip. 5 6. The semiconductor memory device as claimed in item 55 of the patent scope, in which the aforementioned data bus is on one side of the aforementioned column direction of the aforementioned data input / output range, each extending in the aforementioned column direction. 5 7 · If applying The semiconductor memory according to item 56 of the patent scope, in which the 'sub-repositories constituting the plural main-region libraries are arranged on both sides of the row direction of the data bus. 5 8. If a patent is applied for The semiconductor memory of item 57 of the scope, wherein the plurality of sub-regions that constitute the plurality of main-region libraries are four in the row direction and two in the column direction, and a total of eight. The Bureau of Standards and Staff's Consumer Cooperative printed 5-9 kinds of semiconductor memory, which is characterized by a memory chip, a main area library composed of a plurality of auxiliary area libraries arranged on the memory chip, and a memory chip arranged on the memory chip to perform The data input / output range of digital data input and output is common to two or more sub-zones of all the sub-zones that constitute the aforementioned plural main zone library, extending in the row direction and presenting the aforementioned plural main zone library The complex data bus of the data path of the complex number between the secondary library and the data input / output range, the secondary library of the complex number is composed of a self-memory array, and is arranged in the two The paper scale adopts the Chinese National Standard (CNS) A4 specification (210X297mm) 13-Α8 Β8 C8 D8 ^ 09657 Sixth, apply for a small block of patent scope, configured in the above 2 The sense amplifiers between the small blocks and the character lines arranged on the memory cell array, the data lines 'column selection lines' are arranged in the plural middle blocks in the column direction, and the two ends arranged in the column direction One of the sections' the column decoder connected to at least one of the column selection lines' and the one arranged at the two ends in the row direction 'are provided in each of the middle blocks and connected to the character line The complex row decoder ί and the complex DQ buffer disposed on the other one of the two ends in the column direction, and the other one disposed on the other two ends in the row direction, control the complex bit data The read operation and the write operation of the plural data are composed of a grid array controller, and the plural data bus is located on both sides of the row direction of each data input and output range, forming the main part of the plural The plural sub-region libraries of the district library are arranged on both sides of the row direction of each data bus, and the plural sub-region libraries of the plural regions are independent of each other, and read the data of the plural digits For the aforementioned or plural bits of data write operation is to be composed of persons. 60. The semiconductor memory according to item 59 of the patent application scope, wherein each of the plurality of secondary banks is provided between the two small blocks constituting each of the middle blocks, extending in the row direction, The local DQ wire pair connected to the aforementioned sense amplifier, the size of this paper is applicable to the Chinese National Standard (CNS) Α4 specification (210Χ297mm) ---------- installed-(please read the precautions on the back before filling in This page), * τ Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A8 B8 C8 D8 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy VI. The scope of patent application and the above middle block are extended in the above listed directions, connecting the above The local DQ line pair and the overall d Q line pair of the aforementioned DQ buffer. 6 1 • The semiconductor memory device as claimed in item 60 of the patent scope, which further includes a switch disposed between the local wire pair and the overall DQ wire pair. 6 2 The semiconductor memory as claimed in item 61 of the patent scope, wherein the aforementioned open relationship is constituted by an N-channel MOS transistor. 6 3. The semiconductor memory device as claimed in item 59 of the patent scope, wherein the plurality of sub-region libraries are arranged at the other of the two ends in the column direction, the region library selection circuit The selection circuit selects two or more sub-regional libraries among all the sub-regional libraries constituting the above-mentioned main block when performing the above-mentioned plural-digit data reading operation and the aforementioned multi-digit data writing operation The selected secondary library is connected to the aforementioned data bus, so that the non-selected secondary library is disconnected from the aforementioned data bus. 64. The semiconductor memory as claimed in item 63 of the patent scope, wherein in the selected sub-block, the input and output data are passed to and from the selected sub-block library and the foregoing through different aforementioned data buses Those whose data is input or output. 65. The semiconductor memory as claimed in item 59 of the patent scope, which is arranged between the two small blocks and has a column selection switch connected to the column selection line. 6 6. The semiconductor memory as claimed in item 59 of the patent scope, in which the number of the sub-regions of the complex constituting the main bank of the plural is the paper wave scale and the Chinese National Standard (CNS) Λ4 specification is applied (21 〇 > < 297mm) -------- 1 Pack— (please read the precautions on the back before filling out this page) Order -'-., '-Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs Α8 Β8 C8 D8 6. When applying for the patent scope η * The aforementioned data input / output range is the data having η times the data of the aforementioned plural digits, and the plural data input / output simultaneously into the circuit. 6 7. The semiconductor memory as claimed in item 59 of the patent scope, in which 'the respective sub-region banks of the aforementioned plural number constituting the main bank of each plural number, and the plural row decoders having plural row decoders are Arranged in the row direction, the groups of the column selection lines that control the plural column decoders are completely separated from each other. 6 8 · Semiconductor memory as claimed in item 5-9, wherein the row decoder selects any one of the two small blocks and selects 1 from the character line of the selected small block Character line. 6 9. The semiconductor memory as claimed in item 59 of the patent scope, wherein the plurality of sub-region banks constituting the plurality of main-region banks exist in the row direction, and there are 2 in the column direction. Person. 7 0. The semiconductor memory as claimed in item 59 of the patent scope, wherein the main bank of each complex number is synchronized with an external clock to perform the data reading operation of the complex digits and the data writing of the complex digits Activator 〇7 1. A test circuit for testing memory cell arrays with self-plurality blocks and memory cells in at least one of the aforementioned plural blocks, and writing data into blocks simultaneously The input means' and the test circuit of the semiconductor memory of the scratchpad which holds the data written in the at least one block in advance is characterized in that when the test mode is provided, the memory cell of the memory cell array is written into the memory cell Each paper wave scale uses the Chinese National Standard Falcon (CNS) Α4 specification (2 丨 0 > < 297mm) -------— {installed- (please read the precautions on the back before filling in this page) Order L 3〇〇β57 AS B8 C8. D8 VI. Patent application scope register Data, and is the test mode writing and reading means for reading the data of the aforementioned memory cell, (please read the precautions on the back before filling out this page) and write through the data held in the aforementioned register and the aforementioned test mode -Reading means, comparing the data read from the memory cell, judging the goodness of the semiconductor memory based on the comparison result, outputting the comparison means showing the result of the goodness, and the data to be output from the comparison means Is a test output means for output to the outside of the semiconductor memory. 7 2 ·-A test circuit for testing memory grid arrays consisting of self-plural blocks and n-element blocks in n blocks (n is a natural number of 2 or more) of the aforementioned complex blocks, and write simultaneously A block writing method for storing n-bit data and a test circuit for a semiconductor memory that temporarily stores the n-bit data written in the n blocks in advance is characterized by having a test mode At the same time, the n-bit data held in the register is written to the memory cell of the memory cell array at the same time, and is a test mode writing and reading means for reading the n-bit data of the memory cell, Printed by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs and written via the aforementioned η-bit data held in the aforementioned register and the aforementioned test mode writing * reading means' and comparing the aforementioned η-bit data read from the aforementioned memory cell, Based on the comparison result, the goodness of the semiconductor memory is determined, a comparison means for outputting 1-bit data showing the result of the goodness, and the 1-bit data output from the comparison means are output External testing of the semiconductor memory by means of the output "73 as patent application range of the test circuit, Paragraph 72, wherein, the sheet scale applies China National Standard (CNS) Α4 Specification (2 0 &gt!; < 297 mm) 17-Printed by the Employees Consumer Cooperative of the Central Bureau of Economics of the Ministry of Economic Affairs 6. The scope of the patent application is equipped with a latching means to maintain the n-bit data showing the aforementioned comparison results of the aforementioned comparison means, and When the result is unsatisfactory, the n-bit data of the latching means are sequentially supplied to the switching means of the test output circuit. 7 4 • The test circuit as claimed in item 7 2 of the patent application scope, in which the semiconductor memory system performs η-bit type semiconductor memory that simultaneously outputs and inputs η-bit data. The semiconductor memory system has a normal operation mode and has For the n output pads used, the test output circuit is connected to one of the n output pads. 7 5. A data transmission system, which is characterized by a plurality of blocks arranged in the column direction, each block is a switch array composed of a plurality of switches arranged in a matrix, and a row adjacent to the aforementioned switch array The end of the direction is arranged to select the row decoder of the row of the switch array, and the end of the row direction adjacent to the switch array is arranged to extend the local DQ line in the row direction and connected to the switch array The complex switch 'leads the data to the data line of the local DQ line, and is formed on the complex block, is extended in the column direction and is arranged, one end is connected to the overall DQ line of the local DQ line, and is adjacent to the foregoing The end of the row direction of the plural block is arranged, the row decoder of the row of the switch array of the plural block is selected »and the end of the row direction adjacent to the plural block is arranged and connected The data input / output circuit that performs data input / output at the other end of the aforementioned overall DQ line. The table paper scale is applicable to China National Standard (CNS) Λ4 specification (210X297mm) 10101-(please read the precautions on the back before filling out this page) Order '' J --- Printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Install A8 B8 C8. ________ D8 VI. Patent application scope 7 6 For example, the data transmission system of patent application scope item 7 and 5, in which the selector switches arranged in the aforementioned switch array are provided. 7 7. A data transmission system as claimed in item 75 of the patent application scope, which includes a row selection switch connected to the end of the switch array and arranged, and the row selection switch is connected to the row selection line. 78. The data transmission system as claimed in item 7 of the patent scope, which includes a register connected to the end of the switch array and arranged, the register is connected between the data line and the local DQ line By. 7 9. As in the data transmission system of patent application item 75, in which the aforementioned data input / output circuit is the simultaneous input / output of multiple digit data. 8 0 ·-A kind of memory system, which is characterized by a memory chip, a complex number library arranged on the memory chip, and a memory chip arranged on the memory chip, synchronized with the clock signal, for performing data input and output of complex numbers The data input / output range is common to the data bank that is set in the aforementioned plural number bank, extends in the row direction, and presents the data path of the plural number bit between the aforementioned plural number bank and the aforementioned data input / output range, and The CPU chip of the pulse signal, the I / O bus that connects the memory chip and the CPU chip to each other, and each of the plural bank libraries are composed of a self-recorded billion grid array, and are arranged in the two small blocks in the row direction. The sense amplifiers arranged between the two small blocks, and the word lines, data lines, and row selection lines arranged on the memory cell array are arranged in the plural middle blocks in the row direction, ----- -.-- i 袭 ------ 1Τ ------ ^ | (Please read the precautions on the back before filling in this page) This paper scale is applicable to the Chinese National Standard (CNS) Λ4 specification (210Χ297mm ) -19-A 8 B8 · C8 _ D8 _ 6. Scope of patent application and at least one of the two ends arranged in the column direction, a column decoder connected to at least one of the column selection lines, and 2 arranged in the row direction One of the two ends is provided with one in each of the middle blocks, and a row decoder connected to the plural of the word line and the other of the two ends arranged in the row direction are provided in each of the middle zones Each block is provided with a complex DQ buffer and one of the two ends arranged in the row direction to control the reading operation of the complex bit data and the writing operation of the complex bit data The array controller is configured, and each of the complex bank is independent of each other, and is configured to perform the data reading operation of the complex number or the data writing operation of the complex number. Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling in this page) 8 1. A memory system, which is characterized by a memory chip and a plurality of sub-districts located in the aforementioned memory chip The main area library constituted, and the data input / output range which is arranged on the aforementioned memory chip and is synchronized with the clock signal to perform the data input and output of the complex digits, and is commonly set in all the auxiliary area libraries constituting the aforementioned complex main area library Among the two or more sub-zones, extending in the row direction, the complex data bus of the data path of the aforementioned plural digits between the aforementioned sub-zone of the plural primary zone and the aforementioned data input / output range, and generating the aforementioned The CPU chip of the clock signal, the I / ◦ bus that interconnects the memory chip and the CPU chip, and each of the plural sub-region libraries are composed of self-memory arrays and are arranged in the two columns in the row direction The paper scale is applicable to Chinese National Standard (〇 奶) 4 specifications (2 丨 0 > < 297mm) _2 () _ ABCD Ministry of Economy Central Standards Bureau Employee Consumer Cooperative Printed, patent-applicable small blocks' sense amplifiers arranged between the aforementioned two small blocks, and arranged on the aforementioned memory cell array Character line, data line, column selection line, at least one of the two middle blocks arranged in the column direction, and at least one of the two ends arranged in the column direction, connected to at least one of the column selection lines A column decoder, and one of the two ends arranged in the row direction, one for each of the middle blocks, a row decoder 9 connected to the plural of the word line, and a row decoder 9 arranged in the row direction The other of the two ends is provided with a complex DQ buffer in each of the aforementioned middle blocks, and one of the two ends arranged in the row direction controls the reading operation of the aforementioned complex bit data It is composed of the grid array controller of the writing operation of the complex number data, and the sub-libraries of the complex numbers are independent of each other, and perform the data reading operation of the complex number or the complex number. Be added to the material constituting the write operation by. 8 2. A kind of memory system, which is characterized by a memory chip, a complex area library arranged on the memory chip, and a data chip arranged on the memory chip, synchronized with the clock signal to execute data input and output of complex digits The I / O range 'and the common set in the aforementioned plural bank, extending in the row direction, the data bus that presents the aforementioned plural bit data path between the aforementioned plural bank and the aforementioned data input / output range, and generates the aforementioned clock The signal CPU chip 'and the I / 0 bus that interconnects the aforementioned memory chip and the aforementioned cp U chip. This paper standard is applicable to the Chinese National Standard (CNS) A4 specification (210X29? Public Radio) (please read the notes on the back first Fill in this I) again. X 21 7 5 6 05 ο 3 ABCD Printed by the Central Standards Bureau, Ministry of Economic Affairs, Consumer Cooperatives. 6. The range of patent applications for each of the aforementioned plural districts is a self-memory array structure. Two small blocks in the column direction, a sense amplifier arranged between the two small blocks, and a character line 'data line arranged on the memory cell array, a row Line selection, at least one of a plurality of middle blocks arranged in the column direction and at least one of two ends arranged in the column direction, a column decoder connected to at least one of the column selection lines, and a row arranged in the row One of the two ends in the direction is provided with one in each of the aforementioned middle blocks, a row decoder j connected to the plural of the word line, and the DQ of the other of the two ends disposed in the column direction The buffer is composed of a grid array controller arranged at the other of the two end portions in the row direction to control the reading operation of the complex bit data and the writing operation of the complex bit data, and Each complex bank is independent of each other, and is constructed by performing the above-mentioned plural-digit data reading operation or the aforementioned plural-digit data writing operation. 8 3. A memory system, which is characterized by a billion-memory chip, a main area library composed of a plurality of sub-area libraries arranged on the aforementioned memory chip, and a memory chip arranged on the aforementioned billion-chip, synchronized with the clock signal for execution The data input / output range of the data input and output of the plural digits, and the two or more sub-area libraries that are set in common in all the sub-area libraries constituting the aforementioned plural main area library, extend in the row direction and present the aforementioned plural main area The sub-zone of the library and the aforementioned data input and output range -------- f installed ------ ordered ------ {} (please read the precautions on the back before filling this page) The paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). ABCD is printed by the Employees ’Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 6. The plural data bus of the plural data path between the patent application parks and its generation The c PU chip of the clock signal and the I / 0 bus connecting the memory chip and the CPU chip to each other. The plurality of sub-region banks each have a self-memory array configuration and are arranged in the row direction 2 Small blocks, configuration The sense amplifier 'between the two small blocks and the word line arranged on the memory cell array, the data line' column selection line 'are arranged in the plural middle blocks in the column direction, and the ones arranged in the column direction One of the two ends, a column decoder connected to at least one of the column selection lines, and one of the two ends arranged in the row direction, one for each of the middle blocks, connected to the The row decoder of the complex number of the word line and the complex DQ buffer of the other one of the two ends in the column direction, and the other one of the two ends of the row direction control the complex The digital data reading operation is composed of a grid array controller of the complex data writing operation, and the complex sub-libraries of the complex numbers are independent of each other to perform the complex data reading operation or The above-mentioned plural-bit data writing operation is constituted. 8 4. A memory system, which is characterized by a memory chip, a main area library composed of a plurality of auxiliary area libraries arranged on the memory chip, and a memory chip arranged on the memory chip, which is synchronized with the clock signal to execute complex digits Yuanzhi's capital paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) ------- sold out-(please read the precautions on the back before filling this page), -w -23-economy A8 B8. C8 D8 is printed by the employee consumer cooperative of the Central Standards Bureau of the Ministry. 6. The scope of data input and output of the patent application range is common to more than two of all the sub-regional libraries that constitute the aforementioned multiple main-region library The secondary bank, extending in the row direction, presents the complex data bus of the data path of the complex number between the secondary bank of the primary bank and the data input and output range and the c PU that generates the clock signal The chip, and the I / O bus that connects the memory chip and the CPU chip to each other, and each of the plurality of sub-region libraries are composed of self-memory arrays, and are arranged in two small directions in the row direction Blocks, the sense amplifiers arranged between the two small blocks, and the word lines, data lines, and column selection lines arranged on the memory cell array are arranged in the plural middle blocks in the column direction, and are arranged in One of the two end portions in the column direction, a column decoder connected to at least one of the column selection lines, and one of the two end portions arranged in the row direction, one for each of the middle blocks , A complex row solution connected to the aforementioned word line. A coder »and a complex DQ buffer arranged on the other of the two ends in the column direction, and one of the two ends arranged in the row direction On the other hand, it is composed of a grid array controller that controls the reading operation of the complex digital data and the writing operation of the complex digital data, and the complex data bus is in the row direction of each data input / output range On both sides, the aforementioned plural sub-regional libraries constituting the aforementioned plural primary-region library are arranged on both sides of each data bus in the aforementioned row direction, and the paper standard adopts the Chinese National Standard (CNS) A4 specification (210X29 7mm] ~ one 24 one --------? Ao ------ ir ------ ί j (please read the precautions on the back before filling this page) A8 B8 · C8 D8 6. The scope of the patent application The aforementioned multiple sub-libraries are independent of each other, and are constructed by performing the above-mentioned plural-digit data reading operation or the aforementioned plural-digit data writing operation. (Please read the note on the back first Please fill in this page for details) -Installed * 1Τ The paper printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs is printed in accordance with the Chinese National Standard (CNS) A4 (210Χ297mm)