經濟部中央樣準局貝工消費合作社印製 308739 A7 ________B7_五、發明説明（） 發明背景： 本發明與一種可電除可編程唯讀記憶體 (electrically erasable programmable read only memory; EEPROM)有關，特别是一種可同時形成不同厚度之閘極 氧化層與穿隧氧化層之製程有關。 可抹除記憶體大致上可劃分爲下列之類别，包括 EAROM(e 1 ectricalIy alterable read only memory) ' EEPROM、EEPROM-EAROMs、non-volatileSRAMs。 不同之記憶體個别應用於不同之領域，例如低密度（低於 8k)之EAROMs已被應用於收音機之調諸器（consUmer radio tuner)、自動引擎控制器（ant〇m〇ti ve engine controller)，中密度之EE PROMs可用於可變換軟性之傲 存（changeable softable storage)，因此這些記憶想之發 展朝向高信賴度（reliability)與高速（high speed)發展。 製作上述之記憶體均需利用Fowler-Nordheim穿陵 (tunneling)效應，Fowler-Nordheim穿随爲冷電子由石夕 與氧化矽之界面穿越能量位障進入氡化矽之導帶。早期 1970年代之可編程之唯讀記憶體利用一種金屬-氮化物_ 二氧化矽-半導體（MNOS>之結構形成之eaROMs，一種 較新的於1987年問世的爲非揮發金氧半場效電晶體動態 隨機存取記憶體（nonvolatile MOSFET DRAM)利用鐵電 (請先閱讀背面之注意事項再填寫本頁) 裝· 訂 ^ -I1-- 本紙張尺度逋用中國國家標準（CNS ) A4规格（210X297公釐j 五、發明説明（ A7 B7 經濟部中央標準局負工消費合作社印裝 性（ferroelectric)電容之電極化來儲存资 EEPROM製程均利用薄氧化層_懸浮 來= E㈣OM。此種記憶雅之基本構造= 複晶梦之傲存胞’該雙層複晶矽之儲存胞爲一懸浮開極與 一控制閘極之4合結構，懸浮閘極氡化層之厚度约爲 50nm，介於上述兩閘極間之絶緣氣化層也約爲5〇nm。 習知之雙層複晶矽可電除可程式唯讀記億雜 (EEPROM)形成於半導體基板上包含有穿隧氧化層、控制 閘極、懸浮閘極、閘極氧化物及控制閘極與懸浮間極間之 絶緣氡化層。利用電子之Fowler-Nordheim穿域_效應穿随 W極輿汲極間之氡化層，耄子由懸浮閘極穿隧至汲極而造 成懸浮閘極爲相對之正電荷，此現像將臨界電整 (threshold voltage)往負之方向偏移。若是控制閘極施以 高電壓而汲極接地，電子則穿隧至想浮閘極造成臨界電壓 (thresholdvoltage)往正之方向偏移，上述兩種不同之臨 界電壓偏移則分别對應兩種不同之邏輯訊號，例如·0’與 ‘1’。（參閲"SEMICONDUCTOR MEMORIES A Handbook of Design, Manufacture, and Application”，Betty Prince, Chapter 12). 一種傳統之EEPROM製程如第一圈所示，一單晶具 <100 >晶面之矽半導鳢爲基板1 ’首先形成主動區間絶 緣體之場氧化層（field oxide)3，該場氧化層3爲利用微 本紙張又度適用中國國家橾率（CNS ) Α4規格（210X 297公釐） (請先閲讀背面之注意事項再填寫本頁) '1 -、τ Γ % 經濟部中央樣準局貞工消費合作社印製 308739 A7 _____B7 五、發明説明（） 、" ~ 影與姓刻技術氣化梦與氧化梦之複合層及去除光阻後再308739 A7 ________B7_ printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of the invention () Background of the invention: The present invention relates to an electrically erasable programmable read only memory (EEPROM), In particular, it is related to a process of forming gate oxide layers with different thicknesses and tunnel oxide layers at the same time. Erasable memory can be roughly divided into the following categories, including EAROM (e 1 ectricalIy alterable read only memory) 'EEPROM, EEPROM-EAROMs, non-volatile SRAMs. Different memories are individually used in different fields, for example, low-density (less than 8k) EAROMs have been used in radio tuner (consUmer radio tuner), automatic engine controller (ant〇m〇ti ve engine controller ), Medium-density EE PROMs can be used for changeable softable storage (changeable softable storage), so the development of these memory ideas is towards high reliability (reliability) and high speed (high speed). The Fowler-Nordheim tunneling effect is needed to make the above-mentioned memory. The Fowler-Nordheim tunnel is a cold electron passing through the energy barrier through the interface between Shi Xi and silicon oxide and entering the conduction band of radon silicon. The early 1970s programmable read-only memory used a metal-nitride_silicon dioxide-semiconductor (MNOS> structure formed by eaROMs, a newer non-volatile metal oxide half field effect transistor that came out in 1987 The dynamic random access memory (nonvolatile MOSFET DRAM) uses ferroelectricity (please read the precautions on the back before filling in this page). Binding · Order ^ -I1-- This paper standard adopts the Chinese National Standard (CNS) A4 specification (210X297 Mm j V. Description of invention (A7 B7 Electrodeposited ferroelectric capacitors of the negative work consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs to store data. The EEPROM process uses a thin oxide layer _ suspension to = E ㈣ OM. The basic of this memory is elegant Structure = The proud storage cell of the compound crystal dream 'The storage cell of the double-layer compound crystal silicon is a four-in-one structure of a floating open pole and a control gate. The thickness of the radonized layer of the floating gate is about 50nm, which is between the above two. The insulating gasification layer between the gates is also about 50nm. The conventional double-layer polycrystalline silicon can be electrically programmable and can be programmed to read only EEPROM (EEPROM). It is formed on the semiconductor substrate and includes a tunneling oxide layer and a control gate. , Floating gate, The gate oxide and the insulating radon layer between the control gate and the floating interelectrode. The Fowler-Nordheim through-domain effect of electrons is used to pass through the radonized layer between the W pole and the drain, and the decoupling tunnels from the floating gate To the drain, the floating gate has a relatively positive charge. This phenomenon shifts the threshold voltage to the negative direction. If the gate is controlled to apply a high voltage and the drain is grounded, the electron tunnels to float. The gate causes the threshold voltage to shift in the positive direction. The above two different threshold voltage shifts correspond to two different logic signals, such as · 0 'and' 1 '. (See " SEMICONDUCTOR MEMORIES A Handbook of Design, Manufacture, and Application ”, Betty Prince, Chapter 12). A traditional EEPROM manufacturing process is shown in the first circle. A single crystal tool < 100 > Forming field oxide layer 3 of active section insulator, this field oxide layer 3 is made of micro-copy paper and is applicable to China National Standard Rate (CNS) Α4 specification (210X 297mm) (please read the notes on the back first Refill This page) '1-, τ Γ% Printed 308739 A7 by the Zhengong Consumer Cooperative of the Central Prototype Bureau of the Ministry of Economic Affairs _____B7 V. Description of the invention (), " ~ The composite layer of the gasification dream and the oxidation dream of the shadow and surname engraving technology and After removing the photoresist
以熱氧化形成厚度約爲4000-6000埃凌接*几β Q 穴〈埽氧化層3。 接著第一光阻5形成於基板1之上，利用該第一光阻 5爲軍幕進行離子植入形成埋藏濃n型位元線區域 (burued N + bit line region)7。此離子植入之劑量约爲 1E14-1E15 atoms/crn2，植入能量小於1〇〇keV，完成離 子植入形成埋藏濃N型位元線區域7後將第一光p且5去 除。 參閲第二圏，第一二氧化矽層9形成於基板t之上做 爲閘極氧化層9 ’此一氧化石夕層9是於含氧氣想環境中以 熱氧化法於溫度850至1〇〇〇 *C中形成厚度约爲ι〇〇至300 埃之二氧化矽層。第二光阻11接著形成於上述之場氧化 層3及閘極氧化層9之上，以第二光阻11爲軍幕利用溼 仕刻法於閘極氧化層9中形成一開孔（opening)以曝露部 份之基板1。— 參閲第三圖，將上述之基板1置於高溫瀘中施以熱處 理用以形成穿隧氧化層13，同理上述之穿隧氧化層13形 成於含氧氣體環境中以熱氧化法於溫度850至1〇〇〇 ·〇中 形成厚度約爲50至100埃之二氧化矽層，上迷之閘極氧 化層9亦應熱處理而變得比較厚。接著以化學氣相沈積法 形成第一複晶矽層15於場氧化層3、閘極氧化層9及穿 本紙張尺度適用中國國家標準（CNS ) A4規格（210x297公釐） ¾—I (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部中央標隼局員工消費合作社印製 A7 B7 五、發明説明（） 隧氧化層13之上做爲懸浮明極。 如第四圈所示，第二二氡化矽層17形成於上述之第 一複晶梦層15之上做爲絶緣層，然後第二複晶·ε夕層19以 化學氣相沈積法形成形成於第二二氧化碎層17之上做爲 控制閘極。 但是上述之傳统形成穿隊氧化層之製程不僅複雜且 不易控制穿隧氧化層之品質。 螢明目的輿概要 本發明之目的爲同步形成不同厚度之閘極氡化層與 穿隊氧化層’本發明之方法可以省去製程之光軍數目增進 產能。 本發明之-製程利用不同掺雜離子之濃度控制氧化層 厚度並且同時形成不同厚度之閘極氡化層輿穿隧氣化 層’例如離子植入之劑量約爲1E111E13atoins/cm2，植 入能量小於lOOkeV，離子源爲砷或磷可以形成厚度爲5〇 至100埃之氡化層，離子植入劑量約爲1E14-1E15 atoms/cm2 ’植入能量約爲i〇〇keV，以砷或磷爲離子源 可以形成厚度爲150至35〇埃之氧化層，亦即離子濃度越 大’氧化層之厚度越厚。本發明之方法包含：第一次離子 本紙張从適财ϋ®轉準（CNS > A4^ ( 21Gx297y>董） (請先閲讀背面之注意事項再填寫本頁) 裝· 訂 308739 A7 B7 五、發明説明（） 植人以形成輕微掺雜區域於基板中；一光阻圈案形成於該 基板的部份之上；以該光阻爲單幕施以第二次離子植入以 形成濃掺雜區域於基板中；去除該光阻；將該基板施以氧 化製程以形成閘極氡化層於該基板之上以及形成穿隧氧 化層於該主動區的部份之上；及形成一第一複晶矽層於該 閉接氧化層輿該穿隧氡化層之上。 (請先聞讀背面之注f項再填寫本頁) 7.裝.' 訂 線Γ. 經濟部中央棟準局工消費合作社印製 娜 準 揉 家 國 國 I中 用 |逋 - 公 7 9 2 A7 __B7 五、發明説明（） 圈示簡單説明 第一圖爲傳統方法形成埋藏濃N型位元線區域（bur ued N+bit line region)之截面圏。 第二圖爲傳統方法形成閘極氧化層及閘極氧化層之開孔 之截面圖。 第三圖爲傳統方法形成穿隧氧化層與第一複晶層之截面 圖。 第四圈爲傳統方法形成絶緣層與第二複晶層之截面圖。 第五圖爲本發明之方法形成淡摻雜區域之截面圖。 第六圖爲本發明之方法形成濃掺雜區域之截面圖。 第七圈爲本發明之方法形成穿隧氧化層與閘極氧化層之 截面圖。 第八圖爲本發明之方法形成第一複晶層之截面圖。 第九圖爲本發明之方法形成絶緣層與第二複晶層之截面 圖。 (請先閱讀背面之注意事項再填寫本頁) -訂 經濟部中央標準局員工消費合作社印製 本紙張尺度逋用中國國家橾準（CNS ) A4規格（210X297公釐）Thermal oxidation is used to form a thickness of about 4000-6000 Angstrom connection * a few β Q holes <埽 oxidized layer 3. Next, the first photoresist 5 is formed on the substrate 1, and the first photoresist 5 is used to perform ion implantation for the military screen to form a buried n + bit line region 7. The dose of this ion implantation is about 1E14-1E15 atoms / crn2, and the implantation energy is less than 100keV. After the ion implantation is completed to form the buried dense N-type bit line region 7, the first light p and 5 are removed. Referring to the second coil, the first silicon dioxide layer 9 is formed on the substrate t as the gate oxide layer 9 '. This monoxide layer 9 is thermally oxidized at a temperature of 850 to 1 in an oxygen-containing atmosphere. A silicon dioxide layer with a thickness of about 100 to 300 angstroms is formed in 〇〇〇 * C. The second photoresist 11 is then formed on the above-mentioned field oxide layer 3 and the gate oxide layer 9, and the second photoresist 11 is used as a military curtain to form an opening in the gate oxide layer 9 using a wet etching method (opening) ) To expose part of the substrate 1. — Referring to the third figure, the above-mentioned substrate 1 is placed in a high-temperature lube and subjected to heat treatment to form a tunneling oxide layer 13; similarly, the above-mentioned tunneling oxide layer 13 is formed in an oxygen-containing gas environment by thermal oxidation method A silicon dioxide layer with a thickness of about 50 to 100 angstroms is formed at a temperature of 850 to 1,000. The gate oxide layer 9 above should also be heat-treated to become thicker. Next, the first polycrystalline silicon layer 15 is formed by chemical vapor deposition on the field oxide layer 3, gate oxide layer 9 and the size of the paper. The Chinese National Standard (CNS) A4 specification (210x297 mm) is applicable. Read the precautions on the back first and then fill out this page.) A7 B7 printed by the Employee Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs. V. Description of the invention () The tunnel oxide layer 13 is used as a suspended Ming pole. As shown in the fourth circle, the second second radonized silicon layer 17 is formed on the above first polycrystalline dream layer 15 as an insulating layer, and then the second polycrystalline and epsilon layer 19 is formed by chemical vapor deposition It is formed on the second crushed dioxide layer 17 as a control gate. However, the above-mentioned traditional process for forming the tunnel oxide layer is not only complicated but also difficult to control the quality of the tunnel oxide layer. The purpose of the present invention is to form gate radon layers with different thicknesses and through oxide layers simultaneously. The method of the present invention can save the number of optical troops in the process and increase productivity. The process of the present invention uses different concentrations of doped ions to control the thickness of the oxide layer and simultaneously form gate radonization layers and tunneling gasification layers of different thicknesses. lOOkeV, the ion source is arsenic or phosphorus can form a radon layer with a thickness of 50 to 100 angstroms, the ion implantation dose is about 1E14-1E15 atoms / cm2 'and the implantation energy is about 100keV, with arsenic or phosphorus as The ion source can form an oxide layer with a thickness of 150 to 35 angstroms, that is, the greater the ion concentration, the thicker the oxide layer. The method of the present invention includes: the first transfer of ionized paper from Shicai ϋ® (CNS > A4 ^ (21Gx297y > Dong) (please read the precautions on the back before filling out this page). 308739 A7 B7 3. Description of the invention () Implantation to form a lightly doped region in the substrate; a photoresist ring is formed on the part of the substrate; using the photoresist as a single screen, a second ion implantation is performed to form a concentrated Doped regions in the substrate; removing the photoresist; applying an oxidation process to the substrate to form a gate radon layer on the substrate and forming a tunnel oxide layer on the active region; and forming a The first polycrystalline silicon layer is on the closed oxide layer and the tunneling radon layer. (Please read note f on the back and then fill in this page) 7. Install. 'Bookmark Γ. Central Building of Ministry of Economic Affairs Printed by the quasi-bureau of industrial and consumer cooperatives Nazha rubbing home country I I use | 逋-Gong 7 9 2 A7 __B7 V. Description of the invention () Brief description of the circle The first picture is the traditional method to form the buried thick N-type bit line area (Bur ued N + bit line region). The second picture is the traditional method to form the gate oxide layer and gate The cross-sectional view of the opening of the polar oxide layer. The third figure is the cross-sectional view of the tunnel oxide layer and the first polycrystalline layer formed by the conventional method. The fourth circle is the cross-sectional view of the insulating layer and the second polycrystalline layer formed by the conventional method. Figure 5 is a cross-sectional view of a lightly doped region formed by the method of the present invention. Figure 6 is a cross-sectional view of a heavily doped region formed by the method of the present invention. Circle 7 is a tunnel oxide layer and gate formed by the method of the present invention Cross-sectional view of the oxide layer. Figure 8 is a cross-sectional view of the first polycrystalline layer formed by the method of the present invention. Figure 9 is a cross-sectional view of the insulating layer and second polycrystalline layer formed by the method of the present invention. (Please read the back side first Please pay attention to this page and then fill out this page) -The paper standard printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs will be printed in accordance with the Chinese National Standard (CNS) A4 (210X297mm)
I I 經濟部中央揉準局貝工消費合作社印装 A7 B7 五、發明説明（ 發明詳細説昍： 一種EEPROM製程可以同時形成不同厚度之氡化層 (亦即不同厚度之閘極氧化層與穿隧氧化層）將由下述，如 第五圖所示，一單晶具< 100>晶面之矽半導體爲基板 21 ’首先形成隔離主動區間之絶緣場氡化層（fieid 〇xide>23 ’該場氣化層23爲利用微影與蝕刻技術気化發 與氧化矽之複合層及去除光阻後再利用氮化矽與氧化矽 作爲軍幕以熱氡化法形成厚度約爲4000-6000埃之場氧 化層23。 接著一全面性之離子植入用以形成輊微掺雜N型區 域（N tpre light-doped region)。此離子植入之劑量約爲 1E11-1E13 atoms/cm2，植入能量小於l〇〇keV，離子源 爲砷或磷。 參閲第六圈，第一光阻25形成於基板21及場氧化層 之上23，利用該第一光阻25爲軍幕進行離子植入形成埋 藏濃Ν'型位元線區域（burued N+bit： line region)。此離 子植入之劑量約爲lE14-lE15atoms/cm2,植入能量約爲 100keV，離子源爲砷或磷，完成離子植入形成埋藏濃N 型位元線區域後將第一光阻25去除。利用基板1中適當 之離子摻雜濃度可以控制氧化層成長之厚度，亦即離子濃 度越大，氧化層之厚度越厚。 本紙張尺度逋用中國國家梂準（CNS) Α4規格（210X297公釐） -— Μ-- (請先閲讀背面之注意事項再填寫本頁) 訂_ 级 經濟部_央標準局員工消费合作社印製 A7 —_!Z___ 五、發明説明（） 參閲第七圖，一閘極氧化層27以及穿隧氧化層29以 熱氧化法同步形成於基板21之上，此閘極氧化層27以及 穿隧氧化層29於含氧氣體環境中以熱氧化法於温度850 至1000 _C中形成厚度約爲50至100埃穿隧氧化層29(劑 量爲lEll-lE13atoms/cm2)，閘極氧化層27則形成厚度 约爲 150至 350埃之氧化層（劑量爲 1E14-1E15 at〇ms/cm2) ° 參閲第八圈，沈積第一複晶矽層31於上述之基板 21、場氡化層23、閘極氧化層27以及穿隧氧化層29之 上，該第一複晶矽層31以化學氣相沈積法形成厚度爲 1〇〇〇至3000埃之複晶矽，該第一複晶矽層31將做爲 EEPROM之懸浮閘極。本發明之結構若爲單一複晶層可 作爲棋合之用（single poly coupling)，當然本發明亦可 以利用於雙層複晶矽之EEPROM，第二複晶矽將做爲控 制閘極，後續_步驟如下所述。 如第九囷所示，一介電層33如二氧化矽形成於上述 之第一複晶矽層31之上做爲絶緣層，厚度約爲500埃， 然後第二複晶矽層35以化學氣相沈積法形成形成於介電 層33之上做爲控制閘極，同理第二複晶矽層35以化學氣 相沈積法形成厚度爲3000埃之複晶矽。 (請先閱讀背面之注意事項再填寫本頁) -訂 良 9 本紙張尺度遑用中國困家棵準（CNS) A4^_ (2獻297公着）II A7 B7 printed by the Beigong Consumer Cooperative of the Central Bureau of Economic Development of the Ministry of Economy V. Description of the invention (Detailed description of the invention: an EEPROM process can simultaneously form radon layers with different thicknesses (ie, gate oxide layers with different thicknesses and tunneling The oxide layer) will be described below, as shown in the fifth figure, a single crystal with a <100> crystal surface of the silicon semiconductor substrate 21 'first forms an insulating field radonization layer that isolates the active area (fieid 〇xide> 23' The field vaporization layer 23 is a composite layer that uses lithography and etching technology to dissolve the hair and silicon oxide and remove the photoresist, and then uses silicon nitride and silicon oxide as a military curtain to form a thickness of about 4000-6000 Angstroms by thermal radonization. Field oxide layer 23. Then a comprehensive ion implantation is used to form a lightly doped N-type region (N tpre light-doped region). The dose of this ion implantation is about 1E11-1E13 atoms / cm2, the implantation energy Less than 100keV, the ion source is arsenic or phosphorus. Referring to the sixth circle, the first photoresist 25 is formed on the substrate 21 and the field oxide layer 23, and the first photoresist 25 is used for ion implantation for the military screen Form a buried dense Ν 'type bit line area (burued N + bit: line region). The dose of this ion implantation is about lE14-lE15atoms / cm2, the implantation energy is about 100keV, and the ion source is arsenic or phosphorous. After the ion implantation is completed to form the buried N-type bit line region, the first light The resistance 25 is removed. The thickness of the oxide layer can be controlled by using the appropriate ion doping concentration in the substrate 1, that is, the greater the ion concentration, the thicker the oxide layer. The paper standard adopts China National Standards (CNS) A4 specifications (210X297mm)-— Μ-- (Please read the precautions on the back before filling in this page) Order _ Level Economy Ministry _ Central Standardization Bureau Employee Consumer Cooperative Printed A7 —_! Z___ V. Description of invention () See In the seventh figure, a gate oxide layer 27 and a tunnel oxide layer 29 are simultaneously formed on the substrate 21 by a thermal oxidation method. The gate oxide layer 27 and the tunnel oxide layer 29 are thermally oxidized in an oxygen-containing gas environment At a temperature of 850 to 1000 _C, a tunnel oxide layer 29 with a thickness of about 50 to 100 Angstroms is formed (the dose is lEll-lE13atoms / cm2), and a gate oxide layer 27 is formed with an oxide layer with a thickness of about 150 to 350 Angstroms (the dose is 1E14-1E15 at〇ms / cm2) ° refer to the eighth circle, deposition A polycrystalline silicon layer 31 is formed on the substrate 21, the field radonization layer 23, the gate oxide layer 27, and the tunneling oxide layer 29. The first polycrystalline silicon layer 31 is formed by chemical vapor deposition to a thickness of 1. For polycrystalline silicon from 8000 to 3000 angstroms, the first polycrystalline silicon layer 31 will be used as the floating gate of the EEPROM. If the structure of the present invention is a single polycrystalline layer, it can be used as a single poly coupling, Of course, the present invention can also be applied to the EEPROM of the double-layer polycrystalline silicon. The second polycrystalline silicon will be used as the control gate. The subsequent steps are as follows. As shown in the ninth figure, a dielectric layer 33 such as silicon dioxide is formed on the above first polycrystalline silicon layer 31 as an insulating layer with a thickness of about 500 angstroms, and then the second polycrystalline silicon layer 35 is chemically The vapor deposition method is formed on the dielectric layer 33 as a control gate. Similarly, the second polycrystalline silicon layer 35 is formed by chemical vapor deposition to form polycrystalline silicon with a thickness of 3000 angstroms. (Please read the precautions on the back before filling in this page)-Good order 9 This paper is not to be used in China (CNS) A4 ^ _ (2 dedicated 297 public works)
五、發明説明（ 本發明之方珐可以省去製程之光軍數目，另外本發明 《製程利用#雜離子之濃度控制且同步形成不同厚度之 閉極氧化層27與穿遂氧化層29，當然本方法亦可以利用 來同步形成不同厚度之複合氧化層（multi-thickness oxides) ° 本發明以較佳實施例説明如上，而熟悉此領域技藝 者，在不脱離本發明之精神範圍内，當可作些許更動潤 飾’例如本方法同時形成不同厚度之氡化層製程並非只限 定於EEPROM之製程，其專利保護範团更當視後附之申 請專利範圓及其等同領域而定。 (請先閎讀背面之注意事項再填寫本頁) -窣. -•s Γ 与---- 經濟部中央標準局貝工消费合作社印製 本紙張尺度遑用中國國家揉举（CNS ) A4規格（210 X 297公釐）V. Description of the invention (The square enamel of the present invention can save the number of optical troops in the process. In addition, the process of the present invention uses the concentration control of #heteroions and simultaneously forms closed-layer oxide layers 27 and tunnel oxide layers 29 of different thicknesses. Of course The method can also be used to simultaneously form multi-thickness oxides of different thicknesses. The present invention has been described above in the preferred embodiments, and those skilled in the art are familiar with the art without departing from the spirit of the present invention. It can be modified slightly. For example, the process of simultaneously forming radon layers with different thicknesses is not limited to the EEPROM process, and its patent protection group depends on the attached patent application circle and its equivalent fields. (Please Read the precautions on the back first and then fill out this page)-窣.-• s Γ and ---- printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. The paper size is not in China National Standard (CNS) A4 ( 210 X 297 mm)