A7 ^06059 B7 五、發明説明（f ) 〔發明之背景〕 發明之領域 本發明係關於一種製作金氧半場效電晶體（Μ 0 S F E T ) 的方法，尤指一種製作Μ 0 S F Ε Τ的方法，其涉及使用一金屬 膜或金屬矽化物膜來形成閘極。 前技之描述 為了獲得半導體装置之高整合性 < 各種方法已被使用 。例如，一種形成一 Μ 0 S F Ε Τ閘極之薄導電層的方法已為習 知者。一關於形成閘極Μ獲得高整合性的比例原則亦為習 知者。該比例原則解釋了 Μ 0 S F Ε Τ應具一較薄的閘極氧化物 膜Κ進一步增大其電晶體通道内的跨導。 參看圖1至圖4 ，說明一種用於製作具一較薄閘極之 Μ 0 S F Ε Τ的傳統方法。 依據此方法，首先準備一半導體基片1 ，如圖1所示 。於該半導體基片1上，一閘極氧ib物膜2 、一多晶矽層 與一絕緣膜依序地Μ薄片叠置。此後，進行一閘極加圖案 步驟Μ形成一多晶矽層圖案3與一絕緣膜圖案4。在蝕刻 該多晶矽層圖案後，閘極氧化物膜2仍被保留而未被蝕刻 〇 於结果结構之整個上表面之上，一金屬膜5其後被沈 積到一 1 0 0至1 Ο Ο ◦ Α的厚度，如圖2所示該金靨 膜 5 由鎢（W )、钽（T a )、鈦（T i)、組（Μ 〇 )、鉑（P t)、鎳 (N i)或鈷（C 〇 )製成。 -3- 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0乂297公釐） | -裝 訂 『 線 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印装 經濟部中央標準局員工消費合作社印製 S06059 A1 B7 五、發明説明（二） 接著，進行一退火步驟Μ使金靥膜5可與多晶矽曆圖 案3反應，藉此於多晶矽層圖案3的兩側面形成一矽化物 膜6 ，如圖3所示。此時，金屬膜5並未與閘極氧化物膜 2與絕緣膜圖案4反應。因此，金屬膜於其設於閘極氧化 物膜2與絕緣膜圖案4的部位並未雯為矽化物。 此後|設於閘極氧化物膜2與絕緣膜圖案4上剩餘的 金屬膜5依據一各向同性的蝕刻過程，使用該金屬膜5與 金靨矽化物膜6間的蝕刻選擇性之差異而被去除，如圖4 所示。因此，可獲得一包括該多晶矽層圖案3與金靨矽化 物瞑6的閘極9。 然而，依據上述的傳統方法，存在一個問題，即當該 多晶矽層被蝕刻Κ形成該多晶矽層圖案3時，閘極氧化物 膜2可能被不期望地蝕刻。若在閘極氧化物膜2已被蝕刻 的情況下進行後壤的步驟，則一砂化物膜可能被形成於該 半導體基片以及該閘極氧化物膜上。於此情形下，半導體 基片與閘極之間可能發生短路。 〔發明之概要〕 因此，本發明之一目的儀在於解決前技中涉及的上述 問題，並提供一種用於製作一 Μ 0 S F Ε Τ的方法，儘管形成了 一氧化物膜，該方法仍可防止半導體基片與該MOSFET的閘 極間發生短路，藉此不僅消除由MOSFET的損壊所造成的 Μ 0 S F Ε Τ性能退化，而且於處理邊界上獲得一改良。 -4- 本紙張尺度適用中國國家橾隼（CNS ) A4規格（210X297公釐） j 裝 訂 ^ J (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消费合作社印製 A7 B7 五、發明説明（>7 ) 依據本發明之一方面，本發明提供一種用於製作一金 氧矽場效電晶體之方法，包括步驟：依序叠置一閘極氧化 物膜、一第一多晶矽層、一絕緣膜、一第二多晶矽層薄片 於一半導體基片上，並局部蝕刻該第二多晶矽層，藉此形 成一第二多晶矽層圖案；藉由使用該第二多晶矽層圖案作 為一光罩，於局部蝕刻該第一多晶矽膜後所獲之结果结構 上形成一絕緣膜圖案；於形成該絕緣膜圖案後所獲之结果 结構上，沈積一金屬膜；各向異性地蝕刻該金屬膜，藉此 分別於該第二多晶矽層圖案之兩側壁上形成金靨膜側壁； 及藉由使用該第二多晶矽層圖案與該金屬膜側壁作為一光 罩，蝕刻該第一多晶矽層與該閘極氧化物膜，籍此形成一 聞極。 依據本發明之另一方面，本發明提供一種用於製作一 金氧矽場效電晶體之方法，包括步驟：依序叠置一閘極氧 化物膜、一第一多晶矽層、一絕緣膜、一第二多晶矽層薄 片於一半導體基片上，並依據一閘極加圖案處理對該第二 多晶矽層與該絕緣膜加圖案，藉此形成一第二多晶矽層圖 案與一絕緣膜圖案，且其後於該结搆结構上形成一金靨膜 ;各向異性地蝕刻該金靥膜，藉此分別於該第二多晶矽層 圖寨之兩側壁上形成金靨膜側壁；退火該金靨膜，藉此使 該金屬膜與與其接觸的該第二多晶矽層圖案及該第一多晶 矽層反懕，藉此形成一金屬矽化物膜；及藉由使用該第二 多晶矽層圖案與該金屬矽化物膜作為一光罩，蝕刻該第一 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） --------1 ·裝------訂-----？ 線 (請先閱讀背面之注意事項再填寫本頁) A7 B7 五、發明説明（ά ) 多晶矽層與該閘極氧化物膜，藉此形成具一包括該第二多 晶矽層圖案、該金靨矽化物膜、該第一多晶矽層圖案、與 該絕緣膜圖寨之多晶矽化物结構的閘極。 依據本發明再一方面，本發明提供一種用於製作一金 氧矽場效電晶體之方法，包括步驟：依序叠置一閘極氧化 物膜、一第一多晶矽層、一絕緣膜、一第二多晶矽層薄片 於一半導體基片上，並依據一閛極加圖案處理對該第二多 晶矽層與該絕緣膜加圖案，藉此形成一第二多晶矽層圖案 與一絕緣膜圖案，且其後於該结果结構上形成一金屬膜； 退火該金屬膜，藉此使該金屬膜與與其接觸的該第二多晶 矽層圖案及該第一多晶矽層反應，藉此形成一金屬矽化物 .膜，同時加圖案於該第一多晶矽層；及各向異性地蝕刻該 金屬矽化物膜，藉此分別於該第二多晶矽層圖案之兩側壁 上形成金屬矽化物膜，藉此形成具一包括該第二多晶矽層 圖案、該金靥矽化物膜側壁、該第一多晶矽層圖案、與該 絕緣膜圖案之多晶矽化物结構的閘極： 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) ί附圖簡要說明] 本發明的其它目的及方面於以下配合參考附圖的實施 例描述中變得更為清楚。 圖1至圖4係為剖視圖，分別說明一種用於製作一 Μ 0 S F Ε Τ的傳統方法； 圖5至第圖8係為剖視圖，分別說明依據本發明之一 -6- 本紙張尺度逋用中國國家標準（CNS ) Α4規格（210Χ297公釐） 經濟部中央標準局員工消費合作社印裝 A7 B7 五、發明説明（s) 第一黄施例的一種用於形成一 Μ 0 S F E T閘極的方法； 圖3至圖1 2係為剖視圖，分別說明依據本發明之一 第二實施例的一種用於形成一 Μ 0 S F Ε Τ閘極的方法；及 圖1 3至圖1 6係為剖視圖，分別說明依據本發明之 一第三實施例的一種用於形成一 Μ 0 S F Ε Τ閘極的方法。 〔較佳實施例的詳细說明] 參看圖5至圖8 ，說明依據本發明之一第一實施例的 一種用於形成一 Μ 0 S F Ε Τ閘極的方法。 依據本發明之方法，首先準備一半導體基片1 1 ，如 圖5所示，於該半導體基片1 1上，一閘極氧化物膜1 2 與一第一多晶矽層1 7依序地Κ薄片叠置。於該第一多晶 矽層1 7之上，一絕緣膜1 8被沈積至一50〜500Α 的厚度。一第二多晶矽層其後被沈積於該絕緣膜1 8之上 至一 1 00〜500Α的厚度。此後*進行一閘極加圖案 步驟Μ加圖案於該第二多晶矽層，藉此形成一第二多晶矽 層圖案1 3。於此步驟，該第二多晶矽層被蝕刻直至暴露 出該絕緣膜1 8。 使用該第二多晶矽層圖案1 3作為一光罩，該暴露的 絕緣層1 8其後被蝕刻，如圖6所示。於此時，設於該第 二多晶矽層圖案1 3之下的該絕緣膜1 8部位仍被保留而 未被蝕刻。隨後，一金靨膜1 5被沈積於包括該第二多晶 矽層圖案1 3之暴露表面與該第一多晶矽層1 7之暴露表 面的該结果结構之整個暴露表面之上至一 1 0 0〜1 ◦〇 -7- 本紙張尺度逋用中國國家標準（CNS ) Α4规格（210 X 297公釐） --------『：裝------訂-----·~·ι線 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標隼局員工消費合作社印製 A7 B7 五、發明説明（6 ) Ο A的厚度。 該金匾膜1 5被各向異性地蝕刻，藉此於該第二多晶 矽層圖案1 3之側面分別形成金靥膜側壁1 5’ ，如圖7 所示。該金屬膜側壁1 5 ’作用以互相電氣連接該第二多 晶矽層圖案1 3與第一多晶矽層1 7 。 使用該第二多晶矽層圖案1 3與金龎膜側壁1 5 ’怍 為一光罩，該第一多晶矽層1 7與閘極氧化物膜1 2其後 被蝕刻，如圖8所示。因此，可獲得一包括該第二多晶矽 層圖案1 3、金屬膜側壁1 5’ 、加圖案之第一多晶矽層 1 7與加圖案之絕緣膜1 8的閘極1 9。該閘極1 9具一 包括金屬測壁的结構。 依據5至8圖所示的本發明之實施例，儘管設於閘極 1 9之下的閘極氧化物膜1 2具一較小厚度，但由於該第 一多晶矽層1 7充當一蝕刻阻擋膜，故閘極氧化物膜1 2 未被蝕刻。由於閘極氧化物膜被該第一多晶矽層1 7保護 ，其可防止該閘極1 9與基Η 1 1連接。因此，其有可能 防止該半導體裝置被損壞。 圖9至圖1 2係為剖視圖，分別說明依據本發明之一 第二實施例的一種用於形成一 Μ 0 S F Ε Τ閘極的方法。 依據本發明之方法，首先準備一半導體基片21 ，如 圖9所示，於該半導體基片2 1上，一閘極氧化物膜2 2 與一第一多晶矽層2 7依序地以薄片叠置。於該第一多晶 矽層27之上，一絕緣膜被沈積至一 50〜500Α的厚 -8 - 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ29'/公釐） j ‘^私 訂 7 (請先閱讀背面之注意事項再填寫本I) 306059 A7 B7 五、發明説明（，| ) 度。一第二多晶矽層其後被沈積於該絕緣膜之上至一 1 〇 ◦〜5 Ο Ο A的厚度。此後，進行一閘極加圖案步驟以延 該絕緣膜加圖案於該第二多晶矽層，藉此形成一第二多晶 矽層圖寨23與一絕緣瞑圖案28。隨後，一金屬膜25 被沈積於结果结構之整個暴露表而上至一 1 0 ◦〜1〇〇 Ο A的厚度。 然後該金屬膜2 5被各向異性地訑刻，藉此於該第二 多晶矽層圖案2 3之側面分別形成金靨膜側壁2 5 '，如 圖1 0所示。 隨後，進行一退火步驟Μ使金鼷膜2 5可與與其接觸 的該第二多晶矽層圖案2 3及第一多晶矽層2 7反應，藉 此形成一金屬矽化物膜2 6，如圖1 1所示。 該金屬矽化物膜2 6作用Κ將該第二多晶矽層圖案2 3與該第一多晶矽層2 7電氣連接。 使用該第二多晶矽層圖案2 3與金屬矽化物膜2 6作 為一光罩，該第一多晶矽層2 7與閘極氧化物膜2 2其後 被蝕刻 > 如圖1 2所示。因此，可獲得一包括該第二多晶 矽層圖案2 3 、金靥矽化物膜2 6 、加圖案之第一多晶矽 層2 7與絕緣膜圖案2 8的閘極2 9。儘管設於閘極2 9 之下的閘極氧化物膜2 2具一較小厚度，但由於該第一多 晶矽層2 7充當一蝕刻阻擋膜，故閛極氧化物膜2 2未被 蝕刻。 圖1 3至圖1 6餘為剖視圖，分別說明依據本發明之 -9- 本紙張尺度適用中國國家標隼（CNS ) A4规格（210X297公釐） ' -扣衣 訂 J (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（ ) 1 1 I 一 第 三 筲 施 例 的 一 種 用 於 形 成 一 Μ 0 S F E T閛極的方法 0 1 1 I 依 據 本 發 明 之 方 法 > 首 先 準 備 一 半 導 體 基 片 3 1 t 如 1 1 | 圖 1 3 所 示 > 一 閘 極 氧 化 物 膜 3 2 與 — 第 一 多 晶 矽 層 3 7 請 1 1 以 薄 片 叠 置 於 該 半 導 體 基 片 3 1 上 r, 於 該 第 — 多 晶 矽 層 3 閱 讀 背 1 1 7 之 上 > 一 m 緣 膜 被 沈 積 至 .一 5 〇 5 0 0 A 的 厚 度 0 一 ιέ 之 1 1 第 二 多 晶 矽 層 其 後 被 沈 積 於 該 絕 緣 膜 之 上 至 -一 1 0 〇 5 意 事 1 項 I 〇 0 A 的 厚 度 0 此 後 進 行 一 閘 極 加 圖 案 步 驟 K 加 圖 案 於 再 4 該 第 二 多 晶 矽 層 、 絕 緣 膜 與 第 一 多 晶 矽 層 > 藉 此 形 成 一 第 % 本 頁 裝 1 二 多 晶 矽 層 圖 案 3 3 與 一 絕 緣 膜 圖 案 3 8 0 隨 後 — 金 靨 Sw·· 1 I 膜 3 5 被 沈 積 於 结 果 结 構 之 整 個 暴 露 表 面 上 至 一 1 〇 〇 1 I 1 〇 〇 0 A 的 厚 度 0 1 1 訂 1 隨 後 進 行 一 退 火 步 驟 Μ 使 該 金 臑 膜 3 5 可 與 與 之 接 觸 的 該 第 二 多 晶 矽 層 圖 案 3 3 及 第 — 多 晶 矽 曆 3 7 反 atu 懕 9 1 1 藉 此 形 成 一 金 屬 矽 化 物 膜 3 6 如 圖 1 4 所 示 0 1 1 m 後 該 金 屬 矽 化 物 膜 3 6 被 各 向 異 性 地 蝕 刻 藉 此 於 1 線 1 該 第 二 多 晶 矽 層 圖 案 3 3 之 側 面 分 別 形 成 金 屬 膜 側 壁 3 6 t 如 圖 1 5 所 示 0 因 此 > 可 獲 得 一 包 括 該 第 二 多 晶 矽 層 1 | 圈 案 3 3 、 金 鼷 膜 側 壁 3 6 r 加 圖 案 之 第 一 多 晶 矽 層 3 1 I 7 與 加 圖 案 之 絕 緣 膜 3 8 的 閘 極 1 9 1 1 圖 1 6 係 為 — 剖 視 圖 » 顯 示 使 用 該 第 二 多 晶 矽 層 Μ 案 1 1 3 3 、 金 屬 膜 側 壁 3 6 > ·、 加 圖 案 之 第 一 多 晶 矽 層 3 7 與 1 | 加 圖 案 之 絕 緣 膜 3 8 作 為 一 光 罩 之 閘 極 氧 化 物 膜 3 2 的 蝕 1 I 劑 情 況 0 儘 管 設 於 閘 極 3 9 之 下 的 該 閘 極 氧 化 物 膜 3 2 具 1 1 一 10 - 1 1 1 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） A7 B7 五、發明説明（q) 一較小厚度，但由於該第一多晶矽層3 7充當一蝕刻阻擋 膜，故閘極氧化物膜3 2未被蝕刻。該閘極氧化物膜可能 未被蝕刻。 如由以上描述可以顯見，本發明提供一種用於製作一 Μ 0 S F E T的方法，其中一多晶矽層被沈積於一閘極氧化物膜 上作用，以令Μ 0 S F Ε Τ之閘極與Μ 0 S F Ε Τ之基片分離。該多晶 矽層作用Κ防止該閘極氧化物膜於使用一金屬膜或金靨矽 ib物側壁作為一光罩而形成一閘極時被蝕刻。因此，其有 可能防止一短路發生於Μ 0 S F E T之半導體基片與閘極之間， 藉此獲得半導體装置可靠性之提升。 儘管本發明之較佳實施例已用於說明的目的被揭示， 那些熟悉此項技藝之人士應理解未脫離如隨附之申請專利 範圍内所揭示之本發明的範皤與精神的各種變更、添加與 替代物為可能的。 咖 批衣 訂 f 务 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 -11- 本紙張尺度適用中國國家橾準（CNS ) A4規格（210X297公釐）A7 ^ 06059 B7 V. Description of the invention (f) [Background of the invention] Field of the invention The present invention relates to a method of manufacturing a metal oxide half field effect transistor (Μ0 SFET), in particular a method of producing Μ0SF ΕΤ , Which involves using a metal film or metal silicide film to form the gate. Description of the prior art Various methods have been used in order to obtain high integration of semiconductor devices. For example, a method of forming a thin conductive layer of MOSFET gates is well known. A principle of forming a gate M to achieve a high integration ratio is also known. The principle of proportionality explains that M 0 S F E T should have a thinner gate oxide film K to further increase the transconductance in its transistor channel. Referring to FIGS. 1 to 4, a conventional method for fabricating MOSFET with a thinner gate is illustrated. According to this method, a semiconductor substrate 1 is first prepared, as shown in FIG. On the semiconductor substrate 1, a gate oxide film 2, a polysilicon layer and an insulating film are sequentially stacked with M sheets. Thereafter, a gate patterning step M is performed to form a polysilicon layer pattern 3 and an insulating film pattern 4. After etching the pattern of the polysilicon layer, the gate oxide film 2 is still retained without being etched. The entire upper surface of the resulting structure is formed, and a metal film 5 is then deposited to a temperature of 100 to 100 ◦ ◦ The thickness of Α, as shown in FIG. 2, the gold film 5 is made of tungsten (W), tantalum (T a), titanium (T i), group (Μ 〇), platinum (P t), nickel (N i) or Cobalt (C 〇) made. -3- This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 0 297 mm) |-Binding "line (please read the precautions on the back before filling this page) Employee Consumer Cooperative of the Central Bureau of Standards Printing S06059 A1 B7 by the Employees ’Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the Invention (2) Next, an annealing step M is performed to make the gold film 5 react with the polysilicon calendar pattern 3, thereby A silicide film 6 is formed on both sides, as shown in FIG. 3. At this time, the metal film 5 does not react with the gate oxide film 2 and the insulating film pattern 4. Therefore, the metal film is not silicided at the portion where it is provided on the gate oxide film 2 and the insulating film pattern 4. Thereafter | the remaining metal film 5 provided on the gate oxide film 2 and the insulating film pattern 4 is based on an isotropic etching process, using the difference in etching selectivity between the metal film 5 and the gold-thallium silicide film 6 Was removed, as shown in Figure 4. Therefore, a gate electrode 9 including the polysilicon layer pattern 3 and the gold-silicide silicide 6 can be obtained. However, according to the above-described conventional method, there is a problem that when the polysilicon layer is etched K to form the polysilicon layer pattern 3, the gate oxide film 2 may be undesirably etched. If the back soil step is performed with the gate oxide film 2 already etched, a sand film may be formed on the semiconductor substrate and the gate oxide film. In this case, a short circuit may occur between the semiconductor substrate and the gate. [Summary of the Invention] Therefore, an object of the present invention is to solve the above-mentioned problems involved in the prior art, and to provide a method for manufacturing a Μ0 SF Ε Τ, although the formation of an oxide film, the method can still Preventing a short circuit between the semiconductor substrate and the gate of the MOSFET, thereby not only eliminating the degradation of the MOSFET performance caused by the damage of the MOSFET, but also obtaining an improvement on the processing boundary. -4- This paper scale is applicable to China National Falcon (CNS) A4 specification (210X297mm) j Binding ^ J (please read the notes on the back before filling this page) A7 B7 printed by the Employee Consumer Cooperative of the Ministry of Economic Affairs Central Standards Bureau V. Description of the Invention (> 7) According to one aspect of the present invention, the present invention provides a method for manufacturing a metal oxide silicon field effect transistor, including the steps of: sequentially stacking a gate oxide film, a first A polysilicon layer, an insulating film, and a second polysilicon layer sheet on a semiconductor substrate, and the second polysilicon layer is partially etched, thereby forming a second polysilicon layer pattern; by using The second polysilicon layer pattern is used as a photomask to form an insulating film pattern on the resulting structure obtained by partially etching the first polysilicon film; on the resulting structure obtained after forming the insulating film pattern, Depositing a metal film; etching the metal film anisotropically, thereby forming the side walls of the gold-solar film on both side walls of the second polysilicon layer pattern; and by using the second polysilicon layer pattern and the The metal film side wall is used as a photomask, etched A first polysilicon layer and the gate oxide film, thereby forming a pole smell. According to another aspect of the present invention, the present invention provides a method for manufacturing a metal oxide silicon field effect transistor, including the steps of: sequentially stacking a gate oxide film, a first polysilicon layer, and an insulation Film, a second polysilicon layer sheet on a semiconductor substrate, and patterning the second polysilicon layer and the insulating film according to a gate patterning process, thereby forming a second polysilicon layer pattern And an insulating film pattern, and then a gold-thorium film is formed on the structure; the gold-thorium film is etched anisotropically, thereby forming gold on both side walls of the second polysilicon layer The side wall of the tantalum film; annealing the gold tantalum film, thereby inverting the metal film with the second polysilicon layer pattern and the first polysilicon layer in contact therewith, thereby forming a metal silicide film; and By using the second polysilicon layer pattern and the metal silicide film as a photomask, the first paper scale is etched to comply with the Chinese National Standard (CNS) A4 specification (210X297mm) -------- 1 · Install ------ order -----? Line (please read the precautions on the back before filling in this page) A7 B7 V. Description of Invention (ά) The polysilicon layer and the gate oxide film form a pattern including the second polysilicon layer and the gold A gate electrode of a polysilicide structure of a tungsten silicide film, the first polysilicon layer pattern, and the insulating film. According to yet another aspect of the present invention, the present invention provides a method for manufacturing a metal oxide silicon field effect transistor, including the steps of: sequentially stacking a gate oxide film, a first polysilicon layer, and an insulating film , A second polysilicon layer sheet on a semiconductor substrate, and patterning the second polysilicon layer and the insulating film according to a patterning process, thereby forming a second polysilicon layer pattern and An insulating film pattern, and then forming a metal film on the resulting structure; annealing the metal film, thereby allowing the metal film to react with the second polysilicon layer pattern and the first polysilicon layer in contact therewith , Thereby forming a metal silicide film, while adding a pattern to the first polysilicon layer; and anisotropically etching the metal silicide film, thereby respectively on the two sidewalls of the second polysilicon layer pattern Forming a metal silicide film thereon, thereby forming a gate having a polysilicide structure including the second polysilicon layer pattern, the gold-thallium silicide film side wall, the first polysilicon layer pattern, and the insulating film pattern Pole: Employee consumption Printed Society (Read Notes on the back and then fill the page) Brief description other objects and aspects of] the present invention with the described embodiment will become more apparent in the following with reference to the accompanying drawings ί drawings. Figures 1 to 4 are cross-sectional views illustrating a conventional method for making a Μ0 SF Ε Τ; Figures 5 to 8 are cross-sectional views illustrating respectively according to one of the present invention -6- the paper size China National Standards (CNS) Α4 specification (210Χ297 mm) A7 B7 printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Invention description (s) A method for forming a Μ 0 SFET gate in the first yellow embodiment FIGS. 3 to 12 are cross-sectional views, respectively illustrating a method for forming a M0 SF ET gate according to a second embodiment of the present invention; and FIGS. 13 to 16 are cross-sectional views, A method for forming a M 0 SF ET gate according to a third embodiment of the present invention will be described separately. [Detailed Description of the Preferred Embodiment] Referring to FIGS. 5 to 8, a method for forming a MOSFET gate according to a first embodiment of the present invention will be described. According to the method of the present invention, a semiconductor substrate 1 1 is first prepared. As shown in FIG. 5, on this semiconductor substrate 11, a gate oxide film 12 and a first polysilicon layer 17 are sequentially provided. Ground K sheets are stacked. On the first polysilicon layer 17, an insulating film 18 is deposited to a thickness of 50 ~ 500A. A second polysilicon layer is then deposited on the insulating film 18 to a thickness of 100-500Å. Thereafter, a gate patterning step M is applied to the second polysilicon layer, thereby forming a second polysilicon layer pattern 13. In this step, the second polysilicon layer is etched until the insulating film 18 is exposed. Using the second polysilicon layer pattern 13 as a photomask, the exposed insulating layer 18 is then etched, as shown in FIG. At this time, the portion of the insulating film 18 provided under the second polysilicon layer pattern 13 is still left unetched. Subsequently, a gold-solar film 15 is deposited over the entire exposed surface of the resulting structure including the exposed surface of the second polysilicon layer pattern 13 and the exposed surface of the first polysilicon layer 17 to a 1 0 0 ~ 1 ◦〇-7- This paper uses the Chinese National Standard (CNS) Α4 specification (210 X 297 mm) -------- 『: Packing ------ Ordering-- --- · ~ · ι line (please read the precautions on the back before filling out this page) A7 B7 printed by the Employee Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs 5. Invention description (6) Ο A thickness. The gold plaque film 15 is anisotropically etched, thereby forming sidewalls 15 'of the gold film on the sides of the second polysilicon layer pattern 13 as shown in FIG. 7. The metal film side wall 15 'serves to electrically connect the second polysilicon layer pattern 13 and the first polysilicon layer 17 to each other. Using the second polysilicon layer pattern 13 and the gold pinch sidewalls 15 'as a photomask, the first polysilicon layer 17 and the gate oxide film 12 are then etched, as shown in FIG. 8 As shown. Therefore, a gate electrode 19 including the second polysilicon layer pattern 13 3, the metal film sidewall 15 ', the patterned first polysilicon layer 17 and the patterned insulating film 18 can be obtained. The gate electrode 19 has a structure including a metal measuring wall. According to the embodiments of the present invention shown in FIGS. 5 to 8, although the gate oxide film 12 provided under the gate 19 has a small thickness, the first polysilicon layer 17 acts as a The barrier film is etched, so the gate oxide film 12 is not etched. Since the gate oxide film is protected by the first polysilicon layer 17, it can prevent the gate 19 from being connected to the base H 11. Therefore, it is possible to prevent the semiconductor device from being damaged. FIGS. 9 to 12 are cross-sectional views respectively illustrating a method for forming a MOSFET gate according to a second embodiment of the present invention. According to the method of the present invention, a semiconductor substrate 21 is first prepared. As shown in FIG. 9, on the semiconductor substrate 21, a gate oxide film 22 and a first polysilicon layer 27 are sequentially Stack in sheets. On the first polysilicon layer 27, an insulating film is deposited to a thickness of 50 ~ 500Α-8-This paper scale is applicable to Chinese National Standard (CNS) Α4 specification (210Χ29 '/ mm) j' ^ private Order 7 (Please read the precautions on the back before filling in this I) 306059 A7 B7 Fifth, the invention description (, |) degree. A second polysilicon layer is then deposited on the insulating film to a thickness of 10 ◦ ~ 5 Ο Ο A. Thereafter, a gate patterning step is performed to pattern the insulating film on the second polysilicon layer, thereby forming a second polysilicon layer pattern 23 and an insulating ridge pattern 28. Subsequently, a metal film 25 is deposited on the entire exposed surface of the resulting structure up to a thickness of 10 to 100 Å. Then, the metal film 25 is anisotropically engraved, thereby forming side walls 25 ′ of the gold film on the sides of the second polysilicon layer pattern 23, as shown in FIG. Subsequently, an annealing step M is performed so that the gold film 25 can react with the second polysilicon layer pattern 23 and the first polysilicon layer 27 that are in contact therewith, thereby forming a metal silicide film 26, As shown in Figure 11. The metal silicide film 26 acts to electrically connect the second polysilicon layer pattern 23 to the first polysilicon layer 27. Using the second polysilicon layer pattern 23 and the metal silicide film 26 as a photomask, the first polysilicon layer 27 and the gate oxide film 22 are etched afterwards, as shown in FIG. 1 2 As shown. Therefore, a gate electrode 29 including the second polysilicon layer pattern 23, the gold-thallium silicide film 26, the patterned first polysilicon layer 27 and the insulating film pattern 28 can be obtained. Although the gate oxide film 2 2 provided under the gate electrode 2 9 has a small thickness, the first polysilicon layer 27 acts as an etching barrier film, so the oxide film 2 2 is not Etch. Figures 13 to 16 are cross-sectional views, respectively illustrating the -9 according to the present invention- This paper size is applicable to the Chinese National Standard Falcon (CNS) A4 specification (210X297mm) (Notes need to fill out this page) A7 B7 Printed by Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A7 B7 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economics V. Description of invention () Μ 0 SFET method 0 1 1 I According to the method of the present invention > first prepare a semiconductor substrate 3 1 t as shown in 1 1 | FIG. 1 3 > a gate oxide film 3 2 and-first The polysilicon layer 3 7 1 1 1 is stacked on the semiconductor substrate 3 1 in a thin layer r, on the first polysilicon layer 3 reading back 1 1 7> 1 m margin film is deposited to .1 5 〇 The thickness of 5 0 0 A 0 1 1 1 2 The second polysilicon layer is then deposited on the insulating film to-a 1 0 〇5 intention 1 The thickness of I 〇0 A is 0. Then, a gate patterning step K is carried out to pattern the second polysilicon layer, the insulating film and the first polysilicon layer > Two polysilicon layer patterns 3 3 and an insulating film pattern 3 8 0 Subsequently — gold tungsten Sw ·· 1 I film 3 5 was deposited on the entire exposed surface of the resulting structure to a thickness of 1 〇〇1 I 1 〇〇0 A 0 1 1 set 1 followed by an annealing step Μ so that the gold film 3 5 can be in contact with the second polysilicon layer pattern 3 3 and the first polysilicon calendar 3 7 inverse atu 懕 9 1 1 thereby formed A metal silicide film 3 6 as shown in FIG. 1 0 1 1 m after the metal silicide film 3 6 is anisotropically etched to thereby form a line 1 on the side of the second polysilicon layer pattern 3 3 The metal film side wall 3 6 t is formed as shown in FIG. 15. Therefore, it is possible to obtain a Two polysilicon layers 1 | ring case 3 3, gold film side wall 3 6 r patterned first polysilicon layer 3 1 I 7 and patterned insulating film 3 8 gate 1 9 1 1 Figure 16 is — Sectional view »shows the use of the second polysilicon layer M case 1 1 3 3, metal film sidewalls 3 6 >, patterned first polysilicon layer 3 7 and 1 | patterned insulating film 3 8 as Etching of the gate oxide film 3 2 of a photomask 1 I agent situation 0 Although the gate oxide film 3 2 provided under the gate 3 9 has 1 1 a 10-1 1 1 this paper size is suitable for China National standard (CNS) A4 specification (210X297 mm) A7 B7 5. Description of invention (q) A small thickness, but because the first polysilicon layer 37 acts as an etching barrier film, the gate oxide film 3 2 Not etched. The gate oxide film may not be etched. As is apparent from the above description, the present invention provides a method for fabricating a M0 SFET, in which a polysilicon layer is deposited on a gate oxide film to make the gate of M 0 SF Ε Τ and Μ 0 The substrate separation of SF Ε Τ. The polysilicon layer acts as a K to prevent the gate oxide film from being etched when a gate is formed by using a metal film or a sidewall of gold-silicon ib as a photomask. Therefore, it is possible to prevent a short circuit from occurring between the semiconductor substrate and the gate electrode of the MOSFET, thereby improving the reliability of the semiconductor device. Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those familiar with the art should understand various changes that do not depart from the scope and spirit of the invention as disclosed in the accompanying patent application, Additions and substitutions are possible. Coffee Approval Clothing Order f (Please read the precautions on the back before filling this page) Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs -11- This paper standard applies to China National Standards (CNS) A4 (210X297mm)