S0S518 A7 B7 _ 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁) 本發明是有闞於一種在基體上製造溝播式DM O S電 晶鱧的结構和製程，特別是有闞於一新穎及改良的DMO S结構和製程，可Μ減少所需用的光罩次數，因而使生產 成本降低。 半導體元件的生產成本常因所需光罩次數的增加而受 到不利的影響。使用一般方法來製造一雙擴散氧化金羼半 専體（DM0S)元件，往往使成本偏高》其原因在於所 需的光罩次數因為技術上的困難而不易減少，且由於所需 光罩次數之不變，生產成本便不能降低。 除生產成本考慮之外*當製程中所褥光單減少時•生 產率也相對舍增高，因為在使用較少的光罩次數的簡化製 程中，一般而言，不肯定和不可控制之因素因降低而使生 產率改進。然而，在一般的DM0S製程技術中，不易達 成簡化、使用較少光軍次數和改良生產率的製程。 經濟部中央標準局員工消費合作社印製 在DM0S製程中，所需用的光軍次數和DM0S霣 晶《I的结構有密切的闞係。第一 Α圖和第一 Β圃分別顳示 一普通的DM0S元件10和10/的元件结構中在核心 單元區中典型的DM0 S單元的截面園。此DM0 S電晶 體是被一n +基«1 5所支撐，在基體上並形成有一n-晶膜層20。單元1 0包含有一深的P +體區25，一淺 P體區26，一源極區30，在源極區30和P«區26 中園鐃著蘭極40 *並以閘播氧化層35絕緣。然後在D M0S單元1 0上覆蓋M— PSG或BPSG保護層45 ，而後在源極區30之上形成接《點50。如圄所示，不 -4 - 本紙張尺度逋用中國國家標準彳CNS ) A4規格（210X29?公釐） A7 B7 i、發明説明（) 論是平面型或溝檐式DMOS都霈要源極區3 0和P +體 區25間短路形成一通道來通導源極至汲極區的電流。瑄 種一般性的结構製程要有Μ下基本要求： 1. 通常而言，深的Ρ +體區2 5和淺Ρ體區2 6是在 源極區3 0Μ前形成；及 2. 源極區3 0是在淺Ρ體區2 6之後形成*並且在淺 Ρ體區2 6之内有不同的造型。 由於在傳統的DM0 S製程中源極區3 0和淺Ρ體區 2 6有不同的造型，所Μ通常用兩種不同的光軍來形成深 的Ρ +體區25和源極區30。在過去所使用各種不同的 技術企圖來免除做源極植入所需的光軍•但此種技術即使 可以減免光罩，«是有下述其他的技術困難。 第二圖所示為一在Ρ體區2 6中形成源極區3 0的典 型方法。首先在Ρ體區26之上施以源極光罩來形成複數 個光阻隔55，然後Μ離子束60施Μ源極植入，其中部 份的離子束在形成源極區3 0時為光阻隔5 5所阻。由於 在此典型製程中，需用一光罩來形成光阻隔5 5，因之有 許多的美國專利都揭露出各種新方法來除去此光罩。 經濟部中央標準局貝工消費合作社印製 ---------^ -裝-- (請先閱讀背面之注意事項再填寫本頁) 線 在美國專利第4,443,931號「製造有深部的基礎區的 半導體元件方法j (1984年4月24日發表）*巴利加（Baliga )等揭露一元件是Μ在多晶矽閘蝕刻完後沉積一LPCV D氮化曆而製成的。其中施Μ一Ρ +光罩來打開一Ρ +擴 散窗口，然後一Ρ型摻雜劑經由Ρ +擴散窗口擴散•其後 一厚的氧化曆便在Ρ +擴散窗口上成長*再施以活性光覃 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） 經濟部中央標準局貝工消費合作社印裝 A7 ____B7_ 五、發明説明（） 來蝕刻起初的氧化層。因為在P +擴散窗口上長成的氧化 層比較厚，在蝕刻之後會有氧化「塞」殘留覆蓋部份的窗 口。此氧化塞便被用來在源極植入時做阻隔，此法受到技 術困難的限制而不能使電晶體縮小，因為當核心單元尺寸 縮小時，深的P +區可能會入侵到通道。此法也因製程複 雜而不麵實用。 巴利加等人在美國另一専利第4,567,641號「製造有 縮短的擴散區的半導體方法」中掲露一法其中可以免去源 極阻隔光罩。此法的製程顯示在第三A團到第三D圖中（ 在巴利加等之専利利中為第四A至第四D圖）。第三A圖 顯示一半導體200，即一矽晶Η包含有一N +汲極的基 體202和一N區204。在半導體200的上表面20 5上形成一絕緣曆206，上面再接著沉欖含有導電折射 材料的折射靥208。在這折射層208上再生長一曆氡 化矽絕緣雇2 1 0，最後在這絕緣層2 1 0上再沉積上一 氧化铝層211。其後用光石印術產生第三B圖中所示的 光單2 1 6來界定窗口 2 1 7，並在經由窗口的P型掮散 而形成P基礎區218時充做擴散阻隔用。 第三CH顯示經由窗口 2 1 7施行N +擴散而形成一 N +源極區220，其在折射層208下横向延伸而形成 一區2 2 2，此區的横向擴散距離和往下垂直擴散距離约 相等。N*匾的擴散是在增溫的氧化環境中發生，因之， 暴露的表面2 19 (第三B圖中所示）即氧化而形成氧化 層22 1。在第三D圓中，經由窗口 2 1 7在氧化層22 表紙張尺度逋用中國圃家揉芈（CNS > A4规格（210X297公釐〉 -----I-I 1^ 裝 111 11 I 訂----I L--《 線 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作杜印裝 A7 B7 五、發明説明（） 1上施以不等向蝕刻，穿透氧化層和N +區220 ·但使 N +源極220的肩部保持原搛。此不等向蝕刻劑是一垂 直對準的反應離子束或是平面的漿狀蝕刻劑K形成一般為 U形的播224 *或者也可形成V形榷。因此源極區2 2 0是形成於P基礎區218内而不爾用源極光軍。 巴利加等在第4,567,641號専利中所揭霣的半導體元 件製程，因為涉及非等向蝕刻必須穿透數層絕緣磨及折射 材料，如此複雜之程序而使其所限。此種程序較難執行， 因之花費也大。巴利加等的元件有其他的技術限制，即當 在P區2 1 8形成U形榷時，由於N +接觸面積減少，使 接觸電阻相對升高。因之，即使巴利加等的製程能減少源 極植入所需的光罩次數，但因為有較高的接觸電阻和較複 雑的製程·也不是有效的元件生產法。 因之，在生產DM0S功率元件的技藝中，尤其在設 計和製造上仍需有能解決上述困難的結構和製程。爱是， 本發明之主要目的及特點在於： 1. 提供一新的DM0S製程· K減少光罩次數，並以 克腋習知技術所面臨的限制。 2. 提供一改良的DM0S製程，使能免去其中為形成 源極區和P +區而分別需用的光罩•而減少DM0S晶體 製程的光軍次數。 3·提供一改良的DMOS製程，其中在起初氧化靥上 施以式樣的活性光眾•經特別姐態以在靠近源極區表面處 形成複數儸源極植入阻隔椿，Μ達到免除源極植入所需光 -7 - 本紙張尺度適用中國國家橾準（CNS ) Α4規^ ( 210X297公釐） - --------^—裝------訂---L--^ 線 (請先閲讀背面之注意事項再填寫本頁) 303518 A7 B7 五、發明説明（) 罩的目的。 4. 提供一改良的DMOS製程*其中用活性光軍而定 的源極植入姐隔椿的式樣是特別設計，K使其寬度小於體 摻雜劑擴散長度的兩倍•而大於源極接雜劑擴散長度的兩 倍，因而在擴散程序中因為體的合併而在源極阻隔椿下形 成一结合體，而源極區又不致在擴散時在阻隔樁下合併而 得Μ在體區内形成適當的造型。 5. 提供一改良的DMOS製程*其應用一簡化的製程 來減少所需的光罩次數，因而降低生產成本並提髙生產率 〇 這些目的及優點，對具一般技藝者而言，當參照下列 的圖示，並閱謓發明說明並研究各實施例後，一定無可置 疑地能明白本發明所閬述的内容。 為便貴審査委貝瞭解本發明之目的、特擻及功效， 玆藉由下述具«之實施例，並配合所附之圓式· i本發明 做一詳细說明： 圖示的簡單說明： 第一A圖和第一B圈分別為習知技術的平面型和满櫓式D Μ◦ S電晶體截面圖； 經濟部中央標準局貝工消费合作社印製 (請先閲讀背面之注意事項再填寫本頁) 第二面為一截面圖顯示出傳統式使用源極阻隔以植入源極 區之過程； 第三Α圖至第三D圖為截面圖顯示一習知專利中在DMO S電晶體中形成源極區的各步驟； 第四A圈至第四D圖顯示製造本發明之平面型DMO S元 本紙張尺度速用中國國家揉準（CNS > A4規格〆210X297公釐） 經濟部中央標隼局貝工消費合作社印裝 A7 B7 五、發明説明（） 件之各步驟； 第四E圖為本發明之另一實施例；及 第五A画至第五G圖顧示製造本發明之满槽式DMOS元 件之各步驟。 本發明揭露一新穎的DMOS製程*其中可免除傳統 方法中源極植入所需的光罩。其法為用一特別形狀的活性 光軍來使場氧化物定型而留下複數個厚的氧化墊作為植入 阻隔椿。這些厚的氧化墊在源極植入時成為阻隔區，因之 可Μ免去在源極植入前為形成源極胆隔而需的光罩。這些 氧化墊再Μ蝕刻法除去，此一新穎DMOS製程之詳细解 說如下。 第四Α圖至第四D圖為DMOS元件100之製程。 如第四A圖所示*首先在n +基體1 05生長一電阻係數 為0.1至10 ohm-cn之n_晶膜層1 1 0。n +基埋1 05 的霣阻係數為0.001至0.02 ohm-cn ·晶膜曆1 1 0的厚度 和霣阻係數依此元件對通路電阻和崩潰電壓的需求而定。 在一實施例中•晶膜靥1 1 0之厚度約為6至8 nicrons， 再長一厚為50nm至1.0/im之起初的氧化層，其厚度是為 儘量減少寄生效應和在下述步骤中阻隔摻雜劑之植入而定 ，然後施K —活性光罩即第一傾光罩使氧化靥1 1 5的式 樣成型而界定出活性區和複數個源極區阻隔「樁」1 1 8 。此場氧化層116是保持在元件面積的邊緣•在稍後的 製程中形成一终端區。與傅铳製法不同的是複數個源極阻 隔椿1 1 8被保留在源極區，如DΜ Ο S 100中的氧 (請先閲讀背面之注意事項再填寫本頁) -裝. 訂 線- 本紙張尺度適用中國國家搮準（CNS ) Α4規格（210X297公釐） 經濟部中央樣準局貝工消費合作社印装 A7 B7 五、發明説明（) 化墊。阻隔椿的横向尺寸<3是介於源極摻雜劑橫向擴散長 度的兩倍（2LS)和體（通道）摻雜劑横向擴散長度的兩 倍（2 Lb ) 之間，即： 2 Ls ^ d ^ 2 Lb 〇) 第四B_顯示首先施以閘極氧化程序Μ形成一厚摩為2至 200nm之閘極氧化層1 2 ◦，然後在其上沉積一厚為200至 lOOOnm之多晶矽層125，接著施MPOCL3摻雜程序 後，再M60至80 Kev及通量密度為5至8 X 1 0 16/cm2 之砷離子束植入，再加Μ—多晶矽光罩（第二個光罩）做 蝕刻Μ界定多晶矽閘極1 25。其後以30-100 Kev及通量 密度3 X 1 0 13 / cm2至3 X 1 0 14 / cm2來植入P體區 1 30 ·此體植入係Μ源極區上的厚氧化墊，即源極阻隔 椿1 1 8阻隔。起初兩個分開的Ρ體區1 30 — L和1 3 0—R分別形成於阻隔樁118的左、右邊，然後除去光 姐，而升溫至1 000至1 200t：十分鐘至三小時下施 MP體擴散來將P體區1 3 0增至1.0至6.0wm。由於培 1 1 8的寬度d比體摻雜劑横向擴散長度的兩倍小，在擴 散過程中*在阻隔椿1 1 8下的兩儼分開的P體區1 30 就合併為一 PS§區1 30。因此電晶體1 00就包含一擴 散合併的P體區1 3 0其造型為一寬而淺的W形，如第四 B圖所示。S0S518 A7 B7 _ V. Description of the invention () (Please read the notes on the back before filling in this page) The invention is based on the structure and process of manufacturing a trench-type DM OS electro-transformer on a substrate, especially Kan Yu's novel and improved DMO S structure and process can reduce the number of photomasks required, thereby reducing production costs. The production cost of semiconductor components is often adversely affected by the increase in the number of masks required. Use a general method to manufacture a pair of diffused oxidized gold oxide semi-density (DM0S) devices, which often makes the cost higher. The reason is that the number of masks required is not easy to reduce due to technical difficulties, and because of the number of masks required Without change, production costs cannot be reduced. In addition to production cost considerations * When the number of light sheets in the process is reduced, the productivity is also relatively high, because in the simplified process of using fewer mask times, in general, uncertain and uncontrollable factors are reduced due to And improve productivity. However, in the general DMOS process technology, it is not easy to achieve a process that is simplified, uses fewer optical troops and improves productivity. Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs In the DM0S manufacturing process, the number of optical troops required is closely related to the structure of DM0Yi Jing Jing I. The first Α-picture and the first Β-temporary show the cross-section of a typical DMOS cell in the core cell area in the element structure of a common DMOS cell 10 and 10 /, respectively. The DMOS electric crystal is supported by an n + base «15, and an n-crystal film layer 20 is formed on the base. Cell 10 contains a deep P + body region 25, a shallow P body region 26, and a source region 30. In the source region 30 and P «region 26, the blue electrode 40 is formed and the oxide layer 35 is broadcasted by the gate. insulation. Then, the M-PSG or BPSG protective layer 45 is covered on the D MOS cell 10, and then a contact 50 is formed on the source region 30. As shown, no-4-This paper scale uses the Chinese National Standards (CNS) A4 specifications (210X29? Mm) A7 B7 i. Description of invention () Whether it is a flat or ditch eaves type DMOS all have a source The short circuit between the region 30 and the P + body region 25 forms a channel to conduct the current from the source to the drain region. The general structure process of Xuan has the following basic requirements: 1. Generally speaking, the deep P + body region 25 and the shallow P body region 26 are formed before the source region 30 μm; and 2. The source electrode The region 30 is formed after the shallow P body region 26 and has a different shape within the shallow P body region 26. Since the source region 30 and the shallow p-body region 26 have different shapes in the conventional DMOS process, two different light sources are usually used to form the deep p + body region 25 and the source region 30. In the past, various technologies have been used in an attempt to eliminate the optical army required for source implantation. But even if this technology can reduce the photomask, there are other technical difficulties described below. The second figure shows a typical method of forming the source region 30 in the p-body region 26. First, a source mask is applied on the P body region 26 to form a plurality of light barriers 55, and then a M ion beam 60 is applied to the M source implant, and some of the ion beams are light barriers when forming the source region 30. 5 5 blocked. In this typical process, a mask is used to form the light barrier 55, so many US patents disclose various new methods to remove the mask. Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs --------- ^ -installed-- (Please read the precautions on the back before filling out this page) The line is in US Patent No. 4,443,931 "Manufacturing with deep parts Semiconductor device method j (published on April 24, 1984) in the basic area * Baliga (Baliga) and others revealed that a device was fabricated by depositing an LPCV D nitride calendar after etching the polysilicon gate. A P + mask to open a P + diffusion window, and then a P-type dopant diffuses through the P + diffusion window • A thick oxidation calendar will then grow on the P + diffusion window * and then apply active light The paper scale is applicable to the Chinese National Standard (CNS) Α4 specification (210X297 mm) Printed A7 ____B7_ in the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention () to etch the initial oxide layer. Because it grows on the P + diffusion window The formed oxide layer is relatively thick. After etching, there will be a window where the oxide "plug" remains to cover the part. This oxide plug is used as a barrier during source implantation. This method is limited by technical difficulties and cannot shrink the transistor, because when the size of the core unit is reduced, the deep P + region may invade the channel. This method is not practical because of the complicated process. Barriga et al. Disclosed another method in US No. 4,567,641 "Semiconductor Method for Manufacturing Shortened Diffusion Regions" in which source blocking masks can be eliminated. The process of this method is shown in the third A group to the third D chart (the fourth A to the fourth D chart in the parili of Baliga and others). The third figure A shows a semiconductor 200, that is, a silicon crystal H including a substrate 202 having an N + drain and an N region 204. An insulating calendar 206 is formed on the upper surface 205 of the semiconductor 200, and then a refraction 208 containing a conductive refractive material is deposited on the surface of the semiconductor. On this refraction layer 208, a silicon nitride insulating layer was regrown for 2 1 0, and finally an aluminum oxide layer 211 was deposited on this insulating layer 2 10. Afterwards, photolithography is used to generate the light sheet 2 16 shown in the third figure B to define the window 2 1 7 and serve as a diffusion barrier when the P base region 218 is formed through the P-type dispersal of the window. The third CH shows that an N + source region 220 is formed by performing N + diffusion through the window 2 1 7, which extends laterally under the refractive layer 208 to form a region 2 2 2. The lateral diffusion distance of this region and the vertical diffusion downward The distance is about equal. The diffusion of the N * plaque takes place in a warmed oxidizing environment, so that the exposed surface 2 19 (shown in the third figure B) is oxidized to form an oxide layer 22 1. In the third circle D, through the window 2 1 7 on the oxide layer 22, the paper scale is made with Chinese garden furniture (CNS > A4 specification (210X297mm) ----- II 1 ^ loaded 111 11 I set ---- I L-- "Line (please read the precautions on the back before filling in this page) The Central Standards Bureau of the Ministry of Economic Affairs Beigong Consumer Cooperation Du Printed A7 B7 V. Description of invention () 1 unequal orientation Etching, penetrating the oxide layer and the N + region 220 · but keeping the shoulder of the N + source 220 intact. This anisotropic etchant is a vertically aligned reactive ion beam or a planar slurry etchant K The formation of a generally U-shaped broadcast 224 * or a V-shape can also be formed. Therefore, the source region 2 2 0 is formed in the P base region 218 without using the source auroral army. Barriga et al. No. 4,567,641 The disclosed semiconductor device manufacturing process is limited by such complicated procedures as it involves anisotropic etching that must penetrate several layers of insulating and refractive materials. Such procedures are more difficult to perform and therefore cost more. Barry The other components have other technical limitations, that is, when a U-shaped problem is formed in the P region 2 18, the contact area is reduced due to the reduced N + contact area. The resistance is relatively high. Therefore, even if the process of Barriga et al. Can reduce the number of photomasks required for source implantation, it is not an effective component production method because of the higher contact resistance and the more complex process. Therefore, in the technique of producing DMOS power components, especially in design and manufacturing, there is still a need to have a structure and process that can solve the above difficulties. The main purpose and features of the present invention are: 1. To provide a new DMOS process · K reduces the number of photomasks and uses the limitations faced by the conventional technology. 2. Provides an improved DMOS process to eliminate the need for separate photomasks to form the source region and the P + region. And reduce the number of optical troops in the DM0S crystal process. 3. Provide an improved DMOS process, in which an active light beam is applied to the initial oxide oxide. • A special state is used to form a complex source near the surface of the source region. Implant blocking Tsubaki, M can be exempted from the light needed for source implantation -7-This paper scale is applicable to China National Standards (CNS) Α4 regulation ^ (210X297mm)--------- ^-installed- ----- Subscribe --- L-^ line (please read the notes on the back before filling (This page) 303518 A7 B7 5. The purpose of the invention () The cover. 4. Provide an improved DMOS process * In which the source of the active light army depends on the design of the implant is specially designed, K makes it wide Less than twice the diffusion length of the body dopant and more than twice the diffusion length of the source dopant, so in the diffusion process, a combination is formed under the source barrier due to the body combination, and the source region is It will not be merged under the barrier pile during diffusion to obtain an appropriate shape in the body area. 5. Provide an improved DMOS process * which uses a simplified process to reduce the number of masks required, thereby reducing production costs and To improve productivity. For those skilled in the art, when referring to the following diagrams, and after reading the description of the invention and studying the embodiments, it is undoubtedly possible to understand the contents of the present invention . In order for your review committee to understand the purpose, features, and effects of the present invention, the following examples with «, and the accompanying round form : The first picture A and the first circle B are the cross-sectional view of the planar and full-screw D M S transistors of the conventional technology; printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the notes on the back first (Fill in this page again) The second side is a cross-sectional view showing the traditional process of using source blocking to implant the source region; Figures 3A to 3D are cross-sectional views showing a conventional patent in DMO S The steps of forming the source region in the transistor; Figures 4A to 4D show the manufacturing speed of the flat DMO S paper of the present invention. The paper scale is prepared by the Chinese National Standard (CNS > A4 size 〆210X297mm) A7 B7 printed by Beigong Consumer Cooperative of Central Standard Falcon Bureau of the Ministry of Economic Affairs 5. Steps for the description of the invention; Figure 4E is another embodiment of the invention; and Figure 5A to Figure 5G The steps of manufacturing the full-groove DMOS device of the present invention. The present invention discloses a novel DMOS process * in which the mask required for source implantation in the conventional method can be eliminated. The method is to use a special shape of the active light army to shape the field oxide and leave a plurality of thick oxide pads as implant barriers. These thick oxide pads become barriers when the source is implanted, so that the mask needed to form the source bile before implantation can be eliminated. These oxide pads are removed by M etching. The detailed explanation of this novel DMOS process is as follows. Figures 4A to 4D show the manufacturing process of the DMOS device 100. As shown in the fourth diagram A * first, an n_crystalline film layer 1 1 0 having a resistivity of 0.1 to 10 ohm-cn is grown on the n + substrate 105. The resistance coefficient of n + base buried 105 is 0.001 to 0.02 ohm-cn. The thickness and resistance coefficient of the crystal film 1 1 0 depend on the requirements of this component for the resistance of the path and the breakdown voltage. In one embodiment, the thickness of the crystal film 1 1 0 is about 6 to 8 nicrons, and then an initial oxide layer with a thickness of 50 nm to 1.0 / im is added. Its thickness is to minimize parasitic effects and in the following steps Depending on the implantation of the blocking dopant, a K-active photomask, that is, the first tilting photomask, is formed to form the pattern of the oxide 1 1 5 to define the active region and the source regions to block the "pile" 1 1 8 . This field oxide layer 116 is kept at the edge of the device area. A termination area is formed in a later process. The difference with the Fu-Zhong method is that a plurality of source barriers 1 1 8 are retained in the source region, such as oxygen in DΜ Ο S 100 (please read the precautions on the back before filling in this page) -installation. Threading- This paper scale is applicable to China National Standard (CNS) Α4 specification (210X297mm). The Central Sample Bureau of the Ministry of Economic Affairs, Beigong Consumer Cooperatives, prints A7 B7. 5. Description of the invention () pad. The lateral dimension of the barrier element <3 is between twice the lateral diffusion length of the source dopant (2LS) and twice the lateral diffusion length of the body (channel) dopant (2 Lb), ie: 2 Ls ^ d ^ 2 Lb 〇) The fourth B_ shows that the gate oxidation process M is first applied to form a gate oxide layer 1 2 with a thickness of 2 to 200 nm, and then a polysilicon with a thickness of 200 to 100 nm is deposited on it Layer 125, followed by the MPOCL3 doping process, then implanted with arsenic ion beam with M60 to 80 Kev and flux density of 5 to 8 X 10 16 / cm2, and then added M-polysilicon mask (second mask ) Do etching to define the polysilicon gate 1.25. After that, the body region 1 30 is implanted with 30-100 Kev and flux density 3 X 1 0 13 / cm2 to 3 X 1 0 14 / cm2. This body implant is a thick oxide pad on the source region of M, That is source blocking 1 1 8 blocking. At first, two separate P body regions 1 30 — L and 1 3 — 0 — R were formed on the left and right sides of the barrier pile 118 respectively, and then the light sister was removed, and the temperature was raised to 1 000 to 1 200 t: 10 minutes to 3 hours. The MP body diffuses to increase the P body region 130 to 1.0 to 6.0 wm. Since the width d of the culture 1 18 is less than twice the lateral diffusion length of the bulk dopant, during the diffusion process * the two separate P body regions 1 30 under the barrier 1 1 8 merge into one PS§ region 1 30. Therefore, the transistor 100 includes a diffused and merged P body region 1 3 0 whose shape is a wide and shallow W shape, as shown in the fourth B diagram.
在第四C圖中，應甩源極阻隔椿1 1 8為源極阻隔， 並 M60-100 Kev ·通量密度為 5 X 1 0 15/cm2 至 3 X 1 0 16/ cm2做n +植入來形成源極區140。和傳統DM 本紙張尺度適用中國國家揉準（CNS ) Λ4規格（210X297公釐） ^ ·裝 訂 f 踩 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標隼局負工消費合作社印装 A7 B7五、發明説明（） 0 S製法不同的是，此源極植入並不需用光罩。此Π +源 搔區1 4 0再以擴散程序使接面深度到達所要的0.2至1.0 //m。由於阻隔椿1 1 8的寬度d比源極摻雑劑横向掮散 長度的兩倍大，在阻隔椿1 1 8之下的源極區1 40並不 合併。 第四D圖顯示將BP SG或P SG沉積來形成厚為5 ◦ 00至1 5000A的電介質絕緣層145，再M90 0至95 ΟΌ溫度下通MBP SG流或MP SG加密處理 3 0分鐘至一小時，然後用一接觸光罩（第三個光罩）來 蝕刻穿過P SG或PBSG絕緣層1 45和氧化層1 20 來界定接觸窗口。在此蝕刻程序中·阻隔樁1 1 8也被除 去。P +離子植入是在900 — 95〇·〇的氧化或惰性氧 體環境內，ΜΡ +活性程序而形成Ρ +區1 50。最终的 DMOS元件100是用金羼光罩（第四光罩）加Μ金羼 沉積和金属蝕刻來界定源極接點（S)l 60、閛極接點（G) 170、場板（FP)180和等位環（EQR)185而完成。 若需要鈍化層和有式樣的墊•則亦可用墊光罩（第五個光 罩）。因此本發明所揭露之新顆的四或五光罩之DΜ Ο S 製程•是應用特別式搛的起初氧化層和活性光簞次數來做 為源極植入阻隔而成，而達成減少所需光罩的目的。此法 利用源極摻雜劑和體摻雜劑擴散長度的不同，並利用一新 穎的涯極植入阻隔姐態來除去源槿胆隔光罩的必要性。 第四Ε圖為另一實施例其中顯示出Ρ體區1 3 0 — L 和130-R在Ρ體横向擴散時並未合併而有小距離的間 -11 - 本紙張尺度適用中國國家標準（CNS ) Α4规格（210Χ297公釐） (請先閱讀背面之注意事項再填寫本頁) -裝· 訂 年 經濟部中央橾準局貝工消費合作社印製 A7 、、_E_ 五、發明説明（） 隔。而其後的P+植入形成了一p+區橋150，將左邊 的P體區1 30 — L和右邊的PSI區1 30 — R相連。 第五A圔至第五Η園顯示本發明所揭鑼之溝槽式DM OS元件300製程的各步驟。如第五A圖所示，首先先 在n+基SI 3 0 5上長一電胆係數為0.1至10 〇hm-cm的η 晶膜層310，此η +基體3 0 5之電砠係數為0.001至 0.002 ohin-cm。晶膜餍3 1 0之厚度和電阻係數係依元件 之通路電阻和崩潰電壓之需求而定。在一實施例中，此晶 膜庸3 10約厚3至20//1〇。然後生長一厚約1〇11111至10“ m的起初氧化層3 1 5，此厚度是為儘量減少寄生效應和 在下述步驟中阻隔摻雜劑之植入而定，然後施以一活性光 罩（第一個光軍）使氧化層3 15的式樣成型而界定出活 性匾和複數個源極阻隔「椿」3 1 8。此場氧化層3 1 5 是保持在元件面稹的«緣，在稍後的製程中形成一终端厚 。與傅统製法不同的是複數個源極阻隔椿318被保留在 源極區如DM0S 300中之氧化墊。阻隔椿的横向尺 寸d是介於源極播雜劑横向擴散長度的兩倍（2 Ls)和體 (通道）摻雜劑横向擴散長度的兩倍（2Lb)之間。 因之阻隔樁318的寬度可以用方程式⑴來表示。 第五B圖顬示出用一光電阻做光罩（溝槽光罩），以 一乾性而不等向的蝕刻來刻出1.0至2.O/izm宽和1.0至2.0 //m深的满榷。然後在900至1 100Ϊ：之溫度下，施 Μ或乾性或濕性的「播牲打式」氧化程序來形成厚約30 0至2000Α的氧化層，再加Μ—「犧牲打式」蝕刻， -12 - 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） ---------^-裝------訂-----^線 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作社印製 ^3518 A7 -------- 五、發明説明（) 接著再在8 0 0至1 ΙΟΟΐ：溫度下加Μ乾性或濕性的閘 極氧化程序而形成閘極氧化層3 1 9約厚3 0 0至1 0 0 0 A，然後再Μ沉積程序沉積一厚1.5# m至3.0w m之多 晶矽層320 。在此層之上再施K平面蝕刻使厚度成為 0.2至0.4ium，之後在9501下施MPOCL3接雜程 序使多晶矽層3 2 0有20至40 ohm2 / cb的平面電阻。在 第五C圖中所示，在多晶矽3 2 0上施Μ —乾性蝕刻直到 表面被除去而留下源極阻隔椿為止。此多晶矽蝕刻係採用 终端偵測法Κ測知當溝槽上的多晶矽層一除去而立即中止 蝕刻。 在第五D圖中顯示用30至100 Kev，通量密度為2Χ 1 0 13至2x 1 0 14 / cm2的硼離子施行P體植入Μ形成 Ρ體區330。體植入係Μ源極區上的厚氧化墊318 ( 即源極阻隔椿）來阻隔。起初兩個分開的Ρ體區330— L和330 — R分別形成於阻隔樁3 1 8的左、兩邊。第 五Ε圖顯示Ρ應區在升溫至1 000至1 2001C下1 0 分鐘至三小時的擴散處理•來使Ρ體區330的深度增至 1.0至2.0« m。由於阻隔椿的横向宽度d比體摻雜劑横向 擴散長的兩倍為小，在擴散處理時，此二分開的Ρ»區會 在阻隔椿3 1 8之下合併而成為一個P體區3 3 0，因之 電晶體300即含有一由擴散而合併的P體區330其造 型為一寬而淺的W形如第五E園所示。 11+植入係採用50至1001^^通量密度為5\1015 至1 X 1 CM6/cm2之砷或磷離子，並用源極阻隔椿3 1 -13 - 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） f ·裝 訂 ϋ f 銀 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消费合作杜印裝 A7 B7 五、發明説明（） 8作為源棰阻隔施Κη +植入而形成n +區340。和傳 統DMO S製程不同的是•源極植入並不需用光罩。此η + 區再經於900至1 0001C溫度下1 0分鐘至兩小時的 擴散，而得到理想的0*2至l.Owm深的接面深度。由於阻 隔椿的寬度d比源極摻雜劑横向擴敗長度的兩倍為大，此 源極區在阻隔樁318之下就不會合併。 第五F圖中顯示在表面上形成一低壓化學汽沉積（L PCVD)氮化層338。一BPSG或PSG經沉積而 形成一厚約5000至1 5000A之一層345，後在 900至95〇υ下30分鐘至一小時施MBP SG流或 PSG加密處理，然後用一接觸光罩（第三個光罩）來蝕 刻穿過P SG或BPSG層345和氮化層338來界定 接觸窗口。在此蝕刻過程中，阻隔樁3 1 8也被除去。最 終的DMOS元件3 0 0是用金靥光罩（第四個光罩）Μ 金羼沉積和金靥蝕刻來界定源極接點、Μ極接點、埸板、 等位環和通道站（channel stop)，如第五G圖所示，由於 使用氮化曆338就不再需有鈍化靥和墊來作式樣，因之 墊光罩（.第五個光罩）就不禰要了。因之•此新穎的製程 揭露了一個用四個光罩的製程利用特別式樣的起初氧化層 和活性光罩來做為源極植入阻隔而成而達到減少光軍數的 目的。此種改良是由於製程中利用以下各點：1.體摻雜劑 和源極摻雜劑横向擴敗長度不相同，2.利用氮化保護曆3 38，及3.用一新穎的源極植入阻隔組態來免除源槿阻隔 光罩的需求。 -14 - 本紙張尺度適用中國國家揉準（CNS ) A4规格（210X297公釐） I I I I I I —^ -裝 — I I I I I 訂 I I ( 線 (請先閱讀背面之注意事項再填寫本頁) A7 B7 五、發明説明（） 雖然本發明Μ上述之實施例敘述，但Μ下所揭露及說 明之具體描述，並不作為解釋本發明權利範圍之侷限。一 旦閱謓本發明揭露之內容，對具一般技藝人士、各樣之變 化、修改即已明白。因之，下列之專利權利要求項，只要 變化及修改不出本發明的精意及内容者，都應被納入、包 含在本發明權利範圍之内。 I--------C -I-- (請先閱讀背面之注意事項再填寫本頁) 、vs 經濟部中央標準局員工消費合作社印製 -15 - 本紙張尺度適用中國國家梂準（CNS ) A4規格（2丨0X297公釐）In Figure 4C, the source barrier should be thrown away. 1 1 8 is the source barrier, and M60-100 Kev · The flux density is 5 X 1 0 15 / cm2 to 3 X 1 0 16 / cm2.入 来 Formation of the source region 140. And traditional DM This paper standard is applicable to China National Standard (CNS) Λ4 specification (210X297mm) ^ · binding f stamp (please read the precautions on the back before filling in this page) Printed by the Ministry of Economic Affairs Central Standard Falcon Bureau Negative Work Consumer Cooperative Pack A7 B7 V. Description of the invention () 0 The difference in the manufacturing method is that this source implant does not require a photomask. This Π + source scratching area 1 4 0 then uses the diffusion procedure to bring the junction depth to the desired 0.2 to 1.0 // m. Since the width d of the barrier element 1 18 is greater than twice the length of the lateral dispersion of the source dopant, the source regions 1 40 below the barrier element 1 18 do not merge. Figure 4D shows the deposition of BP SG or P SG to form a dielectric insulating layer 145 with a thickness of 5 ◦ 00 to 1 5000A, and then through MBP SG flow or MP SG encryption processing at a temperature of M90 0 to 95 ΟΌ for 30 minutes to one Hours, then use a contact mask (third mask) to etch through the P SG or PBSG insulating layer 1 45 and oxide layer 1 20 to define the contact window. In this etching procedure, the barrier pile 1 1 8 was also removed. P + ion implantation is in the oxidized or inert oxygen environment of 900-95〇.〇, MP + active program to form P + region 150. The final DMOS element 100 is defined by a gold mask (fourth mask) plus M gold coating and metal etching to define the source contact (S) 160, the junction electrode (G) 170, and the field plate (FP) 180 It is completed with the equipotential ring (EQR) 185. If you need a passivation layer and a patterned pad, you can also use a pad mask (fifth mask). Therefore, the new four- or five-mask DM O S process disclosed by the present invention is to use a special type of initial oxide layer and the number of active photodiodes as the source implantation barrier to achieve the reduction of the need The purpose of the photomask. This method takes advantage of the difference in diffusion length between the source dopant and the bulk dopant, and uses a new Yingjiji implantation barrier to remove the necessity of the source mask. The fourth Ε picture is another embodiment which shows that the P body regions 1 3 0 — L and 130-R are not merged when the P body laterally diffuses and there is a small distance between them -11-This paper scale is applicable to the Chinese national standard ( CNS) Α4 specification (210Χ297mm) (Please read the precautions on the back before filling in this page)-installed · A7, _E_ printed by the Central Economic and Trade Bureau of the Ministry of Economic Affairs, Pongong Consumer Cooperative, V. Description of invention () . The subsequent P + implantation forms a p + region bridge 150, connecting the left P body region 1 30-L and the right PSI region 1 30-R. The fifth to fifth circles show the steps of the trench DM OS device 300 manufacturing process disclosed in the present invention. As shown in the fifth diagram A, first, an η crystal film layer 310 with an electric bladder coefficient of 0.1 to 10 ohm-cm is grown on the n + group SI 3 0 5, and the electric coefficient of η + substrate 3 0 5 is 0.001 to 0.002 ohin-cm. The thickness and resistivity of the crystal film 3 1 0 are determined by the requirements of the path resistance and breakdown voltage of the device. In one embodiment, the crystal film is approximately 3 to 20 // 1 thick. Then grow an initial oxide layer 315 with a thickness of about 1011111 to 10 "m. This thickness is to minimize parasitic effects and block the implantation of dopants in the following steps, and then apply an active photomask (First Light Army) The shape of the oxide layer 3 15 is shaped to define the active plaque and a plurality of source barriers "Thun" 3 1 8. The field oxide layer 3 1 5 is kept on the edge of the element surface, and a terminal thickness is formed in the later process. The difference from the Fu control method is that a plurality of source barriers 318 are retained in the source region such as the oxide pad of the DMOS 300. The lateral dimension d of the barrier is between twice the lateral diffusion length of the source dopant (2 Ls) and twice the lateral diffusion length of the bulk (channel) dopant (2 Lb). Therefore, the width of the barrier pile 318 can be expressed by equation (1). The fifth picture B shows that a photoresist is used as a photomask (trench photomask), and a dry and unequal etching is used to engrave 1.0 to 2.0 / izm wide and 1.0 to 2.0 // m deep Full of doubts. Then, at a temperature of 900 to 1 100 Ϊ :, apply M or dry or wet "broadcasting" oxidation process to form an oxide layer with a thickness of about 300 to 2000 A, and then add M-"sacrificial hitting" etching, -12-This paper scale is applicable to China National Standard (CNS) Α4 specification (210Χ297mm) --------- ^-installed ------ order ----- ^ line (please read first Note on the back and then fill out this page) Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs ^ 3518 A7 -------- V. Description of invention () Then add it at 800 to 1 ΙΟΟΙ: temperature A dry or wet gate oxidation process is used to form a gate oxide layer 3 1 9 with a thickness of about 300 to 100 A, and then a polysilicon layer 320 with a thickness of 1.5 # m to 3.0wm is deposited by the M deposition process. K-plane etching is performed on this layer to make the thickness 0.2 to 0.4ium, and then the MPOCL3 junction process is applied under 9501 to make the polysilicon layer 3 20 have a planar resistance of 20 to 40 ohm2 / cb. As shown in the fifth C diagram, dry etching is performed on the polysilicon 320 until the surface is removed, leaving the source barrier. This polysilicon etching system uses the terminal detection method K to detect that the polysilicon layer on the trench is removed as soon as the etching is stopped. In the fifth graph D, it is shown that 30 to 100 Kev and a boron ion with a flux density of 2 × 10 13 to 2 × 10 14 / cm 2 are used to perform P-body implantation M to form the P-body region 330. The body implantation is blocked by a thick oxide pad 318 on the source region (ie, the source block). Initially, two separate P-body regions 330-L and 330-R are formed on the left and both sides of the barrier pile 3 1 8 respectively. The fifth graph E shows the diffusion treatment of the P-stress region at a temperature of 1 000 to 1 2001 C for 10 minutes to 3 hours to increase the depth of the P-body region 330 to 1.0 to 2.0 mm. Since the lateral width d of the barrier stump is smaller than twice the lateral diffusion length of the bulk dopant, during the diffusion process, the two separated P »regions will merge under the barrier stump 3 1 8 to become a P body region 3 30, because the transistor 300 contains a P body region 330 merged by diffusion, and its shape is a wide and shallow W-shape as shown in the fifth E circle. The 11+ implantation system uses 50 to 1001 ^^ flux density of 5 \ 1015 to 1 X 1 CM6 / cm2 arsenic or phosphorus ions, and uses the source to block Tsubaki 3 1 -13-This paper scale is applicable to the Chinese National Standard (CNS ) A4 specification (210X297mm) f · binding ϋ f silver (please read the precautions on the back before filling this page) Employee's consumer cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs A7 B7 5. Invention description () 8 as source The n + region 340 is formed by blocking Kn + implantation. Unlike the traditional DMO S process, the source implant does not require a photomask. This η + region is further diffused at a temperature of 900 to 1 0001C for 10 minutes to two hours to obtain an ideal junction depth of 0 * 2 to 1.0 Wm deep. Since the width d of the barrier element is greater than twice the lateral spreading length of the source dopant, the source region will not merge under the barrier pile 318. Figure 5F shows a low-pressure chemical vapor deposition (LPCVD) nitride layer 338 formed on the surface. A BPSG or PSG is deposited to form a layer 345 with a thickness of about 5000 to 15000A, and then the MBP SG stream or PSG encryption process is applied at 900 to 95 ° V for 30 minutes to one hour, and then a contact mask (third Photomasks) to etch through the P SG or BPSG layer 345 and the nitride layer 338 to define the contact window. During this etching process, the barrier posts 3 18 are also removed. The final DMOS device 3 0 0 is to define the source contact, the M electrode contact, the field plate, the equipotential ring and the channel stop by the gold mask (the fourth mask) Μ Jinqi deposition and gold etch ), As shown in the fifth graph G, because the use of nitride calendar 338 no longer requires passivation and pads as a pattern, so the pad mask (. Fifth mask) is not necessary. Therefore, this novel process reveals that a process using four masks uses a special pattern of initial oxide layer and active mask to form the source implantation barrier to achieve the purpose of reducing the number of optical troops. This improvement is due to the use of the following points in the manufacturing process: 1. The lateral spreading length of the bulk dopant and the source dopant are not the same, 2. The use of a nitride protection calendar 3 38, and 3. The use of a novel source A barrier configuration is implanted to eliminate the need for Yuanjin to block the photomask. -14-This paper scale is applicable to China National Standard (CNS) A4 (210X297mm) IIIIII — ^-装 — IIIII Order II (Line (please read the precautions on the back before filling this page) A7 B7 V. Invention Description () Although the above embodiments of the present invention are described, the specific descriptions disclosed and described below are not intended to limit the scope of the rights of the present invention. Once reading the contents disclosed by the present invention, those skilled in the art and various Such changes and modifications are already understood. Therefore, the following patent claims should be included and included in the scope of the rights of the present invention as long as the changes and modifications do not reveal the spirit and content of the present invention. ------- C -I-- (Please read the precautions on the back before filling out this page), vs. Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs -15-This paper standard applies to China National Standards (CNS ) A4 specification (2 丨 0X297mm)