.. _ * ·—-. .......-. ____:-.. 經濟部中央標準局貝工消費合作社印製 οϋϋόόο Α7 Β7五、發明説明（） 本發明係有闞於平面型DMO S的结構和製程•特別 是有關於一新穎及改良的使用淺擴散程序來製造高密度平 面型DMO S電晶體的结構和製程K達到降低導通電阻而 又不犧牲崩潰電壓的目的。 一般製造平面型雙擴散氧化金属半導體（DMOS) 電晶體的结構和製程常因為技術困難而有所限制。特別是 一般平面型DMOS電晶體是用高摻雜劑P4擴散區在核 心簞元區形成深的P*區而成。此P*摻雜區之形成是特 別為了達到高崩潰電壓和更好的元件韌性而設計。如第一 圖所示，在一個一般的DMOS 10中的深P*區15 是在核心單元區中形成，和一P·區18是在终端區中植 入形成等位環2 0，Μ便避免在终端區發生提早崩潰的現 象。此一般结構的製造有以下缺點：Ο)需用一複雜和昂貴 的氮化硼程序來形成無缺陷的高質量、高摻雜度、深的Ρ |區。雖可用澹硼離子植入代替，但在氧化過程中•此法 無法避免固有的「矽缺陷j等問題。（2)在形成場板時需先 生長厚的氧化層以及其他數個步驟·每個均箱要不同的光 罩*因而造價相當昂貴。⑶為要形成一等位環25，需要 用一額外的Ρ體光罩在Ρ體植入時攔阻離子Κ免避離子進 入通道站（channel stop)區。在第二圜所示的高密度DM 0SI8晶體3 ◦中，因多晶矽閘極之間的空間小，而不能 使用深的P*擴散•因為横向擴散的長度較長，當延伸而 由•只能MP體擴散在場板形成P4區40，而不能肜成 碰到通道區時，可能會造成臨限電壓的浮動。為上述各理 -----------^ -裝------訂-----U.紙 (請先聞讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 83.3. 10,000 Α7 Β7 經濟部中央橾率局貝工消費合作社印製 五、發明説明（） 深P ♦區。 其他的技術包括有在終端區用保護環等法來改良崩潰 電壓。第三A圖至第三E圖顯示製造一般η通道在終端區 有保護環的DMOS電晶體50的製程。首先在η-晶膜 層5 2上長一厚的起初氧化層5 5，再用光罩加Κ濕性蝕 刻來界定一深Ρ*區60，然後用氮化硼或硼植入來形成 Ρ ♦區6 0，再應用熱驅（heating drive)程序將在卩* 區内的摻雜劑驅動來形成一深的P*區60，同時，在P* 區60的表面再生長另一厚的氧化層·其後施Μ—活性光 罩7◦來界定活性區·如第三Β圖所示。在一氧化蝕刻步 驟後，在活性層的Ρ ♦區60表面上留下一氧化塞72 · 如第三C圖所示。然後生長一閘極氧化層·再沉積一層多 晶矽層，再KP〇CL3摻雜來形成一多晶矽。第三 D圖中·顯示在透過一 Ρ體光罩做硼植入，並Κ擴散來形 成Ρ體區7 5後*多晶矽光罩即被剝除。然後不用光罩施 Μ砷或磷植入來形成一 η*區80如第三Ε画所示，在此 一步驟中，氣化塞7 2是用來做為光軍而在植入過程中阻 隔η*鐮子。Μ上描述的製程有以下缺點：首先*由於在 起初氧化層5 5上豳Μ濕性蝕刻使得保護環間的空間不容 易控制。崩潰電壓對分隔保護環6 0間的空間非常靈敏· 對高密度低罨壓DM0S電晶骽其霉壓為100 volts Μ下 者尤其《敏。況且，生長厚的氧化層5 5和一無缺陷高摻 雜劑量Ρ·區60的程序十分昂貴。 對高密度低電壓DM0S電晶體而言，元件的結構和 - 2 ~ 本紙張尺度適用中國國家標準（CNS > Α4说格（210Χ297公釐〉 83.3.10,000 (請先閲讀背面之注意事項再填寫本頁) 、裝i 、?τ " A7 B7 經濟部中央標準局負工消費合作社印製.. _ * ·-. .......-. ____:-.. Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. 5. Description of the invention () This invention has a flat type Structure and process of DMO S • In particular, there is a novel and improved structure and process K for manufacturing high-density planar DMO S transistors using a shallow diffusion process to achieve the goal of reducing on-resistance without sacrificing breakdown voltage. Generally, the structure and process of manufacturing a planar double-diffused metal oxide semiconductor (DMOS) transistor are often limited due to technical difficulties. In particular, the general planar DMOS transistor is formed by forming a deep P * region in the core element region with a high dopant P4 diffusion region. The formation of this P * doped region is specially designed to achieve high breakdown voltage and better device toughness. As shown in the first figure, the deep P * region 15 in a general DMOS 10 is formed in the core unit region, and a P · region 18 is implanted in the terminal region to form an equipotential ring 20. Avoid premature crashes in the terminal area. The manufacture of this general structure has the following disadvantages: Ο) A complex and expensive boron nitride procedure is required to form defect-free high-quality, high-doping, deep P | regions. Although it can be replaced by boron ion implantation, in the oxidation process, this method cannot avoid the inherent "silicon defect j and other problems. (2) In the formation of the field plate, a thick oxide layer and several other steps are required. Each mask requires a different mask * and is therefore quite expensive. (3) To form an equipotential ring 25, an additional P-body mask is needed to block the ion Κ during implantation of the P-body to avoid the ion from entering the channel station (channel stop) area. In the high-density DM 0SI8 crystal 3 shown in the second circle, the space between the polysilicon gates is small and the deep P * diffusion cannot be used. Because the length of the lateral diffusion is longer, when extended By • Only the MP body can diffuse to form the P4 region 40 on the field plate, but not when it touches the channel region, it may cause the threshold voltage to float. For the above reasons ----------- ^ -Installed ------ ordered ----- U. Paper (please read the precautions on the back and then fill out this page) The paper size is applicable to China National Standard (CNS) A4 specification (210X297mm) 83.3. 10,000 Α7 Β7 Printed by the Beigong Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economic Affairs V. Description of invention () Shenzhen P ♦ District. Other technologies Including the use of a guard ring in the terminal area to improve the breakdown voltage. Figures 3A to 3E show the manufacturing process of the general n-channel DMOS transistor 50 with a guard ring in the terminal area. First, in the n-crystal film layer 5 2 a thick initial oxide layer 5 5, then use a photomask and K wet etching to define a deep Ρ * region 60, and then use boron nitride or boron implantation to form Ρ region 60, and then apply The heating drive process drives the dopant in the * region to form a deep P * region 60, and at the same time, another thick oxide layer is regrown on the surface of the P * region 60. —The active photomask 7◦ defines the active area. As shown in the third B. After an oxidative etching step, an oxide plug 72 is left on the surface of the active layer P area 60. As shown in the third C. Then, a gate oxide layer is grown. A polysilicon layer is deposited and doped with KP〇CL3 to form a polysilicon. In the third figure, it is shown that boron is implanted through a P-body mask and K is diffused to form After the P-body region 75, the polysilicon mask is stripped off. Then the arsenic or phosphorus implant is not used to form an η * region 80 as shown in the third E painting In this step, the gasification plug 72 is used as a light army to block η * sickle during the implantation process. The process described in M has the following disadvantages: first * due to the initial oxide layer 5 5 The wet etching of the BM makes the space between the protection rings difficult to control. The breakdown voltage is very sensitive to the space separating the protection ring 60. For the high-density and low-pressure DM0S transistor, the mold pressure is 100 volts. Moreover, the procedure for growing a thick oxide layer 55 and a defect-free high doping dose P · region 60 is very expensive. For high-density low-voltage DM0S transistors, the structure of the device and the paper size are applicable China National Standards (CNS > Α4 said grid (210Χ297mm> 83.3.10,000 (please read the notes on the back before filling out this page), install i,? Τ " A7 B7 Ministry of Economic Affairs Central Standards Bureau Negative Workers Consumer Cooperative Print
五、發明説明（） 製程仍然被生產容量和費用的問題而限制•因之*此技» 仍需要能解決此限制的结構和製程。爰是，本發明之主要 特點在於： ⑴提供一改良的DMO S结構、拓樸和製程Μ克眼上 述諸困難。 ⑵提供一改良的DMOS结構和製程·其中利用淺的 接面而不再需要形成深的Ρ*區，因而可以節省空間而又 不致於在崩潰電壓上妥協。 ⑶提供一改良而簡化的DMOS结構和製程·因而可 以Μ較低費用量產高密度DMO S元件。 (4) 提供一改良的DMOS结構和製程，其中在终端區 的相鄰的保護瓖間的間隔可Κ更精確地界定•而崩潰電壓 也因而可以更準確地控制。 (5) 提供一改良的DMOS结構和製程，其中由於在等 位環區形成的一通道站可Μ阻隔源極和汲極間偁發的溝通 •因而減低漏流。 (6) 提供一改良的DMOS结構和製程，其中由於以高 能和低能硼植入接觸區和等位環區的設計特點•因而可改 良韌度。 玆為使 貴審査委貝能瞭解本發明之目的、特徽及功 效•玆藉由下述具艚之實施例•並配合所附之圈示•對本 發明做一詳细說明： 圖示簡單說明： 第一圖是習知技術中具有高摻雜劑量P*擴散和場板的D (請先閱讀背面之注意事項再填寫本頁) 裝. 、?τ .」 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） 83. 3.10,000 經濟部中央標率局貝工消费合作社印製 A7 B7 _ 五、發明説明（） MOS電晶體的截面圖。 第二画是習知技術中具有一淺Ρ»擴散和場板的DMOS 電晶體的截面圖。 第三A圖至第三F圖為以習知技術製造DMO S的各步驟 之截面圖。 第四A至第四E圖為Μ本發明製程之實施例製造DMO S 的各步驟之截面圈。 第五Α圖至第五D圖為以本發明製程之另一實施例製造D MO S的各步味之截面圖。 第六圖為本發明的一DMOS電晶體之截面圖•其具有改 良之元件韌度。 發明說明： 第四A圖至第四D圖顯示製造本發明一實施例MO S FET元件1 00各步驟。如第四A圖所示，首先在一η* 基賭上面生長一電胆'係數為0.1至1.0 〇hm-CB之η -晶膜 層1 1 0。此基體之電阻係數為0.001至0.007 oh«-cn 。 晶膜層110之厚度和電阻係數依元件對通導霣阻和崩潰 «壓的需求而定。在一實胞例中·晶膜層1 1 0厚度約為 6至8wm，然後施以一閘極氧化處理來形成一厚度為1 00至1 000A的閘極氧化層120，之後在其上沉積 一多晶矽層1 25，再施以一 P0CL3摻雜程序，再接 著植入60至80 Kev，通量密度為5至8 X 1 0ls/ca2的 砷離子。其次加Μ—多晶矽光罩Μ不等向性蝕刻來界定多 晶矽閛極1 25 ·如第四Β圖所示，將光阻剝除•再加以 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） 83. 3.10,000 m *^1* 11— i - I in in —1 —II m 1^1 m· ^~~J. J 牙 、νφ (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標率局負工消费合作社印製 A7 B7_五、發明説明（) 一光罩128,在30至lOOKev ·通量密度為3X1013 至8X 1 014/c·8下做P體植入以形成PJBS1 30和 保護瑭1 33 *之後在升溫至1 000至1 2001溫度 下10分鐘至三小時進行P體擴散使P體區130和保護 環1 3 3深達1.0至20. w m。 第四C圃顯示施以一 η ♦阻隔光軍135 *再以60至 100 Kev，通量密度為8Χ 1 015至1 X 1 016/cm2之離 子束植入形成η♦區。當阻隔光單135被剌除 後· Μ沉積將η+源極區1 4 0驅至理想的接面深度約0.2 至1,0 wm。第四D_中顯示沉積一 BPSG或PSGK 形成一層145·厚度約為5000至15000A •之 後在900至950 *0溫度下30分鐘至一小時，MBP SG流或PSG加密過程處理•之後施Μ接觸光罩148 來蝕刻Μ界定接觸點。一 Ρ4離子植入是在900至95 0 υ在氧化或惰性氣體的環境中Κ活性程序而形成Ρ *區 。嫌後用一金屬光罩施以金靥沉積和金靥蝕刻來界定源極 接觴點170·閘極接觸點180和在終皤區的_道站和 等位環1 90。第四Ε圈顯示完成MOSFET動力元件 100的最後各步驟；先在保護環1 33上沉積金雇接黏 1 9 5Κ使保護環不受外來電場影響同時也和源極區1 4 0相連。對熟悉此技«人士而言•逭通道站等位環1 9 0 •其具有等位環之下形成的區顯然是和一般傳统的等 位環不同的。通道站1 9 0有另一優點即它在源極和汲極 之間形成阻隔•因之可Κ防止元件漏流。閘極接觸點1 8 (請先閱讀背面之注意事項再填寫本頁) 裝· 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） 83. 3.10,000 經濟部中央標率局貝工消费合作社印袋 A7 B7 五、發明説明（） 0和保護環1 33間的空間距離「Xj Μ及保護環1 33 和通道站等位環1 90間的空間距離「Υ」的範園為3.〇 至16/zm ·依處理技術而定。當Μ乾性蝕刻Μ取代目前所 用的濕性蝕刻時•即可得到較小的「X」和「Yj的距雔 〇 第五A圖至第五D圖為製造本發明之另一實施例dm OS元件200的各步驟，包含有一改良的場板組態。在 此，除了光罩的覆蓋和製程中用的材料不同外*其餘的和 第四A圈至第四D画中顯示各步«完全相同。如第五A围 所示•首先在一 η ♦基體上面生長一電阻係數為0.1至1.0 ohB-c«i之η -晶膜層2 10。此基體之電阻係數為0.001 至0.007 oh m-cm。晶膜層2 1 0之厚度和電阻係數依數位 元件對通導電阻和崩潰電壓的需求而定。在一實施例中》 晶膜層2 0厚度約為6至8 ttm。然後施Μ—閛極氧化處 理來形成一厚度為100至1 00 0&的閘極氧化層22 0，之後在其上沉積一多晶矽層225，再施M-P0C L3接鐮程序*再接著植入60至80 Kev，通量密度為5至 8X 1 〇is/c·«的砷雕子。其次加以一多晶矽光軍以不 等向蝕刻來界定多晶矽閘極225，然後將光罩剝除，再 加M —光罩228 ·在30至100 Kev ·通量密度為3x1 〇13至3x 1 下做p體植入以形成p腰區23 〇。之後在升溫至1 000至200010溫度下1 〇分鐘 至三小時進行P體擴散使P體區2 2 0之深度達1.0至2.0 wm。注意和第四B圖不同的是，在第五B圖中光電阻2 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 83. 3.10,000 ^^1 n·— ml 1^1 <l^v I n If HI «^1 (请先聞讀背面之注意事項存填寫本頁) 订Fifth, the description of the invention () The process is still limited by the problems of production capacity and cost. Because of this * this technology »still needs a structure and process that can solve this limitation. Secondly, the main features of the present invention are: (1) Providing an improved DMOS structure, topology, and manufacturing process. The above-mentioned difficulties. ⑵Provide an improved DMOS structure and process. Among them, shallow junctions are no longer needed to form deep P * regions, so space can be saved without compromising on breakdown voltage. (3) Provide an improved and simplified DMOS structure and process. Therefore, high-density DMOS devices can be mass-produced at a lower cost. (4) Provide an improved DMOS structure and process, in which the interval between the adjacent protection tanks in the terminal area can be defined more accurately and the breakdown voltage can thus be controlled more accurately. (5) Provide an improved DMOS structure and process, in which a channel station formed in the equipotential ring area can block the communication between the source and the drain • Therefore, the leakage current is reduced. (6) Provide an improved DMOS structure and process, in which the design characteristics of the contact area and the equipotential ring area are implanted with high-energy and low-energy boron • the toughness can be improved. In order to enable your review committee to understand the purpose, features and effects of the present invention • The following examples are included • With the enclosed circle • To make a detailed description of the present invention: : The first picture is the D of the conventional technology with high doping dose P * diffusion and field plate (please read the precautions on the back and then fill out this page). Installed, .τ? ”This paper size is applicable to Chinese national standards ( CNS) Α4 specification (210 × 297 mm) 83. 3.10,000 A7 B7 _ printed by the Beigong Consumer Cooperative of the Central Standardization Bureau of the Ministry of Economic Affairs V. Invention description () A cross-sectional view of a MOS transistor. The second drawing is a cross-sectional view of a DMOS transistor with a shallow P »diffusion and field plate in the conventional technology. Figures A to F are cross-sectional views of the steps of manufacturing DMO S using conventional techniques. The fourth A to the fourth E are cross-sectional circles of each step of manufacturing the MOS S according to the embodiment of the manufacturing process of the present invention. Figures 5A to 5D are cross-sectional views of various steps of manufacturing MOS S according to another embodiment of the process of the present invention. The sixth figure is a cross-sectional view of a DMOS transistor of the present invention, which has improved device toughness. Description of the Invention: The fourth to fourth figures A to D show the steps of manufacturing the MOSFET device 100 according to an embodiment of the present invention. As shown in the fourth graph A, first, an electric bladder having a coefficient of 0.1 to 1.0 ohm-CB is grown on an η * substrate. The resistivity of this substrate is 0.001 to 0.007 oh «-cn. The thickness and resistivity of the crystalline film layer 110 depend on the requirements of the device for conduction resistance and breakdown voltage. In a real cell example, the thickness of the crystal film layer 1 10 is about 6 to 8 wm, and then a gate oxide treatment is performed to form a gate oxide layer 120 with a thickness of 100 to 1 000 A, and then deposited on it A polysilicon layer 125 is then subjected to a P0CL3 doping process, followed by implantation of 60 to 80 Kev, with a flux density of 5 to 8 X 10 ls / ca2 arsenic ions. Secondly, add M-polysilicon mask M anisotropic etching to define the polysilicon electrode 1 25. As shown in the fourth B picture, strip the photoresist • Then add this paper scale to apply China National Standard (CNS) Α4 specification ( 210Χ297 mm) 83. 3.10,000 m * ^ 1 * 11— i-I in in —1 —II m 1 ^ 1 m · ^ ~~ J. J tooth, νφ (Please read the notes on the back before filling in This page) Printed A7 B7_5. Description of invention () A mask 128, with a flux density of 3X1013 to 8X 1 014 / c Body implantation to form PJBS1 30 and protection ring 1 33 * Afterwards, P body diffusion is performed at a temperature of 1 000 to 1 2001 for 10 minutes to 3 hours to make the P body region 130 and the protection ring 1 3 3 deep to 1.0 to 20. wm. The fourth C garden shows that η is blocked by η ♦ Blocking the light army 135 * Then the ion beam is implanted to form the η ♦ region with 60 to 100 Kev and a flux density of 8 Χ 1 015 to 1 X 1 016 / cm 2. When the blocking light sheet 135 is removed, the M deposition drives the η + source region 140 to the ideal junction depth of about 0.2 to 1,0 wm. The fourth D_ shows the deposition of a BPSG or PSGK to form a layer of 145. Thickness is about 5000 to 15000A • Afterwards at 900 to 950 * 0 temperature for 30 minutes to one hour, MBP SG stream or PSG encryption process • After applying M contact The photomask 148 is used to etch M to define contact points. A P4 ion implantation is to form a P * region in an active or oxidized or inert gas environment at 900 to 95 0 υ. Afterwards, a metal mask was used to apply gold deposit deposition and gold etching to define the source junction 170, the gate contact 180 and the Daozhan station and equipotential ring 1 90 in the final zone. The fourth circle E shows the final steps to complete the MOSFET power element 100; first deposit gold bonding adhesive 1 9 5K on the protection ring 1 33 to make the protection ring not affected by external electric field and also connected to the source region 140. For those who are familiar with this technique, the equipotential ring of the channel station is 1 9 0. • The area formed under the equipotential ring is obviously different from the traditional equipotential ring. The channel station 190 has another advantage in that it forms a barrier between the source and the drain. This prevents the component from leaking. Gate contact point 1 8 (please read the precautions on the back before filling in this page) Pack · This paper size is applicable to China National Standard (CNS) Α4 specification (210X297mm) 83. 3.10,000 Ministry of Economic Affairs Central Standard Rating Bureau Industrial and consumer cooperatives printed bags A7 B7 V. Description of invention () 0 The spatial distance between the protective ring 1 33 and the spatial distance between the protective ring 1 33 and the protective ring 1 33 and the isostatic ring 1 90 of the channel station "Y" 3.〇 to 16 / zm · Depends on the processing technology. When M dry etching replaces the currently used wet etching, the smaller “X” and “Yj distances can be obtained. The fifth A to the fifth D are another embodiment of the present invention for manufacturing dm OS Each step of the element 200 includes an improved field plate configuration. Here, in addition to the cover of the reticle and the materials used in the manufacturing process are different *, the remaining steps are shown in the fourth to fourth D circles The same. As shown in the fifth A circumference. First, an η-crystal film layer 2 with a resistivity of 0.1 to 1.0 oh B-c «i is grown on an η substrate. The resistivity of this substrate is 0.001 to 0.007 oh m -cm. The thickness and resistivity of the crystalline film layer 2 1 0 depend on the requirements of the digital element for on-resistance and breakdown voltage. In one embodiment, the thickness of the crystalline film layer 20 is about 6 to 8 ttm. Then apply Μ- 閛 极 极 體 機 機 機 機體 鈥 擇 鈥 檚 formed a gate oxide layer with a thickness of 100 to 100 0 & 22 0, and then deposited a polysilicon layer 225 on it, and then applied the M-P0C L3 connection process * and then implanted 60 To 80 Kev, arsenic carving with a flux density of 5 to 8X 1 〇is / c · «. Secondly, a polysilicon optical army is defined by anisotropic etching The polysilicon gate 225, and then the photomask is stripped off, and the M-mask 228 is added. The p-body implantation is performed at 30 to 100 Kev and the flux density is 3x10 13 to 3x 1 to form the p waist region 23. Afterwards, P-body diffusion is performed at a temperature of 1 000 to 200010 for 10 minutes to 3 hours to make the depth of the P body region 2 2 0 reach 1.0 to 2.0 wm. Note that unlike the fourth B picture, the fifth B picture Medium light resistance 2 This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 83. 3.10,000 ^^ 1 n · — ml 1 ^ 1 < l ^ v I n If HI «^ 1 (please Read the precautions on the back first and fill in this page)
SQ030Q 經濟部中央標準局真工消費合作社印裝 A7 B7五、發明説明（） 2 8阻隔了终端區因之沒有形成保護環。 第五C圔顧示施K 一 η ♦阻隔光罩235 ·再Μ 60至 100 Kev，通量密度為5Χ 1 01!1至1 X 1 Ole/c·2之離 子束植入·以形成η ♦區。當η·阻隔光罩被剝除後，Μ 沉積將η*源極區24 0驅至理想的接面深度約0.2至1.0 win。第五D圖中顯示沉積一 BP SG或P SGK形成一 層約厚5000至15000A ，之後在900至950 υ溫度下30分鐘至一小時MB P SG流或P SG加密遇 程應理，之後施Μ接觸光罩來鈾刻K界定接觸點。一 P· 離子植入是在9 0 0至9 5 Ot：在氧化或惰性氣體的瓖境 中以活性程序而形成P·區。完成此MOSFET動力元 件的最後步驟是用一金觸光罩Μ金靨沉積和金屬蝕刻來界 定源極接觸點270 ·閘極接觸點280，埸板290和 在終端區的等位環295。 和一般習用製程不同的是在生長起氧化層瑄一步驟上 現已免除，而且也不再需用一活性光罩。埸板290是在 PSG這一步驟形成的（請參照第五D画）•從源極到場 板的連接是以金饜從上跨越，和第一圈中所示一般傅統D M0S所用的多晶矽層連接不同。因此，和習知技術中使 用六個光罩的DM0S製程相較•本發明堪露之製程只需 用五個光罩。在習知技術中所面臨的問題*包括生長厚的 氧化層，形成深且高摻雜劑量的Ρ +區*以及形成埸板和 等位環區的通道站所需的額外的光罩等問題，在本發明新 穎且具改良的结構和製程都得到解決。 I-r丨.-.----ί -裝------訂-----ί叙 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標隼（CNS ) Α4規格（210X297公釐） 83. 3.10,000 經濟部中央標準局員工消費合作社印製 A7 B7 — . __ 五、發明説明（） 第六圈顯示一按本發明為改良韌度之製程所製成之D MOS轚晶體300之截面画。韌度的改良是由於施Μ高 能和低能的Ρ ♦植入而分別形成第六麵中的HP ♦匾36 0和LP*區3 6 5。此在接觸區Μ高能和低能植入產生 了很理想的结果*即降低了基極電阻Re *因之可以避免 因當基極電流I a變大而達到I *R6g〇.6V而偁而開故D MO S元件中的寄生雙極n + pn電晶«的不良效應。因此， 由於元件的R*降低使IeRe降低而降低了偶而開啟雙極 寄生n + pn電晶體的機率•因而改良了韌度。另一方面•在 等位瑁區395内形成一HP*區360可能對通道站效 懕有不良影響•此通道站效應是為防止一通道規象*此現 象可導致從源極到汲極的漏流。這問題可Μ使用一氧化間 隔物3 9 8把等位環接觸點3 9 5絕緣而解決。逭些設計 特點改良了元件300的韌度•由於一通道站在等位環區 内形成如一 η*區•而可以同時保有防止通道現象的功用 。因為高能和低能明植入是在接觸點的開口植入，因此· 如第六圖所示的DM0 S元件3 0 0可以用此五光軍程序 來製造而不需如習知技術中需要其他的光罩。 雖然本發明Μ上逑之實施例敘述》但Κ上所掲«及說 明之具艚描述並不作為解釋本發明榷利範圍之侷限。一旦 Μ讀本發明掲霣之内容*對具一般技藝人士 •各樣之變化 、修改即已明白。因之•下列之專利要求項•只要變化及 修改不出本發明的精意及内容者•都應被纳人•包含在本 發明播利範圍之内。 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） I —~.裝 訂 - Γ.^ (請先閲讀背面之注意事項再填寫本頁)SQ030Q Printed by the Genuine Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A7 B7 V. Description of invention () 2 8 The terminal area is blocked and therefore no protection ring is formed. Fifth C 圔 顾 施 施 K η ♦ Blocking photomask 235 · Then 60 to 100 Kev, flux density of 5 Χ 1 01! 1 to 1 X 1 Ole / c · 2 ion beam implantation · to form η ♦ District. After the η · blocking photomask is stripped, the M deposition drives the η * source region 240 to the ideal junction depth of about 0.2 to 1.0 win. Figure 5D shows the deposition of a BP SG or P SGK to form a layer with a thickness of about 5000 to 15000A, and then the MB P SG flow or P SG encryption process should be handled at 900 to 950 υ for 30 minutes to one hour, and then apply M to light The cover comes with uranium engraved K to define the contact point. One P · ion implantation is in the range of 900 to 9 5 Ot: the P · region is formed in an active process in the environment of oxidizing or inert gas. The final step to complete this MOSFET power element is to define the source contact 270, the gate contact 280, the gate plate 290, and the equipotential ring 295 in the termination area using a gold photomask M gold deposit and metal etching. Unlike the conventional process, the step of growing an oxide layer is now eliminated, and an active photomask is no longer required. The field board 290 is formed in the step of PSG (please refer to the fifth D drawing) Polysilicon layer connections are different. Therefore, compared with the DMOS process using six masks in the conventional technology, the process of the present invention requires only five masks. The problems faced in the conventional technology * include the growth of thick oxide layers, the formation of deep and high doping dose P + regions *, and the additional masks needed to form the channel station of the field plate and the equipotential ring region. In this invention, the novel and improved structure and manufacturing process are solved. Ir 丨 .-.---- ί -installation ------ order ----- ί Syria (please read the precautions on the back before filling in this page) This paper scale is applicable to China National Standard Falcon (CNS) Α4 specification (210X297mm) 83. 3.10,000 Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A7 B7 —. __ 5. Description of the invention () The sixth circle shows that it is made according to the present invention for the process of improving toughness The cross-section drawing of the D MOS crystal 300. The improvement in toughness is due to the implantation of high-energy and low-energy P implanted to form the HP plaque 36 0 and LP * region 3 65 in the sixth side, respectively. The implantation of high-energy and low-energy implants in the contact area M has produced very good results. That is, the base resistance Re is reduced. Therefore, it can be avoided that the base current I a becomes larger and reaches I * R6g.0.6V. Therefore, the adverse effect of the parasitic bipolar n + pn transistor in the DMOS element. Therefore, the reduction in the R * of the device lowers the IeRe and reduces the probability of occasionally turning on the bipolar parasitic n + pn transistor • thus improving the toughness. On the other hand • The formation of an HP * zone 360 in the isocratic zone 395 may have an adverse effect on the effectiveness of the channel station • This channel station effect is to prevent a channel specification Leakage. This problem can be solved by using an isolating spacer 3 9 8 to insulate the isotopic ring contact 3 9 5. These design features improve the toughness of the element 300. Since a channel stands in the equipotential ring area to form an η * area, it can simultaneously maintain the function of preventing the channel phenomenon. Because the high-energy and low-energy bright implants are implanted in the openings of the contact points, the DM0 S component 3 0 0 shown in the sixth figure can be manufactured using this five-light military program without the need for other technologies as in the conventional technology. Mask. Although the description of the embodiments of the present invention is not described, the descriptions and descriptions of the above descriptions are not intended to limit the scope of the present invention. Once Μ read the contents of the present invention * for those of ordinary skill • Various changes and modifications will be clear. Therefore • the following patent requirements • As long as the essence and content of the present invention cannot be changed or modified • all should be accepted • included in the profitable scope of the present invention. The paper size is applicable to China National Standard (CNS) Α4 specification (210X297mm) I — ~. Binding-Γ. ^ (Please read the notes on the back before filling this page)