TW418536B - High density power transistor with punch through prevention, reduced JEFT resistance and high switching speed manufactured by simplified process - Google Patents

Abstract

This invention discloses a manufacturing method of power transistor on the substrate to prevent punch through. This method includes the following procedures. (a) A starting oxide layer is grown on the epitaxy layer that has the first conduction type after this epitaxy layer is formed on the substrate. (b) An active mask is applied to etch the starting oxide layer and to define an active region such that plural ion separations are formed on the epitaxy layer at the same time. A second conduction type ions are then implanted into the plural regions with punch through prevention. (c) The stacked polysilicon layer is deposited and a polysilicon mask is applied to etch this polysilicon layer so as to define plural polysilicon gates. Each one of the gates is stacked with the ion separation below it, and is on top of the region with punch through prevention. At the same time, there is an ion separation between every two neighboring gate regions. (d) The polysilicon mask is removed to perform a second conduction type body implantation, and then a substance diffusion is performed to form plural subjective regions. (e) The ion separation isolated by the gate is used as source separation to implant the first conduction type ion into plural source regions in the subjective region. (f) An insulation layer is formed and processed by a high temperature treatment to intense the insulation layer so as to activate the diffusion of source region. The region with punch through prevention in the source region is kept isolated from JFET, such that the punch through of transistor can be prevented without the increase of JFET resistance.

Description

I 4 ^ 8536-ΑΊ ---- 87 V. Description of the Invention () [Background of the Invention, (Field of Invention)] The present invention relates to the structure and manufacturing process of semiconductive crystals. In particular, the present invention relates to a novel and improved structure and process of a high-density shallow junction semiconducting crystal power element, which has an improved function of preventing breakdown, can maintain a low JFET resistance, and has a higher switching rate, and Only five photomasks are required. Β [f knowing technology] As the density of semiconductor power elements increases, some technical difficulties arise, especially when the distance between cells formed from polycrystalline silicon is reduced, that is, polycrystalline silicon. When the width of the pole is reduced, high JFET resistance is often generated between cells. In order to overcome this high resistance, a shallow junction is usually formed, but the shallow junction is easy to cause the penetration of β. Although the shallow junction element has the advantage of lower JFET resistance, when the penetration occurs, it will Cause damage. There are various methods to prevent punch-through, but they will lead to an increase in r JFET resistance, especially when used in the inert state where the size of the cell is smaller. Known technology patents try to IT to resolve a certain technical problem, but often make Another problem worsened. In order to increase the unit density, reducing the size of the unit is often hindered by technical considerations. Unless these technical issues are first resolved, printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economy-please read the precautions on the back before filling out this page). When making high-density semiconductor power components, there will be problems such as product reliability and component failure. In US 5,479,037 patent "Low Threshold Voltage Crystal Film DMOS Technology", Xie et al. Disclosed the structure of a threshold DMOS power transistor, in which a lightly doped silicon film layer is formed with a lightly doped silicon film. Miscellaneous channel area (see Figure 1). Due to the uneven doping concentration of the crystal film, the shallow crystal film layer is slightly lightened. This paper size is applicable to the Chinese national standard {CNS M4 specification (2 丨 0X297 mm)! 418536 I — Central Samples Bureau of the Ministry of Economic Affairs Printed A7 B7 V. Description of the invention () Doping can minimize the change and change of threshold voltage and crotch puncture susceptibility. Β is in-the crystal film layer with higher doping is placed in a shallow and relatively Below the low-doped crystal film layer, it is located below the channel region to reduce the resistance from the source to the source. Since this highly doped crystal film region is located below the channel region, and is not in the region where the body region is most easily felt by the structure, this high-doped region does not cause a threshold voltage. Although lightly doping the shallow crystal film layer in the DMOS device has the advantages of causing a low threshold voltage and preventing punch-through, the invention of Xie et al. Created another difficulty when the density of Mos cells increased even more. When the DMOS cell is denser, the JFET region between the cells made with a lower doping concentration becomes smaller, and the lightly doped crystal film layer causes the JFET resistance to increase. Therefore, when the cell size is further reduced and the cell density is increased, the applicability of the DMOS structure with a lightly doped crystal film layer is followed. In U.S. Patent No. 5,404,0, "Structure and Process of a Ship SFET Power Element Containing a Termination Structure", Xie et al. Disclosed a semiconductor MOSFET power element with a main active region and a terminal & A first-insulating layer of approximately equal thickness is provided above the active region and the terminal region of the power device, and the main polycrystalline silicon portion is above the active region and the terminal region. An anode electrode is connected to the main polycrystalline silicon portion; a source electrode is connected to the active region and the terminal region is connected to the first polycrystalline silicon portion; or a metal portion may be connected to the second polycrystalline silicon portion. The production of this MOSFET power element requires five photomasks. It provides a unique termination structure, in which the element is divided into a main active area and a peripheral termination area. At the same time, a thickness of about 100 is overlapped on the two areas. To ιοοοΑ's first insulating layer. Due to the structure of this thin oxide layer, ----------- 1 -------, 玎 ------ ^ (Please read the precautions on the back before filling this page: > This paper The dimensions are applicable to Chinese national standards (CNS) A4 specifications (210X297 mm) A7 B7 418536 5. Description of the invention () In particular, the part below the field plate makes the MOSFET element sample when the voltage applied to the field plate exceeds a certain level Inch can suffer from Walk-Out problems. Furthermore, this thin hafnium oxide located between the polysilicon surrounding the second stage may be etched during the fabrication process. Therefore, when the etching process is not precisely controlled, components will be generated. The problem of reliability. Therefore, in the technology of producing MOSFETs with high cell density, especially in design and manufacturing, there is still a need for new structures and methods that can solve these limitations. [Inventive Features] Features of the Invention It is: (ii) providing a new and improved element structure and process to overcome the technical difficulties mentioned above * (2) providing a new and improved element structure, wherein the breakdown prevention area is selective using a specially configured ion barrier Ground formation makes JFET The internal doping concentration will not be adversely affected when the punch-through prevention area is applied in the case of low JFET resistance. (3) A new and improved element structure using five photomasks is provided, and the punch-through prevention area is provided. Ion barriers are selectively formed using a special configuration. The initial doped oxide mask with a special configuration does not reduce the doping concentration in the JFET region, which improves performance by reducing the number of required masks »( 4) Provide a new and improved element structure using five photomasks, where the breakdown prevention area is selectively formed using a specially configured ion barrier. The jFET region is initially oxidized using a special configuration Miscellaneous I! Η I----n I i. Nnnn, ^ 1 T, -B (please read the note on the back before filling out this page) Member of the Central Bureau of Standards of the Ministry of Finance and Economics Paper thick people and General Ningguo National Standard (CNS) A4 specifications (210X297)

418536 The concentration will not decrease, and the idler-drain capacitance Q in the monopole formed in each ship SFET unit is reduced, which increases the switching rate of the element β (5) provides a new and improved using five photomasks The element structure in which the breakdown prevention area is selectively formed using a specially configured ion barrier. The use of a specially configured initial oxidation mask does not reduce the doping concentration of the JFET region, so multiple simulation cells can be implanted as a defensive obstacle, and free ions are absorbed when a polycrystalline silicon finger collapses near the element's. Improved toughness "For those skilled in the art, when referring to the following drawings, reading the description of the invention, and studying the examples, they will undoubtedly understand the content of the present invention. & Brief description of the drawings: FIG. 1 is a cross-sectional view of a DMOS device having low threshold throttling pressure and improved breakdown prevention performance in a conventional technology. 2A to 2D are cross-sectional views of an improved toSFET device manufacturing process according to the present invention. FIG. 3A and FIG. 3B are cross-sectional views of a manufacturing process of another embodiment of the present invention shown in the 2D expansion and the sinking drawings. Figures 4A to 4H show happy drawings of the improved MOSFET device manufacturing process of the present invention. 5A to 5C are cross-sectional views of processes of another embodiment of the present invention shown in FIGS. 4D to 4F. Brief description of drawing number: 100 MOSFET power element 105 N + matrix ---- 7_ This paper scales Long Jiaguan Jiaquan (〇 ^) 八 4 ^ | (210 \ 297 公 酱) —— ~-(Please read first Note on the back, please fill out this page again.) Pack. Printed by the Central Consumers ’Bureau of the Ministry of Economic Affairs, printed by the cooperative 4 185 3 α Α7 • Β7 V. Description of the invention () 110 fT crystal film is printed by the Consumer ’s Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs Layer 115 Initially oxidized layer 115, ion-blocking layer 120, photoresist layer 123, ΓΓ breakdown prevention region 125 r region 125, Ν + source region 130 polycrystalline silicon gate 130 'polycrystalline silicon gate 130 "polycrystalline silicon layer 130,' polycrystalline silicon wafer 140 P Body area 145 r area 150 layer 152 source contact opening 154 gate contact opening · 156 field plate contact opening 157 allotment ring green opening 157 allotment ring source opening 158 allotment ring contact opening 160 P + area 162 source contact 164 gate contact 166 field plate 168 equipotential ring 180 simulation unit 185 active core unit 190 active core unit 200 M0SFET field rate element 205 N + substrate 210 crystal film layer 212 oxide layer 214 silicon nitride layer 216 light Resistive layer 220 N + doped region 225 LOCOS oxide ion barrier 230 Breakthrough prevention zone 230 'Breakthrough prevention If zone 232 Polycrystalline silicon layer 235 Polycrystalline silicon gate 235, Polycrystalline gate 235 "Polycrystalline silicon gate electrode 235, -1 Polycrystalline sand layer 235,' -2 Polycrystalline silicon layer 240 P body zone 245 N + zone 250 layer 252 source contact opening --------- installation-(Please read the precautions on the back before filling this page) This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm) 418536 Invention description (254 2572Bα 264 268 285 Gate contact opening equipotential ring absolute circle F area. Gate contact equipotential ring active core unit 256 Field plate contact opening 258 equipotential ring Insulation opening 262 Source contact 266 Field plate 280 Simulation unit Lithium Ministry Central Standards Bureau Shellfish Consumer Cooperation Du printed [Invention] Figures 2A to 2E show the procedures for making M_τ power element 100 in the present invention. This element has a long life and improved resistance to wear without increasing the resistance. ^ As shown in Figure 2A, firstly, it is grown on a mineral-based II105-N crystal film with a resistivity of (U to L 〇hm_CE). Layer 110. The resistivity of the substrate is 0.001 to 0. 〇7 〇hffl cja; The thickness and resistivity of the crystal film layer ΐΐο depend on the element path resistance and breakdown voltage. 6 In one embodiment, the crystal film layer 11Q is about 6 to 8 # m thick, and then grown An initial oxide layer having a thickness of about 1 {) to 4000 λ. A photoresist layer 120 is formed on the oxide layer U5 by applying a specially configured active photomask. Figure 2B shows that the photoresist layer 120 formed according to the special configuration is used to etch the initial oxide layer 115, and the oxide layer 115 is etched away from the active area to define the active area and the photoresist layer 120 formed in the active area. A plurality of implanted ion barriers 115 ', and thereafter, a boron ion beam with an energy of 30 to 100 kev' and a flux density of 1 X i〇i2 to 1 X i〇13 / cni2 was implanted to implant N crystals. The ff punch-through prevention area 123 is formed in the film layer no. Please refer to Figure 20, after the photoresist layer 12.0 is removed, a polycrystalline silicon layer 130 is deposited on the implanted ion barrier 115 *, and then P0Cl3 is added (please read the note on the back before filling this page) Packing--β This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm) 418536 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs

Doping treatment, followed by implantation with arsenic ions with an energy of 60 to 80 kev and a flux density of 5 to 8 X 1 (Ρ / άη2), and then using a specially configured polycrystalline silicon photomask for anisotropy Etch to define three kinds of polycrystalline silicon poles. In the core 1 rod region 'because the polycrystalline silicon gate 13 is formed on the implanted ion barrier 115'; it has a step shape; The side of the crystal finger-with the polycrystalline lye 13 ° here is etched straight, the bottom _ instead of the bottom shape, and the simulation unit is formed below the side electrode 130 'as follows; polycrystalline silicon in the terminal area The gate electrode 13 is shaped into a isotope according to a special circular ring. This method is used by people in this field. The photoresist is applied after the gate electrode is stripped during etching. The corpus callosum with a flux density of 3 × 1 (^ to 3 × 1 () 14 / ⑽2 was implanted to form a p-body region 140, and then passed through a heated surface to 1200 for 10 minutes to 3 hours. The P-body diffusion procedure was performed to increase the depth of the P-body region to 1.0 to 2.0 " m »Due to the implanted ion blocker 115, more remained in the active region The silicon gate electrode 130 H n + is not necessary. After that, ions with an energy flux density of 60 to iG0 kev 'and an ion flux density of 5 X 1015 to 1 X 10l6 / cm2 are preferably arsenic ions. N + region ί 25. When the soil in the N + source region is formed, there are also a number of breakdowns to prevent "the region in the nucleus and the cell forming the β breakdown prevention region N145 has a lower doping degree" because The use of boron ion implantation to prevent the breakdown of the existing, N-type __ degree view. Please note that f, the difference from the known technology in the invention has a lower doping intrusion prevention zone 145 (; N-zone) is not affected by the electric power of R. It can achieve this effect because it is located in the τ zone under the gate 13G-with a discerning N paper size toward the towel IIII. Nn III ^ (Please read the notes on the back before filling out this page} X 297 feet) Stamps of the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 4 185 36 V. Description of Invention () Type Dopant Concentration * This i The curvature of the implanted ion barrier 115 prevents the breakdown and prevents the ion from penetrating into the JFET region and reduces the concentration there. Therefore, as As shown in Figure 2C, the implanted ion barrier 115 'can solve the concern of the JFET resistance spectrum caused by the decrease in the degree of * in the JFn region caused by the breakdown prevention. The source implantation process is performed to form the source region 125' At this time, the implanted ion barrier 115 'can also be used as the source scale ancestor. When the phytosclerosis barrier is removed, the N + source region 丨 25' is driven to 0.2 to 0.2 by diffusion treatment. Junction depth of ## id. The second D image shows that a BPSG or PSG insulation layer is deposited to form a layer 150 with a thickness of about 5000 to 15000A, and then encrypted at a temperature of 900 to 950 ° C. Process for 30 minutes to 1 hour ** and then apply a contact mask for etching to define the contacts, such as the source opening 152, the 閛 contact opening 154, the field plate contact opening 156, and the equal position absolute green opening 157 Connected to the allele ring opening 158, and then 30 to 60 kev > boron ion implantation with a flux density i (p to 2 X 1015 / CDi2 and then 900 to 950 ° C, oxidized or inert The activation process under the gas environment forms a P + region of 160. Please refer to FIG. 2E. The last MOSFET power element 100 is deposited by metal and a metal mask is used. Etching to define a source contact 162, Peng pole contacts 164, 166 and field plate 168 ^ equipotential ring engraved in metal contact process, metal is deposited on the insulation opening equipotential ring is also removed. A dry polycrystalline silicon etch is performed between the field plate 166 and the equipotential ring 168 in the terminal region. Only the polycrystalline silicon layer is etched without affecting the metal layer. An opening 170 is etched to connect the polycrystalline silicon layer between the field plate 166 and the equipotential ring 168. 130 ”apart. For the polycrystalline silicon electrode 130 surrounding the polycrystalline silicon fingers, that is, polycrystalline _____U____ This paper size applies to the Chinese National Standard (CNS) Λ4 specification (2ί〇 × 297 mm) (Please read the precautions on the back before filling (This page) installed _ < 1Τ

4 185 36 V. Description of the invention (Si gate 164 units near the terminal area need special intentions. Due to the special configuration of 115 and the polycrystalline sands, the oxide layer is the ion barrier, 130 Lin. @ 为 丝 读 加 看 电 鲜 ^ Therefore, the single reduction simulation unit 18G.e When the terminal unit is 〇 can pick up the free real mold unit particles running towards the active core unit in the crystal film layer 110 and the substrate 105_ Placed near the terminal 1 and broken polycrystalline-the manufacturing steps mentioned above can also be used for MOSFETs with initial oxides of 15 to 10000A. Figures 2 and 2B describe the cut-off in addition to the reduction Except for the bridging layer, the rest are almost the same as those in Figure 3A. Please refer to Figure 3A. In the kitchen, the configuration of a ^ terminal area is slightly different from the polycrystalline silicon aurora. The active core unit 185 and the simulation unit 1 are different. The polycrystalline silicon gate electrode is the same as that used for MOSFET elements with an initial oxide layer of medium thickness. The type of polycrystalline silicon gate at the termination is two separate paragraphs UO'nq and 13G '' -2. The remaining steps shown in Figures 3B and 3C and Figures 2 and 2E The descriptions are exactly the same, except that the configuration of the contact light in the terminal area is slightly different. The field plate 1 and the equipotential ring 168 in the terminal area are insulated from each other, without the need for another polycrystalline silicon etching to polycrystalline silicon layer. 130 "'-1 and 13〇' ''-2 are separated. Figure 2F reveals a processed substrate 110 containing a first conductive type dopant» This transistor contains a primary oxide layer 115, which covers and 12 Read the first reading and read the back-5 fill in, I split the page printed by the Central Consumers Bureau of the Ministry of Economic Affairs Consumer Cooperatives printed this paper standard applicable to Chinese National Standard (CNS) A4 specifications (210X297 mm) Central Ministry of Economics Ministry of Economics-4 Consumer Cooperatives Printed 418536 A7 • _____B7__ 5. Description of the invention () The active region on the substrate 11 is opposite. The Λ transistor also contains a primary oxidation ion barrier 115 ′ in the active region on the reference body 110, and it is also included in the A punch-through prevention area 125 on the substrate 110 surrounds the outer green perimeter below the ion barrier 115 ′. At the beginning, the ion barrier] 15 contains a first conductive dopant, the concentration of which is higher than that of the substrate 110 after consensus. low. The 2G figure shows that the transistor further includes a polycrystalline silicon gate 130 with an initial oxide ion barrier 115 'under it, and a breakdown prevention region 145 further below. Therefore, there is a JFET at the ion barrier 115 and away from the breakdown prevention region. Region, so that the resistance of the JFET does not increase. In one embodiment, the power transistor further includes a primary oxide layer 115, which is located next to the dynode 130 that has the primary oxidation source resistance, so that source implantation can be performed without the need for An additional source mask is used. In one embodiment, the power transistor further includes a body region 14 with a second conductive dopant in it. The body region 14 is surrounded by the substrate 1 and 0 outside the punch-through prevention region 145. The outer green perimeter of the polycrystalline silicon electrode 130 has a source region 125 'located in the substrate 11 and is surrounded by a body region 14o containing a first conductive dopant. Figures 4A to 4E show that the present invention has In the shallow body area, there is another modified jjOSFET power element 200 that does not increase the JFET mold resistance. As shown in FIG. 4A, first, a resistivity of 0.1 to 1.0 is grown on an N + substrate 205. cffl N crystal film layer. The resistivity of this crystal film layer is from 0.001 to 0.007 ohm-cin; the thickness and resistivity of the crystal film layer are determined by the resistance to the element path resistance and breakdown f; in one embodiment, the crystal Gu 210 thickness is about 6 to 8 # r, and then grows into a maggot-shaped oxide layer with a thickness of about 500A, and then a low-pressure chemical vapor deposition (Lp⑽ process deposition-Daihua layer 214 covers the oxide layer 212- Later in the body]) Nitriding _______13 This paper size applies to the Chinese country # (CNS) Λ4 specifications (一 2 丨 〇X 291 ^ 1 (Please read the precautions on the back before filling out this page) 'Packing_ Order 418536 A7 B7 Printed by the Central Bureau of the Ministry of Economic Affairs, Shelley Consumer Cooperative, V. Description of the invention () A photoresist layer 216 is formed on silicon with a specially configured active photomask, in order to produce a punch-through prevention area without increasing the JFET resistance A shallow junction MOSFET device. It was then etched by LPCVD nitriding and then implanted with arsenic or phosphorus with a density of 60 kev and a density of 1 (p to 2 X 107 cm2 to be placed below the top surface of the substrate. A plurality of N + doped regions 220 are formed at 0. 5 # m. In FIG. 4B, it is shown that the temperature is 800 to 100 ° C. with steam oxygen. A local silicon oxidation step is performed in the chemical process, that is, LOCOS 〇 formed a plurality of raised oxide ion barriers 225 between the first blocking openings, and the N + region 220 with a higher doping concentration is located underneath. Then, the LPCVD nitride layer 214 is formed. Removal, followed by oxidative etching to remove pad-like oxide, and simultaneously applying a SAC0X treatment to remove the remaining nitride around the perimeter of the LOCOS ion barrier. After that, it is 30 to 100 kev and the flux density is X 1012 to 1 X 1013 / cm2 of ytterbium ion beam is used for low-flux body ion implantation to form n-implanted punch-through prevention area 230 on the substrate that is not blocked by LOCOS oxide ion blocker 225. After SAC0X is etched, it grows to a thickness of about 100 to 100 gate oxide layer. Figure 4C shows that a polycrystalline silicon layer 232 is deposited and then subjected to a polycrystalline POCL doping process, and then a specially configured polycrystalline silicon mask is used to perform a range Anisotropic engraving to define three types of polycrystalline silicon gates. The polycrystalline silicon gate 235 formed in the core cell region has a perimeter with a lower step because it is formed above the LOCOS ion barrier. Nearby, the polysilicon gate 235 is etched with a straight green edge to form a simulation unit below the gate 235, as described below. In the terminal region, the polysilicon gate 235 is shaped using a special isocyclic shape. Form 14 on it (please read the note ^^ on the back before filling this page).

• 1T clothing and paper standards (CNS) M specifications (2⑴χ297 printed by the Central Bureau of Standards of the Ministry of Economic Affairs and printed by the Shellfish Consumer Cooperative I 418536 A7 .___ B7 5. Description of the invention () This is a well-known parity in the art The ring β is for easy understanding. The LOCOS oxide ion blocks 225 and the ions traced in the circle from 2C to 邡. The block 115 'has the same function. After the photoresist is removed in the gate etching, 30 is applied. To 100 kev, an ion beam with a flux density of 3 'X 1013 to 3 X 10-14 / Cin2 was implanted as P 馐 to form the P body region 2.40. The figure 4D shows the use of a temperature increase of 1 to 1200 ° C for 10 minutes to 3 hours for P-body diffusion to increase the depth of P-body region 240 to 1.0 to 2. 〇 " m. Since no longer need to implant LOCOS ions between polycrystalline silicon gates 235 in the active region Blocking, so there is no need to use the commonly used N + blocking photocells. Then, an ion beam of 60 to 100 kev and a flux density of 5 X 1015 to i X 1016 / 〇 / is used ( It is better to use arsenic) for implantation to form the N + region 245. At the same time, a plurality of punch-through preventions are also formed under the 閛 pole 235 in the core unit region. N 'region 230 ,. N-region 230, has a lower doped soil, because the use of boron free-hand implantation to prevent the punch-through process will reduce the existing N-type dopant concentration. Please note that, with The difference between the conventional techniques is that the present invention has a lower doping concentration prevention region 23G '(N region), which does not have an adverse effect on the saint resistance during fabrication. The reason why this result can be achieved is because The JFET region under the gate 235 has always maintained a sufficient N-type doping concentration. This is because the implantation · ion resistance 225 prevents penetration and prevents ion penetration. It enters the jFET region and reduces the concentration there. Therefore, as shown in FIG. 4C, the implantation of LOCOS ion barrier 225 can solve the concern of the increase in JFET resistance caused by the decrease in concentration in the ytterbium region caused by the breakdown prevention. The source implantation process is applied to form When the source region is 240, the implanted LOCOS ion barrier 225 can also be used as the source. ____15__ This paper size is applicable to the Chinese National Standard (CNS) A4 specification {2] 0X297.) One by one---- (Please read the back Note for this page, please fill in this page) Co-op printing equipment 4185 38 Α7 _ * Β7 V. invention is described in (), the sub-barrier. After the ion ions were abducted, the N + source electrode was driven to a depth of 0.6 m by a diffusion treatment of 0.2 m to a depth of 0.6 m. Figure 4D shows that a BPSG weaving PSG absolute green eyebrow is deposited to form a layer of 250 with a thickness of 50G0 to 15000A, and then it is encrypted for 30 minutes to 1 hour at a temperature of 90Q to fl50 C, and then applied. Each contact is defined by etching, such as source release opening 252, 閛 contact opening 1: 1 254, field plate contact opening 256, equipotential ring insulation opening 257, and equipotential ring opening. 258. Boron ions with a flux density of 1015 to 2 X iG15 / cm2 were implanted at 30 to 60 kev, and then treated with 9Q〇 军 邱 〇 oxidation or inert gas to form a P + region 260 « Please refer to FIG. 4E, in which the last MOSFET power element 200 is metal-deposited and etched using a metal mask to define a source contact 262, a gate contact 264, a field plate 2θ6, and an equipotential ring 268. During the metal etching process, metal deposition in the equipotential ring insulation opening is also removed. Figure 4F shows that a dry polysilicon etch is performed between the terminal area 昤 field plate 筹 6 and the chip ring 268 to etch an opening p to separate the polycrystalline silicon layer 235 "into the polycrystalline silicon layer 235, -1, and the field plate 266. A polycrystalline silicon layer 235 ″ -2 is connected to the equipotential ring 268. This dry polycrystalline silicon etch only removes the exposed polycrystalline silicon layer 235 "without affecting the metal layer pair of cells surrounding the polycrystalline silicon gate electrode 235 'near the polycrystalline silicon finger, that is, the polycrystalline silicon gate 2M near-terminal region. Need special attention, because 0) The special configuration of the 5 ion barrier 225 and the polycrystalline silicon body 235 'formed in these cells is a thick oxide layer, that is, the ion barrier 225 and the gate 235' are completely green. The gate f voltage cannot make some units communicate _______ _,-I (Please read the precautions on the back before filling this page) * -β

This paper size applies the Chinese National Standard (CNS) A4 specification (210 × 297 mm) 4 185 36 Printed by the Bayer Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () Electricity, so some of these units are simulation units 280 . When there is a large collapse in the terminal area, these simulation units 280 can pick up freely charged particles, such as freely charged holes, that run toward the crystal film layer 0 and the active core unit 285 in the substrate 205. Near the terminal area, as opposed to polycrystalline silicon fingers, they become a defensive unit of charged particles. Manufacturing steps similar to those described above can also be used for MOSFET devices with LOCOS ion barrier with a thickness of 5000 to 100 Å. The cross-sections depicted in Figures 4A and 4βg are almost identical to Figure 5A, except that LOCOS is thicker than the hand blocker 225. Please refer to Section 5A. Use a polycrystalline silicon alumina polarizer with a slightly different configuration in the terminal area. The polycrystalline silicon electrode 235 of the active core unit 285 and the simulation unit 280 is the same as the cathode of a MOSFET device having a primary oxide layer of medium thickness. The type of the polysilicon gate 235 "in the termination region is two separate paragraphs, '235"'-1 and 235 ','-2, the remaining steps shown in Figures 5B and 5C, and 4D The figure and Figure 4E are exactly the same, except that the configuration of the contact mask in the terminal area is slightly different. The field plate 2 and the equipotential ring 268 in the terminal area are completely green without the need for another polysilicon etch to separate the polysilicon layer 230 "'-1 and 230,',-2. Figure 4G reveals that The processed substrate 210 of the first conductive dopant, the crystal includes a raised locos ion barrier 225 above the processed substrate 21G, and the transistor further includes a punch-through prevention on the substrate 21 The region 230 is surrounded by an outer green perimeter below the ion barrier 225. The LOCOS ion barrier 225 contains a first conductive dopant, whose concentration is lower than that of the substrate 21 after treatment. The 4H shows that the transistor 17 IH ϋ —-ϋ I 1. Ί 11 Order — ~~ ~~ ~~. ^ (谙 Please read the notes on the back before filling this page) This paper size applies the national standard (CNS) M specification of the towel (21〇 χ297 Male foot) 4 185 36 A? • _ B7 V. Description of the invention () It also contains a polycrystalline silicon gate 235, under which LOCOS has oxide ion barrier movement 'lower and has a breakdown prevention area 23o', so the ion There is a JFET region at the block 225 away from the breakdown prevention region, so that the JFET resistance does not increase. In the actual installation, the scale recording also contains-the body region of the red conductive conductive dopant at 24 o'clock in the matrix 210 surrounds the anti-penetration prevention region 230, and the outer periphery of the polycrystalline silicon electrode 235 'has β-source. The pole is located in the substrate 2L0 and is surrounded by the body region 24o containing the first conductive dopant. Although the detailed description of the present invention, the detailed description of the job description and the description, it is not intended to touch. Of this system _ Once you read the disclosure of the present invention, it will be clear to those skilled in the art that various changes and modifications are made. Because: t, the following patent claim items > as long as the changes and modifications do not reveal the present invention Both the spirit and content are included and included in the scope of the rights of the present invention. — * — 1 nn I-— I *---n · --- Order (please read the precautions on the back before filling in this Page) Μ printed by the Central Bureau of Standards of the Ministry of Economic Affairs, Consumer Cooperatives, who prints paper, and who uses standard nails to store the National Winter Standard (CNS) A4 (210X297 mm)

Claims (1)

The Ministry of Economic Affairs is responsible for the production of consumer goods * -cooperative Du Indian equipment VI. Patent application scope 1 · A method for manufacturing -r MOSFET transistors on the substrate to prevent breakdown, the method includes the following steps: (a) forming a first conductive type crystal film layer on the base hip as a drain region, and then growing an initial oxide layer on the crystal film layer; (b) applying an active photomask to etch the Initially oxidize the layer to define an active area and form a plurality of erbium ion barriers on the substrate. Immediately implant a plurality of penetration prevention areas with a second conductive type ion; (c) deposit an overlapping polycrystalline silicon calendar and apply— The polysilicon layer is used to etch the polysilicon layer to define a plurality of polysilicon gates. Each of the gates overlaps with an ion barrier below it and is over the puncture prevention area. There is an ion barrier between the gates; (d) The polycrystalline silicon mask is removed so as to be implanted with a second conductive type altar and then the body is diffused to form a plurality of skeleton regions; (e) the ion barrier is The diaphragm is used as a source barrier to use the A conductive ion is implanted into a plurality of source regions; and (f) a green insulation layer is formed and a high temperature treatment is applied to encrypt the insulating plutonium and further perform the diffusion of the source region, the The punch-through prevention area is separated from the JFET 麄 by phase B to prevent punch-through from occurring in the transistor without increasing the JFET resistance. 2 · The method for manufacturing a MOSFET transistor to prevent punch-through as described in item 1 of the scope of the patent application, wherein the step of forming an initial oxide layer is to form the initial oxide layer having a thickness of about 1000 to 4000 A Therefore, the ion barrier is formed as a plurality of medium paper ft scales. The reason for use is “Household Ratio” "CNS" A4 size (210X297). ^^^ 1 ^^^ 1 ^^^ 1 mm · — ^ 1 (please read the note f on the back of the book first, then this page) Order-Line clock, Ministry of Economic Affairs, Central Bureau, Prospective Bureau, Consumer Cooperation, Du printed 4185 36 Aa Λο ss ^^ __ ^ ____ A 'thickness of patent application scope Block. 3. The method for manufacturing a MOSFET transistor to prevent punch-through as described in item i of the patent application scope, wherein the step of forming an initial oxide layer is to form the initial oxide layer with a thickness of about 4000 to 10,000 A Therefore, a method for forming the MOS barrier as a plurality of low-thickness ionic barriers, as described in item 1 of the scope of patent application, for manufacturing a MOS transistor on the substrate to prevent breakdown, wherein: The step of the crystal layer of a first conductive type is-a step of forming an N-type crystal film layer; and the step of implanting a plurality of redox regions of the second conductive type ion implantation is a P-type implantation Ions to form the punch-through prevention g as an N-type punch-out prevention area. 5. A method for manufacturing a MOSFEr transistor as described in the first paragraph of the application for a patent patent a method to prevent punch-through, wherein the polysilicon layer is etched to define a plurality of polycrystalline silicon electrodes. Each step and the step below the ion barrier weight 4 is a step of etching the electrode with a length that exceeds the ion barrier and is shorter than the lateral diffusion length of the implanted ions, Therefore, the body region formed by diffusing the ions below the pole electrode and the pole electrode near the terminal region are divided by the ion barrier, so a plurality of simulation units are formed, which can be picked up from the vicinity of the terminal region. The function of the freely charged particles that ran by becomes a defensive unit. 6 · — A kind of M0SFET transistor used to make a substrate to prevent the impact of '20-: --- ----------- order --- M (please read the back first Note $ ¾Reprint I) This paper size is in use • National rate (CNS > 8 4 shape (2ΐ〇χ297mm) 418536 AS B8 C8 D8 Ministry of Economic Affairs, Central Government Bureau, Industrial and Consumer Cooperatives, India π. The method of applying for a patent application method includes the following steps: (a) forming a first conductive type crystal film layer as a drain region on the wafer, and then growing a crystal film layer on the crystal film layer; A pad-like nitride layer; (b) applying an active mask to etch the pad-like nitride layer to etch a plurality of LOCOS windows on the base hip, and then implanting with a first conductive type ion to form a layer having Higher density first conductive type ion implanted JFET resistance reduction region; (0) a local silicon oxidation (LOCOS) procedure is applied to form a plurality of raised LOCOS ion barriers in each of the LOCOS windows, and then The pad-like nitride layer is removed; (d) a second conductive type ion implantation is performed in the plurality of balance prevention regions; (e) an overlapping polycrystalline silicon layer is deposited and A polycrystalline silicon mask is used to etch the polycrystalline silicon layer to define a plurality of polycrystalline silicon gates, each of which is overlapped with a LOCOS ion barrier underneath and above the puncture prevention area, and at the same time, adjacent grasshoppers are attacked. There is a LOCOS ion barrier between each of the two gates; (0) the polycrystalline silicon mask is removed to implant a second conductive body and then diffused to form a plurality of body regions; (g) the LOCOS ion The gate between the barriers is used as a source barrier to implant a plurality of source regions with the first conductive type ion in the hip region, and then the ion barrier is removed; and (h) forming an insulating layer and applying A high-temperature treatment to encrypt the insulating layer and then perform diffusion of the source region, and the punch-through prevention region in the source region is isolated from the JFET, thereby preventing use in the electrical paper ruler. Sample rate (CNS > A4 grid (210X297 mm) 1 n I .H. ^ 11 »nn 1 It I order II nin line (please read the notes on the back of the poem before filling this page) Printed by Pui Gong Consumer Cooperative «. 4 18 5 3 6 as B8 _s__ VI. Application The breakdown occurs in the crystal without increasing the resistance of the JFET. 7. The method for manufacturing a MOSFET transistor and the body on the substrate to prevent the breakdown as described in item 6 of the patent application, which prevents the breakdown. The step of LOCOS ion blocker is to form the ion blocker with a thickness of about 1,000 to 4,000 A, thereby forming the LOCOS ion blocker as a plurality of medium-thickness ion barriers. 8. The method for manufacturing a MOSFEi transistor on the substrate to prevent punch-through as described in item 6 of the patent application, wherein the step forming the LOCOS ion barrier is to form the ion at about 4000 to 10000A. The blocking step thus forms the LOCOS ion barrier as a plurality of medium-thickness ion barriers. 9. The method for manufacturing a MOSFET transistor to prevent punch-through as described in item Q of the scope of patent application, wherein: the step of forming the crystal film layer of a first conductivity type is forming N A step of forming a crystal-type film layer; and the step of using the second conductive-type ion implantation to pierce the prevention region is a P-type ion implantation to form the penetration prevention region as a 1Γ-type penetration prevention region. 10 · The method for manufacturing a MOSFET on a substrate as described in item 6 of the patent application to prevent penetration, wherein the polycrystalline silicon layer is etched to define a plurality of polycrystalline silicon gates, and each of the gates is The step that overlaps with the LOCOS ion barrier underneath is a step that etches the gate with a length that exceeds the LOCOS ion barrier but less than the lateral diffusion length of the body implanted ions, thus the gate "Extreme Paper" Standard «« Furniture Rate (CNS > A4 specification U10X297 mm) II — I ^ — Install I — I n silk. (Please read the note f of the back * before reading this | Page) 185 36 A8 B8 C8 D8 The body region formed by the ion diffusion of the patent application park of the Industrial Standards Co., Ltd. of the Ministry of Interest of the People ’s Republic of China, and the gate near the terminal region is separated by the locos ion m. It is separated, thus forming a plurality of simulation units, which have the function of picking up freely charged particles running from the vicinity of the terminal area into a defensive unit. 11 * A method for manufacturing a MOSFET transistor on a treated substrate to prevent punch-through, the method includes the following steps: (a) forming a first conductive type on the treated substrate The initial oxide layer was used as the rubbish electrode region; and (b) ife used an active photomask to etch the initial oxide layer to define an active region and form a plurality of ion barriers on the substrate, and then implanted with a second conductive ion. Enter a plurality of breakdown prevention areas β 12 · The method for manufacturing a MOSFET transistor to prevent breakdown on a previously processed substrate as described in item η of the patent application country, and: ) Depositing an overlapping polycrystalline silicon layer and applying a polycrystalline silicon mask to etch the polycrystalline silicon layer to define a plurality of polycrystalline silicon poles, each gate overlaps with an ion barrier below it, and then penetrates through Above the prevention region, a JFET region is formed below one of the ion barriers and the punch-through prevention. Because the punch-through prevention formation is separated from the JFET interval, the JFET resistance is reduced. No increase. 13 · A method for manufacturing a MOS transistor on a treated substrate to prevent punch-through as described in item 12 of the scope of the patent application, wherein a polycrystalline silicon mask is applied to etch the polycrystalline silicon layer to define a plurality of-( Please read the note on the back first, and then complete the manuscript. I τ K This paper size is difficult to use _ home gradient (CNS) Α4 size (210X297 mm) in the Ministry of Economic Affairs, out of print, printed by the consumer cooperative, 4 185 33 A8 B8 C8 ------------- D8__ VI. The scope of patent application for polycrystalline silicon gates This step is to retain an ion barrier every two adjacent gates, as the initial oxidation The source-blocking step can therefore be used for source implantation without the need for an additional source mask. 14 · As described in the patent application Fangu No. 13 for the production of a A method for preventing breakdown of a MOSFilT transistor, including the following steps: «) removing the polycrystalline silicon photon so as to apply a second conductive body implantation I and then performing bulk diffusion to form a plurality of suspected regions, and te) For the gate of the ion barrier The source of the barrier to a hand _-conductivity Luo present in the plurality of excitation source implantation region. 15 · Method for manufacturing γ »MOSFET transistors on the treated substrate II to prevent punch-through as described in item u of the patent application ★ This step in which an initial oxide layer is formed is a The step of forming the initial oxide layer having a thickness of about 1000 to 4000 A, thereby forming the ion barrier as a plurality of medium thickness ion barriers. 16 · The method used to manufacture a MOSFET transistor on the treated substrate to prevent punch-through as described in item η of the patent application park, wherein the step (a) of forming a primary oxide is a process The initial oxide layer of 4000 to 10,000 A steps, thus forming the ion barrier as a plurality of thick ion barriers. 17 * The method for manufacturing a MOS transistor on a treated substrate to prevent punch-through as described in item 12 of the scope of the patent application, wherein the polycrystalline silicon layer is etched to define a plurality of polycrystalline silicon gates, each of which III I! Nn ^ ml ^ (please fill in the note on the back of this page before filling in this page) This paper uses the standard of the country β family chess standards < CNS > A4 (210X297 mm) 8 0089 ABCD ^ 18536 '------- VI. The patent application Fan Zhi gate overlaps with the ion barrier below it. The step (c) is a process that uses long ions to exceed the ion barrier but less than the rhyme body. The step of entering the lateral diffusion length of the ions, so that the ions formed by diffusing the selected ions and the gate near the terminal region are separated by the ion barrier, thus forming a plurality of simulation units, which It has the function of picking up freely charged particles running near the terminal area and becomes a defensive unit. 18 · A method for manufacturing a MOSFET I crystal on a treated base hip as described in the patent application No. η fillet to prevent punch-through, wherein: the step of forming a primary oxide layer is a forming process The step of 1000 to 4000A of the primary oxide layer, thus forming the ion trap. The barrier acts as a hand-off barrier with a medium thickness of a plurality of copper; and a polycrystalline silicon mask is applied to etch the pseudocrystalline silicon layer to define a plurality of polysilicon gates. The step (c) of the electrode is a step of keeping the polycrystalline silicon layer covering the intermediate layer of the ion thickness of the region near the allelic ring in the 4 terminal region of the substrate, thus forming a merged cross-section ion barrier to The dike body is immersed in the mule, so that the ion barrier of medium thickness can have a reasonable thickness to increase the collapse voltage, and at the same time, it is not affected by the "implantation ion will penetrate the vicinity of the potential ring" Restrictions on thallium analgesia. 19 · The method used to manufacture a MOSFET transistor on a treated substrate to prevent punch-through as described in item 14 of the patent application park, in which: the paper size 瞩 Λ is the national standard (CNS) Α4 Specifications (2 丨 0X297mm)-Binding i II ^ (Please read the note on the back and fill in the original X) Printed by the Central Bureau of Standards of the Ministry of Economic Affairs βζ 工 consuming Cooperative Society Printed by the Central Standards Bureau of the Ministry of Economic Affairs Packing 4l85 36 A8 B8 C8 ______ D8_____ VI. The step (a) of forming an initial oxide layer together with the scope of the patent application is a step of forming the initial oxide layer with a thickness of about 1000 to 4000 A, thus forming the ion barrier as a plurality A medium thickness ion barrier; applying a polycrystalline silicon mask to etch the polycrystalline silicon layer to define a plurality of polycrystalline silicon gates; the step (c) is to keep the polycrystalline silicon layer covering the substrate, near the equipotential ring in the terminal region A step of this medium-thickness ion barrier, so a merged ion barrier is formed to implant ions with an acid spacer, so that the medium-thickness ion barrier can be properly To increase the breakdown voltage without being restricted by the body implanted ions penetrating the combined ion barrier near the ecliptic ring: and a (f) step following the (e) step forms a The insulating layer is subjected to a high temperature process to encrypt the green insulating layer, and at the same time, the source region is diffused. In step (g), a contact mask is applied to etch the insulating layer to define a plurality of contacts. The window and the photomask to open an equipotential ring U in the middle part above the polycrystalline silicon layer on the combined ion barrier, and apply a metal mask to expose the polycrystalline silicon calendar In order to etch and separate the polycrystalline silicon layer through the opening of the ecliptic ring so as to make the ecliptic ring green, the intermediate thickness ion implantation near the ecliptic ring does not require an additional photomask. 20 · The method for manufacturing a MOSFET transistor on a treated substrate to prevent punch-through as described in item 19 of the scope of the patent application, wherein the polycrystalline silicon layer etched on the combined ion barrier is applied. A dry etching process to step the allelic ring green. ---------- install ------- order ------ line (please read and read the notes on the back before buying 4 copies) This # Λ 张 值 It is used in China B countries Kneading rate (CNS) A4 specification (210X297 mm) 185 36 A8 B8 C8 D8 Printed by the Shell Standard Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs »Six. Application for a patent scope 21 A method for preventing power crystals in a region includes the following steps: (a) forming a pad-like layer on the treated substrate; (b) applying an active photomask to etch the pad-like layer and Define a plurality of LOGOS provinces on the processed carcass; (c) Use a single silicon oxide (LQC0S) procedure to form a plurality of raised L0C0S ion barriers in each of the LOCOS windows. The pad calendar is removed; and (d) a plurality of puncture prevention areas are implanted with a gun-type conductive type off-hand. 22 · A method for manufacturing a power transistor having a punch-through prevention region on a treated base hip as described in item 21 of the patent application, wherein the ridge-like layer is etched to pass through the base The number of steps in the boundary line of the LOCOS dome further includes a step of implanting a first conductive ion to form a JFET; preventing the S from containing a high dopant concentration of the first conductive type. 23. The method for cracking a functional transistor with a breakdown prevention region on a treated substrate as described in item 21 of the patent application, which further includes (e) a polycrystalline silicon wafer with a weight of 4 A polysilicon mask is applied to define the polysilicon layer by touching the polysilicon layer, wherein each of the gates overlaps with one of the LOCOS ion barriers below and above the breakdown prevention area Therefore, a JFET region is formed under the LOCOS ion barrier leaving the punch-through prevention area. Since the punch-through prevention area is in line with the JFET area at the size of the paper, it is applicable to China »Jiatizhan (〇 阳) people 4 specifications (210 father 2!) 7 mm) I! II with nh —II cable (please read the note $ item on the back first and then #write this 肓) 6. The patent application Fanyuan A8 B8 C8 D8 LOCOS ion barrier is formed where the ion barrier is formed, so the JFET resistance will not increase. 24. A method for manufacturing a power electric insect body having a punch-through prevention area on a treated substrate as described in item 23 of the patent application, wherein the polycrystalline sand layer is etched to define a plurality of polycrystalline silicon gates, and Each (e) step that each gate overlaps with a LOCOS ion barrier below it is a step of maintaining a LGC0NS ion barrier at every two phased gates, and a source can be applied Implanted without additional light sheet. 25 _ The method for manufacturing a power electric worm hip with a penetration prevention area on a & treated substrate as described in item 24 of the patent application, further comprising the following steps: (f) removing the polycrystalline silicon photomask to A second conductive type of body implantation is performed, and then a block is applied to form a plurality of body regions; (g) the LO ^ S # sub-blocking between the gates is used as a source block, and In the local deterrent region, a plurality of pseudo-polar regions are implanted with the first conductive ion. 26. The method of manufacturing a power transistor with a punch-through prevention region on a treated Gio as described in item 21 of the application Sailey Fan Guo, wherein the step (c) of forming the LOCOS ion barrier is a The step of forming the LOCQS ion barrier with a thickness of about 1000 to 4000 A is difficult to form the LOCOS ion barrier into a plurality of LOCOS ion barriers with a medium thickness. 27 · As described in item 21 of the patent application, on the processed basis ---------------------------- , (Please read the note $ on the back of the page before filling in this page) Du Yin printed by the Ministry of Economic Affairs of the Central Bureau of Vehicles of the People's Republic of China *. This paper uses the Chinese national sample rate (CNS > A4 size (210X297 mm) ) 4 丨 8536 A8 B8 C8 D8 VI. Patent application method for manufacturing a power transistor with a punch-through prevention area, wherein the (c) step hemp forming the LOCOS ion barrier is a layer having a thickness of about 4000 to 10,000 A LOCOS ion blocking step, thus forming the LOCOS ion barrier as a plurality of thick LOCOS ion barriers. 28 · Manufacture the power with a balance prevention zone on the treated substrate as described in item 21 of the patent application scope. The method of transistor, wherein the polycrystalline silicon layer is etched to define a plurality of polycrystalline silicon W poles, and each of the appended poles and a LOCOS element underneath to block the weight of the (c) step is a length exceeding the The step of LOCOS ion blocking and less than the lateral diffusion length of the implanted ions of the body. The entire area formed by the diffusion of the LOGOS mule and the gate near the terminal are separated by the LOCOS ion bile septum, so a plurality of simulation units are formed, which have the ability to pick up fronts running near the terminal area. The function of freely charged particles and 4 is a defensive unit. 29. A method of manufacturing a power crystal puppet with an impulse prevention area on a substrate already located as described in the patent application No. 24, wherein, the forming The step (c) of the LOCOS ion block is a step of forming the LOCOS heteroblock in a thickness of about 1000 to 4000A, so that the LOCOS ion block is formed as a plurality of medium-thickness LOGOS mules blocks; and applying a The polycrystalline silicon mask etches the polycrystalline silicon layer to define a plurality of polycrystalline silicon gates. The step (c) is a section of the medium-thick LOCOS that keeps the polycrystalline layer covering the substrate, the terminal region, and near the equipotential ring. Ion-blocking steps, so the formation of ———————— 赛 ---- «—, π ------ M (please« read the precautions on the back before writing this page V) Ministry of Economic Affairs Printed by the Central Bureau of Standards Shellfish Consumer Cooperative «. This paper Degrees are printed in China ’s National Gradient (CNS) A4 size (210 × 97 mm) 185 36 B8 C8 D8 Printed by the Central Government Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, and applied for a patent application. A combined body ion barrier to block implantation Ions, so that the medium-thickness ion barrier can have a proper thickness to increase the breakdown voltage, and at the same time is not limited by the suspected implanted ions that penetrate the combined hetero-blocker near the potential ring. 30 * The method for manufacturing a power transistor with a punch-through prevention region on a treated substrate as described in item 1 of the patent application, wherein the step (c) of forming the LOCOS ion barrier is a false The step of forming a L excellent 0S ion ancestor with a thickness of about 40 to 100 θ_ is formed, thereby forming the iOCOS barrier ancestor as a plurality of thick LOCOS ion barriers; applying a polycrystalline silicon mask to etch the polycrystalline silicon layer The (e) step aimed at a predetermined number of polycrystalline silicon is a block of the medium-degree LQC0S sculpture that keeps the polycrystalline silicon layer covering the base region, the terminal region, and the vicinity of the equipotential ring. As a result, a combination of body ion barriers were formed to block the implanted ions in the hips, and the medium-thickness anthrax ridges were appropriately thickened to increase the collapse voltage without being affected by the implantation. Sub-penetration of the combined hand-off barrier near the bit rings; and an (h) step following the (g) step to form an insulation layer and apply a high-pressure procedure to insulate the insulation Layer encryption, and at the same time start the diffusion of the source region, and step (i) A contact mask is applied to etch the green insulation layer to define a number of chirped contact windows and the light army is applied to open an equipotential ring opening in the middle portion above the polycrystalline silicon layer on the combined ion barrier. And apply a metal photomask to expose the scale of the paper, using the Chinese «Home Ladder Standard (〇 呢) 8 4 size (210 father 297 mm) --I --- ^ ----- Installation--(Please read the note iliW * on the back first and then on this page J Ministry of Economy-6-Bao Gong Consumer Cooperative Co., Ltd. of Central Standards Bureau *. 4185 36 A8 B8 C8 __ D8 VI. Application scope of this polycrystalline silicon Layer to etch and separate the polycrystalline silicon layer through the bit ring opening to insulate the bit ring, so implanting the medium-thickness LOCOS ion barrier near the bit ring requires additional photomasks. A power transistor on a processed radical containing a first conductive type dopant, the transistor comprising: a primary oxide layer * covering an area of the active region opposite the processed skeleton A primary oxidation sludge located in the active area on the treatment base «; and a bit A punch-through barrier region in the substrate encountered by the treatment is enclosed around an outer edge of the initial oxide ion and contains the first conductive dopant, the dopant concentration of which is higher than that of the treatment. The concentration of the matrix is a value of ** 32. The power transistor on the processed ** containing the first conductive type doped with a dopant, as described in item 31 of the patent application, also contains a polysilicon. The pole is covered with the initial oxidized off-hand cylinder barrier underneath and above the punch-through prevention region, so a JFET region is placed under the off-hand barrier region and the punch-through prevention 1 is engaged, so JFET The electrical time will not increase. 33 · As described in Item 32 of the patent application, the power transistor on the base of the E-treatment pass containing the first conductive dopant, further includes a bit in the gate. In the vicinity of the electrode, the first oxidation source which is used as the original oxidation source barrier is separated from the barrier, so that the source implantation can be performed without an additional photomask. This paper is suitable for two non-standard applications (CNS > Λ4) (2 丨 0X297 mm) ---------------------- r. ^ .--- --- 0, (please read the note on the back, and then write this page) Printed by the Bayer Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 4 18 5 3 6 as BS C8 D8 6. Scope of patent application 34 A power transistor on a treated substrate containing a first conductive dopant as described in item 33, including: _ a bulk region containing a second conductive dopant, located at the Inside the substrate, surrounding an outer edge of the polycrystalline silicon gate outside the punch-through prevention region; and inside the substrate enclosed by the local region containing the first conductive dopant It is very straight. 35. The power transistor in the processed basic clay containing the first conductive type dopant as described in item 31 of the scope of patent application, wherein the initial oxide layer and the initial oxide layer are ion-blocked. The degree of inertia is 1000 to 4000 A, so that a medium-thick initial oxidative off-hand barrier is formed. 36 · As described in item 31 of the scope of patent application, it contains the first conductive The power transistor on the treated substrate of the dopant, where the initial oxygen 1 and the initial oxide layer and the initial oxide layer has a thickness of 4000 to 10000 A, which then forms a thick initial oxide ion barrier. 37 · -A power transistor on a treated substrate containing a first conductive dopant, the transistor comprising: a raised LOCOS barrier is supported by the treated tomb; and a A punch-through barrier region located in the buried substrate there surrounds the periphery of an outer edge below the LOCOS ion barrier and contains the first conductive dopant, the doping concentration of which is higher than that of the treated substrate. The concentration is low. 38 _As described in item 37 of the scope of the patent application, the power transistor on the treated base hip containing the first conductive dopant further contains a -------- ^- ---- Μ ------ ^ 11 ------. Ii (Please read the precautions on the back before writing this page) This paper size is applicable to China National Slope (CNS) A4A grid ( 210X297 mm) The Central Government Bureau of the Ministry of Economic Affairs only prints consumer cooperatives *. 418 5 3) as? S D8 6. Scope of patent application The polysilicon gate is covered by the LOCOS oxide pixel barrier above the breakdown prevention region, so a JFET region is placed below the LOCOS ion barrier region and separated from the breakdown region, so the JFET resistance is not Will increase. 39 _As described in item 32 of the patent application, the power transistor on the processed hip containing the first conductive dopant is further included, and another is located near the electrode and is used as A LOCOS ion barrier of the source bile septum of the LOCOS source can be implanted without the need for an additional mask. 40. The power transistor as described in No. 39 of the patent application, which is located on the already-existing base soil containing the first conductive dopant, and further includes a base in the base and containing a first An intended region of the second-conducting t-type dopant covers the outer edge of the worm-like silicon appendage outside the puncture prevention zone; and a source region located within the substrate is contained The first plant-guiding dopant is surrounded by the local planting area. 41 · An M0SFET power transistor on a grave with a top surface, the ship's 5FET power transistor includes: a plurality of MOSPET power transistor units with a common drain in the substrate, one for each unit A local region and a source region, the body region surrounding the source region below the top surface, and a channel extending along the top surface from the source region above the local region to the drain Area; a gate located on the channel, above the top surface to control the passage ------, _ 33__; __ This paper method uses the Chinese Mingjia ladder standard (CNS > A4 size (210X297) %) --_--- ^ ----- ^ -------- 1T ------ 0, (锖 Read the precautions on the back first and then write the copy 肓) 418536 Α8 BS C8 D8 The Ministry of Economic Affairs ’Central Government Bureau of Industrial and Consumer Cooperatives printed theta, the scope of the patent application said that the gate further includes an ion barrier below it; and a #breakthrough prevention area is located in the substrate, and the body area and the Juxtaposed between one side above the ion barrier, wherein the first conductive-type dopant contained in the punch-through prevention region has a higher concentration than that in the substrate In order to prevent the penetration of the ~ crystal film layer concentration is small, because the hetero-blocker under the gate keeps the penetration prevention region and a JFET region in the substrate located under the gate, Make a JFET current unaffected. 42. The MOSFET power transistor on a substrate with a top surface as described in item 41 of the patent application, wherein the ion barrier below the gate is silicon oxide ion 43. A MOSFfcT power transistor on a substrate «with a top surface as described in the patent claim _ item 42, wherein the mule blocker below the intermediate electrode is a convex LOCOS silicon oxide Carved block 44 · The MOSFET power crystal bond located on the base section with a top surface as described in item 43 of the patent application, which contains a JFET located below the L0c0s ion barrier to reduce electricity. Group area, which contains the first guide "The ion-like concentration is higher than that of the crystalline film layer used to reduce JiET resistance in the substrate" 45 · As described in the 41st patent application The MOSFET power transistor on a substrate with a top surface further contains: A terminal area located above the base hip and opposite to the transistor unit; and a plurality of simulation units near the terminal area, wherein the body area of each simulation unit is connected to the gate electrode in the simulation unit The gate ---:-. --------------------------- order. (Please read the note on the back before filling in this X) 418536 A8 S, the ion barrier insulation under the patent application " where the simulation unit can be used as a lamination unit in the terminal area to pick up Lai Linlin's freely charged particles. 46. The MOSFET power transistor on a substrate having a top surface as described in the patent application Fan Yuan No. 41, wherein the MOSFET power transistor is an N-type MOSFET transistor, of which the first conductive type is An N-type conductive type, and the second conductive type is a p-type conductive type. 47 · The MOSFET power transistor on the top surface of the substrate as described in the first paragraph of the patent application. The body 'where the MsFET power transistor is a P-type MOSFET transistor, of which the first conductive type Is a PS conductive type, and the second conductive type is an N type conductive type. 48 · —a ship's gFET power transistor on a carcass with a top surface, the power t carcass includes: a plurality of tender) gFET power transistor units located in the climbing charter with a common drain. Each unit has a skull region and a source region, the body region surrounds the source region below the top surface, and a channel runs along the top surface from the source region above the skull 11 Extends to the drain region; a gate located on the top surface of the channel to control the channel, wherein the gate further includes an ion barrier below it, of which the gate The capacitance to the drain is reduced by the ion barrier, and the switching rate of the power transistor hip is improved due to fragmentation. 49. The MOSFET power transistor on a substrate with a top surface as described in item 48 of the patent application, which is located in the paper size of each gate electrode «Β 家 榇 丰 (CNS > A4 size (210X297mm) ---, -------- installation ----- order ------ line two, please read the precautions on the back before filling in this page) Economy The Ministry of Central Government Bureau Wu Gong Consumer Co., Ltd. printed oxygen A18536 patent application scope AS B8 C8 DB ^ the ion barrier is-the thickness of the surface to the __ on the oxide described in the base with-the surface of the ion The thickness of each bipolar oxidant ion block of this closed electrode is drawn to 10 _ (please read the note of the first note * ^ 写 本 贳) : Printed by the Industrial and Consumer Cooperatives in 36 ft. Paper size (CNS) (2ΐ〇χ297mm)