TW297938B - The electrostatic discharge protection device and its manufacturing method - Google Patents

Abstract

An electrostatic discharge protection device includes: - A 1st type semiconductor substrate; - Form gate structure on certain position of substrate; - Construct separately the 2nd thick and 2nd light dopant region to form source & drain under two sides of gate structure, in which, the light dopant has more contact depth than thick dopant; - Cover the dielectric on gate structure, source & drain and define 1st & 2nd contact window to expose separately the source & drain region; - Form 1st electrode on dielectric and through the 1st contact window coupled with drain region; - Form 2nd electrode on dielectric and through the 2nd contact window coupled with source area.

Description

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V. Description of the Invention (ι) 207938 The present invention is a protection element built into an integrated circuit, especially related to a variety of electrostatic discharge protection elements and methods of manufacturing the same. Electrostatic discharge (Electrostatic Discharge, usually abbreviated as ESD) stress is almost present in the measurement, assembly, installation and use of integrated circuits, which will cause damage to the integrated circuits and indirectly damage the function of the electronic system. The reason for the formation of electrostatic discharge is usually explained by three models. (1) Human body model (HBND: This is based on US Military Standard No. 883 Method 3015. 6 (MIL-STD-883, Method 3015.6). As defined, it refers to the electrostatic discharge stress caused when static electricity touches the pins of the integrated circuit; (2) machine model (MM): refers to when the static electricity comes into contact with the pin of the integrated circuit The electrostatic discharge stress caused by the existing industry standard EIAJ-IC-121 method 20 test method; (3) charged device model (charged device model (CDM): refers to an integrated circuit that has been charged before In the process of contacting a conductive substance and grounding, it will form an electrostatic discharge pulse through the integrated circuit. —-------- Please refer to Figures 1A and 1B, which show the input pads (input pad) ) And the output buffer junction (output pad) circuit schematic diagram of the electrostatic discharge protection circuit. As shown in FIG. 1A, the input buffer junction pad 5 uses an NMOS transistor Ml to protect the internal circuit 6 (internal circuit), Gate and source of NMOS transistor Ml The base electrode is connected to the VSS potential, and the drain electrode is connected to the input buffer bonding pad 5. Furthermore, as shown in FIG. 1B, the output buffer bonding pad 7 uses a pair of NMOS transistors M2 and PMOS transistors M3 protects the internal circuit 6 from electrostatic discharge damage; the paper standard of NMOS transistor M2 and PMOS transistor M3 is applicable to China National Standard (CNS) Α4 specification (210Χ297mm) (please read the precautions on the back before filling in (This page) --------------- ί I Meal ------ 11Τ —-1 Τ— —III 丄 -Line Economy Ministry Central Standards Bureau Staff Consumer Cooperative Printing and Printing Ministry Printed by the Central Standards Bureau employee consumer cooperative A7 B7 V. Description of the invention (2) The gates are all coupled to the internal circuit 6, and the drains are all connected to the output buffer bonding pad 7, in addition, the source and substrate of the NMOS transistor M2 Both electrodes are connected to the VSS potential, and the source and base electrodes of the PMOS transistor M3 are connected to the VDD potential. Next, please refer to FIG. 2, which shows a cross-sectional view of a conventional ESD protection device fabricated in a semiconductor substrate. Among them, the left side of the figure is an NMOS transistor (for example, Figure 1A, The cross-sectional view of the element M1 or the element M2) of FIG. 1B; the right side of the figure is a cross-sectional view of a PMOS transistor (for example, the element M3 of FIG. 1B). The reference number 1 depends on the difference of the NMOS transistor or the PMOS transistor , Which can be a P-type or N-type region formed in the semiconductor substrate; reference numerals 10 and 11 are field oxides, such as local oxidation method (Local Oxidation of Silicon, LOCOS) At a predetermined position of the substrate 1, an active region 100 is defined between the field oxides 10 and 11; reference number 12 is a gate oxide shield; reference number 13 is a gate electrode layer; reference numbers 14A and 14B are a drain region and a source region, which are respectively located in the substrate 1 under the two sides of the gate electrode layer 13 and are implanted through an N-type or P-type impurity cloth and Region 1 is derived; reference numeral 15 is a dielectric layer, and two contact windows 16 and 17 are defined by etching to expose the drain region 14A and the source region 14B, respectively; furthermore, reference numerals 18 and 19 are conductive layers. It is obtained by etching the same aluminum metal layer. The conductive layers 18 and 9 are respectively Regions 14A and 14B connected to the source region. However, if the device structure shown in Figure 2 is used as an ESD protection device, when the phenomenon of electrostatic discharge occurs, the drain junction will collapse and generate a lot of

In- In— nn n · ^ ^ n— xi ^ ifl--n # nn ^ t nf— ^ 0¾. I-Λ &, (please read the precautions on the back before filling out this page) Standard (CNS) A4 specification (210X297 mm) Printed by the Employees Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 297938 A7 ____ B7 V. Invention description (3) The heat is concentrated at the jl column cylindrical edge 110, This is the bgt spot when the electrostatic discharge stress occurs. This heat energy will be isotropically spread. The isotropically spread causes the metal material of the conductive metal 18 to melt due to heat, and the diffusion puncture (spicking) _ The pole junction may even cause a short circuit between the electrode-less region 14A and the source region 14B, causing the device to be damaged by electrostatic discharge. Therefore, the main object of the present invention is to provide an ESD protection. By forming a conductive block above the source / drain region, the electrode metal is away from the hot spot during the electrostatic discharge stress, which can avoid the defect of the aluminum metal puncturing the junction. Yet another object of the present invention is to provide an ESD protection device with a smaller junction capacitance value, so that the capacitance value of the input / output buffer bonding pads can be reduced. _ Furthermore, another object of the present invention is to provide an ESD protection device with a deep lightly doped region at the source / drain region, which can be used to reduce the ESD current density and enhance the device resistance to ESD stress Ability. Yet another object of the present invention is to provide a method for manufacturing an electrostatic discharge protection device. By diffusing the implanted polycrystalline continuous layer into the substrate to form a deeper junction of the lightly implanted area, it is defined as conductive by etching The block is placed above the source / electrode region. Therefore, the objects of the present invention can be provided by an electrostatic discharge protection device; including: a semiconductor substrate; a gate structure formed at a predetermined position on the bottom; a source region and a drain region, which are located in The base under the two sides of the gate structure is constructed by a densely mixed planting area and a lightly mixed planting area 5 (please read the precautions on the back before filling this page)

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Printed and constructed by the Employee Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs. Among them, the lightly mixed planting area has a deeper junction depth than the concentrated area; Region and the drain region, and is defined as a first contact window and a second contact window, respectively, to expose the drain region and the source region; a first electrode is disposed above the dielectric layer, Coupled to the drain region through the first contact window; and a second electrode disposed on the insulating layer and coupled to the source region through the second contact window. And these objects of the present invention can also be provided by providing a method of manufacturing an electrostatic discharge protection device 'including: (a) providing a semiconductor substrate; ⑻ forming an oxide calendar on the substrate, and defining two openings by etching, exposing The substrate; (C) forming a polycrystalline silicon layer on the oxide layer and contacting the substrate through the openings, wherein the polycrystalline silicon layer is doped with impurities; (d) is subjected to thermal diffusion treatment, The impurities contained in the polycrystalline silicon diffuse into the substrate to form two lightly doped regions under the openings; etching defines the polycrystalline silicon layer as two conductive blocks on the lightly doped regions respectively At the same time, a gate structure is also etched between the conductive blocks; (1) The gate structure and the conductive blocks are used as masks to implant ions into the substrate to form densely doped regions respectively Both sides of the lightly doped region, and the thickly doped region has a shallower junction depth than the lightly doped region; (g) forming a dielectric layer overlying the surface of the substrate and defining two contacts by etching The windows respectively expose the conductive blocks; and (h) form two electrodes Make electrical connection with the conductive blocks through the contact windows, respectively. In order to make the above-mentioned objects, features, and advantages of the present invention more obvious and understandable, a preferred embodiment is described below in conjunction with the attached drawings to explain in detail that this paper standard is applicable to China ## 样 准 (CNS) A4 specification (21〇X 297 Gongchu) --- -------- (I installed ------ ordered ----- ^. Line (please read the notes on the back before filling in This page) Printed by the Employees ’Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention () 5} The following: A brief description of the diagram: Figures 1A and 1B show the input buffer joint pad and wheel-out buffer joint pad, respectively. Circuit schematic diagram of an electrostatic discharge protection circuit; FIG. 2 is a schematic diagram illustrating the structure of a conventional electrostatic discharge protection device; and FIGS. 3A-3E are diagrams illustrating a preferred embodiment according to the present invention. Process cross-sectional view. Embodiment: 4 Refer to FIGS. 3A-3E, which shows a process cross-sectional view according to a preferred embodiment of the present invention. The left side of each drawing is an NMOS transistor (such as FIG. 1A) Element] νπ or element M2) of Figure 1B; a right side of each figure is a PMOS transistor (for example The cross-sectional view of the device M3) in FIG. 1B. The key steps in the manufacturing process are shown below. The details are as follows: First, refer to FIG. 3A. Provide a semiconductor substrate 3, such as P-type or N-type silicon Substrate. Ion implantation is then used to implant ions into the semiconductor substrate 3 to form a dongle region 30. If the ESD protection device to be fabricated is an NMOS device, the dongle region 30 is a P-type dongle region; If the protection element is a PMOS, the donated area 30 is an N-type donated area. The illustration in this embodiment shows both the P-type donated area and the N-shaped parallel area on the left and right sides as an example. As shown in FIG. 3B, the field oxides 31 and 33 are formed on the surface of the dome area 30 by the local oxidation of silicon (LOCOS). The active area of the device is defined between the field oxides 31 and 33. China National Standard (CNS) A4 specification (210X297 Gongchu;) (Please read the precautions on the back before filling this page}-丁 _ 、-* 线

Printed by the Employee Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs and also used as an insulating structure from other transfers. The material of the compounds M and 33 is probably composed of silicon oxide. Then, the surface of the well 30 is thermally oxidized to form a thin oxide layer 34 where it is not covered by the field oxide 31'33. Subsequent chemical vapor deposition (CVD) is used to form the thin polycrystalline material 35 on the thin oxide film 34. A first photoresist layer 36 is re-coated on the thin polymorphic second layer 3S, which is defined as two openings 30 2 and 30 4 by photolithography. Then, using the first photoresist layer as a mask, the thin polycrystalline silicon layer and the thin oxide layer 34 are etched in sequence along the openings 30 2 and 30 4 to expose the donated area 30, that is, the cross-sectional structure shown in FIG. 3C . The thin polycrystalline silicon layer 35 is used to shield the thin oxide layer 34 from contamination. Then, after the first photoresist layer 36 is removed, the phostomeric second layer 37 is formed on the thin polycrystalline layer 35 by chemical vapor deposition, and is in contact with the merged region 30 through the openings 302 and 304. However, the polycrystalline silicon layer 37 is implanted with high-concentration impurities, for example, if the well region 30 is a p-type dongle region, the polycrystalline silicon layer 37 can be implanted with N-type impurities of phosphorus ions, and its implantation energy Approximately between 40 ~ 60KeV 'and the implantation dose is approximately in the range of 5xl0is ~ 5xl0i6cm-2; if the area 30 is an N-type parallel area, the polycrystalline silicon layer 37 can be applied with P-type impurities of BF2 + ions For planting, Fan Yuan with a planting energy of about 40 ~ 60KeV and a planting dose of about 5 × 1015 ~ 5xl016crrT2. This implantation step can be performed using the same mask when forming the p-type or N-type scallop area. Subsequent application of a thermal diffusion process allows impurities contained in the polycrystalline silicon layer 37 to diffuse into the area 30 along the range of the openings 302 and 304, and form the light-seeding area 38 separately, as shown in FIG. 3D Of the cross-sectional structure. If the polysilicon 8 paper standard is applicable (CNS) A4 specification γ ^ χ297 public product) I "—installed ------ · order L ----- ^, line-** (please read the back side first (Notes and then fill this page)

The layer 37 contains N-type impurities, the junction depth of the lightly doped regions 38 and 39 is between 0.4 ~ 0.6μιη, and the concentration is between 5 × 1017 ~ 5x1018cm_3; if the polycrystalline silicon layer 37 contains P-type impurities, the lightness of the junction of the lightly planted areas 38 and 39 is about 0.4 ~ 0.6μηι, and the concentration is about 5xl〇i7 ~ 5xl018cnT3. Printed by the Employee Consumer Cooperative of the Central Bureau of Economic Development of the Ministry of Economic Affairs, coated with a second photoresist layer 40 on the polycrystalline silicon layer 37, and overlaid on the lightly doped areas 38 and 39 by a pattern defined by optical lithography Part of the polycrystalline silicon layer 37 is also used to define the position of the word. Then use the second photoresist layer 40 as a leather curtain. When a gate electrode layer y, J1 ~, the soap is freshly engraved to obtain conductive coatings up to 39 and ▲, which are located on both sides of the gate electrode layer 50; At the same time, the thin polycrystalline silicon layer 35 and the thin oxide layer 34 are also etched. Among them, the gate electrode layer 50 and the thin polycrystalline crushed layer 35 covered by the same are made of polycrystalline silicon material, so only the same electrode layer surface, and The thin oxide layer 34 shielded under the gate electrode layer 50 is used as a 1⁄2 fun walking royal house ^ then ^ and the conductive block moves. For the set, according to the NM〇s or pM〇s abandoned positions are given N Type or p-type binding cloth is implanted in the merged area, forming a painful move. It is divided into two sides 38 and 39. If the densely planted areas 44, 45 are> ^ type ', the junction depth is approximately between 〇1 ~ 〇3 called between = depth' and has between about 5xl〇19 ~ 5xl〇2〇cm-3 Concentration; If the densely planted areas 44, 45 are P-type, the junction depth is approximately between 〇2 ~ 〇.4μπι 'and the concentration range between about 5χ1〇19 ~ 5xi〇2〇cm 3 . The cross-sectional structure shown in Section 3E ® is obtained. Among them, the dense mixed plant g only makes one the drain region of the electrostatic depletion protection element 2 -.................................... ........ " ^ Zhang Shijie still closes the family -------- f I —---- ^-IT ------ f Wei ----- (please Read the precautions on the back first and then fill out this page) A7 A7 The Central Sample Bureau of the Ministry of Economic Affairs Employee Consumer Cooperative Prints the Fifth, Invention Description (8) The concentrated planting area 45 and the light mixing planting area 39 construct an electrostatic discharge protection element Source selection. Subsequently, a dielectric layer 51 is deposited over the entire substrate surface, and through optical lithography and etching procedures, two contact windows (contact Wind0w) 4w47 are formed, exposing the conductive blocks 42 and 43, respectively. Then deposit a metal layer (such as aluminum) 48 and a second electrode 49; wherein, the first electrode 48 is in contact with the conductive block 42 via the contact window 46 and connected to the first! The circuit 7 shown in the figure is connected to the contact window 47 of the second electrode 4 and the conductive block 43, and is connected to the isolation. Section 5e is a cross-sectional view of the structure according to a preferred embodiment of the present invention. In summary, the present invention constructs the non-polar region and the source region by using the combined structure of pain star plant ^ thick ^^ The lightly planted area has a deeper junction depth than the concentrated planted area, such as 31 #, which reduces electrostatic discharge when electrostatic discharge stress occurs, to disperse the heat generated by the plant and lightly blend the concentrated area ϋ is low, so it shows a small junction capacitance value, and it also indirectly decreases ^ In addition, at the place where the planting area is located, due to the presence of (conductive good, block ~ above the lightly mixed planting area, it is far away from the hot spot when electrostatic discharge stress occurs, g Prevent the shortcomings of the electrode metal due to thermal melting to puncture the joint. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone who is familiar with this skill will not deviate from the spirit and Within the scope, some changes and modifications can be made, so the scope of protection of the present invention shall be as defined in the scope of the attached patent application. This paper standard is applicable to the Chinese National Standard (CNS) a ^. &Quot; ( 210 ~ 297 ^ «) '-------- f I shower coat I-(Please read the notes on the back first Items and then Complete this page):, Line !!

Claims (1)

ABCD Printed and applied for patent scope by the Employees Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 1. An electrical discharge protection element-a first-type semiconductor substrate; a gate structure formed at a fixed location of the substrate; a source region and a The drain region, which is located in the substrate below the two sides of the gate structure, is constructed from the second type densely planted area and the second type lightly planted area, wherein The deep junction depth of the densely-doped regions; a dielectric layer covering the gate structure, the source region and the drain region, and is defined as a first contact window and a second contact window, Respectively used to expose the drain region and the source region; a first electrode is disposed above the dielectric layer and is coupled to the drain region through the first contact window; and a second electrode is disposed on the The dielectric layer is coupled to the source region through the second contact window. 2. The ESD protection element as described in the first paragraph of the patent application "wherein" the dielectric layer is an oxide formed by a deposition. 3. The ESD protection element as described in item 1 of the patent application, wherein the first type is a P type and the second type is an N type. 4. The ESD protection element as described in item 3 of the patent application scope, wherein the lightly doped areas have a junction depth between about 〇4 ~ 〇6 " m, and about 5x10. 17 ~ 5xl〇lscm-3 concentration. 5. The ESD protection element as described in item 4 of the patent application scope, wherein the densely planted areas have a junction wood thickness between about 0.1 ~ 0.3 μm and between about 5x10 19 ~ 5x1 〇20 concentration. 11 ....................... installed ........... order ......... first line (please first Read the back of the page; ± Issues and then fill out this page) Wai ^-Iw · 1, please print ab CD Printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, where == the electrostatic discharge protection described in item 1 of the patent scope For the device, the first type is N-type, and the second type is p-type. This application is called the electrostatic discharge protection element described in Item 6 of the patent scope. The lightly planted areas such as lian and others have a degree of approximately 0.4 ~ 0.6 m and a range of approximately 5x1017 ~ 5x10 \ m -Concentration between 3. The ESD protection element described in Item 7 of the application scope of the whistle patent, the densely doped planting areas have a connection depth between about 〇2 ~ 〇4 " m, and about klOi9 ~ 5xl〇2 () cm-3 concentration. In the case of the electrostatic discharge protection element described in item 1 of the scope of the patent application, a conductive block is still provided between the first electrode and the drain electrode. The electrostatic discharge protection element described in item 丨 of the patent application scope, and, a conductive block is still provided between the two electrodes and the source region. u. The static electricity protection element as described in item 丨 of the patent application scope, wherein the drain region is connected to a buffer bonding pad. 12. The electrostatic discharge protection element as described in item 丨 of the patent application scope, wherein the proton electrode structure includes a gate dielectric electrode layer from bottom to top. YY ^ m 13. As stated in the scope of the patent application, the static electricity protection element ^ j where the gate electrode layer and the second electrode are also connected to the-power supply 14.-kind of electrostatic discharge protection element The manufacturing method includes: (a) providing a first-type semiconductor substrate; (b) forming an oxide layer on the substrate, and etching to define a two-fold σ 'to expose the substrate; ... .............. installed ................- T .............. ^ line (please read first (Notes on the back and then fill out this page) 12 The scope of the patent application should be a complex crystal frequency in the oxidation, and also contact the substrate through the openings, wherein the complex crystal layer is supported by the second type impurities ”Jd) Apply thermal diffusion treatment to make the polycrystalline silicon: type impurities = disperse into the substrate to form two second-type lightly planted areas in: ⑷etching defines the polycrystalline second layer as two conductive blocks Separately in the light-weight rooms, at the same time also forming a gate structure on the conductive blocks ^ surface (1) The gate structure and the conductive blocks are used as a mask, and the cloth 2 is formed into the substrate. The second type of strong blend is Both sides of the lightly-doped areas, and the densely-doped areas have a shallower connection than the lightly-doped areas (g) forming a dielectric layer overlying the surface of the substrate, and exposed by a contact window defined by etching The conductive blocks; and (h) forming two electrodes to be electrically connected to the conductive blocks through the contact windows, respectively. 15_ The manufacturing method of the ESD protection element as described in item 14 of the patent scope, Where 'the first type is a? Type and the second type is an n type. J6. The method for manufacturing the ESD protection element as described in item 15 of the patent application range, wherein the lightly doped planting areas have At the junction depth of 〇4 ~ 〇6 " 扪 =, and the concentration 17 between 5 × 1〇17 ~ 5xl〇18cm_3- the method of manufacturing the electrostatic discharge protection element as described in item 16 of the patent scope, Among them, the doped regions have about 〇 "~ 〇3 " between 13 ^ standard er 豕 standard (CNS) A4 specifications ⑽ MW public love) the degree of the scope of the patent application ,: = ΓΧ1 ° 19 ~ 5xl ° 'm · 3 _Nongdu. The manufacturing method of the static electricity described in item w is obtained after planting: 2: Second: The impurities contained in the crystalline sand belong to the scale explant dose, between about 40 ~ 60Kev, And the cloth 4 weight, cleverly in the range between 5x10b ~ 5xl〇1W2 down. For the production of 1921, please refer to the static electricity protection element law as described in item 14 of the patent scope, wherein the first type is the second penalty B system 20 = the static electricity as described in item 19 of the scope Discharge: protection: the connection between the pieces of H Zhuo and other lightly planted areas has about 04 ~ 06 U degrees. The junction chanting degree 'and the concentration between approximately 5xl017 ~ 5xl01w (the junction of the ESD protection element received in item 2 ° where the' concentration exchange area has about U ~. . ^, The indirect surface: degrees 'and the manufacturer of about 5xl〇 ~ 2W3 between ^ ^ 1 of the manufacturer 1 material (iv) item 2G, the static electricity protection element will be inserted into the' second polycrystalline layer These impurities are obtained by suppressing 2+ t, and the implantation energy is about 40 to 10 feet, and the line d is about 5 × 10 5 to 5 × 10w. ^ The system 2 = 1 please refer to the ESD protection element described in item 14 of the patent scope. The gate electrode: the gate pole is applied to the Chinese National Standard (CNS) A4 specification (210 X 297 public daughter) 14