TW297938B - The electrostatic discharge protection device and its manufacturing method - Google Patents
The electrostatic discharge protection device and its manufacturing method Download PDFInfo
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- TW297938B TW297938B TW85100046A TW85100046A TW297938B TW 297938 B TW297938 B TW 297938B TW 85100046 A TW85100046 A TW 85100046A TW 85100046 A TW85100046 A TW 85100046A TW 297938 B TW297938 B TW 297938B
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五、發明説明(ι ) 207938 本發明係有闢於積體電路内的保護元件,特別是有關 於~種靜電放電保護元件及其製造方法。 靜電放電(Electrostatic Discharge,通常簡稱爲ESD )應力幾乎存在於積體電路之量測、組裝、安裝及使用過 程裡,其會肇致積體電路的損壞,並間接損壞電子系統的 功能。而形成靜電放電的原因,通常是以三種模型來解釋 • (1)人體模型(human body model,HBND :這是以美軍軍 事標準 883 號方法 3015. 6(MIL-STD-883,Method 3015.6) 所界定者,係指帶靜電觸及積體電路的接腳時造成 之靜電放電應力;(2)遂直模型(machine model,MM):係 指遂^所帶靜電踫觸積體電路的接腳時所造成之靜電放電 應力,現有工業標準EIAJ-IC-121 method 20的測試方法; (3)帶電荷元件模型(charged device model,CDM):係指 一原已帶有電荷的積體電路在隨後的過程中,接觸導電物 質而接地,則經由積體電路形.成一靜電放電脈衝。 —-------- 請參照第1A和1B圖,所示分別爲輸入緩衝接合墊 (input pad)及輸出緩衝接合塾(output pad)等處靜電放電保 護電路的電路示意圖。如第1A圖所示,輸入緩衝接合垫5 處係利用一 NMOS電晶體Ml來保護内部電路6(internal circuit),NMOS電晶體Ml之閘極、源極、基體極均連接 至VSS電位,其汲極則連接至輸入緩衝接合墊5上。再者, 如第1B圖所示,輸出緩衝接合墊7處係利用一對NMOS 電晶體M2和PMOS電晶體M3保護内部電路6免於靜電放 電破壞;其中,NMOS電晶體M2和PMOS電晶體M3之 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ297公釐) (請先閲讀背面之注意事項再填寫本頁) ---------------ί I 餐------11Τ —-1 Τ— —III 丄-線 經濟部中央標準局員工消費合作社印裝 經濟部中央標準局員工消費合作社印製 A7 B7五、發明説明(2 ) 閘極均耦接至内部電路6,其汲極均連接至輸出緩衝接合 墊7,另外,NMOS電晶體M2之源極和基體極均連接至 VSS電位,PMOS電晶體M3之源極和基體極均連接至 VDD電位。 接著,請參照第2圖,所示爲習知靜電放電保護元件 製作於一半導體基底内的剖面圖。其中,圖示之左側爲一 NMOS電晶體(譬如是第1A圖,之元件Ml或第1B圖之元件 M2)的剖面圖;圖示之右側爲一 PMOS電晶體(譬如是第1B 圖之元件M3)的剖面圖。標號1依據NMOS電晶體或PMOS 電晶體的不同,可分別是形成於半導體基底内之一 P型丼 區或一 N型丼區;標號10、11爲場氧化物(field oxide), 譬如是以局部氧化法(Local Oxidation of Silicon , LOCOS)形成於基底1的既定位置上,並於場氧化物l〇和 11間定義一元件主動區(active region) 100 ;標號12爲一 閘極氧化盾;標號13爲一閘極電極層;標號14A和14B 分別是爲一渡極區(drain region)和一源極區(source region),分設於閘極電極層13兩側下方之基底1内,係經 N型或P型雜質佈植入并區1而得;標號15爲一介電層, 業經蝕刻定義出二接觸窗16和17,用以分別露出汲極區 14A和源極區14B ;再者,標號18和19爲導電層,係經 蝕刻同一鋁金屬層而得,導電層18和]9分別經由接觸窗 16和17與汲極區14A和源極區14B連接。 然若以第2圖之元件結構做爲靜電放電保護元件,當 有靜電放電的現象發生時,汲極接面因累增崩潰產生大量V. Description of the Invention (ι) 207938 The present invention is a protection element built into an integrated circuit, especially related to a variety of electrostatic discharge protection elements and methods of manufacturing the same. Electrostatic discharge (Electrostatic Discharge, usually abbreviated as ESD) stress is almost present in the measurement, assembly, installation and use of integrated circuits, which will cause damage to the integrated circuits and indirectly damage the function of the electronic system. The reason for the formation of electrostatic discharge is usually explained by three models. (1) Human body model (HBND: This is based on US Military Standard No. 883 Method 3015. 6 (MIL-STD-883, Method 3015.6). As defined, it refers to the electrostatic discharge stress caused when static electricity touches the pins of the integrated circuit; (2) machine model (MM): refers to when the static electricity comes into contact with the pin of the integrated circuit The electrostatic discharge stress caused by the existing industry standard EIAJ-IC-121 method 20 test method; (3) charged device model (charged device model (CDM): refers to an integrated circuit that has been charged before In the process of contacting a conductive substance and grounding, it will form an electrostatic discharge pulse through the integrated circuit. —-------- Please refer to Figures 1A and 1B, which show the input pads (input pad) ) And the output buffer junction (output pad) circuit schematic diagram of the electrostatic discharge protection circuit. As shown in FIG. 1A, the input buffer junction pad 5 uses an NMOS transistor Ml to protect the internal circuit 6 (internal circuit), Gate and source of NMOS transistor Ml The base electrode is connected to the VSS potential, and the drain electrode is connected to the input buffer bonding pad 5. Furthermore, as shown in FIG. 1B, the output buffer bonding pad 7 uses a pair of NMOS transistors M2 and PMOS transistors M3 protects the internal circuit 6 from electrostatic discharge damage; the paper standard of NMOS transistor M2 and PMOS transistor M3 is applicable to China National Standard (CNS) Α4 specification (210Χ297mm) (please read the precautions on the back before filling in (This page) --------------- ί I Meal ------ 11Τ —-1 Τ— —III 丄 -Line Economy Ministry Central Standards Bureau Staff Consumer Cooperative Printing and Printing Ministry Printed by the Central Standards Bureau employee consumer cooperative A7 B7 V. Description of the invention (2) The gates are all coupled to the internal circuit 6, and the drains are all connected to the output buffer bonding pad 7, in addition, the source and substrate of the NMOS transistor M2 Both electrodes are connected to the VSS potential, and the source and base electrodes of the PMOS transistor M3 are connected to the VDD potential. Next, please refer to FIG. 2, which shows a cross-sectional view of a conventional ESD protection device fabricated in a semiconductor substrate. Among them, the left side of the figure is an NMOS transistor (for example, Figure 1A, The cross-sectional view of the element M1 or the element M2) of FIG. 1B; the right side of the figure is a cross-sectional view of a PMOS transistor (for example, the element M3 of FIG. 1B). The reference number 1 depends on the difference of the NMOS transistor or the PMOS transistor , Which can be a P-type or N-type region formed in the semiconductor substrate; reference numerals 10 and 11 are field oxides, such as local oxidation method (Local Oxidation of Silicon, LOCOS) At a predetermined position of the substrate 1, an active region 100 is defined between the field oxides 10 and 11; reference number 12 is a gate oxide shield; reference number 13 is a gate electrode layer; reference numbers 14A and 14B are a drain region and a source region, which are respectively located in the substrate 1 under the two sides of the gate electrode layer 13 and are implanted through an N-type or P-type impurity cloth and Region 1 is derived; reference numeral 15 is a dielectric layer, and two contact windows 16 and 17 are defined by etching to expose the drain region 14A and the source region 14B, respectively; furthermore, reference numerals 18 and 19 are conductive layers. It is obtained by etching the same aluminum metal layer. The conductive layers 18 and 9 are respectively Regions 14A and 14B connected to the source region. However, if the device structure shown in Figure 2 is used as an ESD protection device, when the phenomenon of electrostatic discharge occurs, the drain junction will collapse and generate a lot of
In- In— nn n·^ ^n— xi^ifl--n#n n^t nf— ^ 0¾. i - Λ&, (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 經濟部中央標準局員工消費合作社印製 297938 A7 ____ B7 五、發明説明(3) 的熱集中於沒專jl柱孝緣(drain cylindrical edge)處110, 此即爲靜電放電應力發生時的辱乾(bgt spot),此些熱能會 等向散.佈(isotropically spread)造成導電廣18的銘金屬材質 因熱而融解,並擴散穿刺(spiking)汲_極接面,甚者造成没 極區14A和源極區14B的短路,使得元件遭致靜電放電破 壞。 因此,本發明之主要目的,在於提供一種靜電放電保 護,藉由源/汲極區上方形成導電區塊,使電極金屬遠 離靜電放電應力時的熱點,可避免鋁金屬穿刺接面的缺 點。 而本發明之再一目的,在於提供一種靜電放電保護元 件,呈較小接面電容値,故可減低輸入/輸出緩衝接合墊的 電容値。 _ 再者,本發明之另一目的,在於提供一種靜電放電保 護元件,其源/汲極區處設置有較深之淡掺植區,可用以降 低靜電放電電流密度,提昇元件抗靜電放電應力的能力。 而本發明尚有一目的,在於提供一種靜電放電保護元 件的製造方法,藉由已掺植之複晶續層擴散於基底内,形 成較深之淡掺植區接面,並經蝕刻定義呈導電區塊置於源/ 沒極區上方。 因此,本發明之這些目的,可藉由提供一種靜電放電 保護元件;包括:一半導體基底;一閘極結構,形成於該 底的既定位置;一源極區和一汲極區,分設於該閘極結構 兩側下方之該基底内,分別由一濃摻植區和一淡掺植區建 5 (請先閲讀背面之注意事項再填寫本頁} I裝--In- In— nn n · ^ ^ n— xi ^ ifl--n # nn ^ t nf— ^ 0¾. I-Λ &, (please read the precautions on the back before filling out this page) Standard (CNS) A4 specification (210X297 mm) Printed by the Employees Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 297938 A7 ____ B7 V. Invention description (3) The heat is concentrated at the jl column cylindrical edge 110, This is the bgt spot when the electrostatic discharge stress occurs. This heat energy will be isotropically spread. The isotropically spread causes the metal material of the conductive metal 18 to melt due to heat, and the diffusion puncture (spicking) _ The pole junction may even cause a short circuit between the electrode-less region 14A and the source region 14B, causing the device to be damaged by electrostatic discharge. Therefore, the main object of the present invention is to provide an ESD protection. By forming a conductive block above the source / drain region, the electrode metal is away from the hot spot during the electrostatic discharge stress, which can avoid the defect of the aluminum metal puncturing the junction. Yet another object of the present invention is to provide an ESD protection device with a smaller junction capacitance value, so that the capacitance value of the input / output buffer bonding pads can be reduced. _ Furthermore, another object of the present invention is to provide an ESD protection device with a deep lightly doped region at the source / drain region, which can be used to reduce the ESD current density and enhance the device resistance to ESD stress Ability. Yet another object of the present invention is to provide a method for manufacturing an electrostatic discharge protection device. By diffusing the implanted polycrystalline continuous layer into the substrate to form a deeper junction of the lightly implanted area, it is defined as conductive by etching The block is placed above the source / electrode region. Therefore, the objects of the present invention can be provided by an electrostatic discharge protection device; including: a semiconductor substrate; a gate structure formed at a predetermined position on the bottom; a source region and a drain region, which are located in The base under the two sides of the gate structure is constructed by a densely mixed planting area and a lightly mixed planting area 5 (please read the precautions on the back before filling this page)
'6T -----f ·線· 本錄尺度 -—-~~~^'6T ----- f · Line · Recording standard -—- ~~~ ^
經濟部中央標隼局員工消費合作社印裝 構而得’其中,料淡掺植區具有較該等濃㈣區深的接 面深度;一介電層,覆於該閘極結構、該源極區和該汲極 區上,並經定義成一第一接觸窗和—第二接觸窗,分別用 以露出該汲極區和該源極區;一第一電極,設置於該介電 層上方,經由該第一接觸窗耦接至該汲極區;以及一第二 電極,设置於該絕緣層上,並經由該第二接觸窗耦接至該 源極區。 而本發明之這些目的,亦可藉由提供一種靜電放電保 護元件的製造方法’包括:(a)提供_半導體基底;⑻形成 一氧化曆於該基底上,並經蚀刻定義呈二開口,露出該基 底;(C)形成一複晶矽層於該氧化層上,並經由該等開口與 該基底相接觸,其中,該複晶矽層業經雜質摻植;(d)施以 熱擴散處理,使該複晶矽内含之該等雜質擴散進入該基底 内,形成二淡掺植區於該等開口下方;蝕刻定義該複晶 矽層呈二導電區塊分別於該等淡掺植區上,同時亦蝕刻形 一閘極結構於該等導電區塊之間;⑴以該閘極結構和該等 導電區塊做罩幕,佈植離子進入該基底内,形成濃掺植區 分別於該等淡摻植區兩侧,而該等濃掺植區具有較該等淡 摻植區淺的接面深度;(g)形成一介電層覆於該基底表面, 並經蝕刻定義呈二接觸窗分別露出該等導電區塊;以及 (h)形成二電極分別經由該等接觸窗與該等導電區塊做電 性連接。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂 ,下文特舉一較佳實施例,並配合所附圖式,作詳細説明 本紙張尺度適用中國國#'樣準(CNS ) A4規格(21〇 X 297公楚) --- --------(I裝------訂-----^ .線 (請先聞讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印裝 五、發明説明() 5 } 如下: 圖示之簡單説明: 第1A和1B圖係顯示用以分別説明輸入緩衝接合墊和 輪出緩衝接合墊處靜電放電保護電路的電路示意圖; 第2圖係顯示用以説明習知靜電放電保護元件結構的 到面圖;以及 , 第3A-3E圖係顯示用以説明根據本發明一較佳實施例 的製程剖面圖。 實施例: 4參照第3A-3E圖,所示爲根據本發明一較佳實施例 的製程剖面圖。各圖示之左側爲一 NM〇s電晶體(譬如是 第1A圖之元件]νπ或第1B圖之元件M2)的剖面圖;各圖 示之右側爲一 PM0S電晶體(譬如是第1B圖之元件M3)的 剖面圖。所示爲製程中幾個關鍵的步驟,茲詳細説明如下: 首先,該參照第3A圖。提供一半導體基底3,譬如 是P型或N型之矽基底。再以離子佈植的方式,將離子佈 植進入半導體基底3内,形成一丼區30。若所需製得之 靜電放電保護元件爲NMOS元件,則丼區30爲P型丼區; 若保護元件爲PMOS,則丼區30係爲一 N型丼區。本實 施例之圖示同時示以P型丼區和N型并區於左右兩侧爲例 作説明。 再者,如第3B圖所示,以苎部氧化法(Local Oxidation of Silicon,LOCOS)形成場氧化物31、33於丼區30表 面’於場氧化物31和33間定義出元件主動區(active 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公楚;) (請先閲讀背面之注意事項再填寫本頁} -丁 _ 、-* 線Printed and constructed by the Employee Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs. Among them, the lightly mixed planting area has a deeper junction depth than the concentrated area; Region and the drain region, and is defined as a first contact window and a second contact window, respectively, to expose the drain region and the source region; a first electrode is disposed above the dielectric layer, Coupled to the drain region through the first contact window; and a second electrode disposed on the insulating layer and coupled to the source region through the second contact window. And these objects of the present invention can also be provided by providing a method of manufacturing an electrostatic discharge protection device 'including: (a) providing a semiconductor substrate; ⑻ forming an oxide calendar on the substrate, and defining two openings by etching, exposing The substrate; (C) forming a polycrystalline silicon layer on the oxide layer and contacting the substrate through the openings, wherein the polycrystalline silicon layer is doped with impurities; (d) is subjected to thermal diffusion treatment, The impurities contained in the polycrystalline silicon diffuse into the substrate to form two lightly doped regions under the openings; etching defines the polycrystalline silicon layer as two conductive blocks on the lightly doped regions respectively At the same time, a gate structure is also etched between the conductive blocks; (1) The gate structure and the conductive blocks are used as masks to implant ions into the substrate to form densely doped regions respectively Both sides of the lightly doped region, and the thickly doped region has a shallower junction depth than the lightly doped region; (g) forming a dielectric layer overlying the surface of the substrate and defining two contacts by etching The windows respectively expose the conductive blocks; and (h) form two electrodes Make electrical connection with the conductive blocks through the contact windows, respectively. In order to make the above-mentioned objects, features, and advantages of the present invention more obvious and understandable, a preferred embodiment is described below in conjunction with the attached drawings to explain in detail that this paper standard is applicable to China ## 样 准 (CNS) A4 specification (21〇X 297 Gongchu) --- -------- (I installed ------ ordered ----- ^. Line (please read the notes on the back before filling in This page) Printed by the Employees ’Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention () 5} The following: A brief description of the diagram: Figures 1A and 1B show the input buffer joint pad and wheel-out buffer joint pad, respectively. Circuit schematic diagram of an electrostatic discharge protection circuit; FIG. 2 is a schematic diagram illustrating the structure of a conventional electrostatic discharge protection device; and FIGS. 3A-3E are diagrams illustrating a preferred embodiment according to the present invention. Process cross-sectional view. Embodiment: 4 Refer to FIGS. 3A-3E, which shows a process cross-sectional view according to a preferred embodiment of the present invention. The left side of each drawing is an NMOS transistor (such as FIG. 1A) Element] νπ or element M2) of Figure 1B; a right side of each figure is a PMOS transistor (for example The cross-sectional view of the device M3) in FIG. 1B. The key steps in the manufacturing process are shown below. The details are as follows: First, refer to FIG. 3A. Provide a semiconductor substrate 3, such as P-type or N-type silicon Substrate. Ion implantation is then used to implant ions into the semiconductor substrate 3 to form a dongle region 30. If the ESD protection device to be fabricated is an NMOS device, the dongle region 30 is a P-type dongle region; If the protection element is a PMOS, the donated area 30 is an N-type donated area. The illustration in this embodiment shows both the P-type donated area and the N-shaped parallel area on the left and right sides as an example. As shown in FIG. 3B, the field oxides 31 and 33 are formed on the surface of the dome area 30 by the local oxidation of silicon (LOCOS). The active area of the device is defined between the field oxides 31 and 33. China National Standard (CNS) A4 specification (210X297 Gongchu;) (Please read the precautions on the back before filling this page}-丁 _ 、-* 线
經濟部中央標隼局員工消費合作社印製 ,同時亦做爲與其它轉間的絕緣結構。 化物Μ、33的材質大抵是由氧化矽物構成。 然後,對井區30表面施以熱氧化處理,於未被場氧化 物31 ' 33覆蓋處形成一薄氧化層34。後續以化學氣相沈 積法(CVD)形成—薄複晶料35於薄氧化看34上。一第 一光阻層36再塗佈於薄複晶秒層3S上,經光學微影術 (ph〇t〇Hth〇graphy)定義呈二開口 3〇2和3〇4。再以第—光 阻層=做罩幕,沿開口 3〇2和3〇4依序蝕刻薄複晶矽層% 和薄氧化層34,露出丼區30 ,即得如第3C圖所示之剖面 結構。而上述薄複晶矽層35係用以遮蔽薄氧化層34免於 污染之用。 、 接著,去除第一光阻層36後,以化學氣相沈積法形成 複明秒層37於薄複晶妙層35上,並經由開口 302和304 與并區30相接觸。然此複晶矽層37業經高濃度雜質摻植 其内,譬如井區30若爲p型丼區,則此複晶矽層37可施 以磷離子之N型雜質佈植,其佈植能量 約介於40〜60KeV 間’而佈植劑量約介於5xl0is〜5xl0i6cm-2之間的範圍; 若丼區30爲N型并區,則複晶矽層37可施以BF2+離子之 P型雜質佈植,於佈植能量约介於4〇〜60KeV間,以及佈 植劑量約介於5χ1015〜5xl016crrT2間的範園行之。此佈植 步躁可利用形成p型丼區或N型丼區時之同一光罩施行 之。後續施以一熱擴散處理,使複晶矽層37内含之雜質, 沿開口 302和304的範圍擴散進入丼區30内,分1別形成淡 ί參植區38 即得第3D圖所示之剖面結構。若複晶矽 8 本紙張尺度適用標準(CNS) A4規格γ^χ297公產) I 《—裝------·訂L-----^ ,線 -·* (請先閱讀背面之注意事項再填寫本頁)Printed by the Employee Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs and also used as an insulating structure from other transfers. The material of the compounds M and 33 is probably composed of silicon oxide. Then, the surface of the well 30 is thermally oxidized to form a thin oxide layer 34 where it is not covered by the field oxide 31'33. Subsequent chemical vapor deposition (CVD) is used to form the thin polycrystalline material 35 on the thin oxide film 34. A first photoresist layer 36 is re-coated on the thin polymorphic second layer 3S, which is defined as two openings 30 2 and 30 4 by photolithography. Then, using the first photoresist layer as a mask, the thin polycrystalline silicon layer and the thin oxide layer 34 are etched in sequence along the openings 30 2 and 30 4 to expose the donated area 30, that is, the cross-sectional structure shown in FIG. 3C . The thin polycrystalline silicon layer 35 is used to shield the thin oxide layer 34 from contamination. Then, after the first photoresist layer 36 is removed, the phostomeric second layer 37 is formed on the thin polycrystalline layer 35 by chemical vapor deposition, and is in contact with the merged region 30 through the openings 302 and 304. However, the polycrystalline silicon layer 37 is implanted with high-concentration impurities, for example, if the well region 30 is a p-type dongle region, the polycrystalline silicon layer 37 can be implanted with N-type impurities of phosphorus ions, and its implantation energy Approximately between 40 ~ 60KeV 'and the implantation dose is approximately in the range of 5xl0is ~ 5xl0i6cm-2; if the area 30 is an N-type parallel area, the polycrystalline silicon layer 37 can be applied with P-type impurities of BF2 + ions For planting, Fan Yuan with a planting energy of about 40 ~ 60KeV and a planting dose of about 5 × 1015 ~ 5xl016crrT2. This implantation step can be performed using the same mask when forming the p-type or N-type scallop area. Subsequent application of a thermal diffusion process allows impurities contained in the polycrystalline silicon layer 37 to diffuse into the area 30 along the range of the openings 302 and 304, and form the light-seeding area 38 separately, as shown in FIG. 3D Of the cross-sectional structure. If the polysilicon 8 paper standard is applicable (CNS) A4 specification γ ^ χ297 public product) I "—installed ------ · order L ----- ^, line-** (please read the back side first (Notes and then fill this page)
層37内含N型雜質,則淡掺植區38和39之接面深度約介 於0.4〜0.6μιη之間,而濃度約介於5χ1〇17〜5xl〇18cm_3 之間;若複晶矽層37内含P型雜質,則淡摻植區38和39 之接面冰度約介於〇·4〜〇.6μηι之間,而濃度約介於5xl〇i7 〜5xl018cnT3 之間。 經濟部中央梯準局員工消費合作社印製 再者,塗饰一第二光阻層4〇於複晶矽層37上,並經 光學微影術定義圖案覆於淡掺植區38和39上方之部份複 晶矽層37上,同時,亦用以定義呀辞的位置。再以第二光 阻層40做革幕,飯一閘極電極層y,J1 時~,变皂鲜刻得導電覆炎達^和39 ▲,分设於閘極電極層5〇兩側;在此同時,薄複晶矽層 35和薄氧化層34亦予以蝕刻,其中,閘極電極層5〇與其 所覆蓋之薄複晶碎層35同爲複晶矽材質構成,故僅以同一 電極層表又,而閘極電極層5〇下方遮蔽之薄氧化層34, 則做爲一 1¾趣走皇屋^然後^服和導電區塊 動.對集,根據 NM〇s 或 pM〇s 棄 位置分別施以N型或p型缚質佈植入并區%内,形成疼举 ’分設衿淡摻植區38和39兩側。若濃摻植 區44、45爲>^型’則其接面深度約介於〇1〜〇 3叫間 =深度’以及具有約介於5xl〇19〜5xl〇2〇cm-3間的濃度; 若濃摻植區44、45爲P型,則其接面深度約介於〇2〜 〇·4μπι間’以及具有約介於5χ1〇19〜5xi〇2〇cm 3間的濃度 範園。即得如第3E ®所示之剖面結構。其中,濃摻植g 隻整得一靜電放貧保護元件的汲極區二 -..................................... " ^張尺度猶關家 --------f I —----^--IT------f 威----- (請先閱讀背面之注意事項再填寫本頁) A7 A7 經濟部中央樣準局員工消費合作社印褽 五、發明説明(8) 而濃摻植區45和淡摻植區39建構得一靜電放電保護元件 的源極择。 後續沈積一介電層51覆於整個基底表面,並經光學微 影和蚀刻程序,呈二接觸窗(contact Wind0w)4w47,分 別露出導電區塊42和43。再沈積一金屬層(譬如是鋁) 48和第二電極 49 ;其中,第一電極48經由接觸窗46與導電區塊42相接 觸’並連接至第!圖所示之線路7上;而第二電極4 接觸窗47與導電區塊43相連連接至孤。第5e 即爲根據本發明一較佳實施例的結構剖面圖示> 、综上所述,本發明分別利用疼星植^濃^^併合 得之結構建構得沒極區、和源極區,而淡挣植區較之濃捧植 區具有較深的接面深度,如是於靜電放電應力發生時減 靜電放電的31#,用以分散其所產㈣熱^況且淡 摻植區的濃ϋ低,故呈較小的接面電容値,間接亦降^ 接舍塾處的再者,由於淡掺植區上方具有(導良、 區塊〜,使遠離靜電放電應力發生時的熱點,g 防止電極金屬因熱融解穿刺接面的缺點。 雖然本發明已以較佳實施例揭露如上,然其並非用以 限定本發明,任何熟習此項技藝者,在不脱離本發明之精 神和範圍内,當可作些許之更動與潤飾,因此本發明之^ 護範圍當視後附之申請專利範圍所界定者爲準。 本纸張尺度適用中國國家標準(CNS)a^."( 210~297^« )' --------f I淋衣I - (請先閱讀背面之注意事項再填寫本頁) :、!! 線·The layer 37 contains N-type impurities, the junction depth of the lightly doped regions 38 and 39 is between 0.4 ~ 0.6μιη, and the concentration is between 5 × 1017 ~ 5x1018cm_3; if the polycrystalline silicon layer 37 contains P-type impurities, the lightness of the junction of the lightly planted areas 38 and 39 is about 0.4 ~ 0.6μηι, and the concentration is about 5xl〇i7 ~ 5xl018cnT3. Printed by the Employee Consumer Cooperative of the Central Bureau of Economic Development of the Ministry of Economic Affairs, coated with a second photoresist layer 40 on the polycrystalline silicon layer 37, and overlaid on the lightly doped areas 38 and 39 by a pattern defined by optical lithography Part of the polycrystalline silicon layer 37 is also used to define the position of the word. Then use the second photoresist layer 40 as a leather curtain. When a gate electrode layer y, J1 ~, the soap is freshly engraved to obtain conductive coatings up to 39 and ▲, which are located on both sides of the gate electrode layer 50; At the same time, the thin polycrystalline silicon layer 35 and the thin oxide layer 34 are also etched. Among them, the gate electrode layer 50 and the thin polycrystalline crushed layer 35 covered by the same are made of polycrystalline silicon material, so only the same electrode layer surface, and The thin oxide layer 34 shielded under the gate electrode layer 50 is used as a 1⁄2 fun walking royal house ^ then ^ and the conductive block moves. For the set, according to the NM〇s or pM〇s abandoned positions are given N Type or p-type binding cloth is implanted in the merged area, forming a painful move. It is divided into two sides 38 and 39. If the densely planted areas 44, 45 are> ^ type ', the junction depth is approximately between 〇1 ~ 〇3 called between = depth' and has between about 5xl〇19 ~ 5xl〇2〇cm-3 Concentration; If the densely planted areas 44, 45 are P-type, the junction depth is approximately between 〇2 ~ 〇.4μπι 'and the concentration range between about 5χ1〇19 ~ 5xi〇2〇cm 3 . The cross-sectional structure shown in Section 3E ® is obtained. Among them, the dense mixed plant g only makes one the drain region of the electrostatic depletion protection element 2 -.................................... ........ " ^ Zhang Shijie still closes the family -------- f I —---- ^-IT ------ f Wei ----- (please Read the precautions on the back first and then fill out this page) A7 A7 The Central Sample Bureau of the Ministry of Economic Affairs Employee Consumer Cooperative Prints the Fifth, Invention Description (8) The concentrated planting area 45 and the light mixing planting area 39 construct an electrostatic discharge protection element Source selection. Subsequently, a dielectric layer 51 is deposited over the entire substrate surface, and through optical lithography and etching procedures, two contact windows (contact Wind0w) 4w47 are formed, exposing the conductive blocks 42 and 43, respectively. Then deposit a metal layer (such as aluminum) 48 and a second electrode 49; wherein, the first electrode 48 is in contact with the conductive block 42 via the contact window 46 and connected to the first! The circuit 7 shown in the figure is connected to the contact window 47 of the second electrode 4 and the conductive block 43, and is connected to the isolation. Section 5e is a cross-sectional view of the structure according to a preferred embodiment of the present invention. In summary, the present invention constructs the non-polar region and the source region by using the combined structure of pain star plant ^ thick ^^ The lightly planted area has a deeper junction depth than the concentrated planted area, such as 31 #, which reduces electrostatic discharge when electrostatic discharge stress occurs, to disperse the heat generated by the plant and lightly blend the concentrated area ϋ is low, so it shows a small junction capacitance value, and it also indirectly decreases ^ In addition, at the place where the planting area is located, due to the presence of (conductive good, block ~ above the lightly mixed planting area, it is far away from the hot spot when electrostatic discharge stress occurs, g Prevent the shortcomings of the electrode metal due to thermal melting to puncture the joint. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone who is familiar with this skill will not deviate from the spirit and Within the scope, some changes and modifications can be made, so the scope of protection of the present invention shall be as defined in the scope of the attached patent application. This paper standard is applicable to the Chinese National Standard (CNS) a ^. &Quot; ( 210 ~ 297 ^ «) '-------- f I shower coat I-(Please read the notes on the back first Items and then Complete this page):, Line !!
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TW85100046A TW297938B (en) | 1996-01-04 | 1996-01-04 | The electrostatic discharge protection device and its manufacturing method |
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TW85100046A TW297938B (en) | 1996-01-04 | 1996-01-04 | The electrostatic discharge protection device and its manufacturing method |
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