TW297901B - Floating gate memory array - Google Patents

Abstract

A semiconductor memory array, which is applicable to one memory device, and in the memory array one specified memory cell position is determined by decoded row address from row address decoder and decoded column address from column address decoder, comprises of: (1) multiple bit lines connected to column address decoder; (2) multiple word lines connected to row address decoder; (3) multiple first-type source lines connected to row address decoder; (4) multiple memory units, each memory unit has one source or drain connected to one bit line, one gate connected to one word line, and one drain or source connected to one source line; (5) at least one second-type source line arranged to be close to one first-type source line, in which of second-type source line has lower resistance than the first-type's, and one predetermined position of second-type source line in array is connected to one first-type source line.

Description

Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. A7 ______B7_ V. Description of the Invention (I) Field of Invention This invention relates to semiconductor memory devices, in particular to semiconductor memory devices containing floating gate memory arrays. BACKGROUND OF THE INVENTION Floating gate memory devices that are programmed using hot electron injection and erased using Fowler-Nordheim tunneling are well known to everyone and are described in detail in US Patent Nos. 5,029,13 0 and 5,289,41 1. FIG. 1 shows a floating gate memory array device 10 disclosed in U.S. Patent No. 5,289,411. The device 10 includes an array 40 of floating gate memory cells 42. The device 10 also includes an input register 12 to receive the input data to be stored, a sense amplifier 16 to amplify the data signal read by the array 40, and an output register 14 to receive the output from the sense amplifier 16 Read the data signal. A row address decoder 18 receives the row address and generates an address signal on the row address line 26. A column address decoder 20 receives the column address and generates an address signal on the column address line 24. Each column address line 24 is connected to a column decoding circuit 50. The column decoding circuit 50 also receives the column selection line 30 output by a column selection decoder I9. The output of the column decoding circuit 50 is a plurality of column lines 36. A pair of floating gate memory cells 42 are provided at the intersection of each column line 36 and row address line 26. The device 10 further includes a high voltage source 22 to provide the high voltage required for programming and erasing operations. The high voltage is supplied to multiple high-voltage decoders 60, and each high-voltage decoder 60 is received by a high-voltage paper. The paper standard is applicable to the Chinese National Standard (CNS) Α4 specification (2 丨 0> < 297mm). --Subscribe η ------ line (please read the notes on the back before filling in this page) Printed by the Employees and Consumers Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 297301 A7 ___B7_ V. Description of Invention (L) Column Selection Decoder 21 The three high-voltage selection signals on the output line 34, the output of the high-voltage decoder 60 is also connected to the column line 36 output by the corresponding column decoding circuit 50. The operation of the floating gate memory array device 10 is as follows. To write data to the floating gate memory cell 42 on a specific column, the Vcc voltage is applied to the selected column address line 24. The column decoding circuit 50 outputs the threshold voltage Vt to the first column line 36-1 on this particular column, and is applied to the floating gate memory cell 42 on this particular column. The source isolation transistor 44 does not turn on due to the voltage Vt. A voltage of about 12 volts generated by the high voltage source 22 is applied to the second column line (or N + source line) 36-2 via the output of the high voltage decoder 60. Depending on the data to be programmed, the row address line 26 and the drain of the memory cell 42 are led to 0 volts or +5 volts to program the memory cell 42 on the particular column that is enabled. The hot electrons at the source of the specific floating gate memory cell 42 are thus injected and stored in the floating gate electrode of the floating gate memory cell 42. The data stored in the floating gate memory cell on a specific row can be read in a conventional manner. An example is described as follows: A voltage of 0 (ground) is introduced into the source of the floating gate memory cell to be read, a reading voltage of about 2 volts is introduced into the drain, and a voltage of +5 volts is introduced into the gate. This will generate a signal representing the stored charge, which is amplified by the sense amplifier 16 and applied to the output register 14. To erase the floating gate memory unit 42 stored on a particular row of the array 40 Data, the column address line 24 of this column is enabled, and the column selection decoder 19 outputs a signal to the column decoding circuit 50 so that it is connected (please read the precautions on the back before filling this page)-install.,?! Line 2 This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) A7 printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs —___ B7 V. Description of invention (J) Connected to the source isolation transistor 44 of this column The first column line 36-1 of the gate maintains a high voltage, while the second column line 36_2 and the third column line 36-3 maintain a voltage of 0, so the source isolation transistor 44 is turned on, so that the second column line (Or N + source line) 3ό_2 is connected to the common ground line 32. Therefore, the first column line 36-1 is connected to the high voltage output by the high voltage source 22 through the column decoding circuit 50, thus supplying a voltage of about 5 volts to the gate of each floating gate memory unit 42 on the specific column . Then the row address line 20 connected to the drain of each floating gate memory cell 42 on that particular column is pulled to a voltage of 0, and the source isolation transistor 44 (which connects the N + source line 36-2 and the common ground line 32) The source of each floating gate memory cell 42 on that particular column is also pulled to zero voltage. Due to the Fowler-Nordheim tunneling effect, the high voltage applied to the gate of the floating gate memory cell 42 causes the charge stored in the floating gate memory cell 42 to be removed. A floating gate memory array device 10 of the prior art in FIG. 1 has multiple problems. For example, the array 40 uses multiple source isolation transistors 44 to isolate 12 volts (used to program a particular floating gate memory cell 42) to prevent 12 volts from being applied to other floating gate memory cells in the array. Although the use of source isolation transistor 44 as source isolation can reduce the interference during programming, it also reduces the reading current through the floating gate memory cell, thus reducing the reading performance of the array device 10 The programming current output by the device 60 passes through the entire length of the N + source line 36-2 (typically a high-resistance N + diffusion material). The programming current causes a considerable voltage drop on the source line 36-2, so Reduce programming efficiency and performance. And the source isolation transistor 3 (please read the precautions on the back before filling in this page). Installation · -1 ° line · This paper standard is applicable to China National Standard (CNS) Α4 specification (210Χ297 mm) Central Bureau of Standards of the Ministry of Economic Affairs Employee Consumer Cooperative Printed Bag A7 ____B7 5. Description of Invention (+) Body 44 must occupy wafer space, resulting in an increase in the size of the memory array device 10. Another problem is that, during reading, the voltage of Vcc-Vt is directly applied to the gate of each floating gate memory cell 42 on a particular column via the column line 36-1 and / or column line 36-2, All floating gate memory cells 42 on this particular row are therefore stressed by the high Vcc voltage. Furthermore, when the supply voltage increases or is disturbed during reading, due to the Fowler-Nordheim tunneling effect, the charge originally stored in the floating gate memory cell 42 will be caused by the floating gate The electrode is removed ^ From the above description, it is obvious that there is an improved floating gate memory array, which has enhanced programming and reading performance and can eliminate the source isolation transistor and the prior art Other problems. SUMMARY OF THE INVENTION This invention provides an enhanced performance floating gate memory array that shows more programming and reading performance than previous technologies; according to a specific embodiment proposed, a floating gate memory array There is no need to add source isolation transistors on the character lines of the memory array. According to an embodiment of the invention, a memory array is used in the memory device. The location of a memory unit in the memory array is determined by the column address and row address decoders. The memory unit may be a floating gate memory The cell data can be injected into it using a heat carrier, and erased using the Fowler-Nordheim dangerous penetration effect. 4 This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) ----- 1 J ------. ^. (Please read the precautions on the back before filling in this page) Ministry of Economic Affairs A7 _____B7_ printed by the Staff Consumer Cooperative of the Bureau of Standards V. Description of the invention (5) This array contains a bit line connected to the row address decoder, the character line is connected to the column address decoder, and the N + diffusion source line is connected to Column address decoder. Each memory cell has a gate connected to the word line, a drain connected to the bit line, and a source connected to the N + diffused source line. A low-resistance source line (made of metal Π or conductive material) is arranged close to each N + diffused source line, and is electrically connected with a connecting strip at multiple locations. This low-resistance source line reduces the voltage drop on the N + diffusion source line during programming and provides a smaller ground resistance during reading. Another feature of this invention is related to the organization of a page. There are two similar word lines (here even and odd word lines) to form a basic programming unit, and any unit interference during programming It is limited to cells connected to two word lines that are close together. The cells in the remaining non-programmed pages in the array are largely unaffected by the programming. The unit connected to the basic programming unit is erased together during the erase operation. Another feature of this invention is a word line clamp circuit, which can be used to reduce read interference (due to the increase in the Vcc voltage during reading Caused by or changes.> The word line clamp circuit limits the maximum voltage applied to the word line during the reading operation. The immunity of the gate interference due to Vcc changes is therefore enhanced. These and other advantages and features of this invention , Will be more clear due to the following detailed description and accompanying drawings. Brief description of the drawings (please read the precautions on the back before filling in this page)-Binding · Order 5 This paper size is applicable to China National Standard (CNS) A4 Specification (210X297mm)

A7 B7 5. Description of the invention () Figure 1 shows a memory device including a floating gate memory array made in accordance with the prior art. Figure 2 shows a memory device including a floating gate memory array made in accordance with this invention. FIG. 3 shows an exemplary column decoder suitable for the memory device of FIG. 2. FIG. FIG. 4 shows an exemplary high voltage coder suitable for the memory device of FIG. 2. FIG. FIG. 5 shows an exemplary source ground circuit suitable for the memory device of FIG. 2. FIG. FIG. 6 shows an exemplary word line clamping circuit suitable for the memory device of FIG. 2; FIG. 7 discloses an exemplary circuit that generates ZPO and ZP1 signals by the ZSUPPLY signal. Detailed description of the invention This invention will be combined with an exemplary The memory device of the floating gate semiconductor is described as follows. Nevertheless, it must be understood that this invention does not limit a particular type of device or memory unit. On the contrary, this invention can be more widely applied to any semiconductor device whose apparent resistance is an important consideration. Moreover, although this invention is suitable for use in floating gate memory devices, it can also provide significant benefits in other applications. FIG. 2 shows an exemplary floating gate memory array device 100 according to this invention. The device 100 includes an array 40 of floating gate memory cells 42. The device 100 also includes an input register 112, an output register 114, a sense amplifier y This paper standard is applicable to the Chinese National Standard (CNS) Α4 specification (210X297 mm) ^ n · i — ^ n 1 ^ 1 ϋ m (please read the precautions on the back before filling out this page). Ordered by the Ministry of Economic Affairs Central Standards Bureau Employee Consumer Cooperation Du Printed 297901 Printed by the Ministry of Economic Affairs Central Standards Bureau Employee Consumer Cooperative A7 B7 V. Invention Instructions (7) 116 The row address decoder 118 ′ has a column selection decoder 119, a column address decoder 120, a high voltage column selection decoder 121, and a high voltage source 122. These components operate in the manner described above with FIG. 1. For the detailed description of the operation of these components, refer to U.S. Patent Nos. 5,289,411 and 5,029,130. The device 100 also includes a (M + 1) x (P + 1) floating gate memory array 140, which contains a plurality of floating gate memory cells CijA and CijB, where 1 = 0, 1, 2, ... , ^ 1 represents the row address of a specific floating gate memory cell, and j = 〇, 1, 2, ..., P represents the row address of a specific floating gate memory cell. In the specific embodiment illustrated in FIG. 2, any column M of the array 140 includes an even word line WL (M > and an odd word line WL (M + 1), it should be noted that the odd word line WL (M + 1 > and the next column, (M + 1) column, the even word line is different. The even word line WL (M) of the column M is connected to the gate of the memory cell CMjA, the odd character line of the column M The line WL (M) is connected to the gate of the memory cell CMjB. Any row j of the array 140 includes a bit line BL (j) connected to the floating gate memory cells CijA and CijB of row j Drain. The position of each floating gate memory cell of the array 140 is specified by the intersection of the word line WL and the bit line BL. Any column M of the array 140 further includes a source line SL (i) and a The metal source line MSL (i >, both the source line SL (i) and the metal source line MSL (i) pass horizontally through the array 140. Each of the floating gate memory cells CijA and CijB on the ji The source electrodes are all connected to the source line SL (i). The source line SL (1) can be formed by the N + diffusion region. The metal source line MSL (i > is generally arranged to be in even and odd character lines. Scale applies to Chinese countries Standard (CNS) Α4 specifications (210X297mm) --------- 1 clothing-- (Please read the precautions on the back before filling this page)

, 1T line, the Ministry of Economic Affairs, Central Standards Bureau, Employee Consumer Cooperative, A7 B7. V. Description of the invention (§ :) The source line SL (i) is parallel, and can be composed of the metal II area or the second metallization layer in the array 140 Pose. MSL (i) and SL (i) use conductive strips to connect at multiple points in the array 140. The conductive strips can be formed and used by metal II, such as the double poly double metal (DPDM) program. connection. MSL (i) is therefore used to reduce the voltage drop of the traditional N + diffused source line SL (i). The size of the metal source line) is approximately 3.3 microns wide and 9.9 microns long. ] ^ 81 ^ (〇 Can be placed on the N + diffusion source line SL (i), other lower resistance conductive materials can also be used as MSL ⑴, these optional materials include polycrystals (polycide), sand (Silicide), or a metal layer different from metal II. Each memory cell CijA and CijB can be a floating gate memory cell, they can use hot electron injection (hot electron injection) to burn, and use Fowler -Nordheim erases with the wear-through effect. The operation of these floating gate memory cells is a well-known technique and is described in detail in US Patent Nos. 5,029,130. FIG. 3 shows a memory array 140 suitable for FIG. 2 The illustrated column decoder 1 50-i. The column address decoder 120 receives a column address as an input, and decodes the column address to generate a plurality of pre-decoded column address signals XPi, each of which is decoded via 124-i The decoded column address signal XPi is input to the corresponding column decoder 150-i, and each column decoder 150-i via line 130 also receives three other signals 2? 0, 2? 1 sent from the column selection decoder 119 , And 2〇0. Signal 2 卩 0, ZP1 ZG0 can be generated by the column selection decoder 119 or other. The paper size is applicable to the Chinese National Standard (CNS) Α4 specification (210Χ297mm> 0¾ (please read the precautions on the back before filling this page) r Γ A7 B7 5. Invention Description (,) As described in US Patent No. 5,289,41, an appropriate circuit is generated. An example circuit for generating ZPO and ZP1 signals using the ZSUPPLY signal will be described with the following FIG. 7. A specific pre-decoding The column address signal XPi is directly applied to the gates of M1, M3, and M5, and is input to an inverter INV1. INV1 outputs the inverted value of XPi to the gates of M2, M4, and M6. The crystal can be a P- or N-channel metal-oxide-semiconductor field effect transistor. The column selection signals ZP0, ZP1, and ZG0 generated by the column selection decoder 119 are applied to the drains of M1, M3, and M5, respectively. The output of the decoder 150-i is the even word line WL (i), the odd word line WL (i + 1) and the metal source line MSL (i). During reading, each column decoder 150-i The output MSL (i) will be led to the ground potential, and only one odd or even word line will be selected by XPi For example, if XPi is logically high, the even word line WL (i) is connected to the signal ZP0 through Ml. As shown in FIG. 7, the signal ZP0 can be generated by the ZSUPPLY signal. The same as the character line clamp circuit described. The voltage connected to the even word line WL (i) is ZP0 minus the critical voltage Vt of M1. The voltage connected to the odd word line WL (i + 1) via M3 is ZP1 (zero potential during reading). During programming, the even word line WL (i) and the odd word line WL (i + l) are also the same selection method, except that the ZSUPPLY voltage is changed to +2 volts, which is suitable for the floating gate that stores charge in the memory cell Extremely. During programming, if the metal source line MSL (i) of Figure 3 is transformed into a logic high potential XPi selected, then MSL (i) is connected to ZGO via M5. In this case, the paper size of the signal is applicable to China National Standard (CNS) A4 specification (210X297mm) (please read the notes on the back before filling in this page). Pack. Printed by the Ministry of Economic Affairs Central Standards Bureau Employee Consumption Cooperation Du Printed by the Ministry of Economic Affairs Central Standards Bureau Beigong Consumer Cooperative Printed System A7-_! Z_ V. Description of the invention (丨 σ) ZGO may be connected to the supply voltage Vcc. During the erasing period, XPi is a logic high level, and WL (1) and Wl (i + 1) are added to ZPO via Ml, M3, and M5, and ZP1, ZP0 ', and ZP1 are both ZSUPPLY voltages (during erasing Equal to Vcc). Therefore, WL (i) and Wl (i + 1> will be approximately equal to Vcc-Vt »MSL (i) connected to ZGO via M5 (equal to 0 during erasing). Figure 4 shows a memory array suitable for Figure 2 An exemplary high-voltage encoder 160-i of 140. Each high-voltage encoder 160-i is connected to the metal source line MSL and odd and even word lines WL corresponding to the corresponding Η, as shown in the column decoder 150 of FIG. The output of i. The high voltage encoder 160-i receives the SG and SGND generated by the source ground circuit 205 described below and FIG. 5. The high voltage decoder 160-i also receives the SHV and WLHVO generated by the high voltage selective decoder 121 And WLHVE. The high voltage selective decoder 121 can be made using techniques such as those described in US Patent No. 5,289,411. A high voltage coupler 200 couples a high voltage generated by the high voltage source 122 to the selected word line and source Polar line (selected by column decoder 150 · ί and high voltage selection decoder 121). During reading, M10 provides another current path, thus improving reading performance (this point will be explained below). Figure 5 shows a suitable diagram 2. An example source ground circuit of the memory device 2 of 5. The circuit 20 5 receives a Input signal PROG (logic high level during programming). When PROG is high level, M16 receives 0 potential output from inverter INV2, so it is off. M15 receives signal PROG sent from INV3 and turns on. Via M15, signal SGND Therefore, the logic high potential is introduced, and the paper standard of the inverter is in accordance with the Chinese National Standard (CNS> A4 specification (210X: 297 mm). 10 packs -----. 彳 定 ------- line (please first Read the precautions on the back and fill in this page) A7 ____B7_ printed by the Employees ’Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs 5. Invention Description (丨 丨) The output SG of INV4 is a logic low potential, and the output signals SG and SGND are added to the ones in FIG. 4 High-voltage decoder 1 60-i input, and connected to the gate and source of M10 in decoder 160-i, M10 in high-voltage decoder 160-i is therefore cut off, and the drain of M10 will be imported Logic high level, this structure also enhances the punch-through voltage of M10. During the reading and erasing operations, the signal PROG is a logic low level, which causes M15 to turn off and M16 to turn on, and then the signal SG becomes a high potential. And the signal SGND becomes low potential, making The M10 in the high-voltage decoder 160-i is turned on, and the metal source line MSL (i) is connected to the ground potential through M10 and M16. This structure provides another ground path during reading, which will enhance the reading performance. FIG. 6 shows an exemplary word line clamp circuit 210 suitable for the memory device of FIG. 2. The circuit 210 receives the signals PROG, VPWL, and CLAMP0FF generated by an appropriate memory control circuit (not shown). The circuit 210 generates an output signal ZSUPPLY and adds it to the Z-decoder circuit (Z_DEC) 215 shown in FIG. 7, The Z-DEC circuit 215 uses the inverter INV7 and the transistors M2 and M24 to generate the signals ZP0 and ZP1. Then, the signals ZP0 and ZP1 are added to the column decoder 150_i of FIG. 3 as their inputs. The Z-DEC circuit 215 may be combined with the column selection decoder 119 or the word line clamp circuit 210. The operation of the word line clamp circuit 210 of FIG. 6 will be described in more detail below. During programming, the signals PROG and CLAMPOFF are logic high, and the signal VPWL is about +2 volts, so M18 is turned on by PROG, and M19 is output by the inverter INV6. The paper size is applicable to China National Standard (CNS) A4 specifications (210X297mm) ^ -----.— J ------ 0 (Please read the notes on the back before filling out this page) A7 B7 printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs

Fifth, the invention description (丨 2J CLAMPOFF is reversed and ends; the output signal ZSUPPLY is therefore connected to a signal VPWL of approximately +2 volts, and the output signal ZSUPPLY is supplied to the Z-DEC circuit 2 15 shown in FIG. 7 and through this Added to the inputs ZPO and ZP1 of the column decoder 150-i of Fig. 3. During reading, PROG and CLAMPOFF are logic low and M18 is off, M19 and M20 are on, and the supply voltage Vcc is clamped to become the signal ZSUPPLY. The collapse voltage of the nano-diode ZD1 and the resistance of the resistor R1 determine the clamping voltage of the output signal ZSUPPLY. The appropriate breakdown voltage of the ZD1 and the resistance of R1 are 4 volts and lk ohms respectively. Of course, these values can depend on the application. Change. During erasing, PROG is low and CLAMPOFF is high, which causes M18 and M20 to turn off and M19 to turn on. Therefore, through M19 and R1, the unclamped supply voltage Vcc becomes the output signal ZSUPPLY. Memory array device in FIG. 2 The operation will be described in more detail below. Table 1 below excerpts the voltages applied to the terminals of an exemplary memory cell during erase, write, and read operations. The voltages listed are for a US Patent No. 5,029,130 is a cell of the type described. For a cell of this type, the drain of each cell C ^ jA and CijB is connected to the bit line BL (1), the source of each cell CijA and CijB The poles are connected to the source line SL (i), the gate of each cell Cij A is connected to the even word line WL (i), and the gate of each cell CijB is connected to the odd word line WL (i + l) The source of each cell CijA and CijB is also connected to the metal source line MSL (i) by the conductive tape 180. Other types of memory cells can use different connections to the bit line, word line, and source line 12 This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) Approved clothing 1 ^ ------- line (please read the precautions on the back before filling this page) Employee consumption of the Central Standards Bureau of the Ministry of Economic Affairs A7 ____B7 __ printed by the cooperative. V. Description of invention (β) connection, you can also add different voltages during erasing, programming and reading operations. Operation Drain gate source programming 0.6v / 5v Vt + 12V erase 0V + 15V 0V read + 2V + 5V ον Table 1 An erase operation is performed as follows. According to this invention In a specific embodiment, the memory cell Cij A of the array 140 is divided into multiple pages, and each page includes some cells CijA connected to an even word line WL (i) and some connected to an odd word line WL (i + 1) The cell CijB. The smallest erasing unit is a single page, and the contents of all cells on the odd and even character lines of a particular column are erased together. When erasing a specific column, the column decoder 150-i receives a high-level pre-decoded address signal XPi, and enables the corresponding pair of odd and even word lines through the circuit of FIG. 3, and corresponds to the other The word line of the column decoder is maintained in an inactive state. The high voltage source 122 generates the +15 volt potential required for the erase operation. The high voltage selection decoder 121 enables WLHVO and WLHVE but not SHV, and the source ground circuit 205 of FIG. 5 enables the signal SG to be logic high Potential, and connect SGND to ground potential through Ml 6, these signals are connected to the high voltage decoder 160-i 'of FIG. 4 and work together to make M10, M12 and M13 turn on and turn off Mil. The + I5 volt potential generated by the high-voltage source 122 is therefore applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) through the high-voltage paper standard ----- —I II-— ^ 1--. —II--- --·-—II I--. -..... 、 一 -0JJ!!-1---ί-ill (Please read the precautions on the back before filling out this page) Central Standards of the Ministry of Economic Affairs The bureau employee consumer cooperation du printed A7 —_______ B7_ V. Description of invention (丨 p) The coupler 200 and M12, Ml 3 are added to the selected odd and even character line pairs. The corresponding source line MSL (i) is connected to the ground potential through M10 of FIG. 4 and M16 of FIG. 5. Via the source line SL (i) and the metal source line MSL (i), the source of the cell Cij of the page to be erased is connected to the ground potential, via the even word line WL (i) and the odd word line WL ( i + l) The gate of cell Cij is connected to the +15 volt potential, and the bit line BL (j) in row address decoder 118 is also connected to ground potential, so that the drain of cell Cij is connected to ground potential and added at The voltage at each terminal fully meets the erasing conditions in Table 1. Therefore, the cell Cij of the page to be erased is erased due to the Fowler-Nordheim tunneling effect, so that the charge originally stored in the floating gate is shifted. Except (as detailed in US Patent No. 5,029,130 mentioned above). The character lines and source lines of the unselected pages are connected to the ground potential through M2, M4, and M6 in the corresponding column decoder 150-i, and the drain and source of the cell Cij of the unselected pages The pole and gate will be connected to ground potential, which will not cause any interference to the charge originally stored in it. A programming operation can be carried out according to the steps described below. Similarly, in this specific embodiment, the memory cell CijA of the memory array 140 is divided into multiple pages, and each page includes some connected to an even word line WL ( i) Cell Cij A and some cells CijB connected to an odd word line WL (i + 1). The smallest programming unit is a single page. When programming a specific page, the column decoder 15〇-i receives a high potential pre-decoding address signal XPi and enables the corresponding pair through the circuit of FIG. 3 Odd and even character lines and source lines, and corresponding to 14 (please read the notes on the back before filling in this page)-Packing and binding This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) A7 297901 _____B7 V. Description of the invention (j7) The character line and source line to other column decoders are kept in the inoperative state. The even word line WL (i> is connected to the signal ZPO via Ml, the odd word line is connected to the signal ZP1 via M3, and the source line MSL (i) is connected to the signal ZGO via M5. The high voltage source 122 is generated for programming operation The required +12 volt potential, the high-voltage selective decoder 121 enables SHV, but does not enable WLHVO and WLHVE, and the source ground circuit 205 of FIG. 5 drives the signal SG to a logic low level, and connects SGND to MGND via M15 Vcc, these signals are connected to the high voltage decoder 160-i of FIG. 4 and work together to turn off M10, M12, and M13 and turn on Mil. The +12 volt potential generated by the high voltage source 122 is thus applied to the high voltage coupler 200 and Mil The selected source line MSL (i), even and odd word pair (pair) are connected to the ZPO and ZP1 signals relative to the output signal ZSUPPLY of the word line clamp circuit of Figure 6. As mentioned before, burn The ZSUPPLY corresponding signal VPWL during writing, via M1 and M3 in FIG. 3, causes the potential of the Vt series to be connected to the even and odd word lines. The potential of Vt is about +2 volts. The cell Cij of the page to be written The source is connected to the +12 volt potential output by the high voltage source via source line SL (i) and metal source line MSL (i), The gate of cell Cij is connected to the Vt potential through the even word line WL (i > and odd word line WL (i + 1), in response to the programming data sent from the input register 112, the row address decoder 118 controls the bit Element line BL (j), in order to write the required data value into the cell Cij; if you want to program logic 1 data bit, the corresponding cell bit line BL (j) is set to 5 volts, if you want to program The bit line BL (j) of the unit corresponding to the write logic 〇 data bit 'is set to 0.6 volts, so that the unit originally exists due to erasure. This paper standard applies the Chinese National Standard (CNS) Α4 specification (210Χ297 mm) ( Please read the precautions on the back first and then fill out this page)-installed.-· Printed by the Ministry of Economic Affairs, Central Bureau of Standards and Staff Employee Consumer Cooperatives Printed by the Ministry of Economic Affairs, Central Bureau of Standards, Employee Consumer Cooperatives A7 ___ B7 ^ ___ V. Description of Invention ((L ) The logic 0 value remains unchanged. The voltage applied to each terminal fully meets the programming conditions in Table 1, so the cell Cij of the page to be programmed is moved into the charge to the floating gate due to the hot electron injection effect ( As previously mentioned 11.8.? &Amp; 161 ^] ^ 〇.5,02 9,13 0 detailed description). Not selected The word line and source line of the page are connected to the ground potential through M2, M4, and M6 in their corresponding column decoders 15〇-i. During programming, the various bias conditions of the memory cell Cij of the array 140 are summarized as follows: 1. The selected page, character line and line and the burned data is 〇

Drain pole = 0.6 V

Wenji = 2 V Source = 12 V 2. The selected page, character line and line and the data written is 1

Drain = 5 V Gate = 2V Source = 12V 3. Selected page, character line and unselected row

Drain = 5V Gate = 2V Source = 12V 4. The selected page, the other character lines and the selected row and the programming data is 〇

Drain = 0.6V Gate = 0V Source = 12V 5. The selected page, other character lines and selected rows and the programming data is 1

Drain pole 2 5V gate = 0V source = 12V 6. The selected page, other character lines and unselected line paper size are in accordance with Chinese National Standard (CNS) Α4 specification (210X297mm) Read the contents on the back of the page and fill in the actual copy. Ir Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Α7 Β7 5. Invention Description Ο7) Drain = 5V Gate = OV Source = 12V 7. Unselected pages , The other character lines and the selected lines and the burned data is 〇 Drain = 〇. 6 V 閛 极 = OV source = 0V 8. Unselected pages, other character lines and selected The data written and programmed is I Drain = 5V Gate = 0V Source = 0V 9. Unselected pages, other character lines and unselected Row and Pole drain drain = 5V = ον = ον It can be seen from the above bias condition that the programming interference in the memory array 140 of this invention is generally limited to the cell Cij in the selected page; the cell Cij bias condition in the unselected pages makes the original The charge stored in it is generally not disturbed by the operation of page selection by being burned. Table 1 indicates that the read operation is performed by applying a voltage of +2 volts to the drain of the cell Cij of the selected page via the bit line BL (j), and borrowing the even word line WL (i > and the odd word line WL (i + l) Add a voltage of +5 volts to the gate, and add the ground potential to the source via the source line SL (i) and the metal source line MSL (1). These voltages are provided as described above for erasing and burning The writing action is the same. ZSUPPLY is connected to the even and odd character lines via M1 and M3 in Figure 3, and as mentioned before, it is shown in Figure 6 < r ^^^ 1 n ^ i ^^^^ 1 v ^ v— nn ml ^^^^ 1 fluv 1 ^ 1 OJ1 ^ 1 ^ 1 In— (please read the precautions on the back before filling in this page) This paper size is applicable to China National Standard (CNS) Α4 specification (210Χ297 Mm) A7 B7 V. Description of the invention (丨 &) The word line clamp circuit 210 is clamped, and the memory array 140 of this invention is less likely to feel the turbulence of the gate electrode during the reading operation. The body device directly adds Vcc-Vt to the gate of the selected unit, so when Vcc increases or changes, it is likely to cause the moving edge of the gate in the array. (Please read the precautions on the back before filling this page)- β Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs This paper scale applies the Chinese National Standard (CNS) Α4 specification (210Χ29 ·; mm)

Claims (1)

A8 B8 C8 D8々 printed by the Ministry of Economic Affairs Employee Consumer Cooperative of the Ministry of Economic Affairs, patent application Vine® 1. A 1-conductor memory array, which is used in a memory device, a specific memory cell location in the memory array It is determined by the column address decoder decoding the column address and the row address decoder decoding the row address. The array includes: a plurality of bit lines connected to the row address decoder; a plurality of word lines, which Connected to the column address decoder; multiple source lines of the first type, which are connected to the column address decoder;. Multiple memory cells, each memory cell has a source or drain connected to a certain bit Element line, each memory cell has a gate connected to a word line, and each memory cell has a drain or source connected to a source line; at least one source line of the second type is arranged adjacent to One source line of the first type, the source line of the second type has a smaller resistance value than the source line of the first type, the source line of the second type is in the array Some predetermined positions in the are connected to a source line of the first type . 2. The array as described in item 1 of the patent application, where the memory cell is a floating gate memory cell, the data is written using hot carrier injection, and the erase is using the Fowler-Nordlieim dangerous penetration effect. 3. The array as described in item 1 of the patent application, where the first type of source line is composed of N + diffused source lines. 4. The array as described in item 1 of the patent application scope, wherein at least one source line of the second type is made of metal. 5. The array as described in item 1 of the scope of patent application, of which the second type is 297901 (please read the precautions on the back and then fill out this page)-installed · —. The size of the silk paper is based on the national standard of China (CNS) A4 specification (210X297mm) 19 6. Patent application A8 At least one source line in the C8 D8 state is formed in the metal π metallization layer of the semiconductor device. 6. The array as described in item 1 of the patent application scope, which further includes a plurality of source lines of the second type, each source line of the second type has a corresponding and adjacent first type Type source lines, and make electrical connections at predetermined points. 7. The array as described in item 1 of the patent application, where multiple word lines further include interleaved even word lines and odd word lines, and a basic programming page in the memory array includes a pair of adjacent pairs And odd character line. 8. As for the array described in item 7 of the patent application scope, during erasing, a page composed of adjacent even and odd word lines is erased at substantially the same time. 9. The array as described in item 8 of the patent application, wherein the memory device further includes a word line clamp circuit, which can be connected to at least one line of the word line during reading, , And therefore will be applied in the reading action. 10. (Please read the precautions on the back before filling in this page)-Binding I The maximum voltage of the character line printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs is limited. A method in a semiconductor memory array device. The memory array device includes multiple bit lines, multiple word lines, multiple source lines of the first type, multiple memory cells, each Each memory cell has a source or drain connected to a certain bit line, each memory cell has a gate connected to a certain word line, and each memory cell has a drain or source connected to a certain source line This method includes the following steps: Place at least one source line of the second type adjacent to one of the multiple source lines of the first type. The source line of the second type is more suitable than China for the first 2SL silk paper size. National Standards (CNS) A4 specification (210X297mm) Printed by the Ministry of Economic Affairs Central Standards Bureau Beigong Consumer Cooperative A8 B8 C8 D8 VI. The scope of the patent application type source line has a small resistance value; and some in the array The predetermined position connects the source line of the second type and the source line of the plurality of source lines of the first type. 11. The method as described in item 10 of the patent application, where the memory cell is a floating gate memory cell, the data is written using hot carriers, and the erasing is using the Fowler-Nordheim tunneling effect. 12. The method as described in item 10 of the patent application, wherein the first type of source line is composed of N + diffused source lines. 13. The method as described in item 10 of the patent application scope, in which at least one source line of the second type is made of metal. 14. The method according to item 10 of the patent application scope, wherein at least one source line of the second type is formed in the metal II metallization layer of the semiconductor device. 15. The method as described in item 10 of the patent application scope, wherein the step of arranging a source line of the second type further includes arranging a plurality of source lines of the second type, such that each second type The source line has a corresponding first type source line adjacent to it. 16. The method as described in item 10 of the patent application range, in which multiple word lines further include interleaved even word lines and odd word lines, and a basic programming page unit in the memory array includes a pair of phases The adjacent even and odd character lines. 17. The method as described in item 16 of the patent application scope, which further includes a step of erasing adjacent even and odd character lines at substantially the same time. 18. The method described in item I6 of the scope of patent application is also included in the reading (please read the precautions on the back before filling in this page) -install · T set silk 21 This paper standard adopts the Chinese National Standard (CNS) A4 specification (21〇 < 297mm) A8 B8 C8 D8 printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. The patent application scope is to connect the output of the character line clamp circuit to multiple character lines during the application period. One line step, thus limiting the maximum voltage applied to the memory t gate during the read operation. Conductor memory array, including: multiple bit lines; multiple word lines; multiple source lines of the first type; multiple memory cells, each of which has a source or drain connected to a certain line Bit line, each memory cell has a gate connected to a word line, and each memory cell has a drain or source connected to a source line; at least one source line of the second type is connected to A source line of the first type is adjacent, the source line of the second type has a smaller resistance value than the source line of the first type, and the source line of the second type is in the array. The predetermined position is connected to a source line of a first type. 20. The array of claim 19, wherein the source line of the first type is composed of N + diffused source lines, and at least one source line of the second type is composed of Made of metal. (Please read the precautions on the back before filling in this page) -Installation- -I Order 銶 This paper size is suitable for China National Standard (CNS) A4 (210X297mm) 22