JP2601971B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and, more particularly, to a nonvolatile semiconductor memory device which focuses on data erasing in an electrically rewritable nonvolatile semiconductor memory.

[0002]

2. Description of the Related Art An EEPROM (Electric) capable of electrically erasing stored data and rewriting new data.
cally Erasable and Program
mmable Read Only Memory)
Can be erased by an electric signal while being mounted or incorporated on a board. For this reason, the demand for control, IC card (memory card) and the like is rapidly increasing due to its ease of use.

Conventionally, an EEPROM suitable for increasing the capacity
There is known a memory cell structure as shown in FIGS. FIG. 9 is a plan view of a memory cell pattern, and FIG.
0 is a sectional view taken along the line AA 'in FIG. 9, and FIG.
FIG. 12 is a sectional view taken along a line, and FIG.

As shown in these figures, a P-type substrate 13
A gate oxide film 18 having a thickness of about 100 angstroms is formed on a region surrounded by the field oxide film 20 formed thereon. With the gate oxide film 18 interposed therebetween, the first layer floating gate 11 made of polycrystalline silicon is formed. On this floating gate 11, a control gate 12 made of a second layer of polycrystalline silicon is formed via an insulating film 19. The insulating film 19 is made of, for example, O
-NO-structure (Oxide-Nitride-Oxid)
e) has a three-layer structure, and its thickness is about 200 angstroms in terms of an oxide film. Control gate 12
Are used as word lines of this memory cell. An insulating layer 21 is provided on the control gate 12.

Further, the floating gate 11 and the control gate 1
A source 14 and a drain 15 made of an N ⁺ -type diffusion layer are formed on the P-type substrate 13 on both sides of the substrate 2. A contact hole 16 is opened in a region of the insulating layer 21 corresponding to the drain 15. A data line 17 made of an aluminum layer is connected to the drain 15 via the contact hole 16.

As a result of configuring the memory cell as described above, a functional configuration as shown in an equivalent circuit diagram of FIG. 12 can be realized. In FIG. 12, D is a drain 15,
S corresponds to the source 14, and CG corresponds to the control gate 12, respectively.

The operation of the above configuration will now be described.

First, when erasing data, the source 1
For example, 12 volts is applied as an erasing voltage to 4, the drain 15 is floated, and the control gate 12 is set to 0
Bolts. Thus, a relatively high erase voltage is applied between the floating gate 11 and the source 14 via the thin gate oxide film 18. Due to the Fowler-Nordheim tunnel effect, electrons in the floating gate 11
Will be released. As a result, data is erased.

On the other hand, when writing data, about 6 volts is applied to the drain 15, 0 volts to the source 14, and 12 volts to the control gate 12, respectively. as a result,
Impact ionization occurs near the drain 15, electrons are injected into the floating gate 11, and data is written.

When reading data, the drain 15 is set at 1 volt, the source 14 is set at 0 volt, and the control gate 1 is set at 1 volt.
2 is 5 volts. Thus, data “0” or “1” is obtained depending on the presence or absence of electrons in the floating gate 11.

FIG. 13 is a circuit diagram of a conventional semiconductor memory device using the memory cell having the above-described configuration. In particular, a flash type EEPROM having a byte configuration having an output of 8 bits is illustrated.

[0012] As shown in FIG.
They are arranged in a matrix of m rows and n columns. The sources of these memory cells 30 are commonly connected to a terminal SS. The control gates of the memory cells 30 are connected to the row lines WL1 to WLm for each row. The drain of the memory cell 30 is connected to column lines DL1 to DLn for each column.

The terminal SS is connected to an external high-voltage power supply terminal V
Source voltage control circuit 3 to which high voltage is supplied from pp
7 is connected. Row lines WL1 to WLm are connected to row decoder 31. The column lines DL1 to DLn are connected to common connection points N-1 to N-8 via enhancement-type column selection transistors 33-1 to 33-n. The column selection transistors 33-1 to 33-n are
The outputs of the column selection lines CL1 to CLn connected to are connected as gate inputs.

A common connection point N-1 to N-8 and an external high voltage power supply terminal V to which a high voltage is applied at the time of writing and erasing data.
pp are connected to write-in enhancement type load transistors 34-1 to 34-8. The gates of these load transistors 34-1 to 34-8 have:
Write data control circuits 35-1 to 35-8 to which write data Din * 1 to Din * 8 are input from external terminals.
, The write data NDin * 1 to NDin * 8 (/ means an inverted signal) are input.

Further, a row decoder 31 and a column decoder 32
Is supplied with the output SW of the high voltage switching circuit 36. The circuit 36 is supplied with a high voltage from an external high voltage power supply terminal Vpp.

At the common connection points N-1 to N-8, sense amplifiers 38-1 to 38-8 for reading data including load transistors for reading data are provided. Output circuits 39-1 to 39- for outputting data to external terminals are provided to the sense amplifiers 38-1 to 38-8.
8 are respectively connected.

In the source voltage control circuit 37, the erase signal Erase is supplied to the P-type transistor 37 connected in series.
A and are input to the gates of the N-type transistor 37B. P
The output of the commonly connected drain of the N-type transistor 37A and the N-type transistor 37B is
Of the P-type transistor 37D and the gate of the N-type transistor 37E connected in series through the drain to the source of the N-type transistor 37D. The commonly connected drains of the P-type transistor 37D and the N-type transistor 37E are connected to the terminal SS and to the gate of the P-type transistor 37F. The drain of the P-type transistor 37F is connected to the gates of the P-type transistor 37D and the P-type transistor 37A. The source of the P-type transistor 37A and the gate of the N-type transistor 37C are connected to a power supply. Each source of the P-type transistor 37F and the P-type transistor 37D is connected to the external high-voltage power supply terminal Vpp.

Next, the operation of the above configuration will be described.

First, at the time of writing data, 12 volts is supplied to the external high voltage power supply terminal Vpp. When 12 V is applied to the external high-voltage power supply terminal Vpp, 12 V is output to the output SW from the high-voltage switching circuit 36 and supplied to the column decoder 32 and the row decoder 31. Simultaneously, one memory cell 30 for each output bit, that is, one memory cell for each of eight output bits, is provided by column selection lines CL1 to CLn and row lines WL1 to WLm selected by an address signal (not shown). Cell 30
Are selected in total.

Here, a selected one of the row lines WL1 to WLm, for example, 12 volts is applied to the row line WL1 and a selected one of the column selection lines CL1 to CLn,
For example, assume that 12 volts is applied to the column selection line CL1.

Here, the write data Din * 1 to Din
When * 8 is "0", the write data control circuits 35-1 to 35-1 to which a high voltage is applied from the external high voltage power supply terminal Vpp
35-8 is the write data / Din * 1 to / Din * 8
Output about 9 volts. As a result, the load transistors 34-1 to 34-8 are turned on. As a result, the load transistors 34-1 to 34-8 and the column selection transistors 33-1 to 33-1 are respectively connected from the external high-voltage power supply terminal Vpp.
A voltage of about 6 volts is applied to a selected one of the column lines DL1 to DLn via 33-n. Thereby, data is written to corresponding memory cell 30. On the other hand, when the write data Din * 1 to Din * 8 are “1”, the write data / Din * 1 to / Din *
8 becomes 0 volt, and the load transistors 34-1 to 34
-8 turns off. As a result, no voltage is applied to the drain of the selected memory cell 30 and no data is written.

When erasing data, a high voltage of about 12 volts is supplied to the terminal SS from the external high voltage power supply terminal Vpp via the source voltage control circuit 37, and the column selection lines CL1 to CLn and the row line WL1 are supplied. To WLm are all 0 volts. Thereby, all the memory cells 30 are collectively erased.

In this case, the source voltage control circuit 37
Is given an erasing signal Erase. However, the P-type transistor 37A is turned off and the N-type transistor 37B is turned on by the erase signal Erase. Therefore, the P-type transistor 37D is turned on through the N-type transistor 37C, and
The type transistor 37E is turned off. Thus, the external high-voltage power supply terminal Vpp is output to the terminal SS.
At the same time, the gate of the P-type transistor 37F also becomes the external high-voltage power supply terminal Vpp. Therefore, the P-type transistor 37F is off.

When reading data, the load transistors 34-1 to 34-8 for writing data are always turned off, and the output SW output from the high voltage switching circuit 36 is output.
Also becomes 5 V which is the Vcc voltage. The data “1” or “0” of the memory cell 30 selected by the column decoder 32 and the row decoder 31 is applied to the sense amplifiers 38-1 to 38-38.
The signal is sensed and amplified at -8, and output to an external output terminal through output circuits 39-1 to 39-8.

[0025]

As described above, the conventional semiconductor memory device is configured to apply the external high voltage power supply terminal Vpp through the source voltage control circuit 37 when erasing data. Therefore, there is a problem as described below.

FIG. 14 is a waveform diagram showing the operation of each unit when data is erased. FIG. 14A shows the erase signal Eras.
FIG. 4B shows the waveform of the voltage output from the terminal SS with respect to e, and FIG. 4B shows the tunnel current characteristics when a bias is applied to the source of each transistor of the memory cell 30.
Indicates load characteristics of the P-type transistor 37D of the source voltage control circuit 37, respectively.

As shown in FIG. 14A, when the mode becomes the data erasing mode and the erasing signal Erase becomes "1",
The high voltage supplied from the source voltage control circuit 37 to the terminal SS sharply rises to 12 volts. This rise time is less than 1 microsecond.

At the time of erasing data, 0 volt is applied to the control gate of the memory cell 30, the drain is made floating, and the source is supplied with the erasing voltage from the source voltage control circuit 37. However, the tunnel current I of the transistor of the memory cell 30 changes as shown in FIG. 14B with respect to the source voltage Vs. That is, the memory cell 30
When electrons are injected into the floating gate of the transistor and the state is negative, a band-to-band tunnel current flows at a source voltage lower by that voltage. This corresponds to the line T in FIG.
As shown in FIG. At this time, when the band-to-band tunnel current flows by ₁ ampere, electrons are extracted from the floating gate at the intersection Q between the load line R and the line T of the P-type transistor 37D.

As the erasing progresses, the potential of the floating gate rises. Therefore, the interband current gradually disappears, and the operating point becomes 12 volts from the point Q through the line P.

However, if the current flows due to factors other than the leak current, for example, a breakdown current before the source voltage becomes 12 volts, the source voltage does not increase any more and the tunnel current stops. There is.

That is, if the source voltage of the memory cell 30 rises sharply at the time of erasing data, an interband current will flow and the erasing characteristics will be degraded.

An object of the present invention is to solve the above-mentioned problems of the prior art. In providing an erase voltage of a source of a memory cell capable of erasing and rewriting data, a rise time of the erase voltage is controlled, An object of the present invention is to improve the erase characteristics of a memory cell by increasing the voltage stepwise.

[0033]

A first semiconductor memory device according to the present invention is a memory cell having a floating gate and capable of electrically writing and erasing data. A memory cell array in which a plurality of memory cells are arranged, a decoder for selecting a specific memory cell in the memory cell array, and a memory for erasing data in the memory cell. Erasing voltage applying means for supplying an erasing source voltage having a controlled rise time from a low voltage to a high voltage to a source of the cell. In the second semiconductor memory device of the present invention, the erase voltage applying means controls the rise time of the erase source voltage in such a manner that no inter-band current flows even when the erase source voltage rises. Are configured as things.

According to a third semiconductor memory device of the present invention, in the first or second device, the erasing voltage applying means may include:
The time from the low voltage to the high voltage is set to about 1 second or more.

In a fourth semiconductor memory device according to the present invention, in the first to third devices, the erasing voltage applying means makes the rising from the low voltage to the high voltage analog. It is configured as something.

In a fifth semiconductor memory device according to the present invention, in the first to third devices, the erasing voltage applying means may include:
The rise from the low voltage to the high voltage is configured as a digital one.

In a sixth semiconductor memory device of the present invention, in the fifth device, the erasing voltage applying means may arbitrarily set a first rising voltage value from the low voltage to a rising voltage of a first stage. It is configured as one that can be set.

[0038]

When the data is erased, the source of the memory cell is
The erase voltage applying means applies an erase voltage that changes with time from a low voltage to a high voltage. Thereby, erasing is performed properly, and deterioration of the memory cells is prevented.

[0039]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a main part circuit diagram of a semiconductor memory device according to one embodiment of the present invention. In particular, the source voltage control circuit 3
7 is shown. Other circuits are the same as those in FIG. 13, and the configuration of the memory cell is shown in FIGS.
Is the same as that shown in FIG.

As shown in FIG. 1, the erase signal Erase
Is once input to the booster circuit 8 and then supplied to the terminal SS through the output circuit 9.

In the booster circuit 8, the erase signal Erase
Is input to the gate of the N-type transistor 8B and to the inverter 8C. The output of inverter 8C is provided to the gate of N-type transistor 8E. The drain of the N-type transistor 8B is connected to the P-type transistor 8A.
Connected to the drain of The drain of the N-type transistor 8B is connected to the P-type transistor 8D and the N-type transistor 8H.
And each gate of the N-type transistor 8Q. N
The drain of the P-type transistor 8E is
It is connected to the gate of A, the gate of N-type transistor 8F, and the drain of P-type transistor 8D. The drain of N-type transistor 8F is connected to the source of P-type transistor 8G and the source of N-type transistor 8I. The drain of the P-type transistor 8G is connected to the N-type transistor 8H.
Connected to the drain of The oscillation signal OSC is supplied to the inverter 8K. The input terminal of inverter 8K is connected to the source of N-type transistor 8I via capacitor 8L. The output of the inverter 8K is a capacitor 8M
Is connected to the drain of the N-type transistor 8I. The drain of the N-type transistor 8I is connected to the source of the N-type transistor 8J. N-type transistor 8I
Is connected to the source of the N-type transistor 8I, and the gate of the N-type transistor 8J is connected to the source of the N-type transistor 8J. N-type transistor 8N, N-type transistor 80, P-type transistor 8P and N-type transistor 8Q are connected in series. N-type transistor 8N
Are supplied with an external high-voltage power supply terminal Vpp. The gate of N-type transistor 8N is connected to its source. The gate of the N-type transistor 80 is also connected to its source. The gate of the P-type transistor 8P is also connected to its source. A connection point between the source of the N-type transistor 80 and the source of the P-type transistor 8P is connected to the drain of the N-type transistor 8J and the output circuit 9. Source of P-type transistor 8A, P
An external high-voltage power supply terminal Vpp is supplied to the source of the type transistor 8D and the drain of the N-type transistor 8F, respectively. The power supply Vcc is supplied to each of the gate of the P-type transistor 8G and the gate of the P-type transistor 8P.

In the output circuit 9, the signal from the booster circuit 8 is applied to the gate of the N-type transistor 9C and the source of the P-type transistor 9A. P-type transistor 9A
Is supplied to the gate of N-type transistor 9D via inverter 9B. N-type transistor 9C
And the drain of the N-type transistor 9D are both connected to the terminal SS. The external high-voltage power supply terminal Vpp is connected to the drain of the N-type transistor 9C.
Power source Vcc is connected to the source of P-type transistor 9A.

The transistors indicated by symbols such as 8I in FIG. 1 are transistors having a threshold voltage close to 0V.

Next, the operation of the above-described configuration will be described with reference to the waveform diagram of FIG.

Now, when the erase signal Erase rises from "0" to "1", the N-type transistor 8B turns on and the N-type transistor 8E turns off. As a result, the P-type transistor 8A turns off and the P-type transistor 8D turns on. As a result, the N-type transistor 8F is turned on,
The type transistor 8H and the N-type transistor 8Q are turned off. As a result, the source of the N-type transistor 8I becomes “1”. The oscillation signal OSC is given to the N-type transistor 8I and the N-type transistor 8J via the inverter 8K. Therefore, they are turned on alternately. By the action of the capacitors 8L and 8M, the signal of "1" is transmitted to the N-type transistor 8I and the N-type transistor 8M.
Propagating gradually through J. The “1” signal is converted by the N-type transistor 8N, the N-type transistor 80, and the transistor 8P into a voltage that gradually increases to the voltage of the external high-voltage power supply terminal Vpp, and is output to the output circuit 9. The output circuit 9 applies this voltage to the gate of the N-type transistor 9C, and outputs the voltage to the P-type transistor 9A.
And to the gate of the N-type transistor 9D via the inverter 9B. Therefore, the N-type transistor 9D is turned off, and the voltage of the N-type transistor 9C gradually increases in accordance with the gate voltage.

As a result of the above operation, as shown in the waveform diagram of FIG. 2, the voltage of the terminal SS does not rise immediately even when the erase signal Erase rises, but gradually rises to the external level over a certain period of time. The voltage is increased to 12 volts at the voltage power supply terminal Vpp. This time is set to a time of 1 microsecond or more. For this reason, no voltage is applied to the memory cell 30 such that an inter-band current flows instantaneously. Therefore, the erasing operation is performed at a low voltage, and the erasing characteristics can be greatly improved.
Further, since a large inter-band current does not flow, deterioration of a gate oxide film as thin as about 100 Å can be prevented.

In the above embodiment, the N-type transistor 8
The rise time can be set arbitrarily by adjusting the characteristics of the N, N-type transistor 80 and the P-type transistor 8P.

FIG. 3 is a main part circuit diagram of a semiconductor memory device according to another embodiment of the present invention. That is, a portion of the source voltage control circuit 37 is extracted and shown. Also in this example, as in the case of FIG. 1, the other circuit configuration is the same as that of FIG. 13, and the configuration of the memory cell is shown in FIGS.
0, the same as those shown in FIG.

As shown in FIG. 13, the erase signal Erase
Is input to the delay circuit 7B via the inverter 7A. The output of delay circuit 7B is output to node R through inverters 7C and 7D. Erasure signal E
The signal at the node R is supplied to the NAND circuit 7E, and the output thereof is taken out as a signal HEED through an inverter 70. On the other hand, the erase signal Erase inverted by the inverter 7A is extracted as the signal HEEB. Signals HEEB and HEED are output from NOR circuit 7F to the gate of N-type transistor 7K and inverter 7H via inverter 7G. The output of inverter 7H is output to the gate of N-type transistor 7L. The drain of the N-type transistor 7K has P
Drain of P-type transistor 7I and P-type transistor 7J
Are connected. The drain of N-type transistor 7L is connected to the drain of P-type transistor 7J and the gate of P-type transistor 7I. P-type transistor 7
J and the drain of the N-type transistor 7L are output to the gate of the P-type transistor 7N. On the other hand, the signal HEED
Is also input to the gate of the N-type transistor 7M. The signal HEEB is also input to the gate of the N-type transistor 7P. The source of the N-type transistor 7M and the drain of the N-type transistor 7P are both connected to the terminal SS together with the drain of the P-type transistor 7N. P
The sources of the p-type transistor 7I, the p-type transistor 7J and the p-type transistor 7N are connected to an external high-voltage power supply terminal Vp
and the drain of the N-type transistor 7M is connected to the power supply Vcc. The power supply Vcc is lower than the external high voltage power supply terminal Vpp having a voltage of about 12 volts, for example, 5 volts.

Next, the operation of the above configuration will be described with reference to the timing chart of FIG. 4 and the waveform chart of FIG. 4A shows the erase signal Erase, FIG. 4B shows the state of the node R, and FIG. 4C shows the signal HEE.
D, FIG. 4D shows the signal HEEB, and FIG.
Respectively.

Now, the erase signal Erase rises between time t0 and time t2. At this time, as shown in FIG. 4D, the inverter 7 to which the erase signal Erase is input is input.
The signal HEEB which is the output of A is changed from time t0 to time t2.
Is "0" between the two. The inverted signal of the erase signal Erase is delayed by the delay circuit 7B. Therefore, the state of the node R connected to the output via the inverters 7C and 7D becomes a signal that falls at time t1, as shown in FIG. 4B. In the NAND circuit 7E, the NOR condition of the erase signal Erase and the signal of the node R is taken,
This is inverted by the inverter 70. As a result, FIG.
As shown in (C), a signal HEED which becomes "1" between time t0 and time t1 is obtained.

The signals HEED and HEEB obtained as described above are applied to the NOR circuit 7F. Thereby, between the time t1 and the time t2, via the inverter 7G,
“0” is input to the gate of the N-type transistor 7K, and “1” is input to the gate of the N-type transistor 7L via the inverter 7H. As a result, the N-type transistor 7K turns off, the N-type transistor 7L turns on,
The P-type transistor 7I is turned on, and the P-type transistor 7J is turned off. Thereby, the node S connected to the drains of the P-type transistor 7J and the N-type transistor 7L is
As shown in FIG. 4 (E), it becomes “0” from time t1 to time t2. And this signal is applied to the P-type transistor 7
Input to N gate. Thereby, the P-type transistor 7N is turned on during this time.

On the other hand, signal HEED is also supplied to the gate of N-type transistor 7M. As a result, the N-type transistor 7M is turned on from time t0 to time t1. Signal HEEB is applied to the gate of N-type transistor 7P. Thereby, the N-type transistor 7
P is turned off from time t0 to time t2.

That is, when the erase signal Erase is in the "0" state, the signal HEEB and the node S are in the "1" state, and the signal HEED is in the "0" state.
S is a ground level. On the other hand, the erase signal Erase
Rises at time t0, the signal HEED goes to the delay circuit 7
It becomes “1” during the time set in B, that is, between time t0 and time t1. As a result, the N-type transistor 7M having the gate input of the signal HEED is turned on during this time, and charges the terminal SS to the level of (Vcc-Vth). afterwards,
The node S is "0" from time t1 to time t2. As a result, the P-type transistor 7N is turned on, and the terminal SS is set to the level of the external high-voltage power supply terminal Vpp.

As a result of the above operation, as shown in FIG. 5, a relatively low (Vcc-Vth) level voltage is output to the terminal SS between the time t0 and the time t1,
Between time t1 and time t2, the external high voltage power supply terminal Vpp which is a high voltage is output. As a result, a high voltage is applied to the terminal SS step by step. As a result, in the memory cell 30 to which the erasing voltage from the terminal SS is applied to the source, a voltage that causes an instantaneous interband current is not applied. Therefore, the erasing operation is performed at a low voltage, and the erasing characteristics can be greatly improved.

FIG. 6 is a main part circuit diagram of a semiconductor memory device according to still another embodiment of the present invention, in which a portion of a source voltage control circuit 37 is extracted and shown. In this example, as before,
Other circuit configurations are the same as those in FIG. 12, and the configurations of the memory cells are the same as those shown in FIGS. 9, 10, and 11.

As shown in FIG. 6, signal HEED is applied to the gate of N-type transistor 7V and to the gate of N-type transistor 7W via inverter 7X. The drain of N-type transistor 7V is connected to the drain of P-type transistor 7Q and the gate of P-type transistor 7R. The drain of the N-type transistor 7W is
Drain of P-type transistor 7R and P-type transistor 7
Connected to the gate of Q. The drain of the N-type transistor 7V is further input to the gate of the P-type transistor 7S. The P-type transistor 7S is an N-type transistor 7T,
A series circuit is configured together with the N-type transistor 7U.
Drain of N-type transistor 7T and N-type transistor 7
The source of U is connected to the N-type transistor 7 through the node Q.
Connected to the gate of M. An external high-voltage power supply terminal Vpp is connected to each source of the P-type transistor 7Q, the P-type transistor 7R, the P-type transistor 7I, the P-type transistor 7J, the P-type transistor 7S, and the P-type transistor 7N. The external high-voltage power supply terminal Vpp is also connected to the drain of the N-type transistor 7M. The other configuration is substantially the same as the configuration in FIG. 3 except that the gate voltage of the N-type transistor 7M is set to an arbitrary intermediate voltage determined by the gm ratio between the transistors 7T and 7U and applied.

The operation of the configuration shown in FIG.
Will be described with reference to the timing chart of FIG. 7A shows the erase signal Erase, FIG. 7B shows the state of the node R, FIG. 7C shows the state of the signal HEED, FIG. 7D shows the state of the signal HEEB, and FIG. Each is shown.

Now, during the period from time t0 to time t1, the signal H
The EED becomes "1", the gate of the N-type transistor 7V is set to "1", and the gate of the N-type transistor 7W is set to "0" via the inverter 7X. As a result, the P-type transistor 7Q is turned on, the P-type transistor 7R is turned off, and at the same time, the P-type transistor 7S is turned on, and the voltage of the external high-voltage power supply terminal Vpp is applied to the series circuit of the N-type transistor 7T and the N-type transistor 7U. give. As a result, FIG.
As shown in (E), a voltage determined by gm of the N-type transistor 7T and the N-type transistor 7U appears at a node Q which is a connection point between the N-type transistor 7T and the N-type transistor 7U. This voltage Vg is applied to the N-type transistor 7
M gate. As a result, the source of the N-type transistor 7M has the voltage V at the node Q as shown in FIG.
The voltage Vcnt corresponding to g is output and output from the terminal SS.

As described above, according to the configuration of FIG. 6, the voltage output to the terminal SS between the time t0 and the time t1 is
Any voltage between the ground level and the external high-voltage power supply terminal Vpp can be set. Thus, when an erase voltage is applied to the memory cell, the ground level and Vpp
An intermediate level between (12 V) can be freely set by setting gm of the N-type transistor 7T and the N-type transistor 7U.

As a result of the above operation, as shown in FIG. 8, a voltage Vcnt that can be arbitrarily set is output to the terminal SS between time t0 and time t1. Between time t1 and time t2, the external high-voltage power supply terminal V, which is a high voltage,
A voltage of pp is output. As a result, the terminal SS
A high voltage can be applied stepwise. as a result,
In the memory cell 30 to which the erasing voltage from the terminal SS is applied to the source, a voltage at which an interband current flows instantaneously is not applied. Therefore, the erasing operation is performed at a low voltage, and the erasing characteristics can be greatly improved.

In the embodiments shown in FIGS. 3 and 6, the terminal S
In stepwise raising the voltage of S, (Vcc-Vt
h) A configuration in which a voltage Vg or an arbitrary voltage Vg equal to or lower than the external high-voltage power supply terminal Vpp is set in the middle by one step has been exemplified. However, the configuration may be such that the number of steps is further increased and the erase voltage of the terminal SS is gradually increased. In this case, another delay circuit is provided in addition to the delay circuit 7B,
The configuration of FIG. 3 and the configuration of FIG. 6 can be combined, or the configuration of FIG. 6 can be provided in a plurality of stages.

[0064]

As described above, according to the present invention, when erasing data in a memory cell, the erase source voltage applied to the source of the memory cell is gradually increased or gradually increased. In addition, the inter-band current is prevented from flowing regardless of the change of the erase source voltage. Therefore, even if the gate oxide film is thin, it is possible to prevent the deterioration as much as possible and to prevent the deterioration of the memory cell for a long time. It can maintain the reliability as a product for a long time.

[Brief description of the drawings]

FIG. 1 is a main part circuit diagram of a semiconductor memory device according to one embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the configuration of FIG. 1;

FIG. 3 is a main part circuit diagram of a semiconductor memory device according to another embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of the configuration of FIG. 3;

FIG. 5 is a waveform chart for explaining the operation of the configuration shown in FIG. 3;

FIG. 6 is a main part circuit diagram of a semiconductor memory device according to still another embodiment of the present invention.

FIG. 7 is a timing chart for explaining the operation of the configuration of FIG. 6;

FIG. 8 is a waveform chart for explaining the operation of the configuration of FIG. 3;

FIG. 9 is a pattern plan view showing a configuration of a general memory cell.

FIG. 10 is a sectional view taken along line A-A ′ of FIG. 9;

11 is a sectional view taken along line B-B 'of FIG.

FIG. 12 is an equivalent circuit diagram of the memory cell device shown in FIGS. 9 to 11;

FIG. 13 is a circuit diagram of a conventional semiconductor memory device.

FIG. 14 is a waveform chart for explaining the operation of the configuration of FIG.

[Explanation of symbols]

 7B Delay circuit 8 Boost circuit 9 Output circuit 11 Floating gate 12 Control gate 13 P-type substrate 14 Source 15 Drain 16 Contact hole 17 Data line 18 Gate oxide film 19 Insulating film 20 Field oxide film 21 Insulating layer 30 Memory cell 31 Row decoder 32 Column decoder 33-1 to 33-n Column selection transistor 34-1 to 34-8 Load transistor 35-1 to 35-8 Write data control circuit 36 High voltage switching circuit 37 Source voltage control circuit 38-1 to 38-8 Sense Amplifier 39-1 to 39-8 Output circuit WL1 to WLm Row line CL1 to CLn Column select line DL1 to DLn Column line

Claims (6)

(57) [Claims] A memory cell having a floating gate and capable of electrically writing and erasing data, wherein a plurality of memory cells are arranged so that data erasing is performed by applying a high voltage to a source. A memory cell array, a decoder means for selecting a specific memory cell in the memory cell array, and a memory cell source which, when erasing data, rises from a low voltage to a high voltage at a source of the memory cell. A non-volatile semiconductor memory device, comprising: an erase voltage application unit for supplying an erase source voltage whose time is controlled. 2. The erase voltage applying means is configured to control a rise time of the erase source voltage in such a manner that no inter-band current flows even when the erase source voltage rises. Non-volatile semiconductor storage device. 3. The apparatus according to claim 1, wherein said erasing voltage applying means sets a time from said low voltage to said high voltage to about 1 microsecond or more. 4. The apparatus according to claim 1, wherein said erasing voltage applying means makes the rising from said low voltage to said high voltage analog. 5. The apparatus according to claim 1, wherein said erase voltage applying means digitally sets the rise from said low voltage to said high voltage. 6. The apparatus according to claim 5, wherein said erase voltage applying means can arbitrarily set a first rising voltage value from said low voltage to a rising voltage of a first stage.