TW297185B - Tuned control system - Google Patents

Tuned control system Download PDF

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Publication number
TW297185B
TW297185B TW85106444A TW85106444A TW297185B TW 297185 B TW297185 B TW 297185B TW 85106444 A TW85106444 A TW 85106444A TW 85106444 A TW85106444 A TW 85106444A TW 297185 B TW297185 B TW 297185B
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Taiwan
Prior art keywords
circuit
tuning
signal
phase
phase shift
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TW85106444A
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Chinese (zh)
Inventor
Takeshi Ikeda
Tadataka Oe
Akira Okamoto
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Okamura Susumu
Takeshi Ikeda
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Publication of TW297185B publication Critical patent/TW297185B/en

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Abstract

A tuned system includes a tuned circuit 1 that is formed by cascading two phase shifting circuits and non-inverter circuit and a frequency control circuit 2 that includes a synchronous rectification circuit 3, a pulse converter circuit 5, a polarity distinction circuit 6 and a voltage mixed circuit 7. The synchronous rectification circuit 3 performs the synchronous rectification operation to the input signal and the pulse converter circuit 5 outputs the signal with pulse width in correspondence with a phase difference between the frequency of the input signal and a tuned frequency. The polarity distinction circuit 6 distinguishes the polarity of the phase difference, and the voltage mixed circuit 7 generates the control voltage by mixing a voltage in correspondence with a pulse that was output from the pulse converter circuit 5 for a prescribed voltage and applies the control voltage to the turned circuit 1. The tuned circuit 1 equalizes the tuned frequency with the frequency of the input signal of the tuned circuit 1 based on the control voltage that is output from the frequency control circuit 2.

Description

經濟部中央標準局員工消費合作社印製 Α7 Β7 五、發明説明(1 )Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs Α7 Β7 V. Description of the invention (1)

技術領域 I 本發明係關於一種僅讓規定頻率信號通過之調諧控制 方法。 技術背景 己知有利用LC諧振等之各種構成的濾波器或調諧電路 。例如,超外差式接收收信機之中頻放大霣路備有用做滅 波器之機能,習知之中頻放大電路則,一般而言,使用多 數組之中頻變壓器(I FT)及電容器,藉此來實現所需之頻 率特性。例如,在AM收信機之情形時,設定有455kHz之中 心頻率之同時,設定成從此中心頻率失諧9kHz時僅衰減一 規定量。又,使用一個陶瓷濾波器以替代中頻變壓器等, 藉此來寅現所需之頻率持性的AM收信器也已為公知。 且說,在適用上述超外差式接收方式之習知技術方面 ,由於進行調諧之濾波器亦邸中頻放大電路之構成中包含 有中頻變壓器或陶瓷濾波器,所Μ不易將包含有此等之全 體積體化於半導黼基片上。 又,就跟此中頻放大16路組合之局部振盪霣路而言, 簡單者可箱利用局部振盪變壓器之LC振盪器來實現,而高 精度者則藉利用晶體振盪之PLL構成來實現。尤其是,將 局部振盪電路作為PLL構成時,由於包含有用來進行正弦 波振通之霣壓控制式振蘯器(VCO>而難Μ積體化,故一部 分乃使用混合式積體電路(hybrid 1C)。 像這樣,將作為濾波器動作的中頻放大電路且與之組 合Μ構成調諧機構之局部振盪電路也包括在內之全部都予 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X 297公釐) (請先閲讀背面之注意事項再填寫本頁) .裝. 訂TECHNICAL FIELD I The present invention relates to a tuning control method that allows only signals of a prescribed frequency to pass. Technical Background There are known filters or tuned circuits using various configurations such as LC resonance. For example, the super-heterodyne receiver-receiver IF amplifier is equipped with a function as a wave destroyer, while the conventional IF amplifier circuit generally uses multiple arrays of intermediate frequency transformers (I FT) and capacitors , To achieve the required frequency characteristics. For example, in the case of an AM receiver, while setting the center frequency of 455 kHz, it is set to attenuate only a specified amount when the center frequency is detuned by 9 kHz. In addition, it is also known to use a ceramic filter to replace the intermediate frequency transformer, etc., in order to achieve the required frequency persistence AM receiver. Moreover, in the conventional technology that applies the above-mentioned superheterodyne receiving method, since the filter to be tuned also includes an intermediate frequency transformer or a ceramic filter in the configuration of the intermediate frequency amplification circuit, it is not easy to include these The full volume is integrated on the semiconducting ray substrate. In addition, as for the local oscillation of the 16-channel combination of intermediate frequency amplification, the simple one can be realized by using an LC oscillator of a local oscillation transformer, and the high accuracy can be realized by using a PLL structure of crystal oscillation. In particular, when the local oscillation circuit is constituted as a PLL, it is difficult to integrate it due to the inclusion of a sine-wave vibration control type vibrator (VCO>), so part of it uses a hybrid integrated circuit (hybrid 1C). In this way, the IF amplifier circuit that acts as a filter and the local oscillation circuit that constitutes the tuning mechanism in combination with it are all included in this paper standard. The Chinese National Standard (CNS) Α4 specification (210X 297mm) (Please read the precautions on the back before filling in this page). Pack. Order

i、發明説明(2 ) 經濟部中央標準局員工消費合作社印製 Μ積體化,委實並非易事,因此盼望有可將調锴機構全部 稹體化之調諧控制方式。又,縱使將以往即已存在之濾波 器全體或包含此濾波器之電路全體予Μ積體化,只因電路 常數產生很大之偏差,而所裂成之各晶片也變成具有不同 之特性。再者,中心頻率有時也會因溫度等而起大變化, 所Μ縱使積體化,Μ往也沒有可確實達成預期之頻率特性 的調諧控制方式。 發明之揭S 本發明係為了解決此種課題而創作者,其目的係在於 提供一種適於積體化的新穎調諧控制方法。 本發明之調諧控制方法,係包含: 一調諧霣路,包含有:兩値级聯逋接之全帶通型相移 電路;及一加法電路,其係使前述後段相移電路之輪出當 做回授信號回授至前述前段相移電路之輪入側同時,將前 述回‘授信號及_入信號加法後輪入於前段相移電路;藉此 僅讓規定之頻率附近之信號通過;及 一頻率控制18路,係於前述調諧電路,輪入一具有前 述規定頻率附近之頻率的信號時,根據前述調諧電路之輪 入·_出間之相位差,使前述調諧電路之調諧頻率相符於 前述調諧電路之輸入信號的頻率。 而且,進行控制Μ便調諧電路之_入输出間之相位差 消失,使調諧頻率經常追隨輪入信號之頻率與之一致。 圖式之簡單說明 第1圖係調諧控制方法之一實施形態的調諧機構構成 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X297公釐) 6 (請先閱讀背面之注意事項再填寫本頁) 裝· 丨線 A7 B7 五'發明説明(3 ) · Λ 圖; 第2圓係顯示調諧霣路之詳細構成的霣路圈; 第3_係将第2園中所示之前段相移霣路抽出來顯示 的電路園; 第4_為一向董圈,係顯示第3圈中所示之相移霣路 之輪入輸出霣壓與顯現於霣容器等之電壓的两係; 第5圈係將第2圃所示之後段相移電路之構成抽出來 顯示的霣路圖; 第6讕潙一向量圖,係顯示第5圈中所示之相移霣路 之_入輸出霣壓與顯現於電容器等之霣壓的關係; 第7_係顯示頻率控制霄路楕成的霣路圖; 第8圔係調港頻率离於鑰入信號之頻率時的時序圖; 第9國係調渚頻率低於_入信號之頻率時的時序圖; 第10圖係兼作AM檢波的調諧機構之構成圔; 第11圏係利用第10圈所示之調锴機構的、AM收信機之 構成圈; 第12國係兼作FM機構的調諧機構之楕成鼷; 第13囫係第12圃所示之頻率控制霣路的詳.細轚路圖; 第14園係顯示頻率控制霣路之其他構成的詳細霣路鼷 » 第15圖係顯示頻率控制電路之其他構成的詳細霣路圔i. Description of the invention (2) The printing of the M-Consumer Cooperative by the Central Standards Bureau of the Ministry of Economic Affairs is not easy, so I hope that there will be a tuning control method that can integrate all the adjustment institutions. In addition, even if the entire existing filter or the entire circuit including the filter is integrated, only the circuit constants vary greatly, and each chip that has been split has different characteristics. In addition, the center frequency may also vary greatly due to temperature and the like. Even though the M is integrated, there is no tuning control method that can reliably achieve the desired frequency characteristics. DISCLOSURE OF THE INVENTION The present invention was created to solve such problems, and its object is to provide a novel tuning control method suitable for integration. The tuning control method of the present invention includes: a tuning path, including: two-band cascaded full-band-pass phase shift circuit; and an addition circuit, which assumes the rounding of the aforementioned phase shift circuit The feedback signal is fed back to the turn-in side of the preceding phase shift circuit, and at the same time, the feedback signal and the incoming signal are added to the front-end phase shift circuit; thus, only the signal near the specified frequency is passed; and A frequency control 18-way is connected to the tuning circuit. When a signal with a frequency near the predetermined frequency is input, the tuning frequency of the tuning circuit is matched with the phase difference between the round and the out of the tuning circuit. The frequency of the input signal of the aforementioned tuning circuit. Moreover, the phase difference between the input and output of the tuning circuit disappears by controlling M, so that the tuning frequency always follows the frequency of the round-in signal and is consistent with it. Brief description of the drawings Figure 1 is one of the tuning control methods of the implementation form of the tuning mechanism. This paper standard is applicable to the Chinese National Standard (CNS) Α4 specification (210X297 mm) 6 (Please read the precautions on the back before filling this page ) Installation · 丨 Line A7 B7 Five 'invention description (3) · Λ diagram; the second circle shows the detailed composition of the tuned ring road ring; the third circle is the phase shift of the previous segment shown in the second circle The circuit park that the road is drawn out to show; The fourth circle is the always-on circle, which shows the two systems of the in- and output-out voltages of the phase-shifted roads shown in circle 3 and the voltages that appear in the vessels and the like; circle 5 It is a diagram showing the phase diagram of the phase shift circuit shown in the second stage. The sixth diagram is a vector diagram, which shows the _input and output voltage and the phase shift diagram shown in the fifth circle. The relationship between the voltage of the capacitor and the like; the 7th series shows the image of the frequency map of the frequency control road; the 8th series is the timing chart when the frequency of the port is separated from the frequency of the key input signal; the 9th country Timing chart when the frequency of the zhu is lower than the frequency of the incoming signal; Figure 10 is the structure of a tuning mechanism that also serves as AM detection圔; The 11th 圏 uses the adjustment mechanism shown in the 10th circle, and the AM receiver ’s constellation circle; the 12th national system also serves as the FM organization ’s tuning mechanism; the 13th 囫 is shown in the 12th garden. The details of the frequency control circuit are detailed. Detailed diagram of the road; The 14th garden shows the details of the other components of the frequency control circuit. The 15th system shows the details of the other components of the frequency control circuit.

I 第16圈係顯示頻率控制霣路之其他構成的詳細霣路圈 本紙張尺度適用中國國家標準(CNS ) A4规格(210X297公釐) ----------裝I, 請先閲讀背面之注意事一?再填寫本頁 訂 線 經濟部中央標準局貝工消費合作社印裝 297185I The 16th circle shows the details of the other components of the frequency control 霣 路. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) ---------- Install I, please first Note 1 on the back? Fill in this page again. Booking Line Printed by Beigong Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs 297185

經濟部中央標準局員工消費合作社印製 第17園為一霣路圈 的構成; 第18圓為一霣路圔 的其他構成; 第19圖為一電路圖 第2〇圈為一m路鬮 之構成; 第21國為一霣路圔 的其他構成; 第22圖為一霣路圖 構成; 笫23圔為一霣路圓 第25圖為一霣路鼸 第26圔爲一霣路圈 第27圃爲一霣路圈 之構成; 發明説明( 俤頋示包含有LR霣路之相移霣路 係顯示包含有LR電路之相移霣路 係顯示調港霣路之第二變形例; 係顯示包含有路之相移霣路 係顯示包含有LR霄路之相移霄路 係顯示調諧霣路之第四變形例的 係顯示將非反相霣路連接至相移 霣路前段的調渚霣路之構成; 第24圓為一霄路圓,係顯示調港霣路之第六變形例; 係顯示調揩霣路之第七變形例; 係顯示調諧霣路之第八變形例; 係顯示包含有LR®路的相移《路 第28圈爲一霣路圖,係顯示包含有LR霣路的相移霣路 之其他構成; 第29圓為一調锴霣路之霄路躧,係级聯連接第26圖中 所示之前段相移電路而成者; 第30画爲一調谐電路之霄路圈,係级聯連接第26圖中 所示之後段相移電路而成者;及 本紙張尺度適用中國國家標準(CNS > A4規格(210 Χ297公釐) ----------裝------訂-----d——線------^--- (請先閲讀背面之注意事項再填寫本頁) Α7 Β7 經濟部中央標準局員工消費合作社印製 五、發明説明(5 ) ^ 第31圈為一霣路圖,係顙示蓮算放大器之内部構成的 一部分。 用Μ實施發明之最佳形態 Μ下,就本發明調谐控制方法之一實施形態,一面參 照圖式一面具醱說明之。 〔Α.調揩機構之全髏構成及動作〕 本發明之調锴控制方法之特擻,係在於當某頻率之正 弦波倍號輸入於調諧霣路時,檢出調港電路之Μ入輪出間 之相位差,Μ進行可使調諧頻率跟_入倍號一致的控制。 第1圓係適用本發明調諧控制方法的一實施形筋亦即 調諧機構之構成圔。該圔所示之調諧機構包含有:調諧霄 路1,係當做一讓某頻率附近之信號通過的濾波器作用; 及頻率控制電路2,係用Μ進行此調諧m路之通過中心頻 率之控制。 調揩霣路1係包含如後述之兩個相移電路;各相移霣 路分別使所蠄入之交流信號的相位位移一規定量。又,將 兩傾相移霄路合而為一之相位位移Μ,係設定為於規定之 頻率成360° 。又,調皤電路1係設成,可入自外部 之控制信號,在某範園内任意設定調諧頻率。 頻率控制《路2,係於調諧電路1之輪入_出間之相 位差從360°偏移時,即,在鑰入信號之中欲讓其通過之 成分的頻率與調諧«路之調諧頻率不吻合時*控制同步頻 率Μ便除掉此偏差。為了執行這種控制,頻率控制霉路2 乃包含構成有同步整流《路3及控制信號產生S路4。 (請先閲讀背面之注意事項再填寫本頁) -裝. 訂 線 本紙張尺度適用中國國家標準(CNS ) Μ規格(210X297公釐) Α7 Β7 經濟部中央標準局貝工消費合作社印製 五、發明説明(6 ) 同步整流霣路3,係用Μ同步於調揸霣路1之幘出倍 號,俥同步整滾調諧霣路1之輸入倍號。所同步整滾之輪 出則被輸入後段控制信號產生電路4。例如*假定單一頻 率之信號被輸入調諧電路1 *則上述之同步整流霄路3於 調諧頻率與調諧電路1幘入信號之頻率一致且輪入輪出間 之相位差爲360°時,輓出完全的半波整滾波形霣壓,並 從360°偏移時_出柑當於此偏移之霣壓。 控制信號產生霣路4,係包含:脈衝變捵霣路5 ;極 性判別霣路6 ;及電壓合成霣路7。其係用來檢出上述調 谐霣路1之輸入輪出間之相位差同時,判別此相位差之大 小及極性,產生用來除掉柑位差之控制倍號。 脈衝變換電路5,係用來輪出具有對應於顯現霣壓成 分之時間間隔的脈衝寬度之脈衝列;此«壓成分係相當於 輪出自同步整流霄路3之偏移。極性判別霣路6,係利用 相當於輪出自同步整流3之偏移的霉壓成分與半波整流波 形之相位關係,來判別相位差之極性。此相位差之極性, 係用來表示,_入倍號中所包含的應抽出之倍號頻率是否 高或低於調諧頻率者。 電壓合成電路7,係用以產生對應於_出自脈衝變換 霣路5之信號之脈衝寬度的電壓同時,進行電壓之合成( 将所產生之18壓予以加法或減法)*然後將合成後之霄壓 當做控制信號向調諧霣路1_出。 〔Β.調諧電路之詳細構成及動作〕 第2圖係調譜霣路1之詳細霣路圖。調諧霣路1係包 --------(·--裝-- (請先閲讀背面之注意事項再填寫本頁) 訂 Τ 線_ L-. 本紙張尺度逋用中國國家標準(CNS ) Μ規格(2丨0><297公釐) 10 五、 發明説明( A7 B7 經濟部中央標準局員工消費合作社印製 含:兩傾柑移霣路110C及130C,係於規定頻率時進行合計 360°之相位位移;一分懕«路160,係由®阻162及164所 檐成;及一加法電路,係透遇回授《阻170及輪入電阻174 (假定輪入電阻174具有回授霣阻170之16阻值的η倍之電 阻值)之各霣阻而以規定比例将分Κ霣路160之分壓输出 及輪入於输入端子190之信號後予Μ加法者。 第3画係顯示相移電路110C之構成的電路圖。相移霣 路110C,係包含:一蓮算放大器112,係差動放大器之一 棰;可變電胆116及電容器114,係使輸入信號之相位位移 一規定量;一電狙118,係成爲運算放大器之輸入電阻; 霣阻121及123,係構成分® «路;霣阻120,係成爲蓮算 放大器112之回授電阻。 電阻118與霣阻120,係設定成同一霣阻值。又,可變 霉阻116,例如使用FET (場效臁霄晶讎)之通道霣阻值作 爲霣阻醱,可随來自外部之控制霣壓而變更霣阻值。 第4圄為一向量圔,係顯示相移電路110C之_入輪出 霣颳與顧現於霣容器等電壓之關係。如該圏所示,_入霣 壓Ei與分壓_出£〇’之大小及相位之關係,可用二等邊三 角形(即,Μ輸入電壓Ei及分壓_出Eo’爲斜邊,以霣壓 VC1之二倍為底面)來表示;分®霣KEo之振幅係與頻率 無關而同於_入倍號之拫幅,其相位位移董係用第4圖中 所示之必1來表示。 又,相移《路110C之傳輪函數K1求自下式(1)。 Kl=-ai(l~Tis)/(l+Tis) ...(1) 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁) .裝. 訂 線 11 297185 a7 B7 經濟部中央標準局員工消費合作杜印製 發明説明(8 ) * 其中,由霣阻116及霣容器114所成之CR霣路(串聯霣 路,s=j<y,at為相移霣路11〇(:之增益,邸,ai = (l + R21/ R23)>1。但R21為霣阻121之霣阻值,卩23為霣阻123之霣阻 值。 由(1>式可知,相移霄路110C為全帶通霣路,其_出 係與頻率無Μ而一定;相位位移量4 1,係以_入信號為 基準向顒時針旋轉之方向(相位延遲方向)從180°變化 至360° 。又,相移霣路11〇(:可藉著調整R21及R23之霣阻 值而播得大於1之增益。 同樣,第5圖為一電路圖,係顯示相移《路130C之構 成。相移電路130C,係包含:差動放大器之一棰的蓮算放 大器132 ;使輪入倍號之相位位移一規定曇之霣容器134及 霣阻136;成為蓮算放大器132之_入霣阻的霣阻138;構 成分壓«路之«阻141及143;及成為蓮算放大器132之回 授《阻的電阻140。又,霣阻138及霣狙係設定為同一值。 第6圔為一向量圈,係顯示相移霣路130C之輸入輸出 霣鼷與顯現於霣容器等電壓之關係。如該圈所示,輪入電 壓Ei與分壓_出£〇’之大小及相位之鼷係,可用二等邊三 角形(即,以綸入電壓Ei及分壓_出Eo’爲斜邊,Μ霣壓 VR2之二倍為底邊)來表示;綸出電壓Εο之振幅係與頻率 無籣而同於輸入倍號之振幅,其相位位移量係用第6圔中 所不之必2來表不。 又,相位霄路130C之傳輪函數Κ2可求自下式(2)。 K2=az(1-T8s)/(1+T2s) ---(2) 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁) .裝.The 17th Park printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs is the composition of a circle of roads; the 18th circle is the other composition of a circle of roads; FIG. 19 is a circuit diagram. The circle 20 is the composition of a road of 1 m. ; The 21st country is the other composition of a 霣 路 圔; The 22nd picture is a 霣 路 團 's composition; It is composed of a ring road; description of the invention (indicated by the phase shift that includes the LR road, the road that displays the phase shift that includes the LR circuit, and the second modification of the port that adjusts the port; the system includes The phase-shifted roadway with road display includes the phase-shifted roadway with LR roadway. The display shows the fourth modification of the tuned roadway. The system shows the non-inverted roadway connected to the front section of the phase-shifted roadway. The composition of the 24th circle is the Xiaoluyuan circle, which shows the sixth modification of the tuned Hongqiao Road; it shows the seventh modification of the tuned Jiao Road; it shows the eighth modification of the tuned Jiao Road; it shows that it contains Phase shift with LR® road "The 28th circle of the road is a road map, showing other phase shift roads with LR road Composition; The 29th circle is a tuned road, which is formed by connecting the phase shift circuit of the previous stage shown in Figure 26; The 30th drawing is a tuned circuit, which is a cascade Connected by the phase shift circuit shown in the following figure 26; and the paper standard is applicable to China National Standards (CNS & A4 specifications (210 Χ297 mm) ---------- installed --- --- Subscribe ----- d ---- Line ------ ^ --- (Please read the notes on the back before filling out this page) Α7 Β7 Printed by the Employees Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs DESCRIPTION OF THE INVENTION (5) ^ The 31st circle is a picture of the road, which is a part of the internal structure of the amphitheater. The best form of implementing the invention with Μ, one embodiment of the tuning control method of the present invention, one side This is explained with reference to Figure 1. [A. Structure and operation of the whole skeleton of the tuning mechanism] The special feature of the tuning control method of the present invention is that when a sine wave multiple of a certain frequency is input to the tuning path, Detect the phase difference between the input and output of M of the port adjustment circuit, and M will control the tuning frequency to match the _in multiple. The first circle is applicable to this issue An example of the implementation of the tuning control method is the structure of the tuning mechanism. The tuning mechanism shown in this figure includes: Tuning Road 1, which acts as a filter that passes signals near a certain frequency; and frequency control Circuit 2, uses M to carry out the control of the center frequency of the m channel. Tuning circuit 1 includes two phase shift circuits as described below; each phase shift circuit separately shifts the phase of the incoming AC signal A specified amount. In addition, the phase shift M, which combines the two tilted phase shifts into one, is set to 360 ° at the specified frequency. Also, the adjustment circuit 1 is set to be able to enter the external control signal , Set the tuning frequency arbitrarily in a certain fan garden. Frequency control "Route 2, when the phase difference between the turn-in and out of the tuning circuit 1 is shifted from 360 °, that is, in the key-in signal, it wants to pass it When the frequency of the component does not match the tuning frequency of the tuning channel, * control the synchronization frequency M to remove this deviation. In order to perform this control, the frequency control circuit 2 includes a synchronous rectifier circuit 3 and a control signal generating circuit 4. (Please read the precautions on the back before filling out this page)-Packing. The paper size of the binding book is applicable to the Chinese National Standard (CNS) Μ Specification (210X297mm) Α7 Β7 Printed by Beigong Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs DESCRIPTION OF THE INVENTION (6) Synchronous rectification of 霣 路 3 is to use M to synchronize the output multiple of tuned 霣 霣 路 1, and to synchronize the input multiple of tuned 霣 路 1. The wheel output of the synchronized rolling is input to the subsequent stage control signal generating circuit 4. For example * Assuming that a signal of a single frequency is input to the tuning circuit 1 * Then the above synchronous rectifier road 3 is pulled out when the tuning frequency is the same as the frequency of the input signal of the tuning circuit 1 and the phase difference between the rounds and rounds is 360 ° Complete half-wave roll-up waveform pressure, and offset from 360 ° _ out orange should be the pressure of this offset. The control signal generates a circuit 4, which includes: a pulse change circuit 5; a polar discrimination circuit 6; and a voltage synthesis circuit 7. It is used to detect the phase difference between the input wheels of the above-mentioned Tuning Road 1 while judging the magnitude and polarity of this phase difference, and generating a control multiple to remove the difference in position. The pulse conversion circuit 5 is used to wheel out a pulse train having a pulse width corresponding to the time interval of the apparent pressure component; this pressure component is equivalent to the shift from the synchronous rectifier road 3. The polarity discrimination 6 is to determine the polarity of the phase difference by using the phase relationship between the mold pressure component equivalent to the deviation from the synchronous rectification 3 and the half-wave rectification waveform. The polarity of this phase difference is used to indicate whether the frequency of the multiplier included in the multiplier should be higher or lower than the tuning frequency. The voltage synthesizing circuit 7 is used to generate a voltage corresponding to the pulse width of the signal from the pulse conversion circuit 5 while synthesizing the voltage (adding or subtracting the generated 18 voltages) * and then synthesizing Press the control signal as a control signal 1_ out. [B. Detailed structure and operation of the tuning circuit] Fig. 2 is a detailed diagram of the spectrum-modulated en route 1. Tuning Fenglu 1 series package -------- (· --installed-- (please read the precautions on the back before filling out this page). Order T line _ L-. This paper standard uses the Chinese national standard ( CNS) Μ specifications (2 丨 0> < 297mm) 10 V. Description of the invention (A7 B7 Printed by the Employees ’Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Contains: 110C and 130C of the two-inclined oranges on the moving road, at the specified frequency Carry out a total phase shift of 360 °; one minute of «Road 160, which is formed by ® resistances 162 and 164; and an addition circuit, which is a feedback of" Resistance 170 and Round-in Resistance 174 (assuming Round-in Resistance 174 Each feedback resistor having a resistance value of n times 16 of the feedback feedback resistance 170 (n-times resistance value) outputs the divided voltage of the K-channel 160 and the signal input to the input terminal 190 to the M adder in a prescribed ratio. The third drawing is a circuit diagram showing the structure of the phase shift circuit 110C. The phase shift circuit 110C includes: a lotus amplifier 112, which is one of the differential amplifiers; a variable battery 116 and a capacitor 114, which are input signals A specified amount of phase shift; an electric 118, which becomes the input resistance of the operational amplifier; a large resistance 121 and 123, which constitute the component ® «road; The resistance 120 becomes the feedback resistance of the lotus amplifier 112. The resistance 118 and the resistance 120 are set to the same resistance value. In addition, the variable resistance 116 is used, for example, a channel using FET (field-effect protection) As the resistance value, the resistance value can be changed according to the control pressure from the outside. The fourth value is a vector value, which shows the phase shift circuit 110C's in-out and out-of-round scratches, and the presence in the container. The relationship between the voltage. As shown in the circle, the relationship between the size and phase of the _ input pressure Ei and the partial pressure _ out £ ′ can be used as an equilateral triangle (ie, Μ input voltage Ei and partial voltage _ out Eo 'as Hypotenuse, with twice the pressure VC1 as the bottom surface); the amplitude of the minute 霣 KEo is independent of the frequency and is the same as the amplitude of the _ 入 倍 号, and its phase shift is shown in Figure 4 It must be expressed by 1. Also, the phase shift "The transmission function K1 of the road 110C is obtained from the following formula (1). Kl = -ai (l ~ Tis) / (l + Tis) ... (1) This paper size is applicable China National Standard (CNS) A4 specification (210X297mm) (please read the notes on the back before filling in this page). Packing. Thread 11 297185 a7 B7 Employee Consumption Du Yin's description of the invention (8) * Among them, the CR Yuan Road formed by the Yuan resistance 116 and the Yuan container 114 (tandem Yuan Road, s = j < y, at is the phase shift Yuan Road 11〇 (: gain, Di , Ai = (l + R21 / R23)> 1. However, R21 is the resistance value of the resistance 121, and the value 23 is the resistance value of the resistance 123. From the equation (1>, we can see that the phase shift road 110C is full For the band pass road, its outgoing frequency and frequency are constant without M; the phase shift amount 41 is based on the incoming signal as the direction of clockwise rotation (phase delay direction) from 180 ° to 360 °. In addition, the phase shifting path 11 ° (: the gain of greater than 1 can be broadcasted by adjusting the resistance values of R21 and R23. Similarly, Figure 5 is a circuit diagram showing the composition of the phase shifting path 130C. Phase shift The circuit 130C includes: a lotus amplifier 132, which is one of the differential amplifiers; a phase shift of the rounding multiplier by a specified period of time, a container 134 and a resistance 136; Resistance 138; resistance 141 and 143, which form the partial voltage «Road of Resistance», and the feedback resistance 140 of the resistance amplifier 132. Also, the resistance 138 and the resistance are set to the same value. The sixth dimension is a vector The circle shows the relationship between the input and output voltage of the phase-shifting circuit 130C and the voltages that appear in the container. As shown in the circle, the voltage and voltage of the input voltage Ei and the partial pressure_out £ 〇 ' It can be expressed by an equilateral triangle (ie, with the input voltage Ei and the partial pressure_out Eo 'as the hypotenuse, and the double pressure VR2 as the bottom edge); the amplitude of the output voltage Eο is independent of the frequency Same as the amplitude of the input multiplier, the phase shift amount is expressed by the 2 that is not necessary in the 6th circle. Also, the pass of the phase Xiaolu 130C The function Κ2 can be obtained from the following formula (2). K2 = az (1-T8s) / (1 + T2s) --- (2) The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (please Read the notes on the back before filling out this page).

.tT.tT

J —線 t. 12 五、發明説明(9 ) A7 B7 經濟部中央標準局員工消費合作杜印製 其中,T2為由電容器134及電阻136所成之CR電路之時間常 數,s = j<u,a2為相移電路130C之增益,即,a2 = (l + R41/ R43)>1。但R41爲電阻141之電阻值,R43為電阻143之電阻 值。 由(2)式可知,相移電路130C為全帶通電路,其輸出 振幅係與頻率無關而一定;相位位移量4 2則Μ輪入信號 爲基準,向順時針旋轉方向從0°變化至180° 。又,相移 電路130C,可藉著調整R41及R43之電阻值而播得大於1之 增益。 如此,於兩個相移電路110C,130C之各個,將相位位 移一規定量,結果如第4圖及第6圖所示,將調諧電路1 全體之相位位移量,在規定之頻率時,變成360° 。此時 將導自兩値相移電路110C,130C,分壓電路160及回授電 阻170之回授環路之回路增益設定於1 Μ下,藉此來進行 僅使上述規定頻率成分通過之調諧動作。 又,由於從第2圖所示之調諧電路’1之蠄出端子192 ,取出輪入分壓電路160前之相移電路130C之輸出,所Μ 可讓調諧電路1本身具有增益,可進行調諧動作之同時放 大倍號振幅。 又,從式(1)及(2>求出第4圖、第6圖所示之炎1, Φ 2,則必1,0 2可求自下式(3)及(4) Φ l = tan { 2ω Τι/(1-ω 2 Τ ι2)} ...(3) 0 2 = tan { 2 α> Tz/(1-ω 2Ta 2 ) } ...(4) ,則ω =1/Τ時導自兩個相移II路之柑位 (請先閱讀背面之注意事項再填寫本頁) .裝. 訂 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ297公釐) 13 mm Α7 Β7 經濟部中央標準局員工消費合作社印製 五、發明説明(10 ) 位移量之合計變成360°而進行上述調諧動作,此時,决1 =270° ,炎 2=90° 。 一方面,如輸入於前段相移電路110C的信號之頻率係 低於將兩個相移電路合一之相位位移量之合計成360°之 頻率(調諧頻率)時,相加上述4 1及4 2之結果則不會變 成360° 。在此情況時,前段相移電路110C之相位位移量0 1 變成小於270° ,後段相移電路130C之相位位移量0 2則變 成小於90° ,合計之相位位移量於是變成小於360° 。 此時,如欲將調諧頻率接近於實際所輪入的信號之頻 率,則把上述4 1,4 2增大即可。具體言之,只要將第2 圖所示之可變電阻116之兩端電壓VR1增大即可。 一方面,如輸入於前段相移電路110C之信號的頻率係 高於調諧頻率時,相加上述炎1及¢2之結果便不會成為360° 。在此情況時,前段相移電路110C之相位位移量0 1變成 大於270° ,K及後段相移電路130C之相位位移量炎2變成 大於90° ,所Μ合計之相位位移量變成大於360° 。 此時,如欲將調諧頻率接近於實際所輸入的信號之頻 率,則把上述4 1之絕對值弄小即可。具體言之*只要將 第2圖所示之可變電阻116之兩端電壓VR1弄小即可。 如上所說明,由於在第2圖所示之調諧電路1中,將 兩個相移電路lioc,130C级聯連接同時,作成可變更相移 電路110C内之可變電阻116之電阻值,所以即使_入調諧 罨路1之輸入信號之頻率異於調諧頻率,也可使調諧頻率 確實相符於_入信號之頻率。 本紙張尺度適用中國國家標隼(CNS ) Μ規格(210Χ297公釐〉 (請先閱讀背面之注意再填寫本頁) .裝· 、訂 14 經濟部中央樣隼局員工消費合作社印製 A7 B7 五、發明説明(11 ) 又,於第2圖所示之調諧電路1中,由於使用透過分 颳電路160來衰減的信號作為回授信號,同時取出輸入分 壓電路160前之信號當做調諧電路1之輪出,所Μ可進行 從輸入信號中僅抽出規定頻率成分之調諧動作,同時對於 此所抽出之信號進行規定之放大。 又,於第2圖所示之調諧電路1中,由於將相移電路 110C内之電阻118及電阻120之電阻值設定成同一值,同時 將相移電路130内之電阻138及電阻140之電阻值設定成同 一值,所以即使改變調諧頻率,調諧輪出也不會產生振幅 變動。因此,可藉著增大回授電阻170與輸入電阻174之電 阻比η,來提高調諧電路1之Q。 即,如回路增益存在著頻率依存性的話,在增益低之 頻率時,即使將電阻比増大Q也不會升高,但在增益高之 頻率時,回路增益有時超出1而發生振盪。因此,如振幅 變動大時,為了防止這種振盪而不能將電阻比η設定成過 大之值,調諧電路1之Q值為此也變小。一方面,在第2 圖所示之調諧電路中,由於相移電路110C,130C內分別包 含有分饜電路,故即使將電阻比η設定成大值,調諧電路 1之調諧_出也不會產生振幅變動,因而可把電阻比增大 Μ增大Q值。 〔C.頻率控制電路之詳細構成及動作〕 第7圖係顯示頻率控制電路2之構成的電路圖。其係 顯示同步整滾電路3、脈衝變換電路5、極性判別電路6 及電壓合成電路7之各詳細構成。 本紙張尺度適用中國國家標準(CNS ) Α4規格(210 X 297公釐) _ 1 R _ i 裝 I I 訂—— I —__ 線 ί ί (請先閱讀背面之注意事項再填寫本頁) 五、發明説明(l2 A7 B7 經濟部中央標準局員工消費合作社印裝 同步整流電路3,係包含:模擬開關(AS) 30 ;電壓比 較器32 ;電平移相器(LS) 34。於電壓比較器32之一方端繪 入調諧電路1之蝓出信號,而另一方之輸入端則被接地。 電壓比較器32之蝓出,係於調諧電路1之輪出信號之電位 大於0V時變成L電平(例如0V),反之,調諧電路1之輸出 信號之電位為0V以下時變成Η電平(例如規定之正電壓)。 又,電壓比較器32,除了上述輪出端以外更備有一用來輸 出邏輯反相的信號之反相輪出端;此反相輪出端係連接於 後述極性判別電路6。 電平移相器34,係對輪出自電壓比較器32之信號執行 極性反轉同時,進行電平位移,並將具有正極及負極性之 電壓霉平之矩形波當做參考信號輪出。 模擬開關30,係與輪出自電平移相器34之參考信號同 步地動作;例如,當參考信號之矩形波為正極性之電壓電 平時,讓調諧電路1之輓入信號通過,反之,炱極性之電 壓霄平時,遮斷調諧電路1之輪入信號。 脈衝變換電路5,係包含:電壓比較器50;及由電阻 52,54所成之分壓電路。於電壓比較器50之一方輸入端, _入同步整流霄路3内之楔擬開關30之輸出信號;並於另 一方之輪入端,輸入由電阻52及54所成的分壓電路之分壓 輪出。電阻52之一方端被接地;而電阻54之一方端則連接 至貪電源Vss ;此時,將電阻54之電阻值設定成大於電阻52 之電阻值(例如100倍左右),藉此電壓比較器50之反相輪 入端子之電壓被設定爲稍低於0V。 ----------裝-- (請先閲讀背面之注意4^·再填寫本頁) 訂 線 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐) 16 經濟部中央標準局貝工消費合作社印製 Α7 Β7 五、發明説明(13 ) 如上所述,當調諧電路1所輸入之信號的頻率與調諧 頻率一致時,同步整流電路3之輪出波形則變成完全的半 波整流波形,所Μ不會成為負極性。然而,當輸入信號之 頻率與調諧頻率發生镉移時,在對應於此偏移之時序,同 步整流之輸出便產生負極性之電壓成分。而在產生此負極 性之電壓成分時,脈衝變換電路5内之電壓比較器50之輪 出便成為L電平。 極性判別電路6,係包含:兩値倒相電路60,61 ;及 兩値D型觸發電路62,63。 本實施形態,係藉兩個倒相電路60, 61來構成延遲電 路,並使脈衝變換電路5内之電壓比較器50之轜出通過级 聯連接的兩個倒相電路60,61後,輪入於觸發霄路62,63 之各時鐘端子。 於D型觸發電路62之D_入端子,輸入一與同步整流 電路3之參考信號同一時序且不同電平之信號。輸入於此 D輸入端子之信號,則與輓出自脈衝變換電路5之脈衝列 之上升邊同步地被鎖住後,輸入於次级之D型觭發電路63 之D蠄入端子。藉此,次级之D型觸發電路63,根據輪出 自脈衝變換電路5内之電壓比較器50之脈衝列,蠄出一表 示調諧電路1之蝓入輸出信號間之相位差是否大於或小於 360°之Η或L霄平之霣壓。 電壓合成電路7,係包含:兩傾試驗狀態缓衝器700 ,702;差動放大器;及可變偏®電路。其中,差動放大 器包含有運算放大器704;及可變偏壓電路包含有可變電 本紙張尺度適用中國國家標準(CNS ) Α4規格(210 X 297公釐) 17 ^ 裝 訂 ^ I線 (請先閲讀背面之注意事項再填寫本頁) 五、 185 A7 B7 發明説明(u) 經濟部中央標準局員工消費合作社印製 阻 706。 試驗狀態緩衝器700,其輪出端係透過電阻710而連接 至差動放大器之反相輸入端子。此試驗狀態緩衝器700, 係按照輪出自極性判別電路6内之後段觸發電路63輸出端 子Q之信號動作,例如,此信號之邏輯爲Η時直接輪出所 输入之信號,反之,此信號之邏輯爲L時,將輪出端子作 成高阻抗狀態。 同樣,試驗狀態缓衝器702 ,其輸入端係連接至脈衝 變換電路5内之電壓比較器50之反相輪出端,其輪出端則 透過電阻708而連接至差動放大器之非反柑輪入端子。此 試驗狀態緩衝器702,係按照輪出自極性判別電路6内之 後段觸發電路63之反相輪出端子之信號邏輯而動作,例如 此信號之邏輯為Η時直接輪出所輪入之信號,反之,此信 號之運輯為L時將輪出端作成高阻抗狀態。 差動放大器,係將上述兩個試驗狀態缓衝器700 , 702 之各輪出分別輸入於差動輪入端子,將此等差分Μ規定放 大率放大之同時進行規定之平滑動作Μ除去高頻成分,產 生控制電壓。 此差動放大器,具體而言,除了運算放大器704Μ外 ,尚包含:回授電阻712,係插入在蓮算放大器704之反相 翰入端子與輸出端子間;電容器714,係並聯連接於該回 授電阻712 ;電阻716,係用來分壓一輪出自試驗狀態緩衝 器702之信號的電壓電平,藉此來進行蓮算放大器704之二 輪入間之調整,爲此而插入蓮算放大器704之非反相_入 本紙張尺度適用中國國家標隼(CNS ) Α4規格(210X297公釐〉 (請先閱讀背面之注意事項再填寫本頁) -裝- 、τ 丨線 18 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明(15 ) 端子與接地間;電容器718,係並聯連接於該電阻716 ;及 電容器720 ,係插入在運算放大器704之反相輸入端子與接 地間。 又,該蓮算放大器704之反相輪入端子,係透過電阻 722連接可變電阻706之可動端子;該可變電阻706之兩個 固定端子係連接於正電源Vdd及負電源Vss。由此,依由可 變電阻706所形成之偏壓電路,而於蓮算放大器之輪出端 設定規定之偏壓電路。又,如將此可變霄阻706實際形成 在半導體基片上時,可利用FET等之有源元件來形成。此 偏歷電路,係於調諧電路1之調諧頻率與輓入信號之頻率 一致時,用來設定應外加於可變電阻116 (含在調諧電路 1之一方相移電路110C)之柵極的電壓者。 〔C-1.調諧頻率高於輪入信號之頻率時〕 第8圖係調諧電路1之調諧頻率高於输入於調諧電路 1之信號之頻率的時序圖。 如調諧頻率高於調諧電路1之輓入信號之頻率時,導 自兩個相移電路110C,130C全體之相位位移量之合計為小 於360° ,因此,如觀察在某時刻之調諧電路1中所輪入 之兩個信號的話,變成第8圖(A),(B)所示之相位關係。 同步整流電路3内之電壓比較器32,一如第8圖(C) 所示,具有與調諧輪出柑同之頻率及相位,並僅在調諧輪 出之電壓電平為正極性時輪出成為L電平之矩形波。 電平移相器34, 一如第8圖(C>所示,係用Μ反轉電 壓比較器32之蠄出同時進行電壓電平之變換,然後,如第 本紙張尺度適用中國國家標準(CNS ) Μ規格(210 X 297公釐) ,„ -19- I 裝 訂 ^ I Λ&. (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作杜印製 A7 B7 五、發明説明(16 ) 8圖(E)所示,輸出具有絕對值相等的正極性及負極性電 壓狀態的矩形波。 模擬開關30,一如第8圖(F)所示,係以調諧輪出之 零交叉點作爲基準,僅在規定時間取出輸入調諧電路1之 輪入信號。具體言之,以比取出調諧輪出之上半之時序快 一點之時序,取出輸入信號。 電壓比較器50,一如第8圖(G>所示,僅在模擬開關30 之輪出之電壓電平低於〇v時變成乙霣平。 極性判別霣路6内之前段觸發電路62,如第8圖(I〉 所示,係於使電壓比較器之輪出通過兩値倒相電路60, 61 後之信號上升之時序,取入_出自同步整流霄路3内之電 壓比較器32反相輪出端子之信號的邏輯後,加以保持者。 又,後段之觸發電路63,一如第8圖(<0及(K)所示, 接著,於電壓比較器50之輸出從L罨平上升至Η電平之時 序,取入前段觸發電路62之輪出後加Μ保持。 當調諧頻率高於調諧電路1之蠄入倍號之頻率時,從 後段觸發電路63之輸出端子Q輪出通輯Η之信號,並從反 相輪出端子Q輸出通輯L之信號。因此,試驗狀態緩衝器 702之輪出端變成高阻抗狀態,而僅試驗狀態緩衝器7〇〇作 為緩衝器動作(第8圖(L))。 又,試驗狀態702之繪出端由於透過電胆7〇8及716接 地,所以此輸出端之電位,如第8圖(Μ)所示,變成0V。 且說,當試驗狀態缓衝器700當做單純之缓衝器作用 時,輪出自電壓比較器50之反相_出端的信號則透過電阻 本紙張尺度適用中國國家標準(CNS )八4規格(210X29>7公釐) --------一--裝------訂-----I線 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標隼局員工消費合作社印裝 A7 B7 五、發明説明(17 ) 710而輪入於蓮算放大器7〇4之反相_入端子。例如,當將 正極性脈衝餘入於運算放大器704之反相輪入端子時,蓮 算放大器704之輪出端子之電壓則隨此脈衝蝓入而降低。 又,在運算放大器704之反相輪入端子與接地間連接有電 容器704,而在蓮箕放大器704之輸出端子與反相輸入端子 間則連接有霄容器714,使得_出電壓被平滑化,因此, 如第8圖(N)所示,包含有蓮算放大器704之放大器則平穩 地降低對應於透過試驗狀態缓衝器輪入之脈衝寬度的份兒 之輪出電壓,即控制電壓。 在Μ上之動作下,回授至調諧電路1之控制電壓變低 而使調諧電路1之調諧頻率向低方變化。重覆這種控制, 直到調諧電路1之輸入信號之頻率與調諧頻率之镉差消失 為止,待經過一規定時間後,調諧頻率即與輸入信號之頻 率一致。 〔C-2.調諧頻率低於翰入信號之頻率時〕 第9圖係調諧電路1之調諧頻率低於輪入於調諧電路 1之信號之頻率的時序圖。 當調諧頻率低於調諧頻率1之輪入信號之頻率時,導 自兩個相移電路lioc,130C全體之相位位移量之合計為大 於360° ,因此,如觀察在某時刻之輪入於調諧電路1之 兩傾信號的話,變成第9圖(A),(Β)所示之相位關係。 從同步整流電路3内之電壓比較器32輪出與調諧電路 1之調諧輪出同步之信號(第9圖(C)>,於電平移相器34 反轉增大此信號同時進行規定電平位移(第9圖(E))。模 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 21 ----------襄------1T------^ (請先閱讀背面之注意事邛再填寫本頁) Α7 Β7 經濟部中央標準局員工消費合作杜印製 i、發明説明(18 ) 擬開關30係僅在電相移相器34之輪出信號之電壓電平為正 極性時讓調諧電路1之_入信號通過,所Μ變成第9圖(F) 所示之輸出波形。 因此,從脈衝變換電路5内之電壓比較器50,係在第 9圖<F)所示之輪出波形,於電壓電平成負極之時序,輪 出至0V,而於其Μ外之時序則輪出具有規定電壓之脈衝列 (第 9 圖(G))。 極性判別電路6内之兩値觸發霄路62,63之各個,一 如第9圃(D)及(Ε)所示,係用Μ取入輪出自同步整流電路 3内之電壓比較器32反相繪出端子的信號之0V部分(相當 於邐輯L),而從後段觸發電路63之輪出端子Q及其反相 輸出端子,一如第9圖(J),(10所示分別輪出邏輯L及通 輯Η之信號。 此觸發電路63之各_出信號,具有與第8圖相反之邏 輯狀態,而僅電壓合成電路7内之試驗狀態緩衝器702當 做缓衝器動作(第9圖(L),(Μ)〉。因此,於含有運算放大 器704之差動放大器之非反相翰入端子,輸入一具有規定 眤衝寬度之正極性脈衝,從此差動放大器向調諧電路翰出 之控制電壓則平穗地上升(第9圖(Ν)),使調諧電路1之 調諧頻率向高方變化。重覆這種控制*直到調諧電路1之 餘入信號之頻率與調諧頻率之偏差消失爲止,待經過規定 時間後,調諧頻率即與輓入信號之頻率一致。 如此,第1圖所示之調諧機構,係用來進行如除掉調 諧電路1之輪入輪出間相位差等之控制,俥使調諧頻率經 (請先閲讀背面之注意事項再填寫本頁) 裝. 訂 線 本紙張尺度適用中國國家標隼(CNS ) Α4規格(210Χ297公釐) 22 經濟部中央標準局員工消費合作杜印製 A7 __B7_ 五、發明説明(19 ) 常追隨輪入信號之頻率與之一致。因此,如將本實施形態 之調諧機構用於超外差式接收收信機時,可軽易使調諧頻 率相符於所_入之廣播波等之載波頻率。 又,實現本實施形態之調諧電路1及頻率控制電路2 ,係由觸發電路等之各種數字電路、蓮算放大器、電容器 、霄阻所構成。由於每一元件均可形成在半導體基片上, 所Μ可將調諧機構全體積體化於半導體基片上。 〔D.適用於AM收信機時之例子〕 其次,就把上述形態之調諧機構適用於AM牧信機之情 形說明之。由於第7圖所示之頻率控制電路2中包含有同 步整流電路3,所以如第10圖所示,使此同頻整流輸出通 過低通濾波器(LPF) 8,藉此可取出AM檢波信號。 一般而言,同步於某參考信號俾對於輪入信號進行轉 換(switching)之操作,可說等效於參考信號與輪入信號 之混頻。今,假定輪入信號爲頻率互相接近之第一及第二 信號,並將第一信號之頻率設為fl,將第二倍號之頻率設 為f2( = fl + A f〉。又,將參考信號之頻率設為fr。 如使用這種參考信號對輸入信號進行同步整流的話, 由於其相當於進行可用三角函數表示的各倍號彼此間之乘 法,故就結果而言,產生信號之頻率fl及f2與參考信號fr 之和及差之成分。因此,將輪入信號中之第一信號與參考 相乘,藉此顯出fl + fr、f卜fr之各頻率成分;且,將輪入 信號中之第二信號與參考信號相乘,藉此顯出fl + Af + fr 、:fl + Λ f-fr之各頻率成分。 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) I.n H 裝 訂 γ-Λ —線 (請先閱讀背面之注意事項再填寫本頁) A7 B7 五、 經濟部中央標準局員工消費合作社印製 發明説明(20 ) 今假定fr = fl,則藉箸相乘第一信號與參考信號,Μ 顯出2fl、0之各頻率成分;且藉著相乘第二信號與參考信 號Μ顯出2f + Af、Δί。因此,就同步整流餘出而言,顯 出2f + Af、2fl、Δί、0之各頻率成分。在此,所謂頻率 「0」之成分係指直流成分而言。實際上,在此直流成分 中含有調制信號,故分離此直流成分與其Μ外之交流成分 (2f + ^:f、2fl、後僅取出直流成分,藉此可同時利用 同步整流的檢波與調諧分離。 如上所述,由於輪出自低通濾波器8之信號為AM檢波 信號其本身,所Μ不需要另外設置AM檢波電路,可逹成電 路構成。 第11圖爲一楕成圖,係顯示利用第10圜所示的調諧機 構之AM收信機之構成。 高頻放大電路10,係用以高頻放大由天線16所接收的 AM波後_入於調諧電路1者。如上所述,調諧電路1,係 藉頻率控制霍路2來控制調諧頻率,侔使此調諧頻率吻合 於所輪入之AM波所具有的頻率。低頻放大電路12,係對於 輪出自低通濾波器8之信號(AM檢波信號〉進行低頻放大, 然後從揚聲器14綸出轚音。 〔E·適用於FM收信機時之例子〕 其次,就把本實施形態之調諧機構適用於FM收信機之 情形說明之。本實施形態之頻率控制電路2,係於調諧電 路1之輪入信號之頻率變化時,使追隨於該頻率變化藉以 回授至調諧電路1之控制電壓、變化者。因此,在原理上 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐) I ^—1 ^ 裝 111 訂— 111 —線—— (請先閲讀背面之注意事項再填寫本頁) 24 五、 發明説明(21 ) A7 B7 經濟部中央標準局員工消費合作杜印製 ,在此控制電壓中含有調諧電路1之輪入信號的頻率變化 ,卽FM波之調制信號與頻率成分;可將此當做FM檢波信號 使用。 第12圖係兼作FM檢波之調諧機構的楕成圖。又,第13 圖為一電路圖,係顯示第12圖所示之頻率控制電路2的詳 細構成。構成頻率控制電路2的同步整流電路3、脈衝變 換電路5及極性判別電路6之各詳細構成,係與第7圖所 示之各電路的詳細構成相同;電壓合成電路7A之構成則與 第7圖所示之電壓合成電路7有若干之差異。 電壓合成電路7A,係在兩個試驗狀態缓衝器700,702 之後段連接一含有蓮箄放大器704之第一差動放大器方面 ,與第7圖所示之電壓合成電路7相同。除此之外,電壓 合成電路7A,係將具有大致與上述第一差動放大器相同構 成之第二差動放大連接於兩個試驗狀態缓衝器700, 702之 後段。 此第二差動放大器,具體言之,包含有:蓮算放大器 724 ;回授電阻732,係插入在運算放大器724之反相輸入 端子與輸出端子間;電容器724 ,係並聯連接於該回授電 阻732 ;電阻736,係為了進行蓮算放大器724之二輸入間 之調整而插入在運算放大器724之非反相輸入端子與接地 間;電容器738,係並聯連接於該電胆736;及霉容器740 ,係連接於蓮算放大器724之反相輪入端子與接地間。 第一差動放大器,係用來調整跟回授電阻712並聯連 接的電容器等之靜電容量,以產生控制電壓俥使出現於蓮 (請先閲讀背面之注意事項再填寫本頁) -裝· 本紙張尺度適用中國國家標準(CNS ) A4規格(210 X 297公釐) 25 經濟部中央標隼局員工消費合作社印製 Α7 Β7 五、發明説明(22 ) 算放大器704輸出端之電壓平滑且流暢地變化;反觀*第 二差動放大器,係用來調整電容器734,738,740之靜電 容量,以便從出現於運算放大器724輪出端之霉壓除去的 20kHz以上之高頻成分。因此,可從第二差動放大器取出 約20kHzM下之頻率成分,即FM音頻等之FM檢波信號。 就包含有第13圖所示之調諧機構的FM收信機全體之構 成而言,可直接適用第11圖所示的收信機之構成之大部分 (低通濾波器8並不需要)。如考慮文字等之各種數據用 做FM調制信號時,將低頻放大霄路12之後段置換為數據處 理電路即可。 如此,調整平滑電路(含在頻率控制電路2内之電壓 合成電路7A之差動放大器中)之時間常數,藉此可輕易只 取出FM調制信號,因而不箱要另外設置之FM檢波電路,可 使電路構成簡素化。 又,於第13圖所示之調諧機構中,由於使用頻率控制 電路2中所包含之脈衝變換電路5,來變換對應於相位變 化量之脈衝寬度,所以沒有振幅變動之影W,Μ往必需之 限幅器電路也變成不需要。 〔F.頻率控制電路之其他例] 其次,說明有關第1圖所示之頻率控制電路2之其他 構成例。第7圖中顯示詳細構成之頻率控制電路2內之電 壓合成電路7,雖使用了試驗狀態缓衝器,但使用其Μ外 之元件也可。 第14圖係顯示頻率控制電路之其他構成例的詳細電路 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X 297公釐) 26 I I n 訂 1111 ~線 ί ( (請先閱讀背面之注意事項再填寫本頁) A7 B7 經濟部中央標準局員工消費合作社印装 五、發明説明(23 ) 圖,其具有將第7圖所示之電壓合成電路7置換爲電壓合 成電路7B。第14圖所示之電壓合成電路7B,包含有:兩個 附有倒相器之”非或”閘744,746,係用Μ反轉輸入於兩個 鑰入端之信號以求出它們之邏輯積;差動放大器,係於内 部含有蓮算放大器704;及偏壓電路,係於内部含有可變 電胆706。 其次,說明有開第1圖所示的頻率控制電路之其他構 例。第7圖所示之電壓合成電路7 *雖使用試驗狀態緩衝 器,或第14圖所示之電壓合成電路7Β雖用”非或”來構成, 但使用模擬開關以替代這些元件也可。 第15圖係顯示頻率控制電路之其他構成的電路圖、其 具有將第7圖所示之同步整流電路3、眤衝變換電路5、 極性判別電路6及電壓合電路7,分別置換為同步整流電 路3Α、脈衝變換電路5Α、極性判別電路6Α及電壓合成電路 7C之構成。 同步整滾電路3Α包含有模擬開關(AS) 35及電壓比較器 36。此電壓比較器36之反相輪入端子被接地,當輪入於非 反相轤入端子之信號的霣位大於0V時,輪出端則變成正之 規定電平,反之,小於0V時輸出端則變成負之規定電壓電 平。即,使用這種電壓比較器36,藉此可在不使用第7圖 所示之電平移柑器34下,產生正負兩極性之電壓。 脈衝變換電路5A,具有將第7圖所示之電壓比較器50 置換為電壓比較器58之構成;此電壓比較器58,係於輪入 於非反相輓入端子之同步整流輪出之霍壓電平小於0V時繪 I . 訂 I I I —-'. 一 ( (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標率(CMS ) Α4規格(210XW7公釐) 27 -07 - 經濟部中央標準局員工消費合作社印製 297185 at Β7 五、發明説明(24 ) 出負極性之脈衝,而於同步整流輸出之電壓電平為0V或正 極性時,輪出信號之電壓電平變成0V。 極性判別電路6A,包含有:電壓比較器64,係用Μ輪 出具有正Α兩極性之電壓狀態的脈衝列;兩個倒相電路65 ,66,係作為延遲電路動作;及兩値觸發電路67 , 68。 於電壓比較器64之兩値輪入端子,輪入跟輪入於上述 電壓比較器58之兩値輸入端子的信號相同之信號;電壓比 較器64則按照這些輸入電壓之電壓比較結果,輪出具有正 極性或負極性之電壓狀態的脈衝列。 又,兩個倒相電路65,66及兩個觸發電路67,68,係 對應於第7圖所示之兩値倒柑電路60, 61及兩個觸發電路 62, 63 ,在基本上進行同樣之動作,然而暹輯Η對應於規 定正電壓及邏辑L對應於規定負電壓方面*卻相異。 電壓合成電路7C,包含有:兩個模擬開闋(AS)750、 752;由運算放大器754及兩電阻756、758所構成之第一反 相放大器;由運算放大器及二電阻764 , 766所構成之第二 反相放大器;為使該第二反相放大器之餘出鼋平平滑而並 聯連接於電阻766之電容器768 ·,及由連接於正灸電源Vdd ,Vss間之可變電阻770及電阻772所構成之偏壓電路。 一方之模擬開關750 ,係隨輸出自後段《發電路68之 綸出端子Q的信號之電®電平,而進行開蘭之接通/斷開 動作。當輓出自輸出端Q之信號的通輯為Η,即,外加有 正極性之規定電壓時,模擬開關750則透過電阻756將輪出 自脈衝變換霉路5Α内之電壓比較器58的信號,输入於第一 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X 297公釐) 28 --------^—裝------訂-----線 (請先閲讀背面之注意事項再填寫本頁) A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明(25 反相放大器。 第一反相放大器,係用來反轉輓出自此模擬開關750 之信號的電壓極性,然後透過電阻762將反轉此電壓極性 之信號輪入於第二反相放大器。 又,另一方之模擬開關放大器752 ,係隨輪出後段觸 發電路68 (極性判別電路6A内)之反相輪出端子的信號之 電壓電平,而進行開關之接通/斷開動作。當輪出自反相 繪出端子之信號的邐輯,即外加有正之規定電壓時,模擬 開關752則透過電阻754將輪出自脈衝變換電路5A内之電壓 比較器58的信號,轤入於第二反相放大器。 於第二反相放大器之反柑輸入端子連接有:其一端連 接第一反相放大器之輓出端的電阻762;其一端連接由電 阻770所構成之偏壓電路的電阻772;及其一端連接模擬開 關752之輸出端的電阻764。第二反相放大器,係將所加法 之電壓極性再予反轉。又,與此反轉動作同時進行藉肋於 電容器768之電壓平滑化。 其次,說明有關第1圈所示之頻率控制電路的其他構 成例。第16圖係顯示頻率控制電路之其他構成例的詳細電 路圖;其具有將第15圖所示之脈衝變換電路5A、極性判別 電路6A及電壓合成電路7C,分別置換爲脈衝變換電路5B、 極性判別電路6B及電壓合成電路7D之構成。J — line t. 12 V. Description of the invention (9) A7 B7 Printed by the consumer cooperation of the Central Standards Bureau of the Ministry of Economic Affairs. Among them, T2 is the time constant of the CR circuit formed by the capacitor 134 and the resistance 136, s = j < u , A2 is the gain of the phase shift circuit 130C, that is, a2 = (l + R41 / R43)> 1. However, R41 is the resistance value of the resistor 141, and R43 is the resistance value of the resistor 143. It can be seen from the equation (2) that the phase shift circuit 130C is a full band-pass circuit, and its output amplitude is constant regardless of the frequency; the phase shift amount 42 is based on the M-in signal and changes clockwise from 0 ° to 180 °. Also, the phase shift circuit 130C can broadcast a gain greater than 1 by adjusting the resistance values of R41 and R43. In this way, each of the two phase shift circuits 110C, 130C shifts the phase by a predetermined amount. As a result, as shown in FIG. 4 and FIG. 6, the phase shift amount of the entire tuning circuit 1 at a predetermined frequency becomes 360 °. At this time, the loop gain of the feedback loop derived from the two-valued phase shift circuits 110C, 130C, the voltage dividing circuit 160 and the feedback resistor 170 is set at 1 μM, thereby performing only the above-mentioned predetermined frequency component Tuning action. Also, since the output terminal 192 of the tuning circuit '1 shown in FIG. 2 is taken out, the output of the phase shift circuit 130C before entering the voltage divider circuit 160 is taken out, so that the tuning circuit 1 itself can have a gain and can be carried out. Amplify the amplitude of the doubling sign while tuning. In addition, from equations (1) and (2>), the inflammatory 1, Φ 2 shown in Figs. 4 and 6 are obtained, then the required 1, 0 2 can be obtained from the following equations (3) and (4) Φ l = tan {2ω Τι / (1-ω 2 Τ ι2)} ... (3) 0 2 = tan {2 α > Tz / (1-ω 2Ta 2)} ... (4), then ω = 1 / At the time of Τ, it is derived from the two phase shifts of the II position (please read the precautions on the back before filling in this page). Packed. The size of the paper is applicable to the Chinese National Standard (CNS) Α4 specification (210Χ297 mm) 13 mm Α7 Β7 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of invention (10) The total amount of displacement becomes 360 ° and the above tuning operation is performed. In this case, 1 = 270 ° and Yan 2 = 90 °. On the one hand, such as When the frequency of the signal input to the previous phase shift circuit 110C is lower than the frequency (tuned frequency) which is the sum of the phase shift amount of the two phase shift circuits combined into 360 °, the result of adding the above 4 1 and 4 2 is It will not become 360 °. In this case, the phase shift amount 0 1 of the front phase shift circuit 110C becomes less than 270 °, and the phase shift amount 0 2 of the rear phase shift circuit 130C becomes less than 90 °. The total phase shift amount is then become Less than 360 °. At this time, if you want to make the tuning frequency close to the frequency of the actual signal, increase the above 4 1, 4 2. Specifically, as long as the change shown in Figure 2 The voltage VR1 at both ends of the resistor 116 may be increased. On the one hand, if the frequency of the signal input to the previous phase shift circuit 110C is higher than the tuning frequency, the result of adding the above-mentioned inflammations 1 and 2 will not become 360 ° In this case, the phase shift amount 0 1 of the front stage phase shift circuit 110C becomes greater than 270 °, the phase shift amount 2 of the K and the rear stage phase shift circuit 130C becomes greater than 90 °, and the total phase shift amount of M becomes greater than 360 ° At this time, if you want to make the tuning frequency close to the frequency of the actual input signal, you can reduce the absolute value of the above 4 1. The specific value * as long as the variable resistor 116 shown in Figure 2 The voltage VR1 at both ends needs to be reduced. As explained above, in the tuning circuit 1 shown in FIG. 2, two phase shift circuits lioc and 130C are connected in cascade to make it possible to change the phase shift circuit 110C. The resistance value of the variable resistor 116, so even if the input signal into the tuning channel 1 The frequency of the number is different from the tuning frequency, and it can also make the tuning frequency really match the frequency of the incoming signal. This paper standard is applicable to the Chinese National Standard Falcon (CNS) Μ specification (210Χ297mm) (please read the notes on the back before filling in this Page). Installation · Order 14 Printed by the Ministry of Economic Affairs Central Sample Falcon Bureau Employee Consumer Cooperative A7 B7 V. Description of the invention (11) In addition, in the tuning circuit 1 shown in Figure 2, due to the use of the sub-scratch circuit 160 to The attenuated signal is used as the feedback signal. At the same time, the signal before the input voltage divider circuit 160 is taken as the turn-out of the tuning circuit 1. Therefore, the tuning operation of extracting only a predetermined frequency component from the input signal can be performed. The signal is amplified as specified. Also, in the tuning circuit 1 shown in FIG. 2, since the resistance values of the resistor 118 and the resistor 120 in the phase shift circuit 110C are set to the same value, the resistances of the resistor 138 and the resistor 140 in the phase shift circuit 130 are simultaneously set The value is set to the same value, so even if the tuning frequency is changed, there will be no amplitude variation in the tuning round. Therefore, the Q of the tuning circuit 1 can be improved by increasing the resistance ratio η of the feedback resistance 170 to the input resistance 174. That is, if the loop gain has a frequency dependency, at a frequency where the gain is low, Q will not increase even if the resistance is increased, but at a frequency where the gain is high, the loop gain may exceed 1 and oscillate. Therefore, if the amplitude variation is large, the resistance ratio η cannot be set to an excessive value in order to prevent such oscillation, and the Q value of the tuning circuit 1 also becomes small. On the one hand, in the tuning circuit shown in FIG. 2, since the phase shift circuits 110C and 130C include separate circuits, even if the resistance ratio η is set to a large value, the tuning circuit 1 will not tune out Amplitude fluctuations occur, so the resistance ratio can be increased by increasing M to increase the Q value. [C. Detailed structure and operation of the frequency control circuit] FIG. 7 is a circuit diagram showing the structure of the frequency control circuit 2. It shows the detailed structure of the synchronous rolling circuit 3, the pulse conversion circuit 5, the polarity discrimination circuit 6, and the voltage synthesis circuit 7. The size of this paper is applicable to the Chinese National Standard (CNS) Α4 specification (210 X 297 mm) _ 1 R _ i Pack II —— I —__ 线 ί ί (please read the precautions on the back and fill in this page) V. Description of the invention (l2 A7 B7 Employee Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs printed synchronous rectifier circuit 3, including: analog switch (AS) 30; voltage comparator 32; level shifter (LS) 34. Yu voltage comparator 32 One side draws the output signal of the tuning circuit 1 and the other input terminal is grounded. The output of the voltage comparator 32 changes to L level when the potential of the rounding signal of the tuning circuit 1 is greater than 0V ( For example, 0V), conversely, when the potential of the output signal of the tuning circuit 1 is below 0V, it becomes the H level (for example, a prescribed positive voltage). In addition, the voltage comparator 32 has an output logic in addition to the above-mentioned round output terminal The inverting wheel output end of the inverted signal; this inverting wheel output end is connected to the polarity discrimination circuit 6 described later. The level shifter 34 performs the polarity inversion on the signal output from the voltage comparator 32 at the same time, and performs Translational displacement and will have a positive The negative voltage square wave of the mildew is used as the reference signal. The analog switch 30 operates in synchronization with the reference signal output from the level shifter 34; for example, when the rectangular wave of the reference signal is the positive voltage level , Let the pull-in signal of the tuning circuit 1 pass, and conversely, when the voltage of the polarity is low, the turn-in signal of the tuning circuit 1 is interrupted. The pulse conversion circuit 5 includes: a voltage comparator 50; and resistors 52, 54 Into a voltage divider circuit. At the input of one side of the voltage comparator 50, the output signal of the wedge-like switch 30 in the synchronous rectifier road 3; and at the input of the other side, the input is made by resistors 52 and 54 The voltage divider of the voltage divider circuit comes out. One side of the resistor 52 is grounded; and one side of the resistor 54 is connected to the power supply Vss; at this time, the resistance value of the resistor 54 is set to be greater than the resistance value of the resistor 52 (For example, about 100 times), the voltage of the inverting inverting terminal of the voltage comparator 50 is set to be slightly lower than 0V. ---------- Install-(Please read the note 4 on the back first ^ · Fill in this page again) China's national standards apply CNS) A4 specification (210X 297 mm) 16 Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Α7 Β7 V. Description of the invention (13) As mentioned above, when the frequency of the signal input by the tuning circuit 1 is the same as the tuning frequency , The rounded waveform of the synchronous rectifier circuit 3 becomes a complete half-wave rectified waveform, so M will not become negative. However, when the frequency of the input signal and the tuning frequency are shifted by cadmium, the timing corresponding to this offset, The output of the synchronous rectification generates a negative voltage component, and when this negative voltage component is generated, the voltage comparator 50 in the pulse conversion circuit 5 turns to the L level. The polarity discrimination circuit 6 includes: two-valued inverter circuits 60, 61; and two-valued D-type trigger circuits 62, 63. In this embodiment, the delay circuit is formed by two inverter circuits 60, 61, and the voltage comparator 50 in the pulse conversion circuit 5 is made out of two inverter circuits 60, 61 connected in cascade. Enter the clock terminals of the trigger Xiaolu 62,63. At the D_input terminal of the D-type trigger circuit 62, a signal with the same timing and different levels as the reference signal of the synchronous rectifier circuit 3 is input. The signal input to the D input terminal is locked in synchronization with the rising edge of the pulse train pulled out from the pulse conversion circuit 5, and then input to the D input terminal of the secondary D-type circuit 63. Thereby, the secondary D-type trigger circuit 63, according to the pulse train from the voltage comparator 50 in the pulse conversion circuit 5, turns out whether a phase difference between the input and output signals of the tuning circuit 1 is greater than or less than 360 The pressure of ° H or L Xiaoping. The voltage synthesis circuit 7 includes: two-dip test state buffers 700, 702; a differential amplifier; and a variable bias® circuit. Among them, the differential amplifier includes an operational amplifier 704; and the variable bias circuit includes a variable electrical paper. The paper standard is applicable to the Chinese National Standard (CNS) Α4 specification (210 X 297 mm) 17 ^ binding ^ I line (please (Read the precautions on the back before filling this page) 5. 185 A7 B7 Description of Invention (u) Printed Block 706 by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. In the test state buffer 700, the wheel-out terminal is connected to the inverting input terminal of the differential amplifier through a resistor 710. The test state buffer 700 operates according to the signal from the output terminal Q of the trigger circuit 63 in the polarity discriminating circuit 6, for example, when the logic of this signal is H, the input signal is directly rotated, otherwise, the logic of this signal When it is L, the wheel-out terminal is made into a high-impedance state. Similarly, the test state buffer 702 has its input terminal connected to the inverting wheel output terminal of the voltage comparator 50 in the pulse conversion circuit 5, and its wheel output terminal is connected to the non-inverting differential amplifier through a resistor 708 Turn in the terminal. The test state buffer 702 operates in accordance with the signal logic of the inverse wheel out terminal of the later stage trigger circuit 63 in the polarity discrimination circuit 6, for example, when the logic of this signal is Η, the signal in turn is directly wheeled out, otherwise When the operation of this signal is L, the round out end is made into a high impedance state. The differential amplifier is to input each wheel output of the above two test state buffers 700 and 702 to the differential wheel input terminal respectively, and amplify the equal difference M at a predetermined amplification rate while performing a predetermined smooth operation M to remove high frequency components To generate control voltage. This differential amplifier, specifically, in addition to the operational amplifier 704M, includes: a feedback resistor 712, which is inserted between the inverting input terminal and the output terminal of the lotus amplifier 704; a capacitor 714, which is connected in parallel to the feedback Resistor 712; Resistor 716 is used to divide the voltage level of the signal from the test state buffer 702 in order to adjust the two rounds of the lotus amplifier 704, for which the lotus amplifier 704 is inserted Reverse _ The standard of this paper is applicable to China National Standard Falcon (CNS) Α4 specification (210X297mm) (please read the precautions on the back before filling this page) -installation-, τ Cooperative Society printed A7 B7 5. Description of the invention (15) Between the terminal and ground; capacitor 718, connected in parallel to the resistor 716; and capacitor 720, inserted between the inverting input terminal of the operational amplifier 704 and ground. The inverting inverting terminal of the lotus amplifier 704 is connected to the movable terminal of the variable resistor 706 through the resistor 722; the two fixed terminals of the variable resistor 706 are connected to the positive power supply Vdd and the negative power supply Vss Therefore, according to the bias circuit formed by the variable resistor 706, the specified bias circuit is set at the wheel-out end of the lotus amplifier. Furthermore, if the variable resistor 706 is actually formed on the semiconductor base On-chip, it can be formed by active components such as FET. This bias circuit is used when the tuning frequency of the tuning circuit 1 is the same as the frequency of the pull-in signal. It is used to set the variable resistor 116 (included in the tuning The voltage of the gate of one of the phase shift circuits 110C) in circuit 1. [C-1. When the tuning frequency is higher than the frequency of the run-in signal] Figure 8 shows that the tuning frequency of the tuning circuit 1 is higher than the input to the tuning circuit 1. Timing diagram of the frequency of the signal. If the tuning frequency is higher than the frequency of the pull-in signal of the tuning circuit 1, the sum of the phase shifts from the two phase shift circuits 110C and 130C is less than 360 °. Therefore, if observed in The two signals rounded into the tuning circuit 1 at a certain moment become the phase relationship shown in (A) and (B) of Figure 8. The voltage comparator 32 in the synchronous rectifier circuit 3 is as shown in Figure 8 ( C) As shown, it has the same frequency and phase as the tuning wheel output, And only when the voltage level of the tuning wheel is positive, a rectangular wave of L level is output. The level shifter 34, as shown in FIG. 8 (C >, uses the M inverting voltage comparator 32 At the same time, the voltage level conversion is carried out at the same time, then, as the first paper standard is applicable to the Chinese National Standard (CNS) Μ specification (210 X 297 mm), "-19-I binding ^ I Λ &. (Please read first Please pay attention to the back and fill in this page) A7 B7 printed by the consumer cooperation of the Central Standards Bureau of the Ministry of Economic Affairs V. Invention description (16) 8 As shown in Figure (E), the output has positive and negative voltage states with equal absolute values Rectangular wave. The analog switch 30, as shown in Fig. 8 (F), uses the zero crossing point of the tuning wheel as a reference, and only takes out the wheel-in signal input to the tuning circuit 1 at a predetermined time. Specifically, the input signal is taken out at a timing faster than the timing at which the upper half of the tuning wheel is taken out. As shown in FIG. 8 (G >), the voltage comparator 50 becomes yin ping only when the voltage level of the analog switch 30 is lower than 0v. The polarity judgment circuit 62 in the previous stage of the polarity discrimination 6 As shown in Figure 8 (I>, the timing of the signal rise after the round of the voltage comparator passes through the two-phase inverter circuits 60, 61 is taken in_out from the voltage comparator 32 in the synchronous rectifier road 3 After inverting the logic of the signal of the round-out terminal, it is held. The trigger circuit 63 in the latter stage is as shown in FIG. 8 (< 0 and (K), then, the output of the voltage comparator 50 is changed from L The timing of rising from H level to the H level is taken after the round of the trigger circuit 62 in the previous stage is added and maintained by M. When the tuning frequency is higher than the frequency of the multiple of the tuning circuit 1, the output terminal Q of the trigger circuit 63 in the latter stage The signal of pass H is rounded out, and the signal of pass L is output from the inverted turn-out terminal Q. Therefore, the rounded end of the test state buffer 702 becomes a high impedance state, and only the test state buffer 700 is used as a buffer Device operation (Figure 8 (L)). In addition, the drawn end of the test state 702 is transmitted through the electric bladder 7〇8 716 is grounded, so the potential of this output terminal becomes 0 V as shown in FIG. 8 (M). Furthermore, when the test state buffer 700 acts as a simple buffer, the inversion from the voltage comparator 50 occurs _The signal at the end is through the resistance. The paper standard is applicable to the Chinese National Standard (CNS) 84 specifications (210X29> 7mm) -------- One--installed ------ order ---- -I line (please read the precautions on the back and then fill out this page) A7 B7 printed by the Employee Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs 5. Invention description (17) 710 and it is the inversion of the Lotus Amplifier 7〇4 _Input terminal. For example, when a positive-polarity pulse is left in the inverting input terminal of the operational amplifier 704, the voltage of the output terminal of the lotus arithmetic amplifier 704 decreases as the pulse enters. Also, in the operational amplifier 704 A capacitor 704 is connected between the inverting inverting terminal and the ground, and a small container 714 is connected between the output terminal and the inverting input terminal of the lotus dust amplifier 704, so that the output voltage is smoothed. Therefore, as shown in FIG. 8 (N), the amplifier including lotus amp 704 is smoothly lowered corresponding to the transparent After the test state, the pulse width of the pulse width of the buffer is the control voltage. Under the action of M, the control voltage fed back to the tuning circuit 1 becomes lower, causing the tuning frequency of the tuning circuit 1 to The low side changes. Repeat this control until the difference between the frequency of the input signal of the tuning circuit 1 and the cadmium of the tuning frequency disappears, and after a specified period of time, the tuning frequency is consistent with the frequency of the input signal. [C-2. When the tuning frequency is lower than the frequency of the incoming signal] Figure 9 is a timing diagram of the tuning frequency of the tuning circuit 1 being lower than the frequency of the signal rounded into the tuning circuit 1. When the tuning frequency is lower than the rounding signal of the tuning frequency 1 At the frequency, the sum of the phase shifts of the entire 130C from the two phase shift circuits lioc and the total of the 130C is greater than 360 °. Therefore, if you observe the bi-tilt signal that is tuned to the tuning circuit 1 at a certain time, it becomes Figure 9 ( A), (B) shows the phase relationship. From the voltage comparator 32 in the synchronous rectifier circuit 3, a signal synchronized with the tuning wheel of the tuning circuit 1 is output (Figure 9 (C)>, the signal is reversed and increased at the level shifter 34 while the predetermined power Horizontal displacement (Figure 9 (E)). The size of the model paper is in accordance with the Chinese National Standard (CNS) A4 specification (210X297 mm) 21 ---------- Xiang ----- 1T-- ---- ^ (Please read the precautions on the back before filling in this page) Α7 Β7 Employee's consumer cooperation with the Central Bureau of Standards of the Ministry of Economic Affairs du printed i. Invention description (18) The proposed switch 30 is only in the electrical phase shifter When the voltage level of the round-off signal of 34 is positive, let the input signal of the tuning circuit 1 pass through, so that M becomes the output waveform shown in FIG. 9 (F). Therefore, the voltage comparator in the pulse conversion circuit 5 50. It is the rounded waveform shown in FIG. 9 < F). When the voltage level becomes negative, the round is rounded to 0V, and the timing outside it is rounded to the pulse train with the specified voltage (9th). Figure (G)). The two values in the polarity discriminating circuit 6 trigger each of the small roads 62 and 63, as shown in the ninth garden (D) and (E). The 0V part of the signal of the terminal is drawn (equivalent to the L series), and the rounded terminal Q and its inverted output terminal of the trigger circuit 63 from the rear stage, as shown in Figure 9 (J), (10 respectively Signals of logic L and pass H. Each output signal of the trigger circuit 63 has a logic state opposite to that of FIG. 8, and only the test state buffer 702 in the voltage synthesis circuit 7 acts as a buffer (the first Figure 9 (L), (Μ)>. Therefore, at the non-inverting input terminal of the differential amplifier containing the operational amplifier 704, a positive polarity pulse with a specified pulse width is input, from which the differential amplifier is directed to the tuning circuit. The outgoing control voltage rises flatly (Figure 9 (N)), causing the tuning frequency of the tuning circuit 1 to change to a high level. Repeat this control * until the frequency of the remaining signal of the tuning circuit 1 and the tuning frequency Until the deviation disappears, after the specified time has passed, the tuning frequency is the same as the pull-in signal The frequency is the same. In this way, the tuning mechanism shown in Figure 1 is used to perform control such as removing the phase difference between the rounds and rounds of the tuning circuit 1, so that the tuning frequency can be controlled (please read the notes on the back first (Fill in this page again) Packing. The paper size of the binding book is applicable to the Chinese National Standard Falcon (CNS) Α4 specification (210Χ297 mm). 22 Central China Bureau of Economic Affairs Employee Consumer Cooperation Du Printed A7 __B7_ V. Invention Instructions (19) Often follow The frequency of the turn-in signal is consistent with it. Therefore, if the tuning mechanism of this embodiment is used in a super-heterodyne receiver, the tuning frequency can be easily matched to the carrier frequency of the incoming broadcast wave. The tuning circuit 1 and the frequency control circuit 2 implementing this embodiment are composed of various digital circuits such as a trigger circuit, a lotus arithmetic amplifier, a capacitor, and a small resistance. Since each element can be formed on a semiconductor substrate, the M The tuning mechanism can be integrated into a semiconductor substrate in its entire volume. [D. Example when applied to an AM receiver] Next, the case where the above-mentioned tuning mechanism is applied to an AM pastoral machine is explained. Since the frequency control circuit 2 shown in Fig. 7 includes a synchronous rectifier circuit 3, as shown in Fig. 10, the same-frequency rectified output is passed through a low-pass filter (LPF) 8, whereby the AM detection can be taken out Generally speaking, synchronizing with a reference signal to switch the round-off signal can be said to be equivalent to the mixing of the reference signal and the round-off signal. Today, it is assumed that the round-off signal is close to each other in frequency The first and second signals, and set the frequency of the first signal to fl, and the frequency of the second multiple to f2 (= fl + A f>. Also, set the frequency of the reference signal to fr. If you use this If the reference signal synchronously rectifies the input signal, it is equivalent to multiplying the multiples that can be expressed by the trigonometric function. Therefore, as a result, the sum and difference of the frequency fl and f2 of the generated signal and the reference signal fr Ingredients. Therefore, multiply the first signal in the round signal by the reference, thereby showing the frequency components of fl + fr and f bu fr; and, multiply the second signal of the round signal by the reference signal, by This shows the frequency components of fl + Af + fr and fl + Λ f-fr. This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) In H binding γ-Λ-line (please read the precautions on the back before filling this page) A7 B7 V. Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Printed description of the invention (20) Now suppose fr = fl, then by multiplying the first signal and the reference signal by M, M shows the frequency components of 2fl and 0; and by multiplying the second signal and the reference signal by M 2f + Af, Δί. Therefore, in terms of the synchronous rectification residual, each frequency component of 2f + Af, 2fl, Δί, and 0 appears. Here, the component of frequency "0" refers to the DC component. In fact, this DC component contains a modulated signal, so after separating this DC component from its AC component (2f + ^: f, 2fl, and only taking out the DC component, it can simultaneously use synchronous rectified detection and tuning separation As mentioned above, since the signal from the low-pass filter 8 is the AM detection signal itself, there is no need to additionally install an AM detection circuit, and it can be formed into a circuit configuration. Figure 11 is a graph, which shows the use of The structure of the AM receiver of the tuning mechanism shown in the tenth circle. The high-frequency amplifying circuit 10 is used to amplify the AM wave received by the antenna 16 at a high frequency and enter the tuning circuit 1. As described above, tuning The circuit 1 controls the tuning frequency by the frequency control channel 2, so that the tuning frequency is consistent with the frequency of the AM wave that is rounded. The low-frequency amplification circuit 12 is for the round signal from the low-pass filter 8 ( AM detection signal> Amplify the low frequency, and then make a loud noise from the speaker 14. [E · Example when applied to FM receiver] Next, the case where the tuning mechanism of this embodiment is applied to an FM receiver will be explained .This implementation The frequency control circuit 2 is in the state that when the frequency of the turn-in signal of the tuning circuit 1 changes, the control voltage or change that follows the frequency change is fed back to the tuning circuit 1. Therefore, in principle, the paper size is applicable China National Standard (CNS) A4 Specification (210X 297mm) I ^ —1 ^ Pack 111 Order—111—Line—— (Please read the precautions on the back before filling in this page) 24 V. Description of the invention (21) A7 B7 Du-printed by the consumer cooperation of the Central Standards Bureau of the Ministry of Economic Affairs. This control voltage contains the frequency change of the turn-in signal of the tuning circuit 1, and the modulation signal and frequency component of the FM wave; it can be used as an FM detection signal. Fig. 12 is a diagram of the tuning mechanism that doubles as the FM detection. Fig. 13 is a circuit diagram showing the detailed structure of the frequency control circuit 2 shown in Fig. 12. The synchronous rectifier circuit 3 constituting the frequency control circuit 2, The detailed structures of the pulse conversion circuit 5 and the polarity discrimination circuit 6 are the same as the detailed structures of the circuits shown in FIG. 7; the structure of the voltage combining circuit 7A is the same as the voltage combining circuit shown in FIG. 7. 7 There are some differences. The voltage synthesis circuit 7A is connected to a first differential amplifier including a lotus amplifier 704 after the two test state buffers 700 and 702, and is similar to the voltage synthesis circuit shown in FIG. 7 7 is the same. In addition, the voltage synthesis circuit 7A connects the second differential amplifier having the same configuration as the above-mentioned first differential amplifier to the two test state buffers 700 and 702. This second The differential amplifier, specifically, includes: lotus amp 724; a feedback resistor 732 is inserted between the inverting input terminal and the output terminal of the operational amplifier 724; a capacitor 724 is connected in parallel to the feedback resistor 732; The resistor 736 is inserted between the non-inverting input terminal of the operational amplifier 724 and the ground for adjustment between the two inputs of the lotus operation amplifier 724; the capacitor 738 is connected in parallel to the electric bile 736; and the mold container 740 is It is connected between the inverting inverting terminal of the lotus operation amplifier 724 and the ground. The first differential amplifier is used to adjust the electrostatic capacity of the capacitor connected in parallel with the feedback resistor 712 to generate a control voltage so that it appears in the lotus (please read the precautions on the back before filling this page) -install The paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). 25 Printed by the Central Standard Falcon Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs. Α7 Β7. V. Invention Description (22) The voltage at the output of the operational amplifier 704 is smooth and smooth Change; in contrast * The second differential amplifier is used to adjust the electrostatic capacity of the capacitors 734, 738, 740 to remove high frequency components above 20 kHz from the mold pressure appearing at the round-off end of the operational amplifier 724. Therefore, the frequency component at about 20 kHzM, that is, the FM detection signal such as FM audio, can be taken out from the second differential amplifier. As for the overall configuration of the FM receiver including the tuning mechanism shown in Figure 13, most of the configuration of the receiver shown in Figure 11 can be directly applied (the low-pass filter 8 is not required). If various data such as characters are used as the FM modulation signal, it is sufficient to replace the lower section of the low-frequency amplification road 12 with a data processing circuit. In this way, adjust the time constant of the smoothing circuit (included in the differential amplifier of the voltage synthesis circuit 7A in the frequency control circuit 2), by which the FM modulation signal can be easily taken out, so there is no need to separately install an FM detection circuit. Simplify the circuit configuration. Also, in the tuning mechanism shown in FIG. 13, since the pulse conversion circuit 5 included in the frequency control circuit 2 is used to convert the pulse width corresponding to the phase change amount, there is no shadow of the amplitude variation W, M The limiter circuit also becomes unnecessary. [F. Other Examples of Frequency Control Circuit] Next, another configuration example of the frequency control circuit 2 shown in FIG. 1 will be described. Fig. 7 shows the voltage synthesizing circuit 7 in the frequency control circuit 2 with a detailed structure. Although the test state buffer is used, it is also possible to use components other than the M. Figure 14 shows the detailed circuit of other configuration examples of the frequency control circuit. The paper size is applicable to the Chinese National Standard (CNS) Α4 specification (210X 297mm) 26 II n order 1111 ~ line ((Please read the notes on the back first (Fill in this page again) A7 B7 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy 5. Description of invention (23) The figure has the voltage synthesis circuit 7 shown in FIG. 7 replaced with a voltage synthesis circuit 7B. The voltage synthesis circuit 7B shown includes: two NOR gates 744, 746 with inverters, which use M to reverse the signals input to the two key inputs to find their logical product; the difference The dynamic amplifier, which contains the lotus amplifier 704 inside, and the bias circuit, which contains the variable battery 706. Secondly, another configuration example of the frequency control circuit shown in Fig. 1 is described. Fig. 7 The voltage synthesizing circuit 7 shown * * Although a test state buffer is used, or the voltage synthesizing circuit 7B shown in FIG. 14 is configured with an "OR", an analog switch may be used instead of these components. Figure 15 Show the frequency control circuit The circuit diagram constituted by him includes the synchronous rectifier circuit 3, the pulse conversion circuit 5, the polarity discrimination circuit 6 and the voltage combining circuit 7 shown in FIG. 7 respectively, which are replaced by the synchronous rectifier circuit 3Α, the pulse conversion circuit 5Α, and the polarity discrimination The circuit 6A and the voltage synthesis circuit 7C. The synchronous rolling circuit 3A includes an analog switch (AS) 35 and a voltage comparator 36. The inverting input terminal of this voltage comparator 36 is grounded, when the input is non-inverting When the signal of the input terminal is greater than 0V, the round output terminal becomes a positive prescribed level, otherwise, the output terminal becomes a negative prescribed voltage level when it is less than 0V. That is, using this voltage comparator 36, thereby It is possible to generate voltages of positive and negative polarities without using the level shifter 34 shown in Fig. 7. The pulse conversion circuit 5A has a configuration in which the voltage comparator 50 shown in Fig. 7 is replaced with a voltage comparator 58; This voltage comparator 58 is drawn when the Huo voltage level of the synchronous rectifier wheel wheeled in the non-inverting pull-in terminal is less than 0V. I III--'. I ((Please read the notes on the back before reading (Fill in this page) This paper size Printed at 297185 at Β7 using the Chinese National Standard Rate (CMS) Α4 specification (210XW7mm) 27 -07-Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs V. Invention description (24) A negative polarity pulse is output, and the output is synchronous rectified When the voltage level is 0V or positive polarity, the voltage level of the rounding signal becomes 0V. The polarity discrimination circuit 6A includes: a voltage comparator 64, which uses Μ to round out a pulse train having a voltage state of positive A and two polarities ; Two inverter circuits 65, 66, acting as a delay circuit; and two-value trigger circuits 67, 68. The two values in the voltage comparator 64 are rounded into the terminals, and the rounded and rounded in the two of the above voltage comparator 58 The signals of the input terminals are the same; the voltage comparator 64 turns out pulse trains with positive or negative voltage states according to the voltage comparison results of these input voltages. In addition, the two inverter circuits 65, 66 and the two trigger circuits 67, 68 correspond to the two-value inverter circuits 60, 61 and the two trigger circuits 62, 63 shown in FIG. 7, basically the same The action, however, differs in that the H corresponding to the specified positive voltage and the logic L corresponding to the specified negative voltage *. The voltage synthesis circuit 7C includes: two analog open gates (AS) 750, 752; a first inverting amplifier composed of an operational amplifier 754 and two resistors 756, 758; an operational amplifier and two resistors 764, 766 The second inverting amplifier; in order to smooth the rest of the second inverting amplifier, a capacitor 768 connected in parallel to the resistor 766, and a variable resistor 770 and a resistor connected between the positive moxibustion power supply Vdd and Vss The bias circuit formed by 772. The analog switch 750 on one side performs the ON / OFF operation of the open circuit in accordance with the electrical level of the signal output from the output terminal Q of the downstream circuit 68. When the signal output from the output terminal Q is H, that is, when a specified voltage of positive polarity is applied, the analog switch 750 will output the signal from the voltage comparator 58 in the pulse conversion mold 5A through the resistor 756 and input For the first paper size, the Chinese National Standard (CNS) Α4 specification (210X 297 mm) is applicable 28 -------- ^ — installed ------ ordered-line (please read first (Notes on the back and then fill out this page) A7 B7 Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Invention Description (25 Inverting Amplifier. The first inverting amplifier is used to invert the signal pulled from this analog switch 750 The polarity of the voltage is reversed, and the signal inverting the polarity of this voltage is rotated into the second inverting amplifier through the resistor 762. In addition, the analog switching amplifier 752 on the other side follows the round trigger circuit 68 (in the polarity discrimination circuit 6A) The voltage level of the signal of the inverse wheel terminal is reversed, and the on / off action of the switch is performed. When the signal of the signal drawn from the inverted terminal is reversed, that is, when a positive specified voltage is applied, the analog switch 752 is Through the resistor 754, the wheel will come out of the pulse change The signal of the voltage comparator 58 in the circuit 5A is input into the second inverting amplifier. The inverting input terminal of the second inverting amplifier is connected with: one end of which is connected to the resistor 762 of the pull-out end of the first inverting amplifier; One end is connected to the resistance 772 of the bias circuit formed by the resistance 770; and one end is connected to the resistance 764 of the output end of the analog switch 752. The second inverting amplifier inverts the polarity of the added voltage again. This reversal operation simultaneously smoothes the voltage by the capacitor 768. Next, another example of the configuration of the frequency control circuit shown in the first circle will be described. FIG. 16 is a detailed circuit diagram showing another example of the configuration of the frequency control circuit; It has a configuration in which the pulse conversion circuit 5A, the polarity determination circuit 6A and the voltage synthesis circuit 7C shown in FIG. 15 are replaced with the pulse conversion circuit 5B, the polarity determination circuit 6B and the voltage synthesis circuit 7D, respectively.

脈衝變換電路5B,包含有:電壓比較器59,係用以輸 入從同步整流電路3A内之模擬開關35輪出的同步整流輪出 ,於其非反相輸入端子;及分壓電路,係由外加稍低於0V 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐) 29 --------(—裝------訂-----^i線 (請先閲讀背面之注意事項再填寫本頁) A7 B7 五、 經濟部中央標準局員工消費合作社印製 發明説明(26 ) 之電壓给該電壓比較器59之反相繪入端子的電阻52、54所 構成。此電壓比較器59則_出比較結果之具有正負中之某 一方之電壓電平的脈衝列。 極性判別電壓6B,係包含兩觸發電路67,68。此等觸 發電路67, 68,係與第15圖中之極性判別電路6A所用者相 同,其埋輯Η及邏輯L分別對應於規定之正電壓及規定之 負電壓。 電壓合成電路7D,係用作延遲電路動作之同時包含有 :兩値倒相電路780,782,係用以取出互枏反轉之信號, 二極管784及霄阻786,係用Μ從前段倒相電路780之輪出 取出正極性之脈衝;二極管788及電阻790,係用Μ從後段 倒相電路782之輸出取出負極性之脈衝;兩個試驗狀態緩 衝器700 , 702;反相放大器,係包含蓮算放大器760及電 阻766 ;電容器768,係為使此反相放大器之輸出電壓平滑 而並聯連接於電阻766;及镉睡電路,係由一連接在正負 電源Vdd,Vss間之可變電阻770所形成。此中,反相放大 器及偏壓電路,係用來進行與第15圖中之電壓合成電路7C 所包含者基本地相同之動作。 在第16圖所示之16壓合成電路7D方面,由於利用二極 管等來製作正極性之脈衝,所Μ不需要包含有第15圖所示 之蓮算放大器754的第一反相放大器。因此,將一方之試 驗狀態緩衝器700之鑰出及另一方之試驗狀態緩衝器702之 _出,單純透過電阻762或764加以加法後,僅用構成有蓮 算放大器760之反相放大器來反轉極性,即可產生所需之 本紙張尺度適用中國國家標準(CNS ) A4規格(210 X 297公釐) I------^-I餐------tT----- (請先閱讀背面之注意事項再填寫本頁) 30 A7The pulse conversion circuit 5B includes: a voltage comparator 59 for inputting the synchronous rectification wheel output from the analog switch 35 in the synchronous rectification circuit 3A, and its non-inverting input terminal; By adding a little below 0V, the paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X 297mm) 29 -------- (— installed ------ order ----- ^ i Line (please read the precautions on the back before filling in this page) A7 B7 5. The invention description (26) printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. And 54. This voltage comparator 59 outputs a pulse train with a voltage level of either positive or negative of the comparison result. The polarity discrimination voltage 6B includes two trigger circuits 67, 68. These trigger circuits 67, 68. It is the same as that used in the polarity discrimination circuit 6A in FIG. 15, and its buried logic H and logic L correspond to the specified positive voltage and the specified negative voltage, respectively. The voltage synthesis circuit 7D is used as a delay circuit while operating Contains: two-phase inverter circuits 780, 782, used to take out the mutual inversion The signal, the diode 784 and the small resistance 786, use M to take out the positive pulse from the front stage inverter circuit 780; the diode 788 and the resistance 790, use M to take the negative pulse from the output of the rear stage inverter circuit 782; Two test status buffers 700, 702; an inverting amplifier, which includes a lotus amplifier 760 and a resistor 766; a capacitor 768, which is connected in parallel to the resistor 766 to smooth the output voltage of the inverting amplifier; and a cadmium sleeping circuit, It is formed by a variable resistor 770 connected between the positive and negative power supplies Vdd and Vss. Here, the inverting amplifier and the bias circuit are used to perform basic grounding with those included in the voltage synthesis circuit 7C in FIG. 15 The same operation. In the 16-voltage synthesis circuit 7D shown in FIG. 16, since the positive pulse is produced by using a diode, etc., there is no need to include the first inversion of the lotus arithmetic amplifier 754 shown in FIG. 15. Amplifier. Therefore, the key out of one test state buffer 700 and the other test state buffer 702 are simply added through resistors 762 or 764, and only the inverse of the lotus amplifier 760 is used. Amplifier to invert the polarity, you can produce the required paper size. Applicable to China National Standard (CNS) A4 specification (210 X 297 mm) I ------ ^-I 餐 ------ tT- ---- (please read the notes on the back before filling this page) 30 A7

經濟部中央榡準局員工消費合作衽印製 五、發明説明(27 ) ^ 控制電壓。 〔調諧電路之第一變形例〕 包含在第2圖所示之調諧機構中之調諧霣路1,雖於 各相移電路內部含有CR電路,但使用内部含有LR電路Μ代 替CR電路之相移電路,來構成調諧電路也可。 第17圖及第18為一電路圖,係顯示含有LR電路之其他 構成。第17圖所示之相移電路110L,係將由第3圖所示之 相移電路110C内之電容器114及可變電阻116所構成之CR電 路,置換為由可變電阻116及電感器117所構成之LR電路而 成者。 又,第18圖所示之相移電路130L,係將由第5圖所示 之相移電路130C内之可變電阻136及II容器134所成之CR電 路,置換為由電感器137及可變電阻136所構成之CR電路而 成者。 第17圖所示之相移霄路110L係與第2圜所示之前段相 移電路110C等效,而第18圖所示之柑移霣路130L係與第2 圖所示之後段相移電路130C等效,所以可將第2圖所示之 兩個柑移電路110C,130C之某一方或兩方置換為相移電路 110L,130L。 又,比較第3圖所示之相移電路110C及第17圈所示之 相移電路110L,則使形成可變電阻116之FET柵壓變化時各 相位位移量之變化方向,顯示變成相反。因此,欲將相移 電路110C置換爲相移電路110L時,有必要於第7圖中,將 觸發電路63之兩値輓出端子與試驗狀態緩衝器700, 702之 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X297公釐) _ q 1 _ (請先閱讀背面之注意事項再填寫本頁) 裝. 訂 線 經濟部中央標準局員工消費合作社印製 A7 B7五、發明说明(28 ) 連接改換,或者兩値之試驗狀態緩衝器700 , 702之輪出端 之連接對方改換,作若干之霣路之變更,Μ便從頻率控制 電路2外加於調諧電路1之控制電壓之變化方向與調諧電 路1之調諧頻率之變化方向形成相反。 〔調諧電路之第二變形例〕 第19圖係顯示調諧電路之第二變形例的電路圖。包含 在該圖所示之調諧電路1Α之前段相移電路210C,其内部並 未包含分壓電路,而代之將電阻120’之電阻值設定成大於 電阻118’之電阻值,藉此使後段相移電路210C之增益變成 大於1。 同樣,後段相移霄路230C,其内部也未包含有分壓電 路,而代之將電阻140’之電阻值設定成大於電阻138’之電 阻值,藉此使相移電路130C之增益變成大於1。又,相移 電路230C之輸出並未經由分壓電路而直接回授至前段側。 又,與第2圖所示之調諧電路1 一樣,使相移電路230C之 輸出透過分壓電路回授至相移電路210C之輸入钿也可。 電阻119及139,係為了抑制相移電路210C及230C之增 益變動而設置者。此等電阻119及139之電阻值R,宜按照 下式(5)設定。但,於式(5)中,r為電胆118’或電阻138’ 之電阻值,m為電咀120’或電阻140’之電阻值。 R = fflr(m-l) ...(5) 又,第19圖所示之調諧電路1A雖分別於兩値相移電路 210C,230C連接電阻119,電阻139,藉此來防止將調諧頻 率作成可變時之振幅變動,但除掉上述電阻119, 139M構 (請先閱讀背面之注意事項再填寫本頁) .裝.Printed by the Employee Consumption Cooperation of the Central Bureau of Economics of the Ministry of Economy V. Description of the invention (27) ^ Control voltage. [First Modification of Tuning Circuit] The tuning circuit 1 included in the tuning mechanism shown in FIG. 2 includes a CR circuit inside each phase shift circuit, but uses an internal LR circuit M instead of the phase shift of the CR circuit Circuit may be used to form a tuning circuit. Figures 17 and 18 are circuit diagrams showing other configurations including LR circuits. The phase shift circuit 110L shown in FIG. 17 replaces the CR circuit composed of the capacitor 114 and the variable resistor 116 in the phase shift circuit 110C shown in FIG. 3 with the variable resistor 116 and the inductor 117. Composed of LR circuits. In addition, the phase shift circuit 130L shown in FIG. 18 replaces the CR circuit formed by the variable resistor 136 and the II container 134 in the phase shift circuit 130C shown in FIG. 5 with the inductor 137 and the variable It is a CR circuit composed of resistor 136. The phase shift road 110L shown in FIG. 17 is equivalent to the front phase shift circuit 110C shown in the second circle, and the orange shift road 130L shown in FIG. 18 is phase shifted to the rear stage shown in FIG. 2 The circuit 130C is equivalent, so one or both of the two orange shift circuits 110C, 130C shown in FIG. 2 can be replaced with the phase shift circuits 110L, 130L. In addition, comparing the phase shift circuit 110C shown in FIG. 3 with the phase shift circuit 110L shown in the 17th turn, the direction of change of each phase shift amount when the gate voltage of the FET forming the variable resistor 116 is changed is reversed. Therefore, in order to replace the phase shift circuit 110C with the phase shift circuit 110L, it is necessary to pull the two-value pull-out terminals of the trigger circuit 63 and the test status buffer 700, 702 in Figure 7 to the Chinese paper standard. (CNS) Α4 specification (210X297 mm) _ q 1 _ (please read the notes on the back before filling in this page) Packing. Printed A7 B7 by the Consumer Cooperative of the Central Standardization Bureau of the Ministry of Economics and Development 5. Description of invention (28) Change the connection, or change the connection partner at the outgoing end of the two test state buffers 700, 702, and make some changes in the path, M will change the direction of the control voltage applied to the tuning circuit 1 from the frequency control circuit 2 and The direction of change of the tuning frequency of the tuning circuit 1 is opposite. [Second Modification of Tuning Circuit] FIG. 19 is a circuit diagram showing a second modification of the tuning circuit. The phase shift circuit 210C included in the previous stage of the tuning circuit 1A shown in the figure does not include a voltage divider circuit. Instead, the resistance value of the resistor 120 'is set to be greater than the resistance value of the resistor 118', thereby making The gain of the second-stage phase shift circuit 210C becomes greater than one. Similarly, the rear phase shifting road 230C does not include a voltage divider circuit, and instead sets the resistance value of the resistor 140 'to be larger than the resistance value of the resistor 138', thereby making the gain of the phase shift circuit 130C into Greater than 1. In addition, the output of the phase shift circuit 230C is not directly fed back to the front stage side through the voltage divider circuit. As in the tuning circuit 1 shown in FIG. 2, the output of the phase shift circuit 230C may be fed back to the input of the phase shift circuit 210C through the voltage divider circuit. The resistors 119 and 139 are provided to suppress the gain variation of the phase shift circuits 210C and 230C. The resistance value R of these resistors 119 and 139 should be set according to the following formula (5). However, in formula (5), r is the resistance value of the electric bulb 118 'or the resistor 138', and m is the resistance value of the electric nozzle 120 'or the resistor 140'. R = fflr (ml) ... (5) In addition, although the tuning circuit 1A shown in FIG. 19 is connected to the two-value phase shift circuits 210C and 230C respectively with the resistor 119 and the resistor 139, this prevents the tuning frequency from being made Amplitude changes with time, but remove the above resistance 119, 139M structure (please read the precautions on the back before filling this page).

-、1T 線 本纸張尺度適用中國國家標準(CNS ) A4規格(210X25)7公釐) Α7 Β7 經濟部中央標準局員工消f·合作社印製 五、發明説明(29 ) ^ 成調諧電路也可。或者,僅除掉電阻Π9或139之一方Μ構 成調諧電路也可。 〔調諧電路之第三變形例〕 於第19圖所示之調諧電路1Α中,各相移霄路之內部雖 包含有CR電路,並據此作了說明,但使用内部包含有LR電 路以替代CR電路之相移霄路,來構成調諧電路也可。 第20圖為一電路圖,係顯示包含LR電路之相移電路的 構成;其係顯示可與第19圖所示之調諧電路1Α之前段相移 電路210C調變的構成。第21圖為一電路圖,係顯示包含有 LR電路之相移電路之其他構成;其係顯示可與第19圖所示 之調諧電路1A之後段相移電路230C調換的構成。 〔調諧電路之第四變形例〕 於上述調諧電路之第一〜第三變形例中,於级聯連接 兩個相移電路而形成之閉合環路之一部分,連接由電晶體 所成之輪出電路(follower circuit)也可。 第22圖為一電路圖,係顯示調諧電路之第四變形例之 構成。該圖所示之調諧電路1B,係於第2圖所示之調諧電 路1之前段相移霣路110c之更前段,插入由電晶體所成之 轜出電路50者。 此輪出電路50,係包含FET 152,其漏極係連接至正 電源Vdd,而其源極則透過電阻54連接至負電源Vss。又, 輸出電路50,除了由第22圖所示之源輸出電路所形成Μ外 ,也可由射極蝓出霣路所形成。 這樣,如於前段相移電路110C等之更前段,级聯連接 --------^--裝-- (請先閱讀背面之注意事項再填寫本頁) -s-, 1T line paper standard is applicable to China National Standard (CNS) A4 specification (210X25) 7mm) Α7 Β7 Printed by the employees of the Central Bureau of Standards of the Ministry of Economic Affairs and printed by the cooperative. 5. Description of invention (29) can. Alternatively, only one of the resistors Π9 or 139 may be removed to form a tuning circuit. [Third Modification of Tuning Circuit] In the tuning circuit 1A shown in FIG. 19, although the CR circuit is included in each phase-shifting road, and it has been described accordingly, the LR circuit is included instead. The phase shift of the CR circuit can be used to form a tuning circuit. Fig. 20 is a circuit diagram showing the configuration of the phase shift circuit including the LR circuit; it shows the configuration that can be modulated with the previous phase shift circuit 210C of the tuning circuit 1A shown in Fig. 19. Fig. 21 is a circuit diagram showing another configuration of the phase shift circuit including the LR circuit; it shows a configuration that can be exchanged with the phase shift circuit 230C at the rear stage of the tuning circuit 1A shown in Fig. 19. [Fourth Modification of Tuning Circuit] In the first to third modifications of the tuning circuit described above, a part of the closed loop formed by connecting two phase shift circuits in cascade is connected to the round formed by the transistor A circuit (follower circuit) is also possible. Fig. 22 is a circuit diagram showing the configuration of a fourth modification of the tuning circuit. The tuning circuit 1B shown in this figure is the one before the tuning circuit 1 shown in FIG. 2 and the phase shifting circuit 110c before it is inserted into a sheave circuit 50 made of a transistor. The wheel-out circuit 50 includes an FET 152 whose drain is connected to a positive power supply Vdd, and whose source is connected to a negative power supply Vss through a resistor 54. In addition, the output circuit 50 may be formed by the emitter as far as possible, in addition to the source output circuit shown in FIG. 22. In this way, as in the previous stage such as the previous stage phase shift circuit 110C, cascade connection -------- ^-installed (please read the precautions on the back before filling this page) -s

J -線 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 33 經濟部中央標準局員工消費合作社印製 297185 A7 B7 五、發明説明(3〇 ) 由電晶體所成之蝓出電路的話,可補償起因於前段相移電 1100等_入阻抗的損失,較之第2圖等所示之調諧電路1 ,更可使回授電阻170及_入電路174之電阻值變大。尤其 是,欲將調諧電路1B等積體化於半導體基片上時,由於為 了弄小回授電阻170等之電阻值而必須擴大元件之占有面 積,所以連接輸出電路使回授電阻170等之電阻值增大至 某程度為理想。 、 〔調諧電路之第五變形例〕 第2圖所示之調諧電路1雖將合併兩艏相移電路110C 及130C之相位位移量設成360°,但於所级聯連接之相移電 路110C及130C,連接不使相位位移之非反相電路以構成調 諧電路也可。 第23圖爲一電路圖,係顯示將非反相電路350連接至 兩値相移電路前段的調谐電路1C之構成。該圖所示之調諧 電路1C内部之相移電路310C,330C,係於運算放大器112 或132之_出端子未連接分壓電路之酤除外,其餘即具有 與第2圖所示之各相移電路110C,130C相同之構成,傳餘 函數及相位位移量也與相移電路110C,130C相同。但式(1〉 中,at = l;式(2>中a2 = l。又,非反相電路350具有由兩掴 電阻354,356之電阻比所決定之規定增益。 兩個相移電路310C,330C,其增益均成為1。因此, 於第23圖所示之調諧電路1C,將上述非反相電路350之增 益設定成大於1之值,以替代由各相移電路來掙得增益, 藉此補僂由閉合環路所產生之損失,進行規定之調諧動作 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 卜4---J:-------^--裝------訂-----^ i 線 (請先閲讀背面之注意事項再填寫本頁) 34 經濟部中央標準局員工消費合作社印製 A7 ^_ B7_ 五、發明説明(31 ) ο 〔調諧電路之第六變形例〕 第24圖爲一電路圖,係顯示調諧電路之第六變形例; 其係連接相移電路310C’以替代第23圖所示之後段相移電 路310C,並連接相位反相電路180以替代非反相電路150者 。相位反相電路180,具有由兩個轚阻184,186之電阻比 所決定之一規定放大率,藉著增大電阻186之電阻值使之 大於電阻184之電阻值,Μ獲得大於1之增益。 於規定頻率,由於藉兩個相移電路310C,將相位位移 180°,而且藉相位反相電路180將相位反轉,所Μ就全體 而言,相位轉一圈使相位位移量變成360°,進行一規定之 調諧動作。 〔調諧電路之第t變形例〕 第24圖所示之調諧霄路1D,摊例示级聯連接兩値相移 電路310C,但如第25圖所示级聯連接兩値相移電路330C時 也可進行調諧動作。 且說,第23圖〜第25圖所示之調諧電路1C,ID,1E, 雖均構成包含有CR1I路之兩痼相移電路,但構成包含有LR «路之相移電路也可。例如,於第23圖所示之調諧電路1C ,將前段相移電路310C置換為一從第17圖所示之相移電路 110L省略分壓霄路的相移電路,將後段相移電路置換爲一 從第18圖所示之相移霣路130L省略分壓電路之相移電路也 可0 〔調諧電路之第八變形例〕 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) . 裝 訂 ^ 線 (請先閲讀背面之注意事項再填寫本頁) 35 經濟部中央標準局貝工消費合作社印製 A7 B7 五、發明説明(32 ) . 第26圖所示之調諧霣路1F,包含有:兩個相移霣路410C ,430,係分別使所輸入之交流信號之相位位移一規定量 ,藉此於規定頻率進行合計360°之相位位移;一非反柑電 路450,係不改變相移電路之相位而Μ規定放大率放大輸 出者;一分壓電路160,係由設在非反相電路450之後段的 電阻162及164所構成;及一回授霄阻170。 前段相移電路410C,係藉FET 412來產生跟鎗入信號 同相及反相之信號,然後經由電容器414或可變電阻416合 成此等兩値信號作爲輪出信號。 又,將FET 412及後述之FET 432之至少一方置換為雙 極性電晶體也可。 如假定由電容器414及可變電阻416所構成之CR電路之 時間常數為Ti,則相移霣路410C之傳_函數可直接適用式 (1>所示之K1 (但,31<1),相位位移董也等於第2圖所 示之相位位移量。 一方面》後段相移電路430C,係藉FET 432來產生跟 繪入信號同相及反相之信號,然後經由電阻436或電容器 434合成此等兩艏信號作爲輪出信號。 如假定由電容器434及可變電阻436所構成之CR電路之 時間常數為T2,則此相移電路430C之傳輸函數可直接適用 式(2)所示之K2 (但,a2<l),相位位移量也等於第2圖 所示之相移電路130C之相位位移量。 又,非反相電路450,包含有:一 FET 452,係於其漏 極與正電源間連接電阻454 ,並於源極與接地間連接電阻 本紙張尺度適用中國國家標隼(CNS ) A4規格(210X 297公釐) ----------^------1T-----7丨^ (請先閲讀背面之注意事項再填寫本頁) 36 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明(33 ) 456; —電晶體458,其基極係連接至FET 452之漏極同時, 其集電極則經由電阻460連接至FET 452之源極;及電阻 462 ,係用Μ外加適當之偏壓於PET 452。 FET 452,係於柵極輪入交流信號時,從漏極輪出反 相之信號。又,電晶體458,係於基極鑰入此反柑之信號 時,從集電極輸出更將相位反轉之信號,邸,入於 FET 452之柵極的信號之相位作為基準時從集電極輪出同 相之信號,然後從非反相電路450翰出此信號。 藉由兩個相位電路410C,430C全體,使相位位移量之 合計,於規定頻率時成為360°,此時,調整非反相電路 4 50之增益使環路增益成1以下,藉此,維持規定之調諧 動作。 〔調諧電路之第九變形例〕 第26圖所示之調諧電路1F,雖於各相移電路410 , 430C 之內部含有CR電路,但使用含有由電阻及電感器所成之LR 電路(M替代CR電路)之相移霣路,Μ構成調諧電路也可。 第27圖係顯示包含有LR霣路的相移電路之電路圖;其 係顯示可與第26所示之相移電路410C置換的構成。插入在 霣感器417與FET 412之溻極間的電容器419,係用來阻止 直流電流。第28圖係顥示包含有LR電路的相移霣路之電路 画;其係顯示可與第26圖所示之相移電路430C置換的構成 。插入在電阻436與FET 432之漏極間的電容器439,係用 來阻止直流電流者。 〔調諧電路之第十變形例〕 (請先閲讀背面之注意事項再填寫本頁) 裝· 訂 l·. 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X297公釐) „ -3 f - 五、發明説明(34 ) A7 B7 經濟部中央標準局員工消費合作社印裝 第29圖,係將相移電路410C二段级聯連接的調諧電路 1G之電路圖;其係顯示調諧電路之第十變形例。又,第30 圖係將相移電路430C二段级聯連接的調諧電路1H之電路圖 。含在調諧電路1G,1H之反相電路480,係具有由兩個電 阻484,486電阻比所決定之規定增益。 藉由兩傕相移電路410C或兩傾相移電路430C之全體, 使相位位移量之合計•於規定頻率時成為180°,此時,調 整相位反相電路480之增益使環路增益成1M下,藉此維 持規定之調諧動作。 且說,第26圖、第29圖、第30圖所示之調諧電路1F、 1G、1H,係由兩個相移電路及非反相電路,或兩値相移電 路及反相電路所構成;其係利用所連接之三個電路全體, 於規定頻率時使合計之相位位移量成36(Γ,藉此進行規定 之調諧動作。因此,如僅著眼於相位位移置的話,將三個 電路用怎樣之順序連接即有某程度之自由度,可視其需要 決定連接順序。 又,上述調諧電路1G、1Η,雖例示於相移電路内部含 有CR電路之例子,但將其内部含有LR電路之相移電路级聯 連接Η構成調諧電路也可。 於以上所說明之各種調諧霉路,其連接於前段相移電 路内之蓮算放大器或後段相移電路内之蓮算放大器輪出端 的分壓電路中,省略其中一方的分壓電路,或者將分壓比 設定成1也可。又,不需要放大動作時,省略連接至後段 相移電路之後端側的分壓電路,將後段相移電路之輪出直 (請先閲讀背面之注意事項再填寫本頁) •裝. 訂 -線 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X 297公釐) 38 -m* -m* 經濟部中央標隼局員工消費合作杜印製 Α7 Β7 五、發明説明(35 ) . 接回授至前段侧也可。或者,將連接至後段相移電路之後 段側的分壓電路之分E比設定成1也可。 [J ·其他變形例〕 且說,第1圖等所示之各種調諧機構,雖在構成調諧 霣路之相移電路中,用接合型之PET來形成一方之相移電 路内之可變電阻116等,但用其他元件來形成可變電阻也 可。 又,依照上述各調諧霣路,雖藉著改變前段相移電路 内部之可變電阻116, 416之電阻值,來變更調諧頻率,但 將此可變電阻置換爲固定電阻之同時,將後段相移電路内 部之可變電阻136,436置換為由接合型或MOS型之FET所形 成的可變電阻,使外加於此FET柵極之控制霣壓Μ改變全 釀之調諧頻率也可。但若改變控制電壓時之相位位移方向 變成相反時,於第7圖,將觸發電路63之兩個轅出端子與 試驗狀態緩衝器700 , 702之連接改換,或者將兩個試驗狀 態緩衝器700 , 702之輸出端的連接對方改換等,有必要做 若干之變更,以便從頻率控制電路2外加於調諧霣路1之 控制電壓的變化方向與調諧頻率之變化方向成為相反。或 者,將可變電阻分別設在前段及後段之相移電路内部也可 。此時,由於使雙方之相移電路之各相位位移量同時變成 可變,所具有可將全體之調諧頻率之變化量,即調諧頻率 之可變範圍設定於寬大範圍之優點。 又,於第2圖中》將調諧電路内之兩個相移電路前後 對換連接起來也可。 本紙張尺度適用中國國家標隼(CNS ) Α4規格(210X 297公釐) (請先閱讀背面之注意事項再填寫本页) -裝· 訂 297185 Α7 Β7 經濟部中央標準局員工消費合作社印製 五、發明説明(36 ) 又,上述相移霄路110C等,雖使跟電容器114等串聯 地連接的可變霣阻116等之電阻值變化以改變相位位移量 ,藉此改變全體之調諧頻率,但藉著改變電容器114等之 靜電容量來改變全體之調諧頻率也可。 又,於上述實施形態中*雖由使用有蓮算放大器之相 移電路110C等來構成調諧電路1〜1E,藉此可賁現高穩定 度,但進行如本實施形態之相移電路Π0等之用法時,其 補償電壓和霣壓增益並不要求那麼高性能者,所Μ使用具 有規定放大率之差動放大器Μ替代各相移電路内之蓮算放 大器也可。 第31圖係從蓮算放大器之構成中抽出相移電路之動作 所必需之部分的電路圖;其全體係當做具有規定放大率之 差動放大器動作。該圖所示之差動放大器係包含:一由FET 所構成之差動輪入级100 ; —對此差動鑰入级供給定滾之 定流電路102; —對定滾電路供給規定偏壓的偏壓電路104 ;及連接至差動_入级100的檢出放大器106。如該圖所示 ,可省略一用來掙得實際之運算放大器所含之電壓増益的 级聯放大霉路,藉Μ簡略差動放大器之構成,謀求廣頻帶 化。如此,由於可藉著簡略電路來提高動頻率之上限,所 以其份兒可提高使用該差動放大器來構成的調諧電路1等 之調諧頻率上限。 又,本發明並不受上述各種實施形態之限制,可在本 發明之要旨範圍內實施各種變形例。 例如,第2圖中顯示詳細構成之調渚電路1等,雖使 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ297公釐) (請先閱讀背面之注意事項再填寫本頁.) .裝_ 訂 —線 40 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明(37 ) 用回授霣阻170作為回授阻抗元件,及使用輸入電阻174作 為輪入阻抗元件,但由於只要可在不改變各元件所輓入之 信號的柑位蘭係下進行加法就可以,所Μ使用電容器來形 成回授阻抗元件及輪入阻抗元件Μ替代電阻,或者組合電 阻和電容器等俥得以同時調整阻抗之實數份及虛數份之比 也可。 又,由可變電阻來構成回授霄阻170與輪入電阻174中 之至少一方之電阻,使調諧放大器1等中之Q(或頻帶寬 )變成可變也可。 又,於第2圖所示之相移霣路110C等中,雖使用一俩 FET來構成可變電阻116,但将Ρ通道之FET及η通道之FET 並聯連接以構成一個可變電阻也可。如此,由於可組合兩 個FETM構成可變電阻,藉此來改善FET之非線性領域,所 Μ可減少調諧輸出之失真。 產業上之利用可能性 如Μ上所述,本發明之調諧控制方式,係用Μ回授控 制調諧電路之調諧頻率Μ便調諧電路之輪入信號之頻率與 調諧頻率之偏移得以消失,所以可使調諧頻率確實地吻合 於輪入信號之頻率。因此,在積體化調渚機構全體時,即 使所製造之每晶片在頻率特性上有偏差,調諧性也不會離 散。又,決定調諧頻率之各元件之元件常數即使因通度而 變動,也可抑制調諧頻率之變動,也適於積體化。 (請先閱讀背面之注意事項再填寫本頁) -裝. 訂 |線_ 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X297公釐)J-line paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) 33 Printed by the Employees ’Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 297185 A7 B7 V. Description of invention (3〇) The worm made of transistor In the case of a circuit, it can compensate for the loss of the input impedance caused by the previous phase shifter 1100 and so on. Compared with the tuning circuit 1 shown in FIG. 2, the resistance value of the feedback resistor 170 and the input circuit 174 can be increased. In particular, when the tuning circuit 1B and the like are to be integrated on a semiconductor substrate, in order to reduce the resistance value of the feedback resistor 170 and the like, it is necessary to expand the area occupied by the device, so the output circuit is connected to make the resistance of the feedback resistor 170 and the like It is ideal to increase the value to a certain degree. , [Fifth Modification of Tuning Circuit] Although the tuning circuit 1 shown in FIG. 2 sets the phase shift amount of the combined two phase shift circuits 110C and 130C to 360 °, the phase shift circuit 110C connected in cascade And 130C, connect a non-inverting circuit that does not shift the phase to form a tuning circuit. Fig. 23 is a circuit diagram showing the configuration of the tuning circuit 1C connecting the non-inverting circuit 350 to the front stage of the two-value phase shift circuit. The phase shift circuits 310C and 330C in the tuning circuit 1C shown in this figure are except for the output terminal of the operational amplifier 112 or 132 where the voltage dividing circuit is not connected, and the rest have the phases shown in FIG. 2 The shift circuits 110C and 130C have the same structure, and the transfer function and phase shift amount are also the same as the phase shift circuits 110C and 130C. However, in equation (1>, at = l; equation (2> a2 = l. In addition, the non-inverting circuit 350 has a prescribed gain determined by the resistance ratio of the two slap resistors 354, 356. Two phase shift circuits 310C , 330C, the gains all become 1. Therefore, in the tuning circuit 1C shown in FIG. 23, the gain of the non-inverting circuit 350 is set to a value greater than 1, instead of gaining gain by each phase shift circuit, In order to compensate for the losses caused by the closed loop, the prescribed tuning action is carried out. The paper standard is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) BU 4 --- J: ------- ^ --Installed ------ ordered ----- ^ i line (please read the notes on the back before filling in this page) 34 Printed A7 ^ _ B7_ by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (31) ο [Sixth Modification of Tuning Circuit] FIG. 24 is a circuit diagram showing a sixth modification of the tuning circuit; it is connected to the phase shift circuit 310C ′ to replace the subsequent phase shift circuit shown in FIG. 23. 310C, and connected to the phase inverting circuit 180 instead of the non-inverting circuit 150. The phase inverting circuit 180 has two blocking resistors 184, 1 The resistance ratio of 86 determines one of the specified amplification ratios. By increasing the resistance value of the resistance 186 to be greater than the resistance value of the resistance 184, M obtains a gain greater than 1. At the specified frequency, since two phase shift circuits 310C are used, The phase is shifted by 180 °, and the phase is inverted by the phase inverting circuit 180, so as a whole, the phase is turned once to make the phase shift amount become 360 °, and a predetermined tuning operation is performed. [T Modification] The tuning road 1D shown in FIG. 24 exemplifies the two-phase phase shift circuit 310C connected in cascade, but the tuning operation can also be performed when the two-phase phase shift circuit 330C is connected in cascade as shown in FIG. 25. The tuning circuits 1C, ID, and 1E shown in FIGS. 23 to 25 all constitute two phase shift circuits including CR1I, but they may also constitute a phase shift circuit including LR «. For example, in In the tuning circuit 1C shown in FIG. 23, the front-stage phase shift circuit 310C is replaced with a phase shift circuit that omits the voltage divider from the phase shift circuit 110L shown in FIG. 17, and the rear-stage phase shift circuit is replaced with a second Figure 18 shows the phase-shifted road 130L omit the phase shift of the voltage divider circuit Road can also be 0 [The eighth modification of the tuning circuit] This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). Binding ^ Line (please read the precautions on the back before filling this page) 35 Ministry of Economic Affairs Printed A7 B7 by Beigong Consumer Cooperative of Central Bureau of Standards. 5. Description of invention (32). Tuning Fenglu 1F shown in Figure 26 includes: two phase-shifting Fenglu 410C, 430, which respectively make the input AC The phase of the signal is shifted by a specified amount, whereby a total of 360 ° phase shift is performed at the specified frequency; a non-inverted circuit 450, which does not change the phase of the phase shift circuit and M specifies the amplification factor to amplify the output; a voltage divider circuit 160 is composed of resistors 162 and 164 provided in the rear stage of the non-inverting circuit 450; and a feedback resistor 170. The previous-stage phase shift circuit 410C uses the FET 412 to generate the signals in phase and in phase with the shot signal, and then synthesizes these two values through the capacitor 414 or the variable resistor 416 as a round-out signal. In addition, at least one of the FET 412 and the FET 432 described later may be replaced with a bipolar transistor. If it is assumed that the time constant of the CR circuit formed by the capacitor 414 and the variable resistor 416 is Ti, the transfer function of the phase-shifted path 410C can be directly applied to K1 shown in (1> (but, 31 < 1), The phase shift Dong is also equal to the amount of phase shift shown in Figure 2. On the one hand, the rear-stage phase shift circuit 430C uses the FET 432 to generate the signals in phase and in phase with the drawn signal, and then synthesizes this through the resistor 436 or the capacitor 434 If the time constant of the CR circuit formed by the capacitor 434 and the variable resistor 436 is T2, then the transfer function of the phase shift circuit 430C can be directly applied to K2 shown in equation (2) (However, a2 < l), the phase shift amount is also equal to the phase shift amount of the phase shift circuit 130C shown in FIG. 2. The non-inverting circuit 450 includes: an FET 452, which is connected to the drain and positive The connection resistance between the power supply is 454, and the connection resistance between the source and the ground. This paper standard is applicable to the Chinese National Standard Falcon (CNS) A4 specification (210X 297mm) ---------- ^ ----- -1T ----- 7 丨 ^ (Please read the precautions on the back before filling in this page) 36 A7 B7 Central Standard of Ministry of Economic Affairs Printed by the Bureau ’s Consumer Cooperatives 5. Description of invention (33) 456;-Transistor 458, whose base is connected to the drain of FET 452, and its collector is connected to the source of FET 452 via resistor 460; and the resistor 462, using M plus an appropriate bias voltage on PET 452. FET 452, which is an inverted signal from the drain when the gate turns in an AC signal. Also, transistor 458, which is connected to the base key When the signal is reversed, a signal whose phase is reversed is output from the collector. When the phase of the signal input to the gate of the FET 452 is used as a reference, the in-phase signal is output from the collector, and then from the non-inverting circuit 450 This signal is sent out. By the two phase circuits 410C and 430C as a whole, the total phase shift amount becomes 360 ° at a predetermined frequency, and at this time, the gain of the non-inverting circuit 4 50 is adjusted so that the loop gain becomes 1 or less By this, the predetermined tuning operation is maintained. [Ninth Modification of Tuning Circuit] Although the tuning circuit 1F shown in FIG. 26 includes a CR circuit inside each phase shift circuit 410, 430C, the use of resistors and LR circuit formed by inductor (M replaces CR circuit The phase shift circuit, M can also constitute a tuning circuit. Figure 27 shows the circuit diagram of the phase shift circuit including the LR circuit; it shows the structure that can be replaced with the phase shift circuit 410C shown in the 26th. The capacitor 419 between the sensor 417 and the electrode of the FET 412 is used to prevent DC current. Figure 28 is a circuit diagram of a phase-shifted circuit containing an LR circuit; it is shown in Figure 26. The structure of the phase shift circuit 430C replacement is shown. The capacitor 439 inserted between the resistor 436 and the drain of the FET 432 is used to block direct current. [Tenth Modification of Tuning Circuit] (Please read the precautions on the back before filling in this page) Binding · Order l. This paper scale is applicable to the Chinese National Standard (CNS) Α4 specification (210X297 mm) „-3 f- V. Description of the invention (34) A7 B7 Figure 29 printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs is the circuit diagram of the tuning circuit 1G connecting the two-stage cascade of the phase shift circuit 410C; it shows the tenth modification of the tuning circuit Fig. 30 is a circuit diagram of a tuning circuit 1H connecting two stages of a phase shift circuit 430C in cascade. The inverter circuit 480 included in the tuning circuit 1G and 1H has a resistance ratio of two resistors 484 and 486. The predetermined gain is determined by the total of two Kang phase shift circuits 410C or two tilt phase shift circuits 430C, the total amount of phase shift becomes 180 ° at a specified frequency, and at this time, the gain of the phase inversion circuit 480 is adjusted so that The loop gain is 1M, thereby maintaining the specified tuning operation. In addition, the tuning circuits 1F, 1G, and 1H shown in Figure 26, Figure 29, and Figure 30 are composed of two phase shift circuits and non-inverting Circuit, or two-value phase shift circuit and reverse phase The circuit is constituted; it uses all the three connected circuits to make the total phase shift amount to 36 (Γ at a predetermined frequency, thereby performing a predetermined tuning operation. Therefore, if you only focus on the phase shift, you will The order in which the three circuits are connected has a certain degree of freedom, and the connection order can be determined according to their needs. In addition, although the above tuning circuits 1G and 1H are exemplified as examples in which the CR circuit is included in the phase shift circuit, the internal The phase shift circuit of the LR circuit is connected in cascade to form a tuning circuit. In the various tuning circuits described above, it is connected to the lotus arithmetic amplifier in the front stage phase shift circuit or the lotus arithmetic amplifier in the rear stage phase shift circuit. In the voltage divider circuit at the end, one of the voltage divider circuits may be omitted, or the voltage divider ratio may be set to 1. In addition, when an amplification operation is not required, the voltage divider circuit connected to the rear end of the rear-stage phase shift circuit may be omitted. , Straighten out the round of the phase shift circuit in the back stage (please read the precautions on the back before filling in this page) • Binding. Binding-the paper size is applicable to China National Standard (CNS) Α4 specification (210X 297 %) 38 -m * -m * Employee's consumer cooperation of the Central Standard Falcon Bureau of the Ministry of Economic Affairs, duprinting Α7 Β7 V. Description of invention (35). It is also possible to connect the feedback to the front stage side. Or, connect it to the rear stage phase shift circuit The division E ratio of the voltage divider circuit on the segment side may be set to 1. [J · Other Modifications] In addition, various tuning mechanisms shown in Fig. 1 etc. are used in the phase shift circuit that constitutes the tuning circuit. The junction type PET is used to form the variable resistor 116 in one phase shift circuit, but other elements may be used to form the variable resistor. In addition, according to the above tuning paths, although the internal phase shift circuit is changed by changing the internal The resistance value of the variable resistors 116 and 416 is used to change the tuning frequency. However, at the same time that the variable resistor is replaced by a fixed resistor, the variable resistors 136 and 436 in the subsequent phase shift circuit are replaced by a junction type or a MOS type. The variable resistance formed by the FET allows the control voltage applied to the gate of the FET to change the tuning frequency of the whole brewing. However, if the direction of the phase shift becomes reversed when the control voltage is changed, in Figure 7, the connection between the two ends of the trigger circuit 63 and the test status buffer 700, 702 is changed, or the two test status buffers 700 , The connection of the output terminal of 702 is changed, it is necessary to make some changes so that the direction of change of the control voltage applied to the tuning circuit 1 from the frequency control circuit 2 is opposite to the direction of change of the tuning frequency. Or, it is also possible to set the variable resistors inside the phase shift circuits in the front stage and the rear stage respectively. At this time, since the phase shift amounts of the phase shift circuits of both sides are simultaneously changed, there is an advantage that the total tuning frequency variation, that is, the tuning frequency variable range can be set in a wide range. In addition, in Fig. 2, it is also possible to connect the two phase shift circuits in the tuning circuit in a front-to-back direction. This paper scale is applicable to China National Standard Falcon (CNS) Α4 specification (210X 297mm) (please read the precautions on the back before filling in this page)-Installation · Order 297185 Α7 Β7 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs Description of the invention (36) In addition, the above-mentioned phase shifting road 110C, etc., changes the resistance value of the variable resistance 116, etc. connected in series with the capacitor 114, etc. to change the phase shift amount, thereby changing the overall tuning frequency, However, the overall tuning frequency may be changed by changing the capacitance of the capacitor 114 and the like. In the above embodiment, although the tuning circuits 1 to 1E are constituted by a phase shift circuit 110C using a lotus amplifier, etc., whereby high stability can be achieved, the use of the phase shift circuit Π0 of the present embodiment is performed. At this time, if the compensation voltage and the voltage gain do not require such high performance, it is also possible to use a differential amplifier M with a prescribed amplification rate instead of the lotus arithmetic amplifier in each phase shift circuit. Figure 31 is a circuit diagram of parts necessary for the operation of extracting the phase shift circuit from the configuration of the lotus amplifier; the entire system is operated as a differential amplifier with a prescribed amplification factor. The differential amplifier shown in the figure includes: a differential wheel input stage 100 composed of FETs; — a constant current circuit 102 that supplies a constant roll to the differential key input stage; — a prescribed bias voltage that is provided to the constant roll circuit Bias circuit 104; and a detection amplifier 106 connected to the differential input stage 100. As shown in the figure, it is possible to omit a cascade amplifier circuit for gaining the voltage gain contained in the actual operational amplifier, and to simplify the configuration of the differential amplifier by M to achieve a wide band. In this way, since the upper limit of the dynamic frequency can be increased by a simplified circuit, it is possible to increase the upper limit of the tuning frequency of the tuning circuit 1 etc. constructed using the differential amplifier. In addition, the present invention is not limited to the various embodiments described above, and various modifications can be implemented within the scope of the gist of the present invention. For example, Figure 2 shows the detailed configuration of the control circuit 1 etc., although the paper standard is applicable to the Chinese National Standard (CNS) Α4 specification (210Χ297mm) (please read the precautions on the back before filling this page.). Installation _ Order-Line 40 A7 B7 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Invention description (37) The feedback resistance 170 is used as the feedback impedance element, and the input resistance 174 is used as the in-line impedance element, but due to As long as the addition can be performed under the citrus blue system that does not change the signal drawn by each element, the capacitor can be used to form the feedback impedance element and the round impedance element M can replace the resistor, or the combination of the resistor and the capacitor can be used. It is also possible to adjust the ratio of the real part and the imaginary part of the impedance at the same time. In addition, at least one of the feedback resistor 170 and the wheel resistor 174 may be constituted by a variable resistor so that the Q (or frequency bandwidth) in the tuning amplifier 1 or the like may be changed. In addition, in the phase shift circuit 110C shown in FIG. 2 and the like, although one or two FETs are used to constitute the variable resistor 116, it is also possible to connect the FET of the p-channel and the FET of the n-channel in parallel to form a variable resistor . In this way, since two FETs can be combined to form a variable resistor, thereby improving the nonlinear field of the FET, the distortion of the tuning output can be reduced. Industrial application possibilities As mentioned above, the tuning control method of the present invention uses the feedback of M to control the tuning frequency of the tuning circuit, so that the deviation of the frequency of the turn-on signal of the tuning circuit from the tuning frequency is eliminated, so The tuning frequency can be exactly matched with the frequency of the in-turn signal. Therefore, when the entire modulation mechanism is integrated, even if each manufactured wafer has a deviation in frequency characteristics, the tuning property will not be scattered. Furthermore, even if the element constant of each element that determines the tuning frequency varies due to the degree of variation, the variation of the tuning frequency can be suppressed, and it is also suitable for integration. (Please read the precautions on the back before filling in this page)-Pack. Order | Thread _ This paper standard is applicable to China National Standard (CNS) Α4 specification (210X297mm)

Claims (1)

A8 B8 C8 D8 經濟部中央標準局β:工消費合作社印製 々、申請專利範圍 1 · 一捶調諧控制方法,係包含·· 一調諧電路,包含有:兩個级聯連接之全帶通型 相移電路;及一加法電路,其係使前述後段相移電路 之輪出當做回授信號回授至前述前段相移電路之鑰入 侧同前,將前述回授信號及輪入信號加法後綸入於前 述相移電路;藉此,僅讓規定之頻率附近之信號通過 ;及 一頻率控制電路,係於前述調諧電路,輸入一具 有前述規定頻率附近之頻率的信號時,根據前述調諧 電路之_入繪出間之相位差,使前述調諧電路之調諧 頻率相符於前述調諧霣路之輪入信號之頻率。 2. 依據申請專利範圍第1項所述之調諧控制方法,其中 前述調諧電路中所包含之前述兩個相移電路之至 少一方,可隨輪出自前述頻率控制電路之控制信號而 變更相位位移量;當輓入於前述調諧電路之信號的頻 率與前述調諧電路之調諧頻率相異時,使前述兩個相 移電路之至少一方之相位位移量變化,藉此使前述調 諧頻率吻合於前述調諧霣路之_入信號的頻率。 3. 依據申請專利範圍第2項所述之調諧控制方法,其中 前述頻率控制霄路包含有: 一同步整流電路,係根據同步於前述調諧罨路之 輪出信號,對於前述調諧霣路之輪入信號進行同步整 流;及 一控制信锇產生霉路,係根據前述同步整流電路 (請先閱讀背面之注意事項再填寫本頁) 裝· 訂 線 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) _ 42 - 六、申請專利範圍 A8 B8 C8 D8 經濟部中央標準局貝工消費合作社印製 之輪出,進行前述調諧電路之翰入蠄出信號間之相位 差檢出,侔向此相位差消失之方向輪出使前述調諧霄 路之調諧頻率變化的控制信號么' A V 4.依據申請專利範圍第3項所逯之说说控制方法,其中 前述同步整流電路,包含有,: / 一參考信號產生電路,係用K輸出同步於前述調 諧電路之餘出倍號;及 一開關,係同步於前述參考信號,俾通過或遮斷 前述調諧電路之輸入信號。 5_依據申請專利範圍第4項所述之控押方法,其中 前述參考信號產生電路包含有ixlf_較器,將前 述調諧電路之輸出信號之電壓電平跟規定電狙值比較 ,藉此,將按照此比較結果之矩形波當做前述參考信 號輪出; 前述開關,係將前述矩形波所具有之兩値電壓電 平分別作成接通狀態及斷開狀態,當接通狀態時讓前 述調諧電路之鑰入信號通過。 6.依據申請專利範圍第3項所述之調諧控制方法,其中 前述控制信號產生電路包含有: 一脈衝變換電路,係根據前述同步整流電路之輪 出,輓出具有脈衝寬度之信號,此脈衝宽度係對應於 前述調諧電路之輪入輪出間之相位差; 一極性判別電路,係根據前述調辟4輪入輪 出信號中之某一方,判斷前述相位差之極;k、 Hi I m —Λ i I 1 I nf :1 I -- - - - l^n l (請先閱讀背面之注意事項再填寫本頁) 、va 線_ 本紙張尺度逋用中國國家標準(CNS ) A4規格(210X297公釐) 43 _ 4 _ Α8 Β8 C8 D8 經濟部中央標準局員工消費合作社印聚 々、申請專利範圍 . 一電壓合成電路,係用Μ產生與輪出自前述脲衝 變換電路之信號的脈衝寬度成比例的電壓成分,同時 將此電壓成分按照藉肋於前述極性判別電路之判斷結 果,對於規定電歷施Μ加法或減法,藉此來進行控制 霣壓之合成; 將由前述電壓合成電路所合成之前述控制霄壓, 當做前述控制信號輸出。 7. 依據申請專利範圍第2項所述之調諧控制方法,其中 前述調諧電路中所包含之兩個相移霣路之至少 一方,包含有: 一差動放大器,係於反相輪入端子連接第一電阻 之一方端,俥透過前述第一電阻_入交流信號; 一第二電阻,係連接於前述差動放大器之輸出端 與前述差動放大器之反相輪入端子間;及 一串聯電路,係由成自霣容器或II感器之霣抗元 件及第三電阻所構成,可藉前述控制信號來變更時間 常數,且連接於第一電阻之另一方端; 將前述第三霄阻及跟前電抗元件之連接部連接至 前述差動放大器之非反相轎入端子。 8. 依據申請專利範圍第7項所述之調諧控制方法,其中 前述調諧電路,係包含一不改變所《I入之交流信 號之相位即输出之非反相電路,前述非反相罨路係揷 入在由前述级聯連接的兩個相移電路所形成之回授環 路的一部分; (請先閱讀背面之注意事項再填寫本頁) -裝· 訂 線 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X297公釐) 44 A8 B8 C8 D8 經濟部中央標準局員工消費合作社印製 六、申請專利範圍 前述調諧電路,係藉由前述级聯連接的兩値相移 霣路全體,僅讓相位位移量之合計成360。之頻率附 近之信號通過。 9.依據申請專利範圍第7項所述之調諧控制方法,其中 前述調諧電路,係包含一將所輸入之交流信號的 相位反轉输出之反相電路,前述反相霄路係揷入在由 前述级聯連接的兩値相移電路所形成之回授環路的一 部分; 前述調諧電路,係藉由前述级聯連接的兩個相移 電路全體,僅讓相位位移量之合計成180°之頻率附 近之信號通過。 10. 依據申請專利範圍第7項所述之調港控制方法,其中 將分壓電路插入由前述级聯連接的兩個相移電路 所形成的回授環路之一部分; 前述調諧霣路,係將輸入於前述分IS電路之交流 信號作爲調諧信號輪出。 11. 依據申請專利範圍第2項所述之調諧控制方法,其中 前述調諧電路中所包含之前逑兩個相移電路之至 少一方包含有:一差動放大器,係於反相蝓入端子連 接第一電阻之一方端,透過前述第一電阻輪入交流信 號;一第一分壓電路,係連接於前述差動放大器之繪 出端子;一第二霣阻,係連接於前述第一分壓電路之 輪出端與前述差動放大器之反柑輪入端子間;及一串 聯電路,係由成自霣容器或電感器之18抗元件及第三 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁) -裝· 訂 線 經濟部中央標準局員工消費合作社印製 A8 B8 C8 D8 六、申請專利範圍 霣阻所構成,同時可藉前述控制倍號來變更時間常數 且連接至前述第一霄胆之另一方端; 將前述第三電阻及前述電抗元件之連接部連接至 前述差動放大器之非反相輪入端子。 12.依據申請專利範圍第11項所述之調諧控制方法,其中 前述調諧電路1 2係包含一不改變所輪入之交流信 號的相位卽輪出之非反相電路,前述非反相電路係插 入在由前述级聯連接的兩値相移電路所形成的回授環 路之一部分; 前述調諧電路,係藉由前述级聯連接的兩個相移 電路全體2僅讓相位位移量之合計成360°之頻率附 近之信號通過。 13 _依據申請專利範圍第11項所述之調鍇控制方法,其中 前述調諧電路,係包含一將所輸入之交流信號的 相位反轉輪出之反相電路,前述反相電路係揷入在由 前述级聯連接的兩値相移電路所形成之回授電路之一 部分; 前述調諧電路,係藉由前述级聯連接的兩個相移 霣路全體,僅讓相位位移置之合計成180°之頻率附 近之信號通過。 14·依據申請專利範園第11項所述之調諧控制方法,其中 將第二分壓霣路插入由前述级聯連接的兩儸相移 電路所形成的回授環路之一部分; 前述調諧電路,係將输入於前述第二分壓電路之 (請先閱讀背面之注意事項再填寫本頁) .裝. 訂 1 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 2 4b 一 經濟部中央標準局員工消費合作社印製 A8 B8 C8 D8 ☆、申請專利範圍 交流信號作為調諧信號輸出。 15. 依據申請專利範圍第2項所述之調諧控制方法,其中 前述調諧電路中所包含之前述兩傾相移電路之至 少一方包含有:一差動放大器,係於反相輸入端子連 接第一電阻之一方端,透過前述第一霉阻繪入交流信 號;一第二電阻,係連接於前述差動放大器之反相輓 入端子與輪出端子間;一第三電阻,其一方端係連接 至前述差動放大器之反相輓入端子,而另一端則被接 地;及一串聯電路,係由成自電容器或電感器之電抗 元件及第四電阻所構成,同時可藉前述控制信號來變 更時間常數且連接至前述第一電阻之另一方端; 將前述第四電阻及前述電抗元件之連接部連接至 前述差動放大器之非反相輸入端子。 16. 依據申請專利範圍第15項所述之調諧控制方法,其中 前述調諧電路,係包含一不改變所_入之交滾信 號的相位即輪出之非反相電路,前述非反相電路係插 入在由前述级聯連接的兩値相移電路所形成之回授環 路的一部分; 前述調諧電路,係藉由前述级聯逋接的兩個相移 霣路全體,僅讓相位位移置之合計成360°之頻率附 近之倍號通過。 17. 依據申請專利範圍第15項所述之調諧控制方法,其中 前述調諧電路,係包含一將所輸入之交流信號的 相位反轉輪出的反相電路,前述反相電路係揷入在由 •Γ (請先閲讀背面之注意事項再填寫本頁) -裝. 訂 線 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 經濟部中央標準局員工消費合作社印製 Α8 Β8 C8 D8 六、申請專利範圍 _ 前述级聯連接的兩個相位霣路所形成的回授環路之一 部分; 前述調諧電路,係藉由前述级聯連接的兩値相移 電路全體,僅讓相位位移量之合計成180°之頻率附 近的信號通過。 18. 依據申請專利範圍第15項所述之調諧控制方法,其中 將分壓電路插入由前述级聯連接的兩個相移電路 所形成的回授環路之一部分; 前述調諧電路,係將輸入於前述分壓電路之交流 信號作為調諧信號輸出。 19. 依據申請專利範圍第2項所述之調諧控制方法,其中 前述調諧電路,係包含一不改變所輸入之交流信 號的相位即輪出之非反相霄路,前述非反相電路係插 入在由前级聯連接的兩個相移電路所形成之回授電路 之一部分; 前述兩個相移電路之至少一方包含有:變換機構 ,係用以變換所輪入之交流信號成同相及反相之交流 信號,並予Μ繪出;一串聯霣路,係由成自電容器或 電感器之霣抗元件及第一霣阻所構成*同時可藉前述 控制信號來變更時間常數;及合成機構,係透過前述 串聯霣路之一方端合成由前述變換機携所變換的一方 之交流信號,且透過前述串聯霄路之另一端合成另一 方之交流信號。 20·依據申請專利範圍第19項所述之調諧控制方法,其中 本紙張尺度適用中國國家標準(CNS〉A4規格(210X297公釐) 48 li_-------一--裝-- (請先閱讀背面之注意事項再填寫本頁) 訂 —線- 申請專利範圍 A8 B8 C8 D8 經濟部中央標準局員工消費合作社印聚 前述調諧電路,係藉由前述级聯連接的兩個相移 霣路全體,僅讓相位位移量之合計成360。之頻率附 近的信號通過。 21. 依據申請專利範圍第19項所述之調諧控制方法,其中 將分壓電路揷入由前述级聯連接的兩個相移電路 及前述非反相電路所形成之回授環路之一部分; 前述調諧電路,係將輸入於前述分壓電路之交流 信號作為調諧信號輓出。 22. 依據申請專利範圍第19項所述之調諧控制方法,其中 前述兩値相移霣路内之前述變換機構包含有電晶 體;於前述電晶體之源極及漏搔、或者射極及集電極 ,分別連接電阻大致相等之第二電阻;將交流信號輸 於前述電#,k之柵極或基極;於前述轚晶體之源極 (:〇?、 '極間或#、極:v集電極間,連接構成前述串聯電路 之職$ _元件—電阻。 23. 依據申請專利範圍第2項所述之調諧控制方法,其中 前述調諧電路,係包含一將所綸入的交流信號之 相位反轉輓出的反相電路,前述反相電路係插入在由 前述级聯連接的兩値相移電路所形成的回授環路之一 部分; 前述兩個相移電路之至少一方包含有:變換機構 ,係用以變換所鑰入之交流信號成同柑或反相之交流 信號,並予Μ繪出;一串聯電路,係由成自霣容器或 霄感器之電抗元件及第一電阻所構成,且可藉前述控 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X2S»7公釐) 49 (請先閱讀背面之注意事項再填寫本頁) 裝· 訂 線A8 B8 C8 D8 Central Bureau of Standards of the Ministry of Economic Affairs β: Printed by the Industrial and Consumer Cooperatives 々, patent application scope 1 · One-bump tuning control method, including one · Tuning circuit, including: two cascade-connected full band-pass types A phase shift circuit; and an addition circuit which makes the round output of the latter phase shift circuit as the feedback signal to the key input side of the front phase shift circuit as before, after adding the feedback signal and the round signal Into the aforementioned phase shift circuit; thereby, allowing only signals near the specified frequency to pass through; and a frequency control circuit connected to the tuning circuit, when inputting a signal having a frequency near the specified frequency, according to the tuning circuit The phase difference between the input and output plots makes the tuning frequency of the tuning circuit match the frequency of the round-robin signal of the tuning path. 2. The tuning control method according to item 1 of the patent application scope, wherein at least one of the two phase shift circuits included in the tuning circuit can change the phase shift amount in accordance with the control signal from the frequency control circuit When the frequency of the signal pulled into the tuning circuit is different from the tuning frequency of the tuning circuit, the phase shift amount of at least one of the two phase shift circuits is changed, thereby making the tuning frequency coincide with the tuning frequency The frequency of the incoming signal. 3. The tuning control method according to item 2 of the scope of the patent application, wherein the frequency control path includes: a synchronous rectifier circuit based on the wheel output signal synchronized with the tuning path, for the wheel of the tuning path Synchronous rectification of the input signal; and a control signal osmium produces a bad road, according to the aforementioned synchronous rectification circuit (please read the precautions on the back before filling in this page). The paper size of the binding and binding book is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) _ 42-6. The scope of patent application A8 B8 C8 D8 A round printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, to detect the phase difference between the incoming and outgoing signals of the aforementioned tuning circuit. A control signal that changes the tuning frequency of the aforementioned tuning road is output in the direction in which this phase difference disappears' AV 4. According to the control method described in item 3 of the scope of the patent application, the aforementioned synchronous rectifier circuit includes, : / A reference signal generation circuit, which uses K output to synchronize with the remaining multiple of the aforementioned tuning circuit; and a switch, which is synchronized with the aforementioned reference signal , To pass or block the input signal of the aforementioned tuning circuit. 5_ According to the charge control method described in item 4 of the patent application scope, wherein the reference signal generating circuit includes an ixlf_comparator, which compares the voltage level of the output signal of the tuning circuit with a prescribed electrical value, thereby, The rectangular wave according to the comparison result is used as the reference signal in turn; the switch is to make the two voltage levels of the rectangular wave into the on state and the off state respectively, when the on state is turned on, the tuning circuit The key input signal passes. 6. The tuning control method according to item 3 of the patent application scope, wherein the control signal generating circuit includes: a pulse conversion circuit, which extracts a signal having a pulse width according to the round of the synchronous rectifier circuit, the pulse The width corresponds to the phase difference between the round-in and round-out of the tuning circuit; a polarity discrimination circuit determines the pole of the phase difference according to one of the four round-in and round-out signals of the aforementioned tuning; k, Hi I m —Λ i I 1 I nf: 1 I----l ^ nl (please read the precautions on the back before filling in this page), va line_ This paper scale uses the Chinese National Standard (CNS) A4 specification (210X297 Mm) 43 _ 4 _ Α8 Β8 C8 D8 Printed by the Consumers ’Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, and the scope of patent application. A voltage synthesis circuit uses M to generate the pulse width of the signal from the aforementioned urea-impulse conversion circuit. Proportional voltage component, and at the same time, according to the judgment result of the aforementioned polarity discriminating circuit, the voltage component is subjected to M addition or subtraction to the predetermined calendar to thereby synthesize the control voltage; The control voltage synthesized by the voltage synthesis circuit is output as the control signal. 7. The tuning control method according to item 2 of the patent application scope, wherein at least one of the two phase shift paths included in the tuning circuit includes: a differential amplifier connected to the inverting in-phase terminal A square terminal of the first resistor passes through the first resistor_input AC signal; a second resistor is connected between the output terminal of the differential amplifier and the inverting input terminal of the differential amplifier; and a series circuit It is composed of a resistive element and a third resistor that are formed from a Feng container or II sensor, and the time constant can be changed by the aforementioned control signal, and connected to the other end of the first resistor; the aforementioned third resistor and The connection part of the front reactance element is connected to the non-inverting car input terminal of the aforementioned differential amplifier. 8. The tuning control method according to item 7 of the patent application scope, wherein the tuning circuit includes a non-inverting circuit that does not change the phase of the input AC signal, that is, the output, Insert a part of the feedback loop formed by the two phase-shift circuits connected in the aforementioned cascade; (please read the precautions on the back before filling out this page)-The paper size of the binding and binding book is in accordance with Chinese national standards ( CNS) Α4 specification (210X297 mm) 44 A8 B8 C8 D8 Printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 6. The scope of the patent application The aforementioned tuning circuit is the entire two-phase phase-shifted road connected by the aforementioned cascade, only Let the total amount of phase shift be 360. The signal near the frequency passes. 9. The tuning control method according to item 7 of the patent application scope, wherein the tuning circuit includes an inverting circuit that inverts and outputs the phase of the input AC signal. Part of the feedback loop formed by the two cascade-connected phase shift circuits; the tuning circuit is the total of the phase shift amounts to 180 ° by the total of the two cascade-connected phase shift circuits The signal near the frequency passes. 10. The port regulation method according to item 7 of the patent application scope, in which a voltage divider circuit is inserted into a part of the feedback loop formed by the two phase shift circuits connected in the aforementioned cascade; The AC signal input to the aforementioned sub-IS circuit is used as a tuning signal. 11. The tuning control method according to item 2 of the patent application scope, wherein at least one of the two previous phase shift circuits included in the tuning circuit includes: a differential amplifier connected to the inverting input terminal A square terminal of a resistor passes an AC signal through the first resistor; a first voltage divider circuit is connected to the drawn terminal of the differential amplifier; a second resistor is connected to the first voltage divider Between the round out end of the circuit and the inverse round in terminal of the aforementioned differential amplifier; and a series circuit, consisting of 18 anti-components and third paper standards made from self-contained containers or inductors, applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) (please read the notes on the back before filling in this page)-Installation · Threading A8 B8 C8 D8 printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs The time constant can be changed by the control multiplier and connected to the other end of the first antenna; connect the connection portion of the third resistor and the reactance element to the differential amplifier The non-inverted rotation terminal. 12. The tuning control method according to item 11 of the scope of the patent application, wherein the tuning circuit 12 includes a non-inverting circuit that does not change the phase of the alternating AC signal and the non-inverting circuit, the non-inverting circuit is It is inserted into a part of the feedback loop formed by the two-phase phase-shift circuits connected in the cascade; the tuning circuit is formed by the total of two phase-shift circuits connected by the cascade only the total amount of phase shift The signal near the frequency of 360 ° passes. 13 _ The method for controlling the tuning according to item 11 of the scope of the patent application, wherein the tuning circuit includes an inverting circuit that inverts the phase of the input AC signal, and the inverting circuit is A part of the feedback circuit formed by the two cascade-connected phase shift circuits; the tuning circuit is the total of the phase shifts set to 180 ° by the two cascade connected phase shift circuits The signal near the frequency passes. 14. The tuning control method according to item 11 of the patent application park, in which the second voltage-dividing path is inserted into a part of the feedback loop formed by the two cascade phase shift circuits connected in the aforementioned cascade; the aforementioned tuning circuit , Will be input into the aforementioned second voltage divider circuit (please read the precautions on the back before filling in this page). Pack. Order 1 This paper size is applicable to China National Standard (CNS) A4 specification (210X297mm) 2 4b 1. The A8 B8 C8 D8 printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs ☆, the patent application scope AC signal is output as the tuning signal. 15. The tuning control method according to item 2 of the patent application scope, wherein at least one of the two tilt phase shift circuits included in the tuning circuit includes: a differential amplifier connected to the first inverting input terminal One side of the resistor is drawn into the AC signal through the first mold resistance; a second resistor is connected between the inverting pull-in terminal and the wheel-out terminal of the differential amplifier; a third resistor is connected to one end To the inverting pull-in terminal of the aforementioned differential amplifier, and the other end is grounded; and a series circuit is formed by a reactance element and a fourth resistor formed from a capacitor or an inductor, and can be changed by the aforementioned control signal The time constant is connected to the other end of the first resistor; the connecting portion of the fourth resistor and the reactance element is connected to the non-inverting input terminal of the differential amplifier. 16. The tuning control method according to item 15 of the scope of the patent application, wherein the tuning circuit includes a non-inverting circuit that does not change the phase of the incoming rollover signal, that is, turns out. The non-inverting circuit is It is inserted in a part of the feedback loop formed by the two-phase phase-shift circuit connected by the cascade; the tuning circuit is the whole of the two phase-shift circuits connected by the cascade, and only the phase shift is set The total number of times around the frequency of 360 ° is passed. 17. The tuning control method according to item 15 of the patent application scope, wherein the tuning circuit includes an inverting circuit that inverts the phase of the input AC signal, and the inverting circuit is included in the • Γ (Please read the precautions on the back before filling in this page)-Packing. The paper size of the binding is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm). Printed by the Ministry of Economic Affairs Central Standards Bureau Staff Consumer Cooperative Α8 Β8 C8 D8 6. Scope of patent application _ Part of the feedback loop formed by the two cascade-connected phase paths; the tuning circuit is based on the entire two-phase phase-shift circuit connected by the cascade, allowing only phase shift The sum of the quantities is such that the signal near the frequency of 180 ° passes. 18. The tuning control method according to item 15 of the patent application scope, in which a voltage divider circuit is inserted into a part of the feedback loop formed by the two phase shift circuits connected in the aforementioned cascade; The AC signal input to the voltage dividing circuit is output as a tuning signal. 19. The tuning control method according to item 2 of the scope of the patent application, wherein the tuning circuit includes a non-inverting road that rotates without changing the phase of the input AC signal, and the non-inverting circuit is inserted A part of the feedback circuit formed by the two phase-shift circuits connected in the front cascade; at least one of the two phase-shift circuits includes: a conversion mechanism, which is used to convert the alternating AC signal into the same phase and the reverse phase The AC signal of the corresponding phase is plotted for M; a series connection is composed of a resistance element formed from a capacitor or an inductor and the first resistance * At the same time, the time constant can be changed by the aforementioned control signal; and the synthesis mechanism It is to synthesize the AC signal of one side that is carried by the converter through one side of the aforementioned series road, and to synthesize the AC signal of the other side through the other end of the series road. 20. According to the tuning control method described in item 19 of the patent application scope, the paper standard is applicable to the Chinese National Standard (CNS> A4 specification (210X297 mm) 48 li _------- 一-装-( Please read the precautions on the back before filling in this page) Order-Line-Patent Application Scope A8 B8 C8 D8 Central China Bureau of Economic Affairs Employee Consumer Cooperative printed and tuned the aforementioned tuning circuit, which is connected by the two cascaded phase shifts For the whole circuit, only the signal near the frequency with the total phase shift amount of 360 ° is allowed to pass. 21. According to the tuning control method described in item 19 of the patent application scope, the voltage divider circuit is pressed into the cascade connected by the aforementioned Part of the feedback loop formed by the two phase shift circuits and the non-inverting circuit; the tuning circuit pulls the AC signal input to the voltage dividing circuit as a tuning signal. 22. According to the patent application The tuning control method described in item 19, wherein the conversion mechanism in the two-phase phase shift path includes a transistor; the source and drain, or the emitter and collector of the transistor are connected respectively A second resistance with approximately equal resistance; input an AC signal to the gate or base of the aforementioned electric #, k; and to the source of the aforementioned crystal (: 0 ?, 'between or #, pole: v collector, Connect the components that constitute the aforementioned series circuit $ _component-resistor 23. According to the tuning control method described in item 2 of the patent application scope, wherein the tuning circuit includes a phase reversal of the AC signal input Inverting circuit, the inverting circuit is inserted in a part of the feedback loop formed by the two cascaded phase shift circuits; at least one of the two phase shift circuits includes: a conversion mechanism It converts the input AC signal into the same or reversed AC signal, and draws it to M; a series circuit is composed of a reactance element and a first resistor formed from a ballast container or sensor, and can be The size of the control paper mentioned above is applicable to the Chinese National Standard (CNS) Α4 specification (210X2S »7mm) 49 (please read the precautions on the back before filling in this page) 申請專利範圍 經濟部中央標準局員工消費合作社印裝 制信號來變更時間常數;及合成機構,係透過前述串 聯電路之一方端合成由前述變換檐構所變換的一方之 交流信號,且透過前述串聯電路之另一方端合成另一 方之交流信號。 24·依據申請專利範圍第23項所述之調諧控制方法,其中 前述調諧電路,係藉由前述级聯連接的兩個相移 電路全體,僅讓相位位移量之合計成180°之頻率附 近之信號通過。 25.依據申請專利範圍第23項所述之調諧控制方法,其中 將分壓電路插入由前述级聯連接的兩個相移電路 及前反相電路所形成之回授環路之一部分; 前述調諧霄路,係將輪入於前述分暖霣路之交流 信號作為調諧信號_出。 26·依據申請專利範園第23項所述之調諧控制方法,其中 前述兩個相移霣路内之前述變換機構包含有電晶 體;於前述電晶鱧之源極及漏極、或者射極及集電掻 ,分別連接霣阻值大致相等之第二電阻;將交流信號 输入於前述霄晶之柵極或基極;於前述電晶體之源 極X湄極間或射〗極《V集.霜極.間,連接構成前述串聯電 路之前述霄抗元件犮剪述笔一電阻。 27·依據申請尊利範圍第2項所述之調諧控制方法,其中 將構成組件一醱形成於半導體基片上。 (請先閲讀背面之注意事項再填寫本頁) 裝· 訂 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐)The scope of the patent application is changed by the printed signal of the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economy to change the time constant; The other side of the circuit synthesizes the AC signal of the other side. 24. The tuning control method according to item 23 of the patent application scope, wherein the tuning circuit is the total of the two phase shift circuits connected by the cascade, and only the sum of the phase shift amounts to a frequency around 180 ° The signal passes. 25. The tuning control method according to item 23 of the patent application scope, wherein the voltage divider circuit is inserted into a part of the feedback loop formed by the two phase shift circuits and the front inverter circuit connected in the aforementioned cascade; Tuning the Xiaolu is to use the AC signal that has entered the previously divided warm road as the tuning signal. 26. According to the tuning control method described in item 23 of the patent application park, wherein the transformation mechanism in the two phase-shifted paths includes transistors; the source and drain, or the emitter of the transistors And collector, connect second resistors with approximately equal resistance; input the AC signal to the gate or base of the aforementioned crystal; between the source X and the pole of the aforementioned transistor; Frost pole. Connect the resistance of the above-mentioned anti-corresponding element that constitutes the above-mentioned series circuit. 27. The tuning control method according to item 2 of the application scope, in which a component is formed on a semiconductor substrate. (Please read the precautions on the back before filling out this page) Binding · Order This paper size is applicable to China National Standard (CNS) A4 specifications (210X297mm)
TW85106444A 1995-11-09 1996-05-30 Tuned control system TW297185B (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP31756695 1995-11-09
JP31722895 1995-11-09
JP31722795 1995-11-09
JP31739395 1995-11-09
JP31756795 1995-11-09

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TW297185B true TW297185B (en) 1997-02-01

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TW85106444A TW297185B (en) 1995-11-09 1996-05-30 Tuned control system

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