Claims (1)
經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（9 ) (Epi-taxial layer) Epi 上面〔亦類似一種 SOS 結構 (SOS=Silic〇n〇n Sapphire),矽藍寶石生長層〕。 第9圍為利用截割方式所繪出並具有一個接線端PI0 之積體半導體電路，在操作期間，該積體半導體電路之 接線端不僅可引導輸入信號IN,而且，亦可引導輸出信 號OUT (所謂之輸入/輸出接線端）。在此種接線端PI0 上不僅可舆適當之第二電路部份CKT-0相連接，而且， 亦可與適當之第一電路部份CKT-I相連接。對於此種接 線端PI0而言，僅需裝設一値唯一之第一保護電路PADIN ，該保護電路是設在接線端PI0及第一電路部份CKT-I之 間。該唯一之第一保護電路PADIN在操作期間不僅具有 第一保護電路PADIN之保護功能，而且，亦具有第二保 護電路PAD0UT之功能，因而，在接線端PI0及第一保護 電路PADIN間之導線LI部份對第二電路部份CKT-0而言亦 具有另一條導線L01之作用。 根據第9圖所示之實施例，其中，在第一保護電路 PADIN及第一電路部份CKT-I之間裝設有一個通路閘極電 晶體（Pass-gate transistor) PGT並具有其源極及汲極 長度（Source-Drain length)。通路閘棰電晶體PGT之閘 棰不是舆第二供應電位VCC相連接，就是與定時信號 (Timing signal)0相連接β若在操作期間，其閘棰是 與半導體電路之第二供應電位（Second supply potenfial) VCC相連接之情況下，則在操作期間該通路 本紙張尺度適用中國國家標準（CNS > A4規格（210X297公釐） --------^ -裝------訂-----2威 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印裝 A7 B7 五、發明説明（β) 閛捶電晶體PGT具有可傳導性。在其他情況下，即在操 作中之閘棰與定時倍號Φ相連接之情況下，若定時信號 φ已建立起其活性電平（Active level)〔在一傾具有n 鵪波道之電晶體（n-channel-transistor)用作通路阐極 電晶體（Pass-Gate transistor) PGT之情況下：定時 號Φ具一個高電平（High level)〕，則输入信號ίΝ用之 通路閘掻電晶體PGT被連通。在其他之情況下*例如’ 若输入/输出接線端ΡΙ0直接用作输出信號0”之接線端 ，則可能籍定時信號Φ之肋而將通路閛棰電晶體PGT阻 遏，若输入/輸出接線端PI0直接用作输入信號1(|之接 線端，則可使通路閘極電晶體在電氣上連通。因此，在 預先設計時，亦可將通路閛極電晶餵PGT裝設在此種第 一保護電路PADIN内，該第一保護電路與各接線端PI相 連接，則可使該通路閘極電晶體PGT在操作中專門供引 導输入信號I N之需。 第10圖顯示通路閛極電晶體PGT之一種有利之確定尺 寸：因而，閘棰6顯示分別與源極S及汲棰D相隔一定 距離B ,該距離B至少為各電晶醱所箱適當距離值之 1.5倍，該距離值為積醱半導體電路在保護霣路之外面 所具有之距離（例如，在電路部份cu-1，CKT-〇内）。 此外，如在第4及9圖中所示，若附加導線L01之歐 姆值低於引導各値別输出信號之導線L0，則在實例 中所列舉之導線電阻為"〇 . 8歐姆（Ω )"及"2 . 5歃姆（Ω )" -1 2 - 本紙張尺度適用中國國家標準（CNS)A4規格（2丨0X297公瘦） I-------\ .裝------訂-----/咸 (请先閲讀背面之注意事項再填寫本頁) A7 B7 i、發明説明（d) 或"1歐姆，，及"2歐姆"。在此種配置中，各個別之第二 保護電路PADOUT (或各第一保護電路PADIN，如在第9 豳I中所示輸入/輸出接線端PI〇之情況）可比無此種措 施之保護電路更能迅速對一種産生靜電放電（ESD)之現 象作反應。引導輸出信號OUT用之各傾別導線L0因而應 構成至少具有2歐姆之電胆，該電阻則均句分配在各個 別接線端P0 (或PI0)及所屬之第二電路部份（CKT_0)間 之區域内。 眾所週知，在每一個具有第一電路部份CKT_I及第二 電路部份CKT-0之積體半導體電路中，各井狀區域均構 成相同之傳導性（Conductivity)型式，但是，在操作期 間可導致不同之電位（Potential)，利用規格及設計定 則（Specification and design rules)則可確定’此 種井狀區域在最低限度内應構成何種相互間之距離值。 根據本發明之一種積體半導體電路中，若保護電路PADIN ，PAD0UT在場氣化物電晶體FOX之井狀區域，即源極井 (S-well)及汲極井（D-well)分別廚每一個場氣化物電晶 髏FOX構成相互間之距離A，該距離並未超過上述之最 低距離值時，則此種設計較為有利》同樣，此種情況如 在第3及5圖中所示，在該實施例中，（最低）距離值$ 5微米（#m)。若第一保護電路PADIN及/或第二保護電 路PAD OUT在其場氣化物電晶體FOX之源棰及汲極區域S， D經由多數之電氣接觸而與各個別在下面之并狀區域· -13- '本紙張尺度適用中國國家揉準(CNS M4祕（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) .裝· 訂 經濟部中央樣準局員工消費合作社印製 經濟部中央標準局員工消費合作社印裝 A7 B7 五、發明説明（p ) 卽汲搔井（S-well)或源極井（D-well)相連接，則對於一 種最佳防止靜電放電（ESD)發生事件所保護之積體半導 體電路更為有益。例如，此種情況可藉匾域Reg 之第 保護電路PADIt及其場氣化物電晶體FOX。 第11圖以示意圔方式顯示一種可能而有利之保護電路 佈置平視圖。為了一目了然之故，在本圖之場氣化物電 晶體FOX中僅繪出其源極53及汲棰D，而場氧化物電晶體 F〇X之閛掻則未繪出。本_不僅適用於第一保護電路 P A D I N ,而且，亦適用於第二保護罨路P A D 0 U T。因而， 場氣化物電晶FOX則構成指狀電晶體（Finger transistor) ，換言之，其源極S及汲極D均構成指形或梳形，因而 ，毎一源極指總是位於一個汲極指之侧面，反之亦然。 一種此一類型之構造已為所習知之德國專利DE-A 39 07 523所掲示β此種構造之特擻為一種彎曲形（Meandershaped)。 在 此種構 造之進 一步發 展中則 構成習 知之指 狀電晶體，而在其各角隅上則形成指尖，換言之，各個 別電晶髖之指端被切割成斜角。此外，亦可能對指狀電 晶體之設計，使指狀霄晶體之所有角隅均被切剌成斜角 。此種斜角（或去角，Chamfering)亦可構成一種圓形 (Roundness)之型式。 擴散霣阻（Diffusion resistance) Rdif是裝設在用 作零伏特電晶體（Zero-Volt-Transistor)之場控制二極 體ZVT之汲極D及場氧化物電晶體F0X之汲極D之間，因 -1 4 - 本紙張尺度逋用中國國家標準（CNS ) A4規格（2丨0X297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝. 訂 經濟部中央樣準局員工消費合作社印製 A7 、__________B7_ 五、發明説明（^ ) 此，該擴散電阻是在供其使用之最大面積内，換言之， 在預定之電阻值及在一定單位剖面積之電阻僳數 (s P e c i f i c r e s i s t a n c t p e r s e c t i 〇 n a 1 a r 叻 u n i t)之 情況下，該擴散電阻可盡可能擴散其長度及寬度，因而 *對擴散鼋阻Rdif而言則盡可能獲得較大之表面面積。 該表面積則在操作期間容易移除在擴散電阻Rdif内所産 生之損失功率（熱量）。 在第11圖中之場控制二極體（Field contorolled diode)ZVT是具有零伏持電晶體（Zero-volt-transistor) 之功能，其開極G則構成爐灶形（cooking shaped),因 而，在零伏待電晶體之源極（Source) S及汲極（Drain) D之間，該閘棰（Gate) G之區域内構成一定之寬度，因 此，可以盡可能避免發生靜電放霄（ESD)之損害。零伏待 電晶體之閘極G最好在零伏特電晶體之源極S及汲極D 之間分別構成一距離值A ,該距離值至少為電晶體之適 當距離值之1.5倍，該電晶體之距離為積體半導體電路 在保護裝置之外側所具有之距離值（例如，在電路部份 CKT-I , CKT-0)内）。 數種能避免靜電放電損害之有用的其他措施將説明於 後，而各措施均與各供應電位VSS, VCC用之電位匯流排 Pi，P2有關，或者，與在積龌半導體電路中可能存在之 基體偏暖電位（Bias potential of the Substrate) VBB之導線有關。第13圖則顯示在兩條電位匯流排PI, -15- 本紙張尺度適用中國國家標準（CNS ) A4*UM 210X297公釐） •一4裝 訂 ^一戒 (請先閲讀背面之注意事項再填寫本頁) A7 B7 五、發明説明（K ) P2之間裝設有多數之二極體Dd,其裝設之方式可使各二 棰體在積體半導體之調整操作中能産生遏止作用。若靜 電放電（ESD)現象出現時，則在操作期間引導第一供應 電位VSS之電位匯流排Pllrb第二電位匯流排P2 (在操作 期間對第一供應電位VSS所假定引導第二供應電位VCC之 正電位）産生較高之正電位，因此，由於靜電放電現象 所産生之正電位則經由各二極體Dd而漏導至第二電位匯 流排P2内，而且，因而不會造成任何損害。因此，在現 存之情況下，若在相互間之距離内，其最大距離可達10 公厘内裝設一値以上之二極體（如圖中所示），而且， 各二極體互相裝設在有規律之各距離内，則更為有意義 〇 第14圖亦顯示一種與第13圖相當之裝置，在該裝置中 ，各二極體可用場氣化物電晶體F0X-V,各電晶體之閘 搔則與第二電位匯流排P2相連接。同樣，各場氣化物電 晶體FOX-V構成最大為10公厘之相互間之距離，則更為 良好，此外，各電晶體亦應裝設在有規律之距離内。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 有許多積體半導體電路對一個及相同之供應電位俗由 多數之電位匯流排所構成，故亦可以電位匯流排（母線 )(Potential bus)表示β在以下部份將説明根據本發 明之積體半導體電路及其保護裝置之防止過電壓 (Over-voltage)方式，其中，亦構成多數之此種電位匯 流排。在有關之各圖中，基於簡化之原因，僅顯示具有 -1 6 - 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） A7 B7 經濟部中央樣準局員工消費合作社印製 五、發明説明 ( ) 1 1 此 種 電 位 匯 流 排 有 關 之 措 施 〇 1 1 第 1 E 圖 顯 示 具 有 兩 條 第 電 位 匯 流 排 P 1 並 分 別 以 P 1 -1 1 I 及 P 1 -2 標 示 〇 在 操 作 期 間 各 電 位 匯 流 排 假 定 為 本 發 明 積 r—V 請 1 I 體 半 導 體 電 路 之 第 一 供 應 電 位 VSS 〇 根據本發明， 各電 先 閱 讀 1 1 位 匯 流 排 P 1 -1 f P 1 -2 至 少 與 一 對 二 極 體 裝 置 D 1 » D2 ( 圖 背 1 I 之 1 中 所 示 為 二 對 ) 相 連 接 t 其 中 f 任 對 之 各 二 榷 體 裝 置 意 1 I D 1 » D 2均 互 相 以 反 平 行 (A n t i - pa r a 1 1 e ] )方式相並聯。 事 項 1 再 在 第 1 5圖 中 f 毎 一 個 二 極 體 裝 置 D 1或 D2均 分 別 由 各 锢 別 填 1 所 成 % 本 裝 之 二 極 體 組 〇 在 第 1 6 圖 中 所 示 之 裝 置 則 使 每 —- 個 二 頁 1 I 極 體 裝 置 D 1或 D2分 別 包 括 有 一 個 以 上 之 二 極 體 1 例 如 » 1 1 二 個 二 極 體 D 1 -1 9 D 1 -2或 D2 -1 9 D 2 -2 〇 1 I 假 若 第 二 電 位 匯 流 排 P 2 (供 第 二 供 應 電 位 VC C之需）亦 1 1 係 由 多 數 匯 流 排 P 2 -1 * P 2 -2所 組 成 9 則 相 對 地 亦 鼷 有 利 1T 1 〇 此 種 情 況 則 同 樣 在 第 15及 16 圖 中 分 別 在 括 弧 内 另 以 適 1 I 當 之 參 考 符 m 標 示 〇 1 1 對 專 家 而 » 無 疑 很 容 易 理 解 » 對 個 或 相 同 供 應 電 1 1.—— 位 用 之 多 數 電 位 匯 流 排 ( 例 如 f 對 第 一 供 應 電 位 VS S用 線 I 之 多 數 第 一 電 位 匯 流 排 P 1 -1 參 P 1 -2 9 P 1 -3) 可 構 成 不 同 1 1 之 歐 姆 電 阻 (Ohm i c R e s is t a n c e)並 用 作 導 體 之 導 軌 電 阻 1 | 之 需 ( 例 如 » 由 於 導 軌 之 不 同 長 度 及 / 或 不 同 橫 剖 面 所 1 I 引 起 之 不 同 電 阻 ) 〇 在 此 種 情 況 下 則 如 在 第 17 圖 中 所 示 1 1 之 三 條 第 一 電 位 匯 流 排 P 1 -1 9 P 1 -2 » P 1 -3 ( 或 三 條 第 二 1 I 電 位 匯 流 排 P 2 -1 9 P 2 -2 9 P 2 -3 9 相 當 於 在 第 17 圖 中 並 在 1 1 1 -1 7- 1 1 1 1 1 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（^ ) 括弧内所標示之參考符號）。各個別導軌電阻因而分別 以Rl, R2, R3表示並假定R3構成最小之電阻值。在此種 情況下，最有利之方式是使具有較大導軌電阻值之電位 匯流排{在本實例中，則包括具有電阻R1及R2之電位匯 流排Pl-1, P卜2(或P2-1, P2-2)),以星型方式（Star f0rB)與具有成對並分別以反平行方式互相並聯二極體 裝置Dl, D2之各導軌相連接，使能産生最小之值（R3)。 在第17圖中，具有最小電阻值之電位匯流排（或導軌） 為 P1-3 (或 P2-3)。 此外，亦有可能在積體半導體電路之半導體晶Η上使 多數之第一電位匯流排Pl-1, Ρ1-2 (或多數之第二電位 匯流排分別構成本身之電位接線端P-VSS (或P-VCC)。 在此種情況下，最好如在第18及19圖中所示，上述之二 極體装置Dl, D2並非與電位匯流排Ρ卜1, Ρ1-2及可能之 Pl-3(或Ρ2-1, Ρ2-2,及可能之Ρ2-3)相連接（參考第 15至17圖），而是舆各個別之電位接線端P-VSS (或Ρ-VCC)相連接。因此，第19圖則顯示與第17圖相當之情 況，換言之，為一種電位接線端P-VSS (或P-VCC)之星 型連接（S t a r C ο n n e c t i ο η)。 第20及21圖分別為積體半導體電路之有效靜電放電 (ESD)保護措施，該項保護方式是在其半導體晶Η上構 成一基體偏壓電位（Bias potential of the substrate) VBB用之一個或多锢基體偏壓電位接線端P-VBB,該基體 -1 8 - 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ^-裝 訂 ^線 (請先閲讀背面之注意事項再填寫本頁)· A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明 (，7 ) 1 1 偏 壓 電 位 則 在 操 作 期 間 引 導 半 導體 電路操 作 。在 過 去 之 1 1 時 期 内 9 積 體 半 導 體 電 路 在 晶 Η上 所設之 此 種基 體 偏 壓 1 I 電 位 接 線 端 P- VBB是使基體偏壓電位VBB從 外 部經 由 在 外 -N 請 I 殼 上 所 設 之 一 傾 插 脚 (P i e l)而輪入。 但是， 在現今已不 先 閱 1 1 再 有 此 種 方 式 存 在 9 主 要 是 由 於現 代所採 用 之基 體 偏 壓 背 1 之 1 電 位 VBB多半是藉基體偏壓發生器（Bias v ο 1 t a g e 注 意 1 1 ge n e r a t 0 Γ of the S u b s t r a te)之助而在晶片内部産生 事 項 1 I 再 9 因 此 » 此 種 外 部 接 線 端 則 可 放棄 。但是 亦有 可 能 使 填 裝 有 内 本 具 部 基 體 偏 壓 發 生 器 之 積 體半 導體電 路 亦如 同 以 往 頁 ^^ 1 1 之 情 況 而 構 成 此 種 外 部 之 接 線 端， 在操作 期 間， 該 接 線 1 1 端 則 可 引 導 基 體 偏 πΠΙ 壓 電 位 VBB , 例如，可應用在測量及 1 I / 或 試 驗 之 百 的 上 〇 此 外 • 亦 有可 能使此 種 積醴 半 導 體 1 1 電 路 並 非 構 成 插 脚 型 式 之 外 部 接線 端，以 供 基體 偏 mn 壓 電 1Τ 1 位 VB B之用， 但是 (例如， 基於所應用將晶片嵌入外殼 1 I 内 之 裝 配 技 術 之 原 因 ) 9 可 使 半導 體晶片 構 成一 锢 此 種 1 1 基 髏 偏 壓 電 位 接 線 端 P- VB B , -條 (或多條） 之晶Η外 j 部 導 線 可 與 該 接 線 端 連 接 9 各 外部 導線可 引 入積 體 半 導 | 體 電 路 之 外 殼 内 9 而 導 線 之 連 接端 則在積 體 半導 體 電 路 1 1 之 表 面 上 ( 多 半 是 設 在 積 體 半 導體 電路之 端 面上 並 在 聯 1 | 機 數 據 外 殼 { D I L (D at a in L i n e ) case} 内或在顯示 1 1 信 息 處 理 機 外 殼 { D I P (D is Pl ay I n f 〇 r in a t i on 1 1 Pr 0 C e s so r ) C as e} 内 此種措施之作用， 例如， 在外 1 I 殼 内 晶 片 之 裝 配 期 間 可 對 半 導 體晶 片之自 旋 或自 旋 載 體 1 1 1 -1 9- 1 1 1 1 1 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公嫠） A7 B7 五、發明説明（ι8 ) (S p i η n i n g 〇 r S p i η n i n g c a r r i e r )産生機械上之穩定性 ο 在以上所述之各種情況中，其中，可用一條電氣導線 從外殼在表面上之一晶片接線端P-VBB導入積體半導體 電路内，或者，根本以該接線端為插脚，但是，此種接 線端之防止靜電放電（ESD現象發生），則更具有重大意 義，主要是由於經由此種導線可使靜電放電現象作用在 接線端P-VBB,因而，亦作用在積體電路上。 第20圖為此種保護裝置之一有利實施例型式。在基體 偏壓電位VBB用之接線端P-VBB及第一電位匯流排Ρ1之間 裝設有一個場二氧化物電晶體F0X-B,該電晶體之閘極 則與接線端P-VBB相連接，該場氣化物電晶體F0X-B是在 其源極區域S之下面構成另一個井狀區域，即基體偏壓 電位井（V Β Β - w e 1 1)。 第21圖為另一種實施例型式。該實施例型式與第20圖 之實施例型式相比較，其差異僅在於另一锢井狀區域， 即基體偏壓電位井（VBB-well)是裝設在場氧化物電晶體 F0X-B之汲極區域D之下面，而並非在源極匾域S之下 面。 , •裝 訂 -" ! (請先閲讀背面之注意事項再填寫本頁) 經滴部中央標準局員工消費合作社印製 -20- 本紙張尺度適用中國國家標準（CNS〉A4規格（210X297公釐）Printed by the Employees and Consumers Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A7 B7 V. Description of the invention (9) (Epi-taxial layer) Epi above [also similar to a SOS structure (SOS = Silic〇n〇n Sapphire), sapphire growth layer]. The ninth circle is an integrated semiconductor circuit drawn by a cutting method and having a terminal PI0. During operation, the terminals of the integrated semiconductor circuit can guide not only the input signal IN, but also the output signal OUT. (The so-called input / output terminals). This terminal PI0 can be connected not only to the appropriate second circuit part CKT-0, but also to the appropriate first circuit part CKT-I. For this type of terminal PI0, it is only necessary to install a unique first protection circuit PADIN, which is provided between the terminal PI0 and the first circuit part CKT-I. The only first protection circuit PADIN not only has the protection function of the first protection circuit PADIN during operation, but also has the function of the second protection circuit PADOUT. Therefore, the conductor LI between the terminal PI0 and the first protection circuit PADIN Part of the second circuit part CKT-0 also has the function of another wire L01. According to the embodiment shown in FIG. 9, a pass-gate transistor PGT is provided between the first protection circuit PADIN and the first circuit part CKT-I and has its source And the drain length (Source-Drain length). The gate of the channel gate transistor PGT is either connected to the second supply potential VCC or to the timing signal 0. If during operation, the gate is connected to the second supply potential of the semiconductor circuit (Second supply potenfial) When VCC is connected, during the operation, the paper standard of this channel is applicable to the Chinese National Standard (CNS > A4 specification (210X297mm) -------- ^ -installed ----- -Order ----- 2 Wei (please read the notes on the back before filling in this page) A7 B7 printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs V. Description of Invention (β) The Hammer Transistor PGT is conductive In other cases, that is, when the gate in operation is connected to the timing multiplier Φ, if the timing signal φ has established its active level (active power with n qua channels at one tilt) When the crystal (n-channel-transistor) is used as a pass-gate transistor (Pass-Gate transistor) PGT: the timing number Φ has a high level (high level), then the channel gate for the input signal The crystal PGT is connected. In other cases * for example ' If the input / output terminal PI0 is directly used as the output signal 0 ”terminal, the channel signal transistor PGT may be suppressed by the rib of the timing signal Φ, if the input / output terminal PI0 is directly used as the input signal 1 ( | The terminal can make the path gate transistor electrically connected. Therefore, during the pre-design, the path gate electrode transistor can also be installed in this first protection circuit PADIN with the PGT. The protection circuit is connected to each terminal PI, so that the channel gate transistor PGT can be used exclusively for guiding the input signal IN during operation. Figure 10 shows an advantageous determination of the size of the channel gate transistor PGT: , Gate 6 shows a certain distance B from the source S and drain D respectively, the distance B is at least 1.5 times the appropriate distance value of each transistor, the distance value is that the semiconductor circuit is in the protection of the road The distance outside (for example, in the circuit part cu-1, CKT-〇). In addition, as shown in Figures 4 and 9, if the ohmic value of the additional wire L01 is lower than the guide output signal The lead L0 is listed in the example The wire resistance is " 〇. 8 ohms (Ω) " and " 2. 5 歃 姆 (Ω) " -1 2-This paper scale is applicable to China National Standard (CNS) A4 specifications (2 丨 0X297 male thin) I ------- \ .install ------ order ----- / salty (please read the precautions on the back before filling this page) A7 B7 i. Description of invention (d) or " 1 ohm, and " 2 ohm ". In this configuration, each second protection circuit PADOUT (or each first protection circuit PADIN, as in the case of the input / output terminal PI〇 shown in Section 9) is comparable to a protection circuit without such measures It can more quickly react to a phenomenon that produces electrostatic discharge (ESD). The individual lead wires L0 for guiding the output signal OUT should therefore form an electric bladder with at least 2 ohms, and the resistance should be distributed between each terminal P0 (or PI0) and the second circuit part (CKT_0) to which it belongs Within the area. As we all know, in each integrated semiconductor circuit with a first circuit part CKT_I and a second circuit part CKT-0, each well-shaped region constitutes the same conductivity type, but, during operation, it can cause Different potentials (Specification and design rules) can be used to determine the distance between such well-shaped areas in the minimum. According to an integrated semiconductor circuit of the present invention, if the protection circuit PADIN and PADOUT are located in the well-shaped area of the field gasification transistor FOX, namely the source well (S-well) and the drain well (D-well), respectively A field gasification electric crystal FOX constitutes the distance A between each other, and the distance does not exceed the above minimum distance value, then this design is more advantageous. ”Similarly, this situation is shown in Figures 3 and 5, In this embodiment, the (lowest) distance value is $ 5 microns (#m). If the first protection circuit PADIN and / or the second protection circuit PAD OUT are in the source and drain regions S and D of their field vapor transistor FOX, D is connected to each of the parallel regions below by a large number of electrical contacts- 13- 'This paper scale is applicable to the Chinese National Standard (CNS M4 secret (210X297mm) (please read the notes on the back before filling this page). Binding · Order the Ministry of Economic Affairs Central Sample Bureau Employee Consumer Cooperative Printed by the Ministry of Economy A7 B7 printed by the Central Standards Bureau employee consumer cooperative. V. Description of invention (p) The connection of S-well or source well (D-well) is the best way to prevent the occurrence of electrostatic discharge (ESD) The integrated semiconductor circuit protected by the event is more beneficial. For example, in this case, the first protection circuit PADIt of the plaque field Reg and its field vaporization transistor FOX can be used. Figure 11 shows a possible and beneficial protection in a schematic way. Plan view of the circuit layout. For the sake of clarity, only the source 53 and drain D are drawn in the field vapor transistor FOX in this figure, but the field oxide transistor F〇X is not drawn. This _ not only applies to the first The protection circuit PADIN is also suitable for the second protection circuit PAD 0 UT. Therefore, the field gasification transistor FOX constitutes a finger transistor (Finger transistor), in other words, its source S and drain D both constitute a finger Shape or comb shape, therefore, every source finger is always on the side of a drain finger, and vice versa. A structure of this type has been shown by the known German patent DE-A 39 07 523. The special feature of the structure is a curved shape (Meandershaped). In the further development of this structure, it constitutes the conventional finger-like transistors, and the fingertips are formed on its corners, in other words, the fingers of each different crystal hip The ends are cut into bevels. In addition, the design of the finger transistors may be such that all corners of the finger crystals are cut into bevels. Such bevels (or chamfering) may also constitute A type of roundness. Diffusion resistance (Diffusion resistance) Rdif is installed on the drain D and field oxide of the field control diode ZVT used as a zero-volt transistor (Zero-Volt-Transistor). Between the drain D of the crystal F0X, because -1 4-The size of this paper adopts the Chinese National Standard (CNS) A4 specification (2 丨 0X297mm) (please read the notes on the back before filling out this page). It is printed by the Employee Consumer Cooperative of the Central Sample Bureau of the Ministry of Economic Affairs System A7, __________B7_ V. Description of the invention (^) Here, the diffusion resistance is within the largest area available for its use, in other words, the predetermined resistance value and the resistance number in a certain unit cross-sectional area (s P ecificresistanctperse cti 〇na In the case of 1 ar unit), the diffusion resistance can diffuse its length and width as much as possible, so for the diffusion resistance Rdif, the largest surface area is possible. This surface area makes it easy to remove the lost power (heat) generated in the diffusion resistor Rdif during operation. In the field control diode in Figure 11 (Field contorolled diode) ZVT has the function of zero-volt-transistor (Zero-volt-transistor), its open pole G constitutes a cooker shape (cooking shaped), therefore, in Between the source S and the drain D of the zero-volt standby transistor, the area of the gate G constitutes a certain width, therefore, electrostatic discharge (ESD) can be avoided as much as possible Damage. The gate electrode G of the zero-volt transistor is preferably formed a distance value A between the source electrode S and the drain electrode D of the zero-volt transistor, and the distance value is at least 1.5 times the appropriate distance value of the transistor. The crystal distance is the distance value that the integrated semiconductor circuit has on the outside of the protection device (for example, within the circuit part CKT-I, CKT-0). Several other useful measures to avoid electrostatic discharge damage will be described later, and each measure is related to the potential busbars Pi, P2 for each supply potential VSS, VCC, or may be present in the semiconductor circuit The Bias potential of the Substrate is related to the VBB wire. Figure 13 shows the two potential bus bars PI, -15- This paper scale is applicable to the Chinese National Standard (CNS) A4 * UM 210X297 mm) • One 4 binding ^ one ring (please read the notes on the back before filling in (This page) A7 B7 V. Description of invention (K) A large number of diodes Dd are installed between P2. The way of installation allows each diode to have a deterrent effect in the adjustment operation of integrated semiconductors. If an electrostatic discharge (ESD) phenomenon occurs, the potential bus bar Pllrb of the first supply potential VSS is guided during operation to the second potential bus bar P2 (the second supply potential VCC assumed to lead to the first supply potential VSS during operation (Positive potential) generates a higher positive potential. Therefore, the positive potential generated by the electrostatic discharge phenomenon leaks into the second potential busbar P2 through each diode Dd, and therefore, will not cause any damage. Therefore, in the existing situation, if the distance between each other, the maximum distance of up to 10 mm can be installed with more than one diode (as shown in the figure), and the diodes are installed with each other. Set at regular distances, it makes more sense. Figure 14 also shows a device equivalent to Figure 13, in this device, each diode can use field vaporized transistor F0X-V, each transistor The gate is connected to the second potential bus P2. Similarly, the FOX-V of each field gas transistor constitutes a maximum distance of 10 mm from each other, which is better. In addition, each transistor should also be installed within a regular distance. Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page). There are many integrated semiconductor circuits for one and the same supply potential. It is composed of most potential buses, so it can also be potential. The bus (Potential bus) represents β. In the following part, the over-voltage prevention method of the integrated semiconductor circuit and the protection device thereof according to the present invention will be explained. Among them, most of these potential busses also constitute row. In the relevant figures, for reasons of simplification, it is only shown that the paper size is -1 6-This paper standard is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) A7 B7 Printed by the Employee Consumer Cooperative of the Central Sample Bureau of the Ministry of Economic Affairs System V. Description of the invention () 1 1 Measures related to this potential bus 〇1 1 The first E figure shows that there are two first potential buses P 1 and they are marked with P 1 -1 1 I and P 1 -2 respectively. During operation, each potential bus is assumed to be the product r-V of the present invention. The first supply potential of the bulk semiconductor circuit is VSS. According to the present invention, each power first reads the 1-bit bus P 1 -1 f P 1 -2 Connect to at least one pair of diode devices D 1 »D2 (two pairs shown in Figure 1 I of the back) t where f is any two pairs of device devices 1 ID 1» D 2 are inverse to each other Parallel (A nti-pa ra 1 1 e]) parallel connection. Matter 1 In figure 15, each f of a diode device D 1 or D2 is filled by 1% respectively. The installed diode group 〇 The device shown in figure 16 Make every two pages 1 I diode device D 1 or D2 include more than one diode 1 for example »1 1 two diodes D 1 -1 9 D 1 -2 or D2 -1 9 D 2 -2 〇1 I If the second potential bus P 2 (for the second supply potential VC C) is also 1 1 is composed of the majority of the bus P 2 -1 * P 2 -2 9 is relatively relatively Favorable 1T 1 〇 This situation is also marked in brackets in Figures 15 and 16 respectively with a suitable reference symbol of 1 I. 〇1 1 For experts »It is undoubtedly easy to understand» For one or the same supply of electricity 1 1 .—— The majority of potential busbars for bit use (eg f for the first supply potential VS S for the majority of the first power supply Bit busbars P 1 -1 Refer to P 1 -2 9 P 1 -3) Can form different 1 1 ohmic resistance (Ohm ic R es is tance) and be used as the guide rail resistance of the conductor 1 | (Different resistance caused by 1 I of different lengths and / or different cross-sections) 〇 In this case, as shown in Figure 17 1 1 three first potential busbars P 1 -1 9 P 1 -2 » P 1 -3 (or three second 1 I potential busbars P 2 -1 9 P 2 -2 9 P 2 -3 9 is equivalent to in Figure 17 and at 1 1 1 -1 7- 1 1 1 1 1 1 This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm). The A7 B7 is printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. 5. Description of Invention (^) Reference symbols indicated in parentheses). The resistance of each individual rail is therefore represented by R1, R2, R3 and assumes that R3 constitutes the smallest resistance value. In this case, the most advantageous way is to make the potential bus bar with a larger rail resistance value {in this example, it includes the potential bus bars with resistance R1 and R2 Pl-1, P Bu 2 (or P2- 1, P2-2)), connected in a star-shaped manner (Star f0rB) and each guide rail of a pair of diode devices Dl, D2 connected in parallel with each other in an anti-parallel manner, so as to generate the minimum value (R3) . In Figure 17, the potential bus bar (or rail) with the smallest resistance value is P1-3 (or P2-3). In addition, it is also possible to make the majority of the first potential busbars Pl-1, P1-2 (or the majority of the second potential busbars on the semiconductor crystal H of the integrated semiconductor circuit respectively constitute their own potential terminals P-VSS ( Or P-VCC). In this case, as shown in Figures 18 and 19, it is better that the above-mentioned diode device Dl, D2 is not connected to the potential busbars P1, P1-2 and possibly P1. -3 (or P2-1, P2-2, and possibly P2-3) are connected (refer to Figures 15 to 17), but are connected to different potential terminals P-VSS (or P-VCC) Therefore, Fig. 19 shows a situation equivalent to Fig. 17, in other words, a star connection (S tar C ο nnecti ο η) of the potential terminal P-VSS (or P-VCC). 20 and 21 The figures are the effective electrostatic discharge (ESD) protection measures of integrated semiconductor circuits. The protection method is to form a Bias potential of the substrate (Bias potential of the substrate) on the semiconductor crystal H. One or more substrates for VBB Bias potential terminal P-VBB, the substrate -1 8-This paper size is applicable to China National Standard (CNS) A4 specification (210X297mm) ^ -installed Order ^ line (please read the precautions on the back before filling in this page) · A7 B7 Printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Invention Instructions (, 7) 1 1 The bias potential guides the semiconductor circuit during operation Operation. In the past 1 1 period 9 this kind of substrate bias of the integrated semiconductor circuit on the crystal H 1 I potential terminal P-VBB is to make the substrate bias potential VBB pass from outside to outside -N please I One of the tilt pins (P iel) provided on the shell turns in. However, it is no longer read first 1 1 and then this way exists 9 mainly due to the majority of the current-used substrate bias back 1 1 potential VBB It is due to the substrate bias generator (Bias v ο 1 tage Note 1 1 ge nerat 0 Γ of the S ubstra te) that the matter is generated inside the chip 1 I then 9 Therefore »This external terminal can be abandoned. However, it is also possible that the integrated semiconductor circuit filled with the base bias generator in the internal part also constitutes such an external terminal as in the case of the previous page ^^ 1 1. During operation, the terminal 1 1 It can guide the substrate bias πΠΙ piezoelectric potential VBB, for example, can be used in the measurement and 1 I / or test a hundred. In addition • It is also possible to make this integrated semiconductor 1 1 circuit does not constitute a pin type external terminal , For the substrate bias mn piezoelectric 1T 1 bit VB B, but (for example, based on the reason for the application of the assembly technology of the chip embedded in the housing 1 I) 9 can make the semiconductor chip constitute a single 1 1 base Bias potential terminal P- VB B,-(or more) crystal Η outer j part of the wire can be connected to the terminal 9 each external wire can be introduced into the integrated semiconductor | body circuit housing 9 and the wire The connection terminal is on the integrated semiconductor circuit 1 1 On the surface (mostly on the end surface of the integrated semiconductor circuit and in the 1 | machine data case {DIL (D at a in L ine) case} or in the display 1 1 information processor case {DIP (D is Pl ay I nf 〇r in ati on 1 1 Pr 0 C es so r) C as e} within the role of such measures, for example, during the assembly of the chip in the outer 1 I shell can spin on the semiconductor wafer or spin carrier 1 1 1 -1 9- 1 1 1 1 1 This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 public daughter) A7 B7 5. Invention description (ι8) (S pi η ning 〇r S pi η ningcarrier) Produces mechanical stability. In each of the above-mentioned cases, one of the electrical wires can be introduced into the integrated semiconductor circuit from one of the chip terminals P-VBB on the surface of the housing, or, at all, the terminal is used as Pins, but the prevention of electrostatic discharge (ESD phenomenon) of this terminal is more important, mainly because the static electricity can be Electrical phenomenon acts terminal P-VBB, thus, also acts on the integrated circuit. Figure 20 shows an advantageous embodiment of this type of protection device. A field oxide transistor F0X-B is installed between the terminal P-VBB for the substrate bias potential VBB and the first potential bus bar P1, and the gate of the transistor is connected to the terminal P-VBB Connected, the field gas transistor FOX-B forms another well-shaped region under its source region S, that is, the substrate bias potential well (V Β Β-we 1 1). Figure 21 is another embodiment type. The difference between this embodiment type and the embodiment type in FIG. 20 is that the other well-shaped region, that is, the substrate bias potential well (VBB-well) is installed in the field oxide transistor F0X-B Below the drain region D, not below the source plaque region S. , • Binder- "! (Please read the precautions on the back before filling out this page) Printed by the Employee Consumer Cooperative of the Central Bureau of Standards -20- This paper scale is applicable to the Chinese National Standard (CNS> A4 specification (210X297 mm )
第8 2 1 1 0 09 5號「積體半導體電路」專利案 (85年8月修正） 杰申請專利範圍 1. 一種具有半導體基體（Sub)之積體半導體電路，該積 體半導體電路包括有： —至少一個第一電位匯流排（P1),在操作期間，該電 位匯流排可引導半導體電路之第一供應電位（VSS), —至少一個第二電位匯流排（P2)，在操作期間，該電 位匯流排可引導半導體電路之第二供應電位（VCC), —至少一個供輸入信號（IN)接收及處理用之第一電路 部份（C K T - I), —至少一個第二電路部份（CKT-0),在該電路部份内 ,於半導體電路之操作期間至少可産生半導體電路 之一個輸出信號（OUT)及 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) ——個防止過電壓之保護裝置，其中，在每一個供引 導輸入信號（IN)之導線（LI)用之接線端（PI)上設有 一個第一保護電路（PADIN),該保護電路裝設在各 個別接線端（PI)及第一電路部份（CKT-I)之間並具有 以下之特擻： -在引導輸入信號（IN)之導線（LI)及第一電位匯流 排（P 1)之間裝設有在電氣上互相並聯之一個場氧 化物電晶體（F 0 X )及一個場控制二極體（Z V T ),其 -1 - 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公嫠）No. 8 2 1 1 0 09 No. 5 "Integrated Semiconductor Circuit" Patent Case (Amended in August 1985) Jie applied for patent scope 1. An integrated semiconductor circuit with a semiconductor substrate (Sub), the integrated semiconductor circuit includes : At least one first potential bus (P1), during operation, the potential bus can guide the first supply potential (VSS) of the semiconductor circuit,-at least one second potential bus (P2), during operation, The potential bus can guide the second supply potential (VCC) of the semiconductor circuit,-at least one first circuit part (CKT-I) for receiving and processing the input signal (IN),-at least one second circuit part (CKT-0), in the circuit part, at least one output signal (OUT) of the semiconductor circuit can be generated during the operation of the semiconductor circuit and printed by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the notes on the back first (Fill in this page again) ——A protection device against overvoltage, in which a first protection circuit (P) is provided on each terminal (PI) for the lead (LI) of the lead input signal (IN) ADIN), the protection circuit is installed between each terminal (PI) and the first circuit part (CKT-I) and has the following special features:-the lead (LI) and the lead (LI) of the input signal (IN) and A field oxide transistor (F 0 X) and a field control diode (ZVT) electrically connected in parallel with each other are installed between the first potential busbar (P 1), -1-This paper size is applicable China National Standards (CNS) A4 specifications (210X297 public daughter)