TW296474B - - Google Patents

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TW296474B
TW296474B TW085103887A TW85103887A TW296474B TW 296474 B TW296474 B TW 296474B TW 085103887 A TW085103887 A TW 085103887A TW 85103887 A TW85103887 A TW 85103887A TW 296474 B TW296474 B TW 296474B
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bonding
input
semiconductor
distance
integrated circuit
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TW085103887A
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Chinese (zh)
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Yamaha Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/01004—Beryllium [Be]
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    • H01L2924/01006—Carbon [C]
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    • H01L2924/01033—Arsenic [As]
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    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
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    • H01L2924/01082—Lead [Pb]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

經濟部中央榡隼局員工消費合作社印裝 A7 B7 五、發明説明（1 ) 發明背景： (a )發明領域 本發明有關於半導體積體電路裝置，特別有關於一種 能夠避免引線間短路的半導體積體電路裝置》 (b )相關技藝說明 在積體電路（I C )之半導體晶片中，於晶片週邊區 域處設有結合墊。結合墊經由結合線（引線）而與封裝構 件的內部引線連接。 結合墊通常等距安置成一線。如果使用到數個結合墊 ’則通常以狹窄之固定間距安置，以便利接線結合器之機 器作業。如果一列結合墊數目不夠，則可設置兩列或更多 列的結合墊，並使每一列結合墊在側向上平移例如半個間 距’以使一列結合墊與其內外列的結合墊成交錯安置。在 某些情形下，結合墊的配置係根據電路限制來決定。 圖3 A示出在晶片週邊區域中成列安置之結合墊的配 置一例。在矽晶片5 1的週邊區域中設置了一列結合墊 5 2。相鄰結合墊5 2之間的距離d爲固定》 圖3 B示出兩列結合墊成鋸齒狀交錯安置的一例。兩 列結合墊5 4沿矽晶片5 1的週邊區域交錯安置而構成鋸 齒狀或棋盤狀圖型。此種鋸齒狀圖型可供設置多個結合墊 。各列中相鄰結合墊之間的距離d爲固定。 對設有多個結合墊的半導體晶片進行接線結合時，半 導體晶片角落區域處的結合線之間有短路的危險。如果使 «μ· 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公慶） 扯衣！ (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局貝工消费合作社印製 A7 _____B7 五、發明説明（2) 用塑膠模，樹脂流很可能造成結合線間的短路。 發明節要： 本發明目的之一便是要提供一種結合線之間較少短路 的半導體積體電路裝置。 本發明的另一目的是要提供一種能夠確保結合線之間 有均勻距離的半導體積體電路裝置。 依據本發明之第一部份內容，乃是提供有一種半導體 稹體電路裝置，包含：具有多個內引線的一個封裝構件； 一個半導體積體電路晶片，此晶片具有一個週邊區域，區 域中含有多個輸入/輸出墊，該半導體積體電路晶片爲於 各角落處結合在一起的側邊所界定：以及將內引線與輸入 /输出墊電氣互連的引線，其中在接近角落之一的一個區 域中，引線與半導體積體電路晶片的側邊之一以6 0度或 更小的角度相交，且輸入/輸出墊之間的距離較其他區域 中者爲寬，以使引線之間的距離大體均勻。 如果結合墊以相等間距安置，與半導體積體電路晶片 側邊以6 0度或小於6 0度的角度相交的引線間的距離便 變得很短。即使在此種情形下，如果將晶片上輸入/输出 結合墊之間的距離在角落區域處設定得較長以使引線間的 距離大體均勻，便可避免避免引線間短路的危險。 依據本發明之另一部份內容，乃是提供有一種半導體 裝置，包含：具有多個內引線的一個封裝構件；一個矩形 半導體晶片，此晶片爲於各角落處結合在一起的四邊所界 本紙張尺度適用中國國家橾準（CNS ) A4规格（210x297公釐〉_ ς _ I n —Ml 訂 (請先閱讀背面之注意事項再填寫本頁) A7 B7 296474 五、發明説明（3) (請先閲讀背面之注意事項再填寫本頁) 定；以鋸齒形狀成內外直線沿半導體晶片四邊安置的結合 墊；以及將內引線端部與輸入/輸出墊電氣互連的引線， 其中位於側邊中央區域的各內結合墊係安置在一對外結合 墊的中分處，且位於側邊角落區域的各內結合墊係安置在 由一對外結合墊中分處朝向中央區域處，以使結合線之間 的距離在沿外結合墊延伸的一條虛擬線上大體均勻。 由於將結合線之間的距離維持爲大體固定，故結合線 之間便難以發生短路。 圖式之簡要說明： 圖1 A至1 D爲示意圖，示出依據本發明實施例之半 導體裝置的結構。 圖2爲放大部份平面圖，示出依據本發明實施例之引 線框中結合墊與內引線之特別配置。 圖3 A至3 D爲示意圖，示出習知結合墊及習知結合 墊與內引線的配置。 經濟部中央榡準局員工消費合作社印褽 較佳實施例之詳細說明： 吾人曾對結合墊之間短路的原因進行研究。 圖3 C爲示意平面圖，示出一個如圖3 A所示之矽晶 片片結（die bond )至一引線框平台上，且其結合墊以 伊線結合至引線框之內引線的情形。接線5 6具有一個供 安置半導體晶片於其上的平台5 7、一個支持平台5 7的 支持桿5 8、和多個要與結合墊以接線結合的內引線5 9 本紙悵尺度通用中國國家橾準（CNS ) A4規格（210X 297公釐） β 經濟部中央標準局員工消費合作社印裝 A7 B7 五、發明説明（Ο 。雖然圖中未示’不過在內引線外側設有防止模製樹脂流 動的護邊及外引線。 矽晶片5 1爲具有四邊的矩形’結合至引線框平台 5 7的中心部份’其各邊與平台5 7的對應各邊平行。圍 繞平台5 7設有必要數目的引線框內引線5 9 »矽晶片 5 1上的結合墊5 2經由結合線5 3而與內引線5 9電連 接。結合墊5 2以等距沿矽晶片5 1的四邊成一列安置。 在接線5 6之平台5 7的角落區域處，內引線5 9間的距 離較平台5 7中心或中間部份處內引線5 9間的距離要長 〇 結合墊全部以等距沿結合墊的安排方向而設置。內引 線5 9安置在較矽晶片5 1爲寬的區域中。因此，在矽晶 片5 1各邊中心區域處與結合墊5 2連接的結合線5 3大 體上與矽晶片的各邊垂直。不過，在矽晶片5 1角落區域 處與結合墊5 2連接的結合線5 3相對於矽晶片各邊則呈 歪斜，如圖3 C所示。因此’角落區域處結合線間的距離 d 1便較中心區域處結合線間的距離d 2爲短。 隨著結合線間距離變短，以密封樹脂（例如環氧樹脂 )來模製圖3 C所示結構時便有短路的危險，因爲結合線 5 3會爲樹脂流動所帶動。 圖3 D爲圖3 B所示矽晶片的示意平面圖，其呈鋸齒 形狀安置的結合墊經由結合線而與引線電連接。結合墊 5 4呈鋸齒形狀沿矽晶片5 1週邊的帶狀區域安置。引線 框5 6與圖3 C所示者相似，但引線框平台5 7在接近支 本紙张尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） — I I I . 裝 ^ —訂 —^ (請先閱讀背面之注意事項再填寫本頁) A7 _____B7_ 五、發明説明（5) 持桿5 8處設有一個凹處。 與圖3 C所示情形相似，在矽晶片5 χ角落區域處與 結合墊5 4連接的結合線5 3相對於矽晶片各邊呈歪斜。 在鋸齒圖型安排下，內外結合墊的連接狀況相當不同。接 近結合墊5 4處的結合線5 3之間的距離並不均匀；某些 結合線之間的距離非常短》在圖3 D所示結合狀態中，於 矽晶片5 1的角落區域處，從內引線延伸出之結合線幾乎 要與從更接近角落區域處的外引線所延伸出之結合線相接 觸。在此狀態下進行塑膠模製，會有樹脂流動帶動結合線 而造成短路的危險。 如上所述’連接半導體晶片上之結合墊與封裝單元（ 例如引線框）之內引線的結合線間的距離在接近角落區域 處會變得很短。因此，可預期到發生短路危險的可能性很 大。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 圖1 A爲根據本發明實施例之半導體積體電路裝置的 放大部份圖。矽晶片1上製有半導體積體電路，並有多個 結合墊2a ’ 2b...成列安置在矽晶片的週邊區域處 。這些結合墊2與結合線3連接。 隨著結合墊的位置接近矽晶片1的角落區域，結合墊 之間的距離便安排得得較長。圖1 A中，結合墊2 a與 2 b間的距離設定成比結合墊2 e與2 f間的距離要長。 即使在中間區域處，結合墊間的距離也逐漸改變》 由於結合墊2之間的距離隨著結合墊位置接近角落區 域而變長，因此歪斜連接的結合線之間的距離（最短距離 本紙張尺度適用中國國家標準（CNS〉A4規格（210X 297公釐） 經濟部中央標準局員工消費合作社印製 A 7 B7 五、發明説明（6) )便大體成爲均勻。封裝內引線間的距離亦可以相似方式 逐漸改變。 內引線側的結合線間距離大體上均很寬，故即使距離 均勻化’短路的危險仍很低。使接近矽晶片處的結合線間 距離均句化是一項基本重點。該距離可定義爲由各結合墊 至相鄰結合線中心側的垂直線長度^ 以上述方式改變矽晶片週邊區域處的結合墊配置，便 可使結合線間的距離至少在接近矽晶片處大體均勻。 ffll B爲示意圖，示出矽晶片1上安置在結合墊的區 域。政晶片1的平面大體成正方形β矽晶片1的週邊區域 界定·一個帶狀迴路區域5。此帶狀區域具有固定的寬度w ’例如5 0 0 。在本說明書中，安置在此帶狀區域中 的結合墊稱爲「大體成直線安置的結合墊」。在帶狀迴路 區域5所圍繞的中心區域中形成積體電路I c。 圖1 C示出矽晶片、引線框、與結合線之間的關係。 結合墊2安置在矽晶片丨的週邊區域中。矽晶片1與引線 框6的平台7片結。支持桿8由平台7的角落區域朝對角 線方向延伸。引線框的多條內引線9安置在相鄰支持桿8 間的空間中。連接內引線9與結合墊2的結合線3之方向 是傾斜的。如果晶片1各邊與結合線3之間的角度0爲 6 0度或更小，則結合線間的距離與結合墊間的距離相較 便顯著縮短。例如，角度0爲6 0度時，結合線3之間的 距離便爲結合墊間距離的約8 7%或約〇 9。角度0爲 4 5度時，結合線3之間的距離便爲結合墊間距離的約 本紙浪尺度適用中國國家標準（CNS )八4規格（210X297公釐） ^ ^-- (請先閱讀背面之注意事項再填寫本頁) -s 經濟部中央橾準局員工消費合作社印製 A7 _B7 五、發明説明（7) 71%或約〇. 7。視晶片形狀與位置以及結合墊位置而 定，角度0可能更小。.因此，經由改變結合墊位置或結合 墊與內引線的相對位置，便可有效地將結合線間的距離設 定成大體均勻，特別以角度0爲60度或更小時爲然》 「 大體均匀」意指最小距離爲最大距離的0. 9以上。結合 墊之間的延長距離範圍可設定爲晶片半邊之約4 0 %的外 側部份。在各半邊之約2 0%的外側部份中，結合線間的 距離顯著減少。僅有此區域中的結合墊可採延長間距來安 置。 圖1 D示出以鋸齒圖型安置之結合墊的實施例。兩列 結合墊4大體成直線安置於矽晶片1之結合墊區域中。結 合墊之間的距離隨著結合墊位置接近矽晶片1之角落區域 而變長》不過請注意內結合墊4b ，4d，...相對於 外結合墊4a ，4c ，...在側向上有所偏移，亦即內 結合墊4 b距離相鄰之外結合墊4 a與4 c的距離並非相 等，而是距離接近角落區域處的外結合墊4 a較遠、距離 接近中間區域處的外結合墊4 c較近。在此種結合墊配置 安排下，如果以垂直於晶片1各邊的方式來連接結合線， 結合線間的距離便十分不規則。不過由於結合線實際上相 對於晶片1之側邊呈傾斜狀態，故結合線之間的距離，例 如在一條延伸經過外結合墊的線上，便成爲均勻》連接一 結合墊的結合線和連接相鄰結合墊的相鄰結合線間的距離 可由相鄰結合墊對連接中間結合墊之結合線的垂直線長度 來決定》 本紙张尺度適用中國國家標準（CNS ) A4規格（210X 297公釐）,n ---------ά,.------ir------ (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準扃員工消費合作社印製 Α7 Β7 五、發明説明（8) 砂晶片1與引線框6的平台7片結。支持桿8由平台 7½角落區域朝對角線方向延伸。最接近支持桿8的內引 線9 a經由結合線3 a而與矽晶片1上的外結合墊4 a電 連接。相似地，次一內引線9 b經由結合線3 b而與矽晶 片1上的外結合墊4 b電連接。 支持桿8之延伸線相對於矽晶片1的側邊的角度約爲 4 5度》將最接近支持桿8的內引線9 a與最接近矽晶片 1角落區域的結合墊4 a互連的結合線3 a與矽晶片1的 側邊相交於略大於4 5度角。 詳言之’與最接近矽晶片1角落區域的結合墊4 3連 接的結合線與矽晶片1的側邊相交之角度雖然略大於4 5 度角’但遠小於6 0度角。 如果內外結合墊安置在矽晶片1上時如圖1A所示使 位於角落位置的結合墊之間距離較長，且如圖1 D所示使 內外結合墊的位置彼此偏移，則結合墊之間的距離便可有 效地保持均勻。 爲使結合線之間的距離保持均勻，結合墊之間的距離 應由晶片側邊中央區域朝向角落區域逐漸增加。不過，結 合墊間距離若採連績改變方式，可能會使罩模圖型設計和 接線結合程序變得較爲複雜。 在晶片各邊中央區域處，結合線與晶片各邊大體成垂 直相交。此時即使將結合墊等距安置，結合線之間的距離 也僅改變少許。因此，可不必改變所有結合墊的位置，只 要改變接近晶片角落區域處的結合墊位置，便可確保達成 本紙浪尺度逋用中國國家標準（CNS ) A4規格（210Χ 297公釐） (請先閱讀背面之注意事項再填寫本頁) -裝 訂 經濟部中央標準局員工消費合作社印製 296474 at _ B7 — '.............. "' _ _ 五、發明説明（9) 所要的效應。 例如’假設晶片每一邊上安置了 η個結合墊，則僅需 調整η個結合墊中接近角落區域的約1 5 %者之位置，便 可有效地保持結合線間有均勻的距離。若調整η個結合墊 中接近角落區域的約2 0%者間的距離，則更佳》 就另一觀點言之’可將結合墊與內引線之位置予以調 整，而使結合線間最大距離對最小距離的比例爲1 · 4或 更小’最好爲1 _ 3 5或更小。所述距離可定義爲在延伸 經過結合墊之線上的距離，或由一結合墊至與次一結合墊 連接之結合線的垂直線長度。 圖2示出結合墊安置成鋸齒圖型的半導體I c裝置之 特定結構實例。半導體晶片1具有兩列結合墊，安置在晶 片週邊區域上寬度約爲5 0 〇 的一個區域中。結合墊 成內外兩列交錯安置，呈所謂的鋸齒狀圖型。 半導體晶片1片結至引線框平台7的中心部份》在引 線框平台的外側設有多條圍繞平台的內引線9。內引線9 與結合墊4的配置係安排成，使與內引線和結合墊相交的 結合線3之間距大體相等。 與結合墊和內引線相交的結合線之最短長度爲4. 1 mm’最長長度爲4. 7mm，平均長度爲4. 4mm» 在圖2所示佈局中，IC裝置的左右半部之結合墊與引線 框呈對稱配置，且引線框具有一百四十個接腳。 在本實例中，內引線之內端在平台7的每一側邊上構 成三條直線。內引線9可採不同的佈局。例如，可將內引 本紙張尺度適用中國國家橾準（CNS > A4規格（210X297公釐） ----- I m n I I li I n n - ------ T I--II ________.- , A (請先閱讀背面之注意事項再填寫本頁) -12 - A7 ___B7_ 五、發明説明（10) 線予以終結，而安排成在平台7的每一側邊上構成兩條直 線。 接線結合之後，以例如環氧樹脂之模製樹脂來密封晶 片’覆蓋住半導體晶片及護邊內部的引線框區域而暴露外 引線。 在上述實施例中，如上所述係以塑膠來模製半導體 I C裝置。本發明亦可應用至其他封裝，例如陶瓷封裝。 採用陶瓷封裝或其他類似封裝時則不會發生樹脂流動的情 形。如果使用塑膠封裝，則維持結合線間距離均勻是很重 要的’因爲樹脂流動會帶動結合線。前述配置對於3 mm 或更長的結合線而言尤爲有效。 本發明已就較佳實施例予以說明如上，但本發明並不 僅侷限於所述實施例。對於熟習本技術之士而言，很顯然 在不脫離由後述申請專利範圍所界定之發明範圍下，可對 本發明作各種的修改變化、改良與組合。 I-------------IT------J 乂 (請先閲讀背面之注意事項再填寫本页) 經濟部中央標準局員工消費合作杜印製 本紙張尺度適用中國國家標準（CNS > A4規格（210X297公釐）A7 B7 Printed by the Consumer Cooperative of the Central Falcon Bureau of the Ministry of Economic Affairs 5. Description of the invention (1) Background of the invention: (a) Field of the invention The present invention relates to semiconductor integrated circuit devices, in particular to a semiconductor product capable of avoiding short circuit between leads "Body circuit device" (b) Related art description In a semiconductor wafer of an integrated circuit (IC), a bonding pad is provided at a peripheral area of the wafer. The bonding pads are connected to the internal leads of the package member via bonding wires (leads). The bonding pads are usually placed in a line at equal intervals. If several bonding pads are used, they are usually placed at a narrow fixed pitch to facilitate the machine operation of the wire bonding coupler. If the number of bonding pads in one row is not enough, two or more rows of bonding pads may be provided, and each row of bonding pads may be laterally shifted by, for example, a half pitch to stagger the bonding pads of one row and the bonding pads of the inner and outer rows. In some cases, the placement of bond pads is determined by circuit limitations. Fig. 3A shows an example of the arrangement of bonding pads arranged in a row in the peripheral area of the wafer. A row of bonding pads 52 is provided in the peripheral area of the silicon wafer 51. The distance d between adjacent bonding pads 52 is fixed. FIG. 3B shows an example in which two rows of bonding pads are arranged in a zigzag pattern. The two rows of bonding pads 54 are staggered along the peripheral area of the silicon wafer 51 to form a zigzag or checkerboard pattern. This zigzag pattern can be equipped with multiple bonding pads. The distance d between adjacent bonding pads in each column is fixed. When wiring bonding a semiconductor wafer provided with a plurality of bonding pads, there is a risk of short circuits between the bonding wires at the corner regions of the semiconductor wafer. If the paper size of «μ · is applied to the Chinese National Standard (CNS) A4 specification (210X 297 Gongqing) (Please read the precautions on the back before filling in this page) Order A7 _____B7 Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economy V. Invention description (2) Using plastic molds, resin flow is likely to cause a short circuit between the bonding wires. SUMMARY OF THE INVENTION One of the objects of the present invention is to provide a semiconductor integrated circuit device with fewer short circuits between bonding wires. Another object of the present invention is to provide a semiconductor integrated circuit device capable of ensuring a uniform distance between bonding wires. According to the first part of the present invention, there is provided a semiconductor device circuit device, including: a package member having a plurality of inner leads; a semiconductor integrated circuit chip having a peripheral area, the area containing A plurality of input / output pads, the semiconductor integrated circuit chip is defined by the sides joined together at each corner: and a lead electrically interconnecting the inner lead and the input / output pad, one of which is near one of the corners In the area, the lead intersects one of the sides of the semiconductor integrated circuit chip at an angle of 60 degrees or less, and the distance between the input / output pads is wider than that in the other areas, so that the distance between the leads Generally uniform. If the bonding pads are arranged at equal intervals, the distance between the leads intersecting the side of the semiconductor integrated circuit wafer at an angle of 60 degrees or less becomes very short. Even in this case, if the distance between the input / output bonding pads on the wafer is set to be longer in the corner area so that the distance between the leads is substantially uniform, the risk of short circuit between the leads can be avoided. According to another part of the present invention, there is provided a semiconductor device including: a package member having a plurality of inner leads; a rectangular semiconductor chip, which is bounded by four sides bound together at each corner The paper scale is applicable to China National Standard (CNS) A4 (210x297mm) _ ς _ I n —Ml order (please read the precautions on the back before filling in this page) A7 B7 296474 V. Description of invention (3) (please Read the precautions on the back before filling in this page); the bonding pads placed in a zigzag shape into the inner and outer straight lines along the four sides of the semiconductor wafer; and the leads that electrically interconnect the ends of the inner leads and the input / output pads, which are located in the center of the side The inner bonding pads of the area are arranged in the middle branch of the outer bonding pad, and the inner bonding pads in the side corner area are arranged from the branch of the outer bonding pad toward the central area, so that the bonding line is The distance between them is substantially uniform on a virtual line extending along the outer bonding pad. Since the distance between the bonding lines is maintained to be substantially fixed, it is difficult for the bonding lines to be short. Brief description of the drawings: FIGS. 1 A to 1 D are schematic diagrams showing the structure of a semiconductor device according to an embodiment of the present invention. FIG. 2 is an enlarged partial plan view showing bonding pads in a lead frame according to an embodiment of the present invention Special configuration with inner leads. Figures 3 A to 3 D are schematic diagrams showing the conventional bonding pads and the configuration of the conventional bonding pads and inner leads. The Ministry of Economic Affairs Central Bureau of Precincts Employee Consumer Cooperative printed details of the preferred embodiment. Explanation: I have studied the cause of short circuit between bonding pads. Figure 3C is a schematic plan view showing a silicon die as shown in Figure 3A to a lead frame platform and their bonding The pad is bonded to the lead in the lead frame with a wire. The wiring 56 has a platform 5 7 for placing the semiconductor wafer on it, a support rod 58 for supporting the platform 57, and a plurality of bonding pads Inner leads combined with wiring 5 9 The standard size of this paper is universal China National Standard (CNS) A4 specification (210X 297 mm). Β Printed by the Ministry of Economy Central Standards Bureau Employee Consumer Cooperative A7 B7 5. Description of invention (Ο. Although not shown in the figure 'However, the outer lead of the inner lead is provided with a protective edge and an outer lead to prevent the flow of the molded resin. The silicon wafer 51 is a rectangle with four sides' and is bonded to the central part of the lead frame platform 5 7'. Corresponding to the sides are parallel. Around the platform 5 7, a necessary number of lead wires in the lead frame 5 9 »the bonding pads 5 2 on the silicon wafer 5 1 are electrically connected to the inner leads 5 9 via the bonding wires 5 3. Equidistantly arranged in a row along the four sides of the silicon wafer 51. In the corner area of the platform 5 7 of the wiring 5 6, the distance between the inner leads 5 9 is shorter than the distance between the inner leads 5 9 at the center or middle part of the platform 5 7. To be long, the bonding pads are all arranged at equal intervals along the arrangement direction of the bonding pads. The inner leads 59 are arranged in a wider area than the silicon wafer 51. Therefore, the bonding line 53 connected to the bonding pad 52 at the center area of each side of the silicon wafer 51 is substantially perpendicular to each side of the silicon wafer. However, the bonding wire 53 connected to the bonding pad 52 at the corner area of the silicon wafer 51 is skewed with respect to each side of the silicon wafer, as shown in FIG. 3C. Therefore, the distance d 1 between the joint lines at the corner area is shorter than the distance d 2 between the joint lines at the center area. As the distance between the bonding wires becomes shorter, there is a risk of short-circuiting when molding the structure shown in FIG. 3C with a sealing resin (such as epoxy resin), because the bonding wires 53 will be driven by the flow of resin. 3D is a schematic plan view of the silicon wafer shown in FIG. 3B, and the bonding pads arranged in a zigzag shape are electrically connected to the leads via bonding wires. The bonding pad 54 is arranged in a zigzag shape along the band-shaped area around the silicon wafer 51. The lead frame 5 6 is similar to the one shown in FIG. 3 C, but the lead frame platform 5 7 applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) — III. Binding — — Order — ^ Please read the precautions on the back before filling in this page) A7 _____B7_ 5. Description of the invention (5) There is a recess at the 5 and 8 of the holding rod. Similar to the situation shown in FIG. 3C, the bonding wire 53 connected to the bonding pad 54 at the corner area of the silicon chip 5 is inclined with respect to each side of the silicon chip. Under the zigzag pattern arrangement, the connection conditions of the inner and outer bonding pads are quite different. The distance between the bonding wires 53 near the bonding pad 54 is not uniform; the distance between some bonding wires is very short. In the bonding state shown in FIG. 3D, at the corner area of the silicon wafer 51, The bonding wire extending from the inner lead is almost in contact with the bonding wire extending from the outer lead closer to the corner area. Plastic molding in this state may cause the resin flow to drive the bonding wire and cause a short circuit. As described above, the distance between the bonding wire connecting the bonding pad on the semiconductor wafer and the lead in the package unit (such as a lead frame) becomes very short near the corner area. Therefore, it is expected that there is a high possibility of a short-circuit hazard. Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling in this page). Figure 1 A is an enlarged view of a semiconductor integrated circuit device according to an embodiment of the present invention. A semiconductor integrated circuit is fabricated on the silicon wafer 1, and a plurality of bonding pads 2a '2b ... are arranged in rows at the peripheral area of the silicon wafer. These bonding pads 2 are connected to bonding wires 3. As the position of the bonding pad approaches the corner area of the silicon wafer 1, the distance between the bonding pads is arranged to be longer. In FIG. 1A, the distance between the bonding pads 2a and 2b is set to be longer than the distance between the bonding pads 2e and 2f. Even in the middle area, the distance between the bonding pads gradually changes. Since the distance between the bonding pads 2 becomes longer as the bonding pads approach the corner area, the distance between the skew-connected bonding lines (the shortest distance on this paper) The standard is applicable to the Chinese National Standard (CNS> A4 specification (210X 297mm). A 7 B7 is printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention (6)). The similar approach gradually changes. The distance between the bonding wires on the inner lead side is generally wide, so even if the distance is uniform, the risk of short-circuiting is still very low. Sentencing the distance between bonding wires near the silicon wafer is a basic focus The distance can be defined as the length of the vertical line from each bonding pad to the center side of the adjacent bonding line ^ By changing the bonding pad configuration at the peripheral area of the silicon wafer in the above manner, the distance between the bonding lines can be at least close to the silicon wafer It is substantially uniform. Ffll B is a schematic diagram showing the area where the bonding pad is placed on the silicon wafer 1. The plane of the political wafer 1 is substantially square and the periphery of the beta silicon wafer 1 Domain definition · A strip-shaped loop area 5. This strip-shaped area has a fixed width w ', such as 500. In this specification, the bonding pads arranged in this strip-shaped area are called "substantially linear bonding pads" The integrated circuit Ic is formed in the central area surrounded by the strip-shaped loop area 5. FIG. 1C shows the relationship between the silicon wafer, the lead frame, and the bonding wires. The bonding pad 2 is placed on the periphery of the silicon wafer The silicon wafer 1 is bonded to the platform 7 of the lead frame 6. The support rod 8 extends diagonally from the corner area of the platform 7. The multiple inner leads 9 of the lead frame are placed in the space between adjacent support rods 8 The direction of the bonding wire 3 connecting the inner lead 9 and the bonding pad 2 is inclined. If the angle 0 between the sides of the wafer 1 and the bonding wire 3 is 60 degrees or less, the distance between the bonding wires and bonding The distance between the pads is significantly shorter. For example, when the angle 0 is 60 degrees, the distance between the bonding lines 3 is about 8 7% or about 〇9 of the distance between the bonding pads. When the angle 0 is 45 degrees , The distance between the bonding lines 3 is about the distance between the bonding pads. National Standard (CNS) 84 specifications (210X297mm) ^ ^-(please read the precautions on the back before filling in this page) -s A7 _B7 printed by the Employee Consumer Cooperative of the Central Department of Economics of the Ministry of Economic Affairs 7) 71% or about 0.7. Depending on the shape and position of the wafer and the position of the bonding pad, the angle 0 may be smaller. Therefore, by changing the position of the bonding pad or the relative position of the bonding pad and the inner lead, it can be effectively Set the distance between the bonding lines to be substantially uniform, especially if the angle 0 is 60 degrees or less. "Generally uniform" means that the minimum distance is greater than 0.9 at the maximum distance. The extended distance between bonding pads can be It is set to about 40% of the outer part of the half of the wafer. In the outer part of about 20% of each half, the distance between the bonding lines is significantly reduced. Only the bonding pads in this area can be installed with extended spacing. FIG. 1D shows an embodiment of a bonding pad arranged in a zigzag pattern. The two rows of bonding pads 4 are arranged in a substantially straight line in the bonding pad area of the silicon wafer 1. The distance between the bonding pads becomes longer as the bonding pads are closer to the corner area of the silicon wafer 1 "However, please note that the inner bonding pads 4b, 4d, ... are relative to the outer bonding pads 4a, 4c, ... on the side There is a deviation, that is, the distance between the inner bonding pad 4 b and the adjacent outer bonding pads 4 a and 4 c is not equal, but is farther from the outer bonding pad 4 a near the corner area and closer to the middle area The outer bonding pad 4c is closer. Under this arrangement of bonding pads, if the bonding wires are connected perpendicularly to the sides of the wafer 1, the distance between the bonding wires is very irregular. However, since the bonding wire is actually inclined with respect to the side of the wafer 1, the distance between the bonding wires, for example, on a line extending through the outer bonding pad, becomes uniform. The bonding wire and the connecting phase connecting a bonding pad The distance between the adjacent bonding lines of the adjacent bonding pads can be determined by the length of the vertical line between the adjacent bonding pads and the bonding line connecting the intermediate bonding pads. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm), n --------- ά, .------ ir ------ (Please read the precautions on the back before filling out this page) Printed by the Ministry of Economic Affairs Central Standards Employee Consumer Cooperative Α7 Β7 V. Description of the invention (8) The sand wafer 1 is connected to the platform 7 of the lead frame 6. The support bar 8 extends diagonally from the 7½ corner area of the platform. The inner lead 9a closest to the support rod 8 is electrically connected to the outer bonding pad 4a on the silicon wafer 1 via the bonding wire 3a. Similarly, the next inner lead 9 b is electrically connected to the outer bonding pad 4 b on the silicon wafer 1 via the bonding wire 3 b. The angle of the extension line of the support rod 8 relative to the side of the silicon wafer 1 is about 45 degrees. The combination of the inner lead 9 a closest to the support rod 8 and the bonding pad 4 a closest to the corner area of the silicon wafer 1 The line 3 a intersects the side of the silicon wafer 1 at an angle slightly larger than 45 degrees. In detail, the angle at which the bonding line connected to the bonding pad 4 3 closest to the corner area of the silicon wafer 1 intersects the side of the silicon wafer 1 is slightly larger than 45 degrees but is far smaller than 60 degrees. If the inner and outer bonding pads are placed on the silicon wafer 1 as shown in FIG. 1A, the distance between the bonding pads at the corners is longer, and the positions of the inner and outer bonding pads are shifted from each other as shown in FIG. 1D. The distance between them can be effectively kept uniform. In order to keep the distance between the bonding lines uniform, the distance between the bonding pads should gradually increase from the central area on the side of the wafer toward the corner area. However, if the distance between the bonding pads is changed continuously, the pattern design of the mask mold and the wiring combination procedure may become more complicated. At the central area of each side of the wafer, the bonding line substantially perpendicularly intersects each side of the wafer. At this time, even if the bonding pads are arranged equidistantly, the distance between the bonding lines changes only slightly. Therefore, it is not necessary to change the position of all the bonding pads, as long as the bonding pads close to the corner area of the wafer are changed, it can ensure that it meets the paper wave standard and uses the Chinese National Standard (CNS) A4 specification (210Χ 297 mm) (please read first (Notes on the back and then fill in this page)-Printed at the 296474 at _ B7 — '.............. "' _ _ V. Invention Description (9) The desired effect. For example, assuming that n bonding pads are placed on each side of the wafer, it is only necessary to adjust the position of approximately 15% of the n bonding pads close to the corner area to effectively maintain a uniform distance between the bonding lines. If the distance between about 20% of the η bonding pads close to the corner area is adjusted, it is better. ”From another point of view, the position of the bonding pad and the inner lead can be adjusted to maximize the distance between the bonding wires The ratio to the minimum distance is 1 · 4 or less', preferably 1_3 5 or less. The distance can be defined as the distance on the line extending through the bonding pad, or the length of the vertical line from a bonding pad to the bonding line connected to the next bonding pad. Fig. 2 shows a specific structural example of a semiconductor IC device in which bonding pads are arranged in a sawtooth pattern. The semiconductor wafer 1 has two rows of bonding pads and is arranged in a region with a width of about 500 on the peripheral region of the wafer. The bonding pads are arranged in two rows staggered inside and outside in a so-called zigzag pattern. A semiconductor wafer 1 piece is connected to the center part of the lead frame platform 7> A plurality of inner leads 9 surrounding the platform are provided on the outside of the lead frame platform. The inner lead 9 and the bonding pad 4 are arranged so that the distance between the bonding wire 3 crossing the inner lead and the bonding pad is substantially equal. The shortest length of the bonding wire that intersects the bonding pad and the inner lead is 4.1 mm ', the longest length is 4.7 mm, and the average length is 4. 4 mm »In the layout shown in FIG. 2, the bonding pads on the left and right half of the IC device It has a symmetrical configuration with the lead frame, and the lead frame has one hundred and forty pins. In this example, the inner ends of the inner leads form three straight lines on each side of the platform 7. The inner leads 9 can adopt different layouts. For example, the paper size of the internal reference can be applied to the Chinese National Standard (CNS > A4 specification (210X297mm) ----- I mn II li I nn------- T I--II ________. -, A (Please read the precautions on the back before filling in this page) -12-A7 ___B7_ V. Description of invention (10) The line is terminated, and arranged to form two straight lines on each side of the platform 7. Wiring After bonding, the die is sealed with a molding resin such as epoxy resin to cover the semiconductor chip and the lead frame area inside the bezel to expose the outer leads. In the above embodiments, the semiconductor IC is molded with plastic as described above Device. The present invention can also be applied to other packages, such as ceramic packages. When using ceramic packages or other similar packages, resin flow does not occur. If plastic packages are used, it is important to maintain a uniform distance between bonding wires. The flow of resin will drive the bonding wire. The foregoing configuration is particularly effective for bonding wires of 3 mm or longer. The present invention has been described above in terms of preferred embodiments, but the present invention is not limited to the embodiments. As far as the scholars of this technology are concerned, it is obvious that various modifications, improvements and combinations of the present invention can be made without departing from the scope of the invention defined by the scope of the patent application described later. I ----------- --IT ------ J 乂 (please read the precautions on the back before filling out this page). The printing standard of the paper is printed in accordance with the Chinese Consumer Standards (CNS > A4 specification (210X297 Mm)

Claims (1)

經濟部中央標羋局員工消費合作社印製 Λ8 B8 C8 __ D8 ___ 六、申請專利範圍 1 . 一種半導體積體電路裝置，包含： 具有多個內引線的一個封裝構件； —個半導體積體電路晶片，此晶片具有一個週邊區域 ，區域中含有多個輸入/輸出墊，該半導體稹體電路晶片 爲於各角落處結合在一起的側邊所界定；以及 將內引線與輸入/輸出墊電氣互連的引線’ 其中在一個區域中，引線與半導體積體電路晶片的側 邊以6 〇度或更小的角度相交，且輸入κ输出墊之間的距 離較寬，以使引線之間的距離大體均勻。 2. 如申請專利範圔第1項之半導體積體電路裝置’ 其中所述輸入/輸出墊沿半導體稹髖電路晶片的側邊成列 安置，且所述引線間最大距離對引線間最小距離的比例爲 1· 4或更小，而各引線長度爲約3mm或更長。 3. 如申請專利範圍第1項之半導體稹體電路裝置’ 其中所述封裝構件爲一引線框，且該半導體稹體電路裝置 尙包含一個塑膠構件，模製封住所述封裝構件與引線框。 4. 如申請專利範圍第2項之半導體稹體電路裝置’ 其中所述封裝構件爲一引線框，且該半導體積體電路裝置 尙包含一個塑膠構件，模製封住所述封裝構件與引線框。 5. 如申請專利範圍第1項之半導體稹體電路裝置， 其中所述輸入/輸出墊沿半導體積體電路晶片的側邊成內 外兩列安置，且在半導體積體電路晶片側邊的中央區域處 ’內列之輸入/输出墊的安置位置對應於一對外列输入/ 輸出墊的中間位置，而在側邊的角落區域處，內列之輸入 本紙浪尺度適用中國國家榡华（CNS ) Λ4現格（21«X：^7公趁） ---------A------IT------1 (請先閱讀背面之注意事項再填寫本頁) 14 ABCD 經濟部中央標隼局負工消費合作社印裝 六、申請專利範圍 /輸出墊的安置在由中間位置朝向側邊中央區域偏移的位 置。 6.如申請專利範圍第1項之半導體積體電路裝置， 其中假設中央區域處的垂直線長度爲1，則在中央區域側 邊處由各輸入/輸出墊至相鄰結合線的垂直線長度爲約 0 . 9至約1。 7 .如申請專利範園第5項之半導體積體電路裝置， 其中假設中央區域處的垂直線長度爲1 ，則在中央區域側 邊處由各輸入/輸出墊至相鄰結合線的垂直線長度爲約 0 . 9至約1 » 8. 如申請專利範圔第1項之半導體積體電路裝置， 其中所述與沿半導體稹體電路晶片週邊區域安置的輸入/ 輸出墊連接的內引線之內端係沿三條直線安置》 9. 如申請專利範圍第5項之半導體稹體電路裝置， 其中所述與沿半導體積體電路晶片週邊區域安置的輸入/ 輸出墊連接的內引線之內端係沿三條直線安置。 10. —種半導體裝置，包含： 具有多個內引線的一個封裝構件； 一個矩形半導體晶片，此晶片爲於各角落處結合在一 起的四邊所界定； 以鋸齒形狀成內外直線沿半導髖晶片四邊安置的結合 墊；以及 將內引線端部與輸入/輸出墊電氣互連的引線， 其中位於側邊中央區域的各內結合墊係安置在一對外 本紙張尺度適用中國國家標窣（CNS〉Λ4現格（210Χ 297公釐) ~~~' -15 - ---------Ί —-----ΪΤ------'*1 (請先閱讀背面之注意事項再填寫本頁) 8 8 8 8 ABCD 六、申請專利範圍 結合墊的中分處，且位於側邊角落區域的各內結合墊係安 置在由~對外結合墊中分處朝向中央區域處，以使結合線 之間的距離在沿外結合墊延伸的一條虛擬線上大體均勻。 1 1 .如申請專利範圍第1 0項之半導體裝置’其中 假設中央區域處的垂直線長度爲1 ，則在中央區域側邊處 由各輸入/輸出墊至相鄰結合線的垂直線長度爲約〇· 9 至約1。 ---------_*农|-----ΪΤ------1 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印奴 本紙張尺度適用中阀阀家標準（CNS ) Λ4说格（210X297公簸） 16 -Printed Λ8 B8 C8 __ D8 ___ by the Employee Consumer Cooperative of the Central Standardization Bureau of the Ministry of Economic Affairs VI. Patent Scope 1. A semiconductor integrated circuit device, including: a package member with multiple inner leads; — a semiconductor integrated circuit chip The chip has a peripheral area containing multiple input / output pads. The semiconductor chip circuit chip is defined by the side edges joined together at each corner; and the inner leads are electrically interconnected with the input / output pads 'Leads' where the lead intersects the side of the semiconductor integrated circuit wafer at an angle of 60 degrees or less, and the distance between the input and output pads is wider so that the distance between the leads is approximately Evenly. 2. The semiconductor integrated circuit device as claimed in Item 1 of the patent application, wherein the input / output pads are arranged in a row along the side of the semiconductor chip, and the maximum distance between the leads to the minimum distance between the leads The ratio is 1.4 or less, and the length of each lead is about 3 mm or more. 3. As stated in the first patent application, the semiconductor package circuit device 'wherein the package member is a lead frame, and the semiconductor package circuit device includes a plastic member, which molds and seals the package member and the lead frame . 4. The semiconductor device circuit device as claimed in item 2 of the patent scope, wherein the packaging member is a lead frame, and the semiconductor integrated circuit device includes a plastic member, which molds and seals the packaging member and the lead frame . 5. The semiconductor device circuit device as claimed in item 1 of the patent scope, wherein the input / output pads are arranged in two rows inside and outside along the side of the semiconductor integrated circuit chip, and in the central area of the side of the semiconductor integrated circuit chip The placement of the input / output pads in the row corresponds to the middle position of the outer input / output pads, and in the corner area of the side, the input paper size of the row is applicable to the Chinese national huahua (CNS) Λ4 Cash (21 «X: ^ 7 public advantage) --------- A ------ IT ------ 1 (please read the precautions on the back before filling this page) 14 ABCD Printed by the Central Standard Falcon Bureau of the Ministry of Economy Consumer Cooperatives 6. The scope of patent application / output pads is placed at a position offset from the middle position toward the side central area. 6. The semiconductor integrated circuit device as claimed in item 1 of the patent scope, where the vertical line length at the central area is assumed to be 1, then the vertical line length from each input / output pad to the adjacent bonding line at the side of the central area It is about 0.9 to about 1. 7. If the semiconductor integrated circuit device of patent application No. 5 is applied, where the length of the vertical line at the central area is assumed to be 1, the vertical line from each input / output pad to the adjacent bonding line at the side of the central area The length is about 0.9 to about 1 »8. The semiconductor integrated circuit device according to item 1 of the patent application, wherein the inner leads connected to the input / output pads arranged along the peripheral area of the semiconductor chip circuit chip The inner ends are arranged along three straight lines. ”9. The semiconductor device circuit device as claimed in item 5 of the patent scope, wherein the inner ends of the inner leads connected to the input / output pads arranged along the peripheral area of the semiconductor integrated circuit chip Place along three straight lines. 10. A semiconductor device, including: a package member having a plurality of inner leads; a rectangular semiconductor chip defined by four sides joined together at each corner; a semi-conducting hip chip in a zigzag shape forming an inner and outer straight line Bonding pads arranged on four sides; and leads electrically interconnecting the ends of the inner leads and the input / output pads, wherein the inner bonding pads located in the central area of the sides are arranged on the outer paper size and are applicable to the Chinese National Standard (CNS) Λ4 present grid (210Χ 297mm) ~~~ '-15---------- Ί —----- ΪΤ ------' * 1 (Please read the notes on the back first (Fill in this page again) 8 8 8 8 ABCD 6. The center of the joint pad of the patent application range, and the inner joint pads located in the corner area of the side are placed from the center of the outer joint pad toward the central area. Make the distance between the bonding lines substantially uniform on a virtual line extending along the outer bonding pad. 1 1. If the semiconductor device in the scope of patent application No. 10 'assumes that the length of the vertical line at the central area is 1, then at the center Input / output at the side of the area The length of the vertical line from the pad to the adjacent bonding line is about 0.9 to about 1. ---------_ * 农 | ----- ΪΤ ------ 1 (please read the back first Please pay attention to this page and then fill out this page) The paper standard of the Indian Consumer Standard Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs is applicable to the Chinese Valve Standard (CNS) Λ4 said grid (210X297 public) 16-
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JP3274633B2 (en) 1997-09-29 2002-04-15 ローム株式会社 Semiconductor integrated circuit device
JP6100648B2 (en) 2013-08-28 2017-03-22 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method of semiconductor device

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