3907 A7 _____B7 五、發明説明（) ' 發明之背景 技術範圍 本發明關於動態隨機存取記憶體dram，更明確而 言，關於一種在DRAM中預防資料喪失的方法。該 DRAM使用擴張資料輸出(Extended Data Out)模式，即 EDO模式。本發明提供了一種邏輯電路其能產生一位址鎖 定輸出與一資料鎖住輸出。該位址鎖定輸出被饋入至一位 址輸入緩衝器，而該資料鎖住輸出被饋入至一資料輸出緩 衝器。前述位址輸入緩衝器被鎖定且資料輸出緩衝器被鎖 住直至該等資料被建立爲止。 ' 習知技術 當EDO模式被用於動態隨機存取記憶體陣列中，分頁 模式循環時間被降低而資料輸出循環時間保持不變。假使 在分配來讀取該資料的時窗結束前該資料未被完全建立的 話，則該資料就有可能會喪失。 發明之效果 有鑑於此’本發明之目的在於提供一種自我定時位址 鎖定與資料鎖住電路以在讀出的過程保護該資料。 經濟部中央標率局貝工消费合作社印裝 --------1 裝— (請先閲讀背面之注意事項再填寫本頁) 發明槪要 在記憶體電路，例如動態隨機存取記憶體中，當使用 擴張資料輸出模式時，分頁模式循環時間被降低而資料輸 出周期保持不變。這會造成資料喪失的問題。圖1A顯示 習知之不具有擴張資料輸出模式的記憶體讀出之定時循 環。如圖1A所示，在列位址閃控線(RAS)80爲邏輯“Γ的 2 本紙張尺度適爪中國國家標準（CNS ) Λ4規格（210X297公釐） 經濟部中央樣唪局負工消费合作社印装 A7 B7 五、發明説明（） 情況，行位址閃控線(CAS)81由邏輯“Γ變成邏輯“〇”之後 資料82會被建立，且前述資料82必需在行位址閃控線 (CAS)81回到邏輯“Γ之前被建立好。 圖1B顯示了當使用擴張資料輸出模式時可能發生的 資料喪失問題。更明確而言，其顯示了具有擴張資料輸出 模式的傳統記億體讀出之定時循環。如圖1B所示，在列 位址閃控線(RAS)83爲邏輯“Γ的情況，行位址閃控線 (CAS)84由邏輯“Γ變成邏輯“0”之後資料85會被建立。當 使用擴張資料輸出模式時，行位址閃控線(CAS)84具有較 高的時序率，故在行位址閃控線(CAS)84由邏輯“0”變成邏 輯“Γ之前資料85並未完全建立。結果如圖1A所示，造成 資料喪失。 有鑑於此，本發明之第一目的係在於提供一自我定時 位址鎖定及資料鎖住電路，以預防使用擴張資料輸出模式 的動態隨機存取記憶體中的資料喪失。 本發明之另一目的係在於提供一使用自我定時位址鎖 定及資料鎖住電路的動態隨機存取記憶體電路，以預防使 用擴張資料輸出模式的記憶體陣列中之資料喪失。 上述目的係藉由一資料鎖住及位址鎖定定時控制電路 來達成，此種資料鎖住及位址鎖定定時控制電路提供一位 址鎖定輸出及一資料鎖住輸出，其會將位址輸入緩衝器鎖 定直到資料被完全建立並鎖位爲止。 當行位址閃控線變成邏輯“Γ時，前述位址鎖定輸出會 變'成邏輯“1”，然後在行位址閃控線已回到邏輯時前述 _______ 3 本紙張尺度通用中园國家標準（CNS ) Λ4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝_ -訂 經濟部中央橾準局員工消费合作社印装 293907 A7 _B7____ 五、發明説明（） 位址鎖定輸出仍然保持在邏輯“r，直到位址鎖定致能線回 到邏輯爲止。當前述資料鎖住致能線變成邏輯“Γ時前 述資料鎖住輸出會變成邏輯“Γ，且行位址閃控線爲邏輯 “0”，或是位址鎖定輸出變成邏輯“〇”，行位址閃控線爲邏 輯“〇”。當前述資料鎖住致能線變成邏輯且位址鎖定輸 出變成邏輯“Γ，或者當行位址閃控線爲邏輯“Γ時，前述 資料鎖住輸出會變成邏輯“〇”。位址鎖定輸出與資料鎖住輸 出是用以將位址輸入緩衝器鎖定，直到資料完全建立並鎖 在位址輸入緩衝器內爲止。 以下藉由圖式配合較佳實施例以更進一步的說明如何 實施本發明。 圖式之簡單說明 圖1A表示用於習知技術之不具有EDD的DRAM之 列位址閃控線、行位址閃控線及資料等之定時循環； 圖1B表示用於習知技術之具有EDD的DRAM之列位 址閃控線、行位址閃控線及資料等之定時循環； 圖2表示與記憶體陣列共同使用之資料鎖住及位址鎖 定定時控制電路的方塊圖； 圖3表示資料鎖住及位址鎖定定時控制電路的方塊 圖； 圖4表示資料鎖住及位址鎖定定時控制電路的邏輯 量， 圖5表示用於本發明之具有EDD的DRAM之列位址 閃控線、行位址閃控線、資料、反相資料鎖定致能、反相 4 ^紙浪尺度通用中國國家標隼（CNS ) Λ4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 裝· 訂 經濟部中央橾準局貝工消费合作社印製 A7 ____B7_ 五、發明説明（） 資料鎖住致能、定時控制電路輸出、位址鎖定電路輸出及 資料鎖住電路輸出等。 較佳實施例之詳細描述 參考圖2，其中顯示了本發明之資料鎖住及位址鎖定 定時控制電路，其用於一個具有擴張資料輸出模式的記憶 體陣列，例如動態隨機存取記憶體等。資料鎖住及位址鎖 定定時控制電路31具有來自列位址閃控線18、行位址閃 控線19及反相讀出線20的輸入，資料線信號偵測電路30 具有來自記憶體陣列（未顯示）的資料線10及反相資料線 11作爲輸入端，並具有反相資料鎖住致能線12及反相位 址鎖定致能線13作爲輸出端，該等資料線被饋入資料鎖住 及位址鎖定定時控制電路31的輸入端。前述資料鎖住及位 址鎖定定時控制電路31具有一位址鎖定輸出14連接至位 址輸入緩衝器32的輸入端，以及一資料鎖住輸出15連接 至資料輸出緩衝器33的輸入端。位址輸入緩衝器32具有 複數個位址輸入端16，而資料輸出緩衝器33具有複數個 資料輸出端17。 當資料鎖住及位址鎖定定時控制電路31的位址鎖定輸 出14爲邏輯“Γ時，在位址輸入緩衝器32中的位址會被鎖 定在位址輸入緩衝器32內直到位址鎖定輸出14回到邏輯 “〇”爲止。當資料鎖住及位址鎖定定時控制電路31的資料 鎖住輸出15爲邏輯“1”時，在資料輸出緩衝器33中的資料 會被鎖定在資料輸出緩衝器33內直到資料鎖住輸出15回 到邏輯“0”爲止。此種位址輸入緩衝器32及資料輸出緩衝 5 (請先閱讀背面之注意事項再填寫本頁) 袈. 訂 本紙張尺度適闲中國國家標準（CNS > Λ4規格（210〆297公釐） 經濟部中央樣準局貝工消费合作社印装 A7 _B7_____ 五、發明説明（） 器33的控制可以預防在擴張資料輸出模式中，行位址閃控 線在資料被完全建立與鎖住前變成邏輯“Γ所可能造成的資 料喪失。 圖3表示前述資料鎖住及位址鎖定定時控制電路的方 塊圖，其中包括：定時控制電路71、位址鎖定電路72及 資料鎖住電路73 〇定時控制電路71有輸入端接到行位址 閃控線19、列位址閃控線18及反相讀出線20。定時控制 電路71的輸出端21接到資料鎖住電路73的第一輸入端， 資料鎖住電路73的第二輸入端接到反相資料鎖住致能線 12，而資料鎖住電路73的輸出端15接到資料輸出緩衝器 (未示於圖3 )〇位址鎖定電路72的第一輸入端接到反相 位址鎖定致能線13，而第二輸入端接到行位址閃控線 19。前述位址鎖定電路72的輸出端14接到資料鎖住電路 73的第一輸入端21，並接到位址輸入緩衝器（未示於圖 3)的輸入端。 當列位址閃控線18爲邏輯“0”時，定時控制電路71的 輸出端21爲邏輯“〇”，資料鎖住電路73的輸出端15爲邏 輯“〇”，位址鎖定電路72的輸出端14具有與行位址閃控線 19相同的大小。吾人感興趣的部份是定時循環中之讀出部 份，亦即當列位址閃控線18爲邏輯“Γ，反相讀出線20爲 邏輯“0”，而讀出線爲邏輯“Γ之時。 在列位址閃控線18已變成邏輯“Γ後，反相讀出線20 爲邏輯“0”的情況下，定時控制電路71之輸出端21會保持 爲邏輯“0”直到行位址閃控線19變成邏輯“1”爲止。當行位 _ 6 適用中國國家標準（CNS ) M規格（2丨0 X 29·7公釐y ~ ~ ~ (請先閱讀背面之注意事項再填寫本頁) .裝. 訂 203907 A7 B7 經濟部中央揉隼局員工消费合作社印製 五、發明説明（） 址閃控線19爲邏輯“Γ時，定時控制電路71之輸出端21 保持爲邏輯“〇”，而當行位址閃控線19變成邏輯“0”時其會 變成邏輯“Γ。圖5顯示了列位址閃控線90、行位址閃控 線91、及定時控制電路輸出95的定時關係。當行位址閃 控線19再度變成邏輯“Γ時，定時控制電路71的輸出端 21會變成邏輯“〇”。換而言之，每當行位址閃控線19爲邏 輯“Γ時定時控制電路71之輸出端21均爲邏輯“0”，而當 行位址閃控線19再度變成邏輯“〇”時定時控制電路71之輸 出端21就會回到邏輯“1”。 每當行位址閃控線19爲邏輯“Γ時，位址鎖定電路72 的輸出端14爲邏輯“Γ。而當行位址閃控線19降到邏輯 “〇”之後，位址鎖定電路72的輸出端14會保持在邏輯 “Γ，直到反相位址鎖定致能線13由邏輯“0”變成邏輯 “Γ，且位址鎖定致能線由邏輯“Γ變成邏輯“0”。圖5顯示 了列位址閃控線90、行位址閃控線91、反相位址鎖定致 能94及位址鎖定電路輸出96的時間關係。 在定時控制電路71的輸出端21爲邏輯“Γ的情況下， 資料鎖住電路73的輸出端15保持爲邏輯“0”直到反相資料 鎖住致能線12由邏輯“1”變成邏輯“〇，，（資料鎖住致能線由 邏輯“〇”變成邏輯“1”），然後輸出端15變成邏輯“Γ。資 料鎖住電路73的輸出端15保持爲邏輯“Γ直到定時控制電 路71的輸出端21或者位址鎖定電路72的輸出端14變成 邏輯’然後輸出端15變成邏輯“0”。圖5顯示了列位址 閃控線90、行位址閃控線91、反相資料鎖住致能93、定 7 (請先聞讀背面之注意事項再填寫本頁) 装· 訂 本紙張尺度適用中國國家橾隼（（^)八4規格（210/ 297公釐> 2^3907 at B7 經濟部中央梯準局貝工消费合作社印裝 五、發明説明（） 時控制電路輸出95、位址鎖定電路輸出96及資料鎖住電 路輸出97的時間關係。 請再度參考圖5，其中顯示了列位址閃控線90、行位 址閃控線91、資料92、位址鎖定電路輸出96及資料鎖住 電路輸出97的時間關係。當行位址閃控線91由邏輯“0”變 成邏輯“Γ時，一個新的位址會被引入以選擇一組新的資 料。若來自先前位址選擇的資料未在新位址進來之前被建 立的話，則來自先前位址選擇的資料會被蓋過去而喪失 掉。如圖5所見者，在行位址閃控線91由邏輯“0”變成邏 輯“Γ之前（這會造成一個新的位址），資料並未完全被建 立。然而，位址鎖定電路的輸出96與資料鎖住電路的輸出 97保護這資料直到它被完全建立並鎖住爲止。 圖4顯示了能實現圖3的方塊圖與圖5的定時關係之 邏輯電路圖的一例。其中的定時控制電路括：第一 nor 電路51、第二NOR電路53及第三NOR電路52，與第一 反相器41及第二反相器42。第三NOR電路52的輸出端 22接到第一 NOR電路51的一個輸入端，第一 NOR電路 51的輸出端21接到第三NOR電路52的一個輸入端，前 述輸出端21並且爲定時控制電路的輸出。第一 NOR電路 51的一個輸入端接到行位址閃控線19，列位址閃控線18 與第一反相器41串聯而接到第一 NOR電路51的另一個輸 入端，行位址閃控線19與第二反相器42串聯而接到第二 NOR電路53的一個輸入端，第二NOR電路53的另一個 輸入端接到反相讀出線20，第二NOR電路53的輸出端接 8 ----------裝-- (請先閱讀背面之注意事項再填寫本頁) 訂 本紙張尺度遴用中國國家樣準（CNIS ) Λ4規格（210X 297公釐） 經濟部中央橾準局貝工消费合作社印策 A7 _________B7 五、發明説明（） 到第三NOR電路52之剩下的一個輸入端。 參考圖4及圖5中所顯示的列位址閃控線、行位址閃 控線、及定時控制電路輸出的定時關90、91、及95。當 列位址閃控線18爲邏輯“0”時，第一 NOR電路51的輸出 端21，亦即前述定時控制電路的輸出端，爲邏輯“0” ；當 行位址閃控線19爲邏輯“Γ時，第一 NOR電路51的輸出 端21爲邏輯“0”。當行位址閃控線19保持在邏輯“0”而列 位址閃控線18切換至邏輯“Γ的情況下，第一 NOR電路 51的輸出端保持在邏輯“0”。此外，在列位址閃控線18爲 邏輯“Γ的情況下，當行位址閃控線19切換至邏輯“1”第一 NOR電路51的輸出端21仍然會保持爲邏輯“0”。而當列 位址閃控線18爲邏輯“Γ且反相讀出線20爲邏輯“0”的情 況下，當行位址閃控線19由邏輯“Γ切換成邏輯“0”，第一 NOR電路51的輸出端21會切換成邏輯“1”，且保持爲邏 輯“1”直到行位址閃控線由邏輯“0”切換成邏輯“1”，第一 NOR電路51的輸出端21再由邏輯“Γ切換成邏輯“0”。在 列位址閃控線18保持爲邏輯“1”且反相讀出線20保持爲邏 輯“0”的情況下，定時循環會形成一種重複以下兩種情形的 形狀，包括：當行位址閃控線19爲邏輯“0”時，第一 NOR 電路51的輸出端21爲邏輯“1”，當行位址閃控線19爲邏 輯“1”時’其爲邏輯“0”。若反相讀出線20爲邏輯“Γ則第 一 NOR電路51的輸出端21會在整個定時循環中保持爲邏 輯“0，，。 參考圖4，前述位址鎖定電路包括：第四NOR電路 __9 本紙張尺度適用中國國家榡準（CNS ) Λ4規格（210X297公釐j I—» -- I ^^1 n n I n ^ —1 I- :1 ml HI I I TV 0¾ - Te (請先閱讀背面之注意事項再填寫本頁) kl __B7 五、發明説明（） 54、第一 NAND電路63、第二NAND電路64、第三反 相器46、第四反相器43、第五反相器44、第六反相器 45 〇第一 NAND電路63的一個輸入端接到前述定時控制 電路的輸出端21。第一 NAND電路63的輸出端接到二 NAND電路64的一個輸入端，第二NAND電路64的輸出 端14亦爲前述位址鎖定電路的輸出端。行位址閃控線19 與第四反相器43、第五反相器44、第六反相器45串聯而 接到第二NAND電路64的另一個輸入端。第四NOR電路 54的一個輸入端接到反相位址鎖定致能線13，前述位址 鎖定電路的輸出端14與第三反相器46串聯而接到第四 NOR電路54的另一個輸入端。第四NOR電路54的輸出 端接到第一 NAND電路63的一個輸入端。 經濟部中央搮準局貝工消费合作社印製 (請先閱讀背面之注意事項再填寫本頁) 參考圖4及圖5中所顯示的列位址閃控線90、行位址 閃控線91、反相位址鎖定致能94、定時控制電路輸出95 及位址鎖定電路輸出96的定時關係。當行位址閃控線19 爲邏輯“Γ時，前述位址鎖定電路的輸出端14爲邏輯“Γ， 當行位址閃控線19爲邏輯“0”且前述定時控制電路的輸出 端21爲邏輯“0”時，前述位址鎖定電路的輸出端14爲邏輯 “〇”。當行位址閃控線19由邏輯“Γ切換成邏輯“0”時，前 述位址鎖定電路的輸出端14保持爲邏輯“Γ直到反相位址 鎖定致能線13由邏輯“0”切換成邏輯“1”爲止，然後輸出端 14才切換成邏輯“0”。其原因在於當行位址閃控線19爲邏 輯“〇”的期間，前述定時控制電路的輸出端21會保持爲邏 輯“1”。 _ 10 本紙張尺度適用中國國家標準（CNS ) Λ4坭格（2HVX 297公釐） 經濟部中央樣準局貝工消费合作社印製 A7 ______ B7 五、發明説明（） 參考圖4 ’資料鎖住電路包括：第三NAND電路 61、第四NAND電路62、及第七反相器47。第三NAND 電路61的一個輸入端接到反相資料鎖住致能線π，另一 個輸入端接到前述位址鎖定電路的輸出端14。第三 NAND電路61的輸出端接到第四NAND電路62的一個輸 入端。第四NAND電路62的另一個輸入端接到前述定時 控制電路的輸出端21，第四NAND電路62的輸出端接到 第七反相器47的輸入端。第七反相器47的輸出端丨5爲前 述資料鎖住電路的輸出端。 參考圖4及圖5中所顯示的列位址閃控線90、行位址 閃控線91、反相資料鎖住致能93、定時控制電路輸出95 及資料鎖住電路輸出97的定時關係。若前述定時控制電路 的輸出端21爲邏輯“〇”，則前述資料鎖住電路的輸出端15 爲邏輯“0” ；若前述定時控制電路的輸出端21爲邏輯“Γ， 且若反相資料鎖住致能線12爲邏輯“0，，，或者前述位址鎖 定電路的輸出端14爲邏輯“〇”，則前述資料鎖住電路的輸 出端15爲邏輯“1” ；另—方面，若前述定時控制電路的輸 出端21爲邏輯“1”，且若反相資料鎖住致能線12爲邏輯 “1”，並且前述位址鎖定電路的輸出端14爲邏輯“Γ，則前 述資料鎖住電路的輸出端15爲邏輯“0”。 參考圖5，當行位址閃控線91切換成邏輯“Γ時前述 位址鎖定電路的輸出端位址鎖定電路輸出96會切換成邏輯 “Γ ’並且一直保持爲邏輯“1”直到反相位址鎖定致能94切 換爲邏輯“Γ (位址鎖定致能線切換爲邏輯“0”）爲止。當 11 (請先閲讀背面之注意事項再填寫本頁) 裝. 訂 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公釐） A7 293907 五、發明説明（） 前述位址鎖定電路的輸出端饋入位址輸入緩衝器，該位址 輸入緩衝器會被鎖定，直到資料92被建立爲止。當反相資 料鎖住致能93切換成邏輯“0”，亦即資料鎖住致能線切換 成邏輯“Γ時，前述資料鎖住電路的輸出端97會切換爲邏 輯“Γ，且會保持爲邏輯“1”直到行位址閃控線91再度切換 回邏輯“Γ爲止。當該資料鎖住電路的輸出端97饋入資料 輸出緩衝器，該資料輸出緩衝器會被鎖住直到行位址閃控 線切換到邏輯“Γ，開始下一次的行讀出爲止。 綜上所述，圖4的邏輯電路可產生位址鎖定電路與資 料鎖住電路所需的輸出。 在發明詳細說明中所提出之具體的實施態樣或實施例 僅爲了易於說明本發明之技術內容，而並非將本發明狹義 地限制於該實施例，在不超出本發明之精神及以下之申請 專利範圍之情況，可作種種變化實施。 (請先閱讀背面之注意事項再填寫本頁) 裝· 訂 經濟部中央搮隼局另工消费合作社印製 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公釐）3907 A7 _____B7 5. Description of the invention () 'Background of the invention Technical scope The present invention relates to a dynamic random access memory dram, more specifically, a method for preventing data loss in DRAM. The DRAM uses the Extended Data Out mode (EDO mode). The present invention provides a logic circuit that can generate a one-bit address lock output and a data lock output. The address lock output is fed into an address input buffer, and the data lock output is fed into a data output buffer. The aforementioned address input buffer is locked and the data output buffer is locked until the data is created. 'Conventional technology When EDO mode is used in a dynamic random access memory array, the paging mode cycle time is reduced and the data output cycle time remains unchanged. If the data is not completely created before the end of the time window allocated to read the data, the data may be lost. Effects of the Invention In view of this, the object of the present invention is to provide a self-timed address lock and data lock circuit to protect the data during reading. Printed by the Beigong Consumer Cooperative of the Central Standard Rating Bureau of the Ministry of Economic Affairs -------- 1 Pack — (Please read the precautions on the back before filling this page) The invention must be in a memory circuit, such as dynamic random access memory In the body, when the expansion data output mode is used, the paging mode cycle time is reduced and the data output cycle remains unchanged. This will cause the problem of data loss. Fig. 1A shows a conventional timing cycle of memory readout without an expanded data output mode. As shown in FIG. 1A, at the address of the line flash control line (RAS) 80 is logical "Γ 2 paper size suitable for China National Standards (CNS) Λ4 specifications (210X297 mm). Cooperatives printed A7 B7 V. Description of the invention () In case, the row address flash control line (CAS) 81 changes from logic “Γ” to logic “〇”, data 82 will be created, and the aforementioned data 82 must be flash controlled at the row address The line (CAS) 81 is established before returning to the logic "Γ. Figure 1B shows the data loss problem that may occur when using the expanded data output mode. More specifically, it shows the traditional billions of dollars with the expanded data output mode. Timing cycle of volume read. As shown in FIG. 1B, in the case where the column address flash control line (RAS) 83 is logic "Γ, the row address flash control line (CAS) 84 changes from logic" Γ to logic "0" After that, the data 85 will be created. When the extended data output mode is used, the row address flash control line (CAS) 84 has a higher timing rate, so the row address flash control line (CAS) 84 changes from logic "0" to Logic "Γ Prior to the data 85 has not been fully established. The results are shown in Figure 1A, causing data loss. In view of this, the first object of the present invention is to provide a self-timed address lock and data lock circuit to prevent data loss in the dynamic random access memory using the extended data output mode. Another object of the present invention is to provide a dynamic random access memory circuit using self-timed address lock and data lock circuits to prevent data loss in the memory array using the expanded data output mode. The above purpose is achieved by a data lock and address lock timing control circuit. This data lock and address lock timing control circuit provides an address lock output and a data lock output, which will input the address The buffer locks until the data is completely established and locked. When the row address flashing line becomes logic "Γ, the aforementioned address lock output will become 'logic" 1 ", and then when the row address flashing line has returned to logic, the aforementioned _______ 3 National Standard (CNS) Λ4 specification (210X297mm) (Please read the precautions on the back before filling in this page) Packing _ -Order 293907 A7 _B7____ Printed by the Central Consumer ’s Bureau of the Central Ministry of Economic Affairs. The address lock output remains at logic "r" until the address lock enable line returns to logic. When the aforementioned data lock enable line becomes logic “Γ”, the aforementioned data lock output becomes logic “Γ, and the row address flash control line becomes logic“ 0 ”, or the address lock output becomes logic“ 〇 ”, the row bit The address flash line is logic "〇". When the aforementioned data lock enable line becomes logic and the address lock output becomes logic "Γ, or when the row address flash line is logic" Γ, the aforementioned data lock output becomes logic "〇". The address lock output and data lock output are used to lock the address input buffer until the data is completely established and locked in the address input buffer. In the following, the drawings and the preferred embodiments are used to further explain how to implement the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A shows the timing cycle of column address flash lines, row address flash lines, and data for DRAMs without EDD used in the conventional technology; FIG. 1B shows the conventional technology used in the conventional technology. EDD DRAM column address flash line, row address flash line and data timing cycle; Figure 2 shows the block diagram of the data lock and address lock timing control circuit used in conjunction with the memory array; Figure 3 Figure 4 shows the block diagram of the data lock and address lock timing control circuit; Figure 4 shows the logic of the data lock and address lock timing control circuit, and Figure 5 shows the row address flash control of the DRAM with EDD used in the present invention Line, line address flash control line, data, reverse phase data lock enable, reverse phase 4 ^ paper wave standard general Chinese national falcon (CNS) Λ4 specifications (210X297 mm) (please read the notes on the back before filling in This page) Binding · Order A7 ____B7_ printed by the Beigong Consumer Cooperative of the Central Department of Economic Affairs of the Ministry of Economic Affairs 5. Description of the invention () Data lock enable, timing control circuit output, address lock circuit output and data lock circuit output, etc. Refer to FIG. 2 for a detailed description of the preferred embodiment, which shows the data lock and address lock timing control circuit of the present invention, which is used in a memory array with an expanded data output mode, such as dynamic random access memory, etc. . The data lock and address lock timing control circuit 31 has inputs from the column address flash control line 18, row address flash control line 19, and inverted readout line 20, and the data line signal detection circuit 30 has a memory array (Not shown) the data line 10 and the inverted data line 11 are used as input terminals, and have the inverted data lock enable line 12 and the reverse phase address lock enable line 13 as output terminals, and these data lines are fed in The input terminal of the data lock and address lock timing control circuit 31. The aforementioned data lock and address lock timing control circuit 31 has an address lock output 14 connected to the input terminal of the address input buffer 32, and a data lock output 15 connected to the input terminal of the data output buffer 33. The address input buffer 32 has a plurality of address input terminals 16, and the data output buffer 33 has a plurality of data output terminals 17. When the address lock output 14 of the data lock and address lock timing control circuit 31 is logic "Γ, the address in the address input buffer 32 will be locked in the address input buffer 32 until the address is locked The output 14 returns to the logic "0". When the data lock output 15 of the data lock and address lock timing control circuit 31 is logic "1", the data in the data output buffer 33 will be locked at the data output In the buffer 33 until the data lock output 15 returns to a logic "0". This address input buffer 32 and data output buffer 5 (please read the precautions on the back before filling in this page) 袈. Book size Leisure China National Standard (CNS > Λ4 specification (210〆297mm) Printed A7 _B7_____ by the Beige Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs V. Invention description () The control of the device 33 can be prevented in the expansion data output mode Before the data is completely established and locked, the row address flash control line becomes logic "Γ, which may cause data loss. Figure 3 shows the block diagram of the aforementioned data lock and address lock timing control circuit, which includes : Timing control circuit 71, address lock circuit 72, and data lock circuit 73. Timing control circuit 71 has inputs connected to row address flash control line 19, column address flash control line 18, and inverted readout line 20. The output 21 of the timing control circuit 71 is connected to the first input of the data lock circuit 73, the second input of the data lock circuit 73 is connected to the inverted data lock enable line 12, and the data lock circuit 73 The output terminal 15 is connected to the data output buffer (not shown in FIG. 3). The first input terminal of the address lock circuit 72 is connected to the reverse phase address lock enable line 13, and the second input terminal is connected to the row address flash Control line 19. The output terminal 14 of the aforementioned address lock circuit 72 is connected to the first input terminal 21 of the data lock circuit 73 and to the input terminal of an address input buffer (not shown in FIG. 3). When the flash line 18 is logic "0", the output 21 of the timing control circuit 71 is logic "0", the output 15 of the data lock circuit 73 is logic "0", and the output 14 of the address lock circuit 72 has The same size as the row address flash line 19. The part I am interested in is the read part of the timed loop , That is, when the column address flash line 18 is logic "Γ, the inverted read line 20 is logic" 0 ", and the read line is logic" Γ. The flash address line 18 at the column address has become logic "After Γ, when the inverted readout line 20 is logic" 0 ", the output 21 of the timing control circuit 71 will remain at logic" 0 "until the row address flash line 19 becomes logic" 1 ". Row _ 6 Applicable to China National Standard (CNS) M specifications (2 丨 0 X 29 · 7mm y ~ ~ ~ (please read the precautions on the back before filling out this page). Install. Order 203907 A7 B7 Central Ministry of Economic Affairs Printed by Falcon Bureau Employee Consumer Cooperative V. Description of the invention () When the address flash control line 19 is logic "Γ, the output 21 of the timing control circuit 71 remains at logic" 〇 ", and when the row address flash control line 19 becomes When logic "0", it will become logic "Γ. Fig. 5 shows the timing relationship of the column address flash control line 90, the row address flash control line 91, and the timing control circuit output 95. When the row address flash line 19 becomes logic "Γ" again, the output 21 of the timing control circuit 71 becomes logic "〇". In other words, the timing is performed whenever the row address flash line 19 is logic "Γ" The output terminals 21 of the control circuit 71 are all logic "0", and when the row address flash line 19 becomes logic "0" again, the output terminal 21 of the timing control circuit 71 will return to logic "1". Whenever the row address flash line 19 is logic "Γ, the output terminal 14 of the address lock circuit 72 is logic" Γ. When the row address flash line 19 drops to logic "0", the output terminal 14 of the address lock circuit 72 will remain at logic "Γ" until the reverse phase address lock enable line 13 changes from logic "0" to logic "Γ, and the address lock enable line changes from logic" Γ to logic "0". Figure 5 shows the column address flash control line 90, row address flash control line 91, reverse phase address lock enable 94 and bit The time relationship of the address lock circuit output 96. In the case where the output 21 of the timing control circuit 71 is logic "Γ, the output 15 of the data lock circuit 73 remains at a logic" 0 "until the inverted data locks the enable line 12 changes from logic “1” to logic “〇”, (the data lock enable line changes from logic “〇” to logic “1”), and then output 15 becomes logic “Γ”. The output terminal 15 of the data lock circuit 73 remains at logic "Γ until the output terminal 21 of the timing control circuit 71 or the output terminal 14 of the address lock circuit 72 becomes logic" and then the output terminal 15 becomes logic "0". Figure 5 shows Column address flash line 90, row address flash line 91, inverted data lock enable 93, Ding 7 (please read the precautions on the back before filling this page) Falcon ((^) August 4 specifications (210 / 297mm > 2 ^ 3907 at B7 Ministry of Economic Affairs, Central Bureau of Standards and Technology, Beige Consumer Cooperative Printed by Fifth, Invention Description (), control circuit output 95, address lock circuit Time relationship between output 96 and data lock circuit output 97. Please refer again to Figure 5, which shows column address flash line 90, row address flash line 91, data 92, address lock circuit output 96 and data lock The time relationship of the circuit output 97. When the row address flash line 91 changes from a logic "0" to a logic "Γ, a new address will be introduced to select a new set of data. If selected from the previous address If the data is not created before the new address comes in, then come The data selected by the previous address will be overwritten and lost. As seen in Figure 5, before the row address flash line 91 changes from logic "0" to logic "Γ (this will cause a new address), the data and Not completely established. However, the output 96 of the address lock circuit and the output 97 of the data lock circuit protect this data until it is fully established and locked. Figure 4 shows the block diagram of FIG. 3 and FIG. 5 An example of a logic circuit diagram of the timing relationship. The timing control circuit includes: a first nor circuit 51, a second NOR circuit 53 and a third NOR circuit 52, and a first inverter 41 and a second inverter 42. The third The output terminal 22 of the NOR circuit 52 is connected to an input terminal of the first NOR circuit 51, the output terminal 21 of the first NOR circuit 51 is connected to an input terminal of the third NOR circuit 52, and the aforementioned output terminal 21 is a timing control circuit. One input terminal of the first NOR circuit 51 is connected to the row address flash control line 19, and the column address flash control line 18 is connected in series with the first inverter 41 and connected to the other input terminal of the first NOR circuit 51. The row address flash line 19 is connected in series with the second inverter 42 One input terminal of the second NOR circuit 53, the other input terminal of the second NOR circuit 53 is connected to the inverted readout line 20, and the output terminal of the second NOR circuit 53 is connected to 8 ---------- -(Please read the precautions on the back before filling out this page) The standard paper size selection is China National Standards (CNIS) Λ4 (210X 297mm). The Ministry of Economic Affairs, Central Bureau of Standardization, Beigong Consumer Cooperative Institution A7 _________B7 Fifth, the invention () to the remaining one input terminal of the third NOR circuit 52. Refer to the column address flash line, row address flash line, and timing control circuit output shown in FIG. 4 and FIG. 5. Time off 90, 91, and 95. When the column address flash line 18 is logic "0", the output 21 of the first NOR circuit 51, that is, the output of the aforementioned timing control circuit, is logic "0"; when the row address flash line 19 is At logic "Γ, the output 21 of the first NOR circuit 51 is logic" 0. "When the row address flash line 19 remains at logic" 0 "and the column address flash line 18 switches to logic" Γ " The output of the first NOR circuit 51 remains at logic "0". In addition, in the case where the column address flash line 18 is logic “Γ”, when the row address flash line 19 is switched to logic “1”, the output terminal 21 of the first NOR circuit 51 will remain at logic “0”. When the column address flash line 18 is logic "Γ" and the inverted readout line 20 is logic "0", when the row address flash line 19 is switched from logic "Γ to logic" 0 ", the first The output terminal 21 of the NOR circuit 51 will be switched to a logic "1" and remain at a logic "1" until the row address flash line is switched from a logic "0" to a logic "1". The output terminal 21 of the first NOR circuit 51 Then switch from logic "Γ" to logic "0". In the case where the column address flash line 18 remains at a logic "1" and the inverted readout line 20 remains at a logic "0", the timing loop will form a shape that repeats the following two situations, including: when the row address When the flash line 19 is a logic "0", the output terminal 21 of the first NOR circuit 51 is a logic "1", and when the row address flash line 19 is a logic "1", it is a logic "0". If the inverted readout line 20 is logic "Γ", the output 21 of the first NOR circuit 51 will remain at logic "0" for the entire timing cycle. Referring to FIG. 4, the aforementioned address locking circuit includes: a fourth NOR circuit __9 This paper standard is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297mm j I— »-I ^^ 1 nn I n ^ —1 I-: 1 ml HI II TV 0¾-Te (please read the precautions on the back before filling in this page) kl __B7 V. Description of invention () 54, first NAND circuit 63, second NAND circuit 64, third inversion 46, the fourth inverter 43, the fifth inverter 44, the sixth inverter 45. One input terminal of the first NAND circuit 63 is connected to the output terminal 21 of the aforementioned timing control circuit. The output terminal is connected to an input terminal of the second NAND circuit 64, and the output terminal 14 of the second NAND circuit 64 is also the output terminal of the aforementioned address lock circuit. The row address flash control line 19 and the fourth inverter 43, fifth The inverter 44 and the sixth inverter 45 are connected in series and connected to the other input terminal of the second NAND circuit 64. One input terminal of the fourth NOR circuit 54 is connected to the reverse phase address lock enable line 13, the aforementioned address The output terminal 14 of the lock circuit is connected in series with the third inverter 46 to the other input terminal of the fourth NOR circuit 54. The fourth NOR circuit 54 The output terminal is connected to an input terminal of the first NAND circuit 63. Printed by the Beigong Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page). The timing relationship between the address flash line 90, the row address flash line 91, the reverse phase address lock enable 94, the timing control circuit output 95 and the address lock circuit output 96. When the row address flash line 19 is logic "When Γ, the output terminal 14 of the address lock circuit is logic" Γ, when the row address flash control line 19 is logic "0" and the output terminal 21 of the timing control circuit is logic "0", the address The output 14 of the lock circuit is a logic "0." When the row address flash control line 19 is switched from a logic "Γ to a logic" 0 ", the output 14 of the aforementioned address lock circuit remains at a logic" Γ until the reverse phase The address lock enable line 13 is switched from logic "0" to logic "1", and then the output terminal 14 is switched to logic "0". The reason is that when the row address flash control line 19 is logic "〇", The output 21 of the aforementioned timing control circuit will remain at a logic "1". _ 10 This paper scale is applicable to the Chinese National Standard (CNS) Λ4 dia (2HVX 297mm) Printed by the Central Sample Bureau of the Ministry of Economic Affairs Beigong Consumer Cooperative A7 ______ B7 V. Description of invention () Refer to Figure 4 'Data lock circuit includes: The third NAND circuit 61, the fourth NAND circuit 62, and the seventh inverter 47. One input terminal of the third NAND circuit 61 is connected to the inverted data lock enable line π, and the other input terminal is connected to the aforementioned address The output terminal 14 of the lock circuit. The output terminal of the third NAND circuit 61 is connected to an input terminal of the fourth NAND circuit 62. The other input terminal of the fourth NAND circuit 62 is connected to the output terminal 21 of the aforementioned timing control circuit, and the output terminal of the fourth NAND circuit 62 is connected to the input terminal of the seventh inverter 47. The output terminal 5 of the seventh inverter 47 is the output terminal of the aforementioned data lock circuit. Refer to the timing relationships of the column address flash line 90, row address flash line 91, inverted data lock enable 93, timing control circuit output 95, and data lock circuit output 97 shown in FIGS. 4 and 5. . If the output terminal 21 of the timing control circuit is logic "0", the output terminal 15 of the data lock circuit is logic "0"; if the output terminal 21 of the timing control circuit is logic "Γ, and if the data is inverted The lock enable line 12 is logic "0", or the output terminal 14 of the address lock circuit is logic "0", then the output terminal 15 of the aforementioned data lock circuit is logic "1"; on the other hand, if The output 21 of the timing control circuit is logic "1", and if the inverted data lock enable line 12 is logic "1", and the output 14 of the address lock circuit is logic "Γ, then the data lock The output terminal 15 of the circuit is logic "0". Referring to FIG. 5, when the row address flash control line 91 is switched to logic "Γ", the output of the address lock circuit 96 of the address lock circuit is switched to logic "Γ" 'And remain at logic "1" until the reverse phase address lock enable 94 is switched to logic "Γ (address lock enable line is switched to logic" 0 "). When 11 (please read the precautions on the back before filling in this page). The size of this paper is applicable to the Chinese National Standard (CNS) Λ4 specification (210X 297mm) A7 293907 V. Description of invention () The output terminal is fed into the address input buffer, and the address input buffer will be locked until the data 92 is created. When the inverted data lock enable 93 is switched to logic "0", that is, the data lock enable line is switched to logic "Γ, the output terminal 97 of the aforementioned data lock circuit will be switched to logic" Γ, and will remain It is logic “1” until the line address flash line 91 is switched back to logic “Γ” again. When the output 97 of the data lock circuit is fed into the data output buffer, the data output buffer will be locked until the line position The address flash line is switched to logic "Γ" until the next row readout. In summary, the logic circuit of FIG. 4 can generate the output required by the address lock circuit and the data lock circuit. The specific implementation forms or embodiments proposed in the detailed description of the invention are only for easy description of the technical content of the present invention, and do not limit the present invention to the embodiment in a narrow sense, without exceeding the spirit of the present invention and the following applications The scope of patents can be changed in various ways. (Please read the precautions on the back before filling in this page) Binding · Order Printed by the Central Office Falcon Bureau of the Ministry of Economic Affairs Printed by the Co-operative Consumer Cooperatives