TW247370B - - Google Patents

Info

Publication number
TW247370B
TW247370B TW082109364A TW82109364A TW247370B TW 247370 B TW247370 B TW 247370B TW 082109364 A TW082109364 A TW 082109364A TW 82109364 A TW82109364 A TW 82109364A TW 247370 B TW247370 B TW 247370B
Authority
TW
Taiwan
Application number
TW082109364A
Other languages
Chinese (zh)
Original Assignee
At & T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by At & T Corp filed Critical At & T Corp
Application granted granted Critical
Publication of TW247370B publication Critical patent/TW247370B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/082—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being tapered via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/092—Manufacture or treatment of dielectric parts thereof by smoothing the dielectric parts
TW082109364A 1992-11-12 1993-11-06 TW247370B (index.php)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/975,235 US5268332A (en) 1992-11-12 1992-11-12 Method of integrated circuit fabrication having planarized dielectrics

Publications (1)

Publication Number Publication Date
TW247370B true TW247370B (index.php) 1995-05-11

Family

ID=25522812

Family Applications (1)

Application Number Title Priority Date Filing Date
TW082109364A TW247370B (index.php) 1992-11-12 1993-11-06

Country Status (5)

Country Link
US (1) US5268332A (index.php)
EP (1) EP0597634A3 (index.php)
JP (1) JPH06224188A (index.php)
KR (1) KR100276146B1 (index.php)
TW (1) TW247370B (index.php)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2926864B2 (ja) * 1990-04-12 1999-07-28 ソニー株式会社 銅系金属膜のエッチング方法
US6297110B1 (en) 1994-07-29 2001-10-02 Stmicroelectronics, Inc. Method of forming a contact in an integrated circuit
JPH11506744A (ja) 1995-06-07 1999-06-15 ノウブン ファーマシューティカルズ インク． 室温で液体である低分子量薬を含む経皮組成物
CN102157437B (zh) * 2010-02-11 2013-12-25 中国科学院微电子研究所 半导体结构的形成方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4708770A (en) * 1986-06-19 1987-11-24 Lsi Logic Corporation Planarized process for forming vias in silicon wafers
EP0263220B1 (en) * 1986-10-08 1992-09-09 International Business Machines Corporation Method of forming a via-having a desired slope in a photoresist masked composite insulating layer
US5022958A (en) * 1990-06-27 1991-06-11 At&T Bell Laboratories Method of etching for integrated circuits with planarized dielectric

Also Published As

Publication number Publication date
US5268332A (en) 1993-12-07
JPH06224188A (ja) 1994-08-12
KR100276146B1 (ko) 2001-01-15
EP0597634A3 (en) 1994-08-24
EP0597634A2 (en) 1994-05-18
KR940012505A (ko) 1994-06-23

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Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent