TW225592B - - Google Patents

Info

Publication number
TW225592B
TW225592B TW082100288A TW82100288A TW225592B TW 225592 B TW225592 B TW 225592B TW 082100288 A TW082100288 A TW 082100288A TW 82100288 A TW82100288 A TW 82100288A TW 225592 B TW225592 B TW 225592B
Authority
TW
Taiwan
Application number
TW082100288A
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of TW225592B publication Critical patent/TW225592B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
TW082100288A 1991-12-16 1993-01-18 TW225592B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/808,108 US5359723A (en) 1991-12-16 1991-12-16 Cache memory hierarchy having a large write through first level that allocates for CPU read misses only and a small write back second level that allocates for CPU write misses only

Publications (1)

Publication Number Publication Date
TW225592B true TW225592B (zh) 1994-06-21

Family

ID=25197883

Family Applications (1)

Application Number Title Priority Date Filing Date
TW082100288A TW225592B (zh) 1991-12-16 1993-01-18

Country Status (5)

Country Link
US (1) US5359723A (zh)
JP (1) JPH07502356A (zh)
AU (1) AU3333793A (zh)
TW (1) TW225592B (zh)
WO (1) WO1993012484A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI454909B (zh) * 2010-06-24 2014-10-01 Intel Corp 減少記憶體裝置之功率消耗之記憶體裝置、方法及系統

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US5761722A (en) * 1995-01-30 1998-06-02 Sun Microsystems, Inc. Method and apparatus for solving the stale data problem occurring in data access performed with data caches
US5893921A (en) * 1995-02-10 1999-04-13 International Business Machines Corporation Method for maintaining memory coherency in a computer system having a cache utilizing snoop address injection during a read transaction by a dual memory bus controller
US5737748A (en) * 1995-03-15 1998-04-07 Texas Instruments Incorporated Microprocessor unit having a first level write-through cache memory and a smaller second-level write-back cache memory
US5761709A (en) * 1995-06-05 1998-06-02 Advanced Micro Devices, Inc. Write cache for servicing write requests within a predetermined address range
US5652859A (en) * 1995-08-17 1997-07-29 Institute For The Development Of Emerging Architectures, L.L.C. Method and apparatus for handling snoops in multiprocessor caches having internal buffer queues
US5794243A (en) * 1995-12-11 1998-08-11 International Business Machines Corporation Method and apparatus for executing a binary search in a data cache
US5778431A (en) * 1995-12-19 1998-07-07 Advanced Micro Devices, Inc. System and apparatus for partially flushing cache memory
US5875462A (en) * 1995-12-28 1999-02-23 Unisys Corporation Multi-processor data processing system with multiple second level caches mapable to all of addressable memory
JP3618442B2 (ja) * 1996-02-08 2005-02-09 株式会社東芝 マイクロプロセッサのパワーエスティメータ装置
US5920891A (en) * 1996-05-20 1999-07-06 Advanced Micro Devices, Inc. Architecture and method for controlling a cache memory
US5875469A (en) * 1996-08-26 1999-02-23 International Business Machines Corporation Apparatus and method of snooping processors and look-aside caches
US5946710A (en) * 1996-11-14 1999-08-31 Unisys Corporation Selectable two-way, four-way double cache interleave scheme
US5960455A (en) * 1996-12-30 1999-09-28 Unisys Corporation Scalable cross bar type storage controller
US5875201A (en) * 1996-12-30 1999-02-23 Unisys Corporation Second level cache having instruction cache parity error control
US6122711A (en) 1997-01-07 2000-09-19 Unisys Corporation Method of and apparatus for store-in second level cache flush
US5860093A (en) * 1997-01-21 1999-01-12 Unisys Corporation Reduced instruction processor/storage controller interface
US5960457A (en) * 1997-05-01 1999-09-28 Advanced Micro Devices, Inc. Cache coherency test system and methodology for testing cache operation in the presence of an external snoop
US5923898A (en) * 1997-05-14 1999-07-13 International Business Machines Corporation System for executing I/O request when an I/O request queue entry matches a snoop table entry or executing snoop when not matched
US6003106A (en) * 1998-05-27 1999-12-14 International Business Machines Corporation DMA cache control logic
US6094605A (en) * 1998-07-06 2000-07-25 Storage Technology Corporation Virtual automated cartridge system
WO2000051004A1 (en) * 1999-02-22 2000-08-31 Infineon Technologies Ag Methods and apparatus for facilitating direct memory access
US6564305B1 (en) * 2000-09-20 2003-05-13 Hewlett-Packard Development Company Lp Compressing memory management in a device
US6629211B2 (en) 2001-04-20 2003-09-30 International Business Machines Corporation Method and system for improving raid controller performance through adaptive write back/write through caching
EP1304620A1 (en) * 2001-10-17 2003-04-23 Texas Instruments Incorporated Cache with selective write allocation
AU2002953500A0 (en) * 2002-12-20 2003-01-09 Redbank Manor Pty Ltd A system and method of requesting, viewing and acting on search results in a time-saving manner
US7519775B2 (en) * 2006-02-23 2009-04-14 Sun Microsystems, Inc. Enforcing memory-reference ordering requirements at the L2 cache level
US9047197B2 (en) * 2007-10-23 2015-06-02 Oracle America, Inc. Non-coherent store instruction for fast inter-strand data communication for processors with write-through L1 caches
US8327121B2 (en) * 2008-08-20 2012-12-04 Mips Technologies, Inc. Data cache receive flop bypass
US8392651B2 (en) * 2008-08-20 2013-03-05 Mips Technologies, Inc. Data cache way prediction
US8935484B2 (en) * 2011-03-31 2015-01-13 Hewlett-Packard Development Company, L.P. Write-absorbing buffer for non-volatile memory
TWI454922B (zh) * 2011-12-19 2014-10-01 Phison Electronics Corp 記憶體儲存裝置及其記憶體控制器與資料寫入方法
CN103186470B (zh) * 2011-12-30 2016-04-20 群联电子股份有限公司 存储器储存装置及其存储器控制器与数据写入方法
KR20210066631A (ko) 2019-11-28 2021-06-07 삼성전자주식회사 메모리에 데이터를 기입하기 위한 장치 및 방법

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI454909B (zh) * 2010-06-24 2014-10-01 Intel Corp 減少記憶體裝置之功率消耗之記憶體裝置、方法及系統

Also Published As

Publication number Publication date
US5359723A (en) 1994-10-25
JPH07502356A (ja) 1995-03-09
WO1993012484A1 (en) 1993-06-24
AU3333793A (en) 1993-07-19

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