218934 A6 B6 經濟部中央標準居貝工消費合作社印製 五、發明説明（/ ) 本發明偽一種共源閘極之縮小型靜電保護電路，主要 為改善傳統MO S F E T靜電保護迴路過份佔用晶片面積 之缺黏者，令後晶矽閘極拉近並與源極接觸區接觸，據以 使整痼保護霣路之寬度縮減，達到縮小佔用面積者，並免 除復晶矽閘極之外接線路，而共用該源極接觸區予以導送 電壓進人，亦同時達到降低稹體霣路之配線複雜度者。 按現今積醱電路而論，雖可使傳統元件之匾積大幅縮 小，逹到産品小型及多功能化之要求，然相對的，積體電 路亦有其致命傷，由於今日積證電路超大部份採用省電性 能優異之C Μ〇S或其他Μ 0 S相關材料構成，對於靜電 敏惑度高，可能因靜電造成損害或是其使用赛命降低，故 而現今積鼷電路因應之道即為於其各外接接腳位置連接所 謂的『防靜電保護電路（ESD)』，此等防靜電保護電 路之構造即為如第一画所示，即於各値輸入端（I / Ρ ) 對應於正電源（V D D )及負電源（V S S )之間分別跨 接以Ρ通道M〇 S F Ε Τ及Ν通道MO S F Ε Τ所構成， 其中，該Ρ或Ν通道MOSFET之汲極（D)偽共同連 接在該輸入端（I /ρ )上，而其閜極及源極（s )即以 並聯方式連接在正電源（VDD)及負電源（VSS)上 ，以當輸入端（Ι/P)受靜電作用時，可藉由該Ρ或Ν 通道MO S F Ε Τ提供一類似於稽纳二極髏之定電鼴作用 ，形成靜導通路徑達到中和異常靜電現象，以免造成後缠 積髏迴路閘極氣化屬之損害者。 本纸張尺度適用中國國家標準（CNS>甲4规格（210 X 2£17公釐） (請先閲讀背面之注意事項再塡寫本頁> 丨裝_ 訂. ^1Β934 Α6 Β6 經濟部中央標準局貝工消費合作社印製 五、發明説明（>〃) 上 述 防 靜 電 保 護 電 路 實 以 下 ΕΠ 針 對 Ν 或 Ρ 通 道 Μ 〇 如 第 二 圖 及 第 三 圖 所 示 9 m Τ 防 靜 電 保 護 電 路 之 俯 視 圖 中 9 於 — Ρ 型 或 Ν 型 基 底 ( Ν + ( 或 Ρ + ) 共 用 源 極 ( 之 N + ( 或 Ρ + ) 汲 極 ( 7 7 2 ) 與 兩 側 之 汲 極 ( 7 1 6 2 ) ( 6 1 ) ( 6 3 ) 以 ) ( 或 正 電 源 V D D ) 連 接 點 ( I Ρ ) » 而 相 郤 接 觸 形 成 有 二 氣 化 矽 閘 氣 化 層 ( 6 2 ) 與 兩 側 接 9S 區 6 1 層 内 則 含 有 一 複 晶 δ夕 閘 極 ( 該 共 用 源 極 ( 6 2 ) 兩 側 分 S F Ε Τ 防 靜 電 保 護 電 路 » 2 ) 更 需 各 別 拉 出 引 線 以 供 V D D 丨 連 接 > 而 前 述 各 値 所 示 1 令 各 値 接 觸 區 ( 6 1 ( δ 1 ) ( 5 2 ) 分 別 向 外 ±nj m ( I / Ρ ) 及 連 接 至 負 電 惟 以 前 述 第 三 圖 該 等 架 等 稱 及 等 距 配 置 此 舉 即 顯 際應用在積體電路上之構造， S F E T之結構予以說明之， 為傳统N或P通道MOSFE 及剖面圖，於第三圖之剖面圖 5 〇 )上有一位在中央位置之 7 2)及對稱設在左、右位置 1 ) ( 7 3 ),該共用源極（ )(73)上方均有接觸區（ 分別形成可供負電源（VSS 之端點及供輸入訊號之輸入端 區！ 6 1 )〜（6 3 )之問則 8 0)，且界於該共用源極（ )(6 3 )間之二氣化矽绝结 5 1) ( 5 2 ),以使對應 別形成兩組N或P通道之Μ Ο 且各複晶矽閘極（5 1 ) (5 負電源（V S S )(或正電源 外接引線即如第二圖之俯視圖 )〜（63)及兩複晶矽閛極 延伸接點，以供分別做為輸入 源或正電源上。 構設計下，各相應之構造偽呈 過份佔用晶Η面積，故本發人 (請先,!;!4背面之注意事項再塡寫本頁) 本紙張尺度適用中國國家標準（CNS)甲4規格（210 X 297公釐） 218934 A6 _B6_ 五、發明説明（}) SP思及欲縮小此等防靜電保護電路之彳占用面積現象，惟改 變结構設計下卽需考慮各種階面，如構造改變後不致造成 靜電保護效果降低及不影鎏既有機能，故而經實際相當多 次的實驗證實，此等MOSFET防靜電保護電路遭受靜 霄破壞後，其故障或破壞的位置均集中在做為輸入端點之 汲極位置，可能為汲極之接觸區（6 i) (63)經由接 觸窗刺穿至基底（50)位置（contact spiking)、複晶矽 閘極（5 1 ) ( 5 2 >熔化而使其與基底（5 0 )間形成 短路（poly filament)、汲極接觸區（6 1) (6 3)與 複晶矽閘極（5 1) (5 2)造成短路（contact short to P 〇 1 y)或者是汲極（7 1 ) ( 7 3 )與複晶矽閘極（5 1 ) (5 2 )間之閘氯化層（8 0 )崩潰（g a t e oxide breakdown)所致，而歸纳上述造成破壊之原因均與該共用 源極（7 2 )及該源極接觸區（6 2 )無關，故本發明人 即針對該共用源極（72)及其接觸區（62)不致造成 防靜電特桂變化之因素下，即針對源極相關部位之佔用面 積縮小的方面進行研究，终發明出一種縮小型靜電保護電 路。 經濟部中央標準局Λ工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 本發明之主要目的在於提供一種縮小型靜電保護電路 ,主要將兩側之複晶矽閛極予以拉近至源極接觸區兩側邊 位置並與之相互接觸，並同時將源極區域之寬度適當縮減 ，此時，由於將兩刨複晶矽閘極拉近與源極接觸下，邸達 到適當縮小其佔用寬度及佔用面積大小，獲致縮小髏積之 本纸張尺度適用中國國家標準（CNS)甲4規格（210 X 297公釐） 經濟部中央櫺準局5工消費合作社印製 218934 A6 _B6 五、發明説明（* ) 優點。 本發明之次一目的在於提供一種縮小型靜電保護電路 ，前述將兩側複晶矽閛極拉近並接觸該源極接觸區後，更 可直接免除該兩複晶矽閛極之外接線路，可直接藉由源極 接觸區同時導送電壓至源極及兩複晶矽閘極上，更具有簡 1佈局複雜度之優點。 為使 貴審査委員能進一步瞭解本發明之结構，特獻 及其他目的，玆 附以圖式詳細說明如后： (一） ._式部份： 第一圖：偽防靜電保護電路之等效電路圖。 第二圖：偽習見防靜電保護電路之俯視圖。 第三圖：傜習見防靜電保護電路之剖面圖。 第四圖：偽本發明之俯視圖。 第五圖：偽本發明之剖面圖。 (二） .圖號部份： (10) t 5 Q )基底 （2 0) ( 8 0 )氣化層 (3 1) (3 3) (7 1) ( 7 3 )汲極 (3 2 ) ( 7 2 )源極 （41) (42) (51) (5 2 )複晶矽閘極（3 1 1 ) (3 2 1 ) (3 3 1 )( 6 1)〜(6 3 )接觸區 本發明據以達成縮小防靜電保護電路（E S D )之實 際寬度大小而獲致縮小其佔用面積之構造上，主要為將源 極接觸區兩側位置之複晶矽閘極予以拉近並與源極接觸區 (請先閱讀背面之注意事項再填寫本頁) 丨裝. 訂· i線- 本纸張尺度適用中國國家標準（CNS)甲4规格（210 X 297公笼） 經濟部中央標準居员工消费合作社印製 218934 A6 _B6 五、發明説明（：） 相接觸，其構造即為如第四、五圖之俯視圖及剖面圖所示 ，而由第五圖該剖面圖中，其構造槪與前述習見防靜電保 護電路雷同（假定複晶矽閜極之通道長度為1接觸 區至複晶矽閘極邊緣同樣為1 Am)，而不同處係在於源 極接觭區（3 2 1)左右兩側之複晶矽閘極（4 1) ( 4 2 )予以向内側各別拉近約1 . 5 a m ,並與該源極接® 區（3 2 1)相互接觸，且源極接觸區（3 2 1)亦予適 當加寬，以做為源極（32)及兩複晶矽閘極（41)( 42)之共用接镝區（3 2 1),且對應在源極接觸區（ 3 2 1)下方之源極（3 2 )則做相應縮小其寬度大小， 以令该兩拉近之複晶矽閛極(41) (42)分別對應在 源極（32)與外側兩汲極（3 1 ) (33)之間，而兩 汲極接觸區（3 1 1) (331)卽連接至輸入端（1/ P)，源極接觸區（321)則與供連接負電源VSS ( 或正電源VDD)者，據以構成雙輸入端P通道或N通道 S F ET之防靜電保護電路。 依照上述構造設計下，即因兩側之複晶矽閘極分別向 内側拉近約1. 5 #πι後，故其每一痼相同於前述第五圖 之單元構造约可縮小約3 之佈局長度，並以設置六組 單元構造為例，即可減少18 pm之佈局長度，當可逹到 縮小佔用面積之效果，而該縮減後所剩餘之空間則可視實 際霱要予以加大汲極接觴窗至複晶矽閘極邊緣之距離，據 以提昇防靜電保護能力。 (請先-fr背面之注意事項再塡寫本頁> 本紙張尺度適用中國國家標準（CNS>甲4规格（210 X 297公釐> Α6 Β6 五、發明説明（又） 此外，本發明該等溝造除了具有前述可達到縮小佔用 面積之功效及可藉由該_減後所空出之空間做為加大汲極 接觸區面積以達到提昇防靜電保護能力及提昇散熱面稹外 ，尤以其兩複晶矽閘極（4 1 ) ( 4 2 )設為與源極接觸 區（3 2 1)相互接镝之設計，可由源極接觸區（32 1 )同時做為供應兩複晶矽閘極（4 1 ) (42)霣源之共 用端點，達到免除習見複晶矽閘極所需之外接導線或導線 佈局者，此可由第四圖之俯視圖觀之，提高保護電路之密 度、縮短接腳至接胞1間的距離與可達到降低導線佈局複雜 度者。 且本發明所改荽之溝造，更僅在該不損及防靜電能力 之源極部份予以適當改變其配置型態及相應關係，且經由 實驗證明並無住何影饗，更有前述諸多優點存在，此外， 本發明該等構造更可如前述僅需改變植入井區及源/汲極 之材質即可直接製成Ν或Ρ通道防靜電保護電路，亦可應 用於積體電路用以縮小佔用面積之用途上及做為高接脚數 靜電保護電路之用，應苻專利申請要件，爰依法提出申請 (請先Μ讀背面之注意事項再埸寫本頁} —裝. 訂. 經濟邾中央標準局R工消费合作社印製 本纸張尺度適用中國國家標準（CNS)甲4規格（210 X 297公货）218934 A6 B6 Printed by Jubei Consumer Cooperative, a central standard of the Ministry of Economic Affairs 5. Description of the invention (/) The present invention is a reduced-type electrostatic protection circuit with a common source gate, mainly to improve the traditional MO SFET electrostatic protection circuit. For those who are not sticky, the rear crystalline silicon gate is brought closer and is in contact with the source contact area, according to which the width of the protective path is reduced, and the occupied area is reduced, and the polycrystalline silicon gate is not connected to the circuit. And the source contact area is shared to conduct voltage into people, and at the same time, it can reduce the wiring complexity of the ballet road. According to today's integrated circuits, although the plaque of traditional components can be greatly reduced to meet the requirements of small and multi-functional products, on the contrary, integrated circuits also have their fatal injuries. It is composed of C MOS or other Μ 0 S related materials with excellent power saving performance. It is highly sensitive to static electricity, which may cause damage due to static electricity or reduce the life of its use. Therefore, the current response of the circuit is to Each external pin position is connected to the so-called "anti-static protection circuit (ESD)". The structure of these anti-static protection circuits is as shown in the first picture, that is, each input terminal (I / Ρ) corresponds to the positive The power supply (VDD) and the negative power supply (VSS) are connected across the P channel MOSFET and N channel MO SFET, respectively, wherein the drain (D) of the P or N channel MOSFET is pseudo-connected At this input (I / ρ), and its source and source (s) are connected in parallel to the positive power supply (VDD) and the negative power supply (VSS), so that when the input terminal (Ι / P) is During static electricity, the P or N channel MO SF Ε Τ can provide a similar Zener diode skull of a given electrical mole role in the formation of static conduction path and reach the abnormal phenomenon of static electricity, so as not to cause skull wrapped around the product gate circuit gasification by genus damage. The size of this paper is applicable to the Chinese National Standard (CNS> A4 specifications (210 X 2 £ 17mm) (Please read the precautions on the back before writing this page> 丨 Installation_ Order. ^ 1Β934 Α6 Β6 Central Ministry of Economic Affairs Printed by Beigong Consumer Cooperative of the Bureau of Standards 5. Description of the invention (> 〃) The above anti-static protection circuit is implemented as follows. Π For the N or P channel Μ 〇 As shown in the second and third figures, the 9 m Τ anti-static protection circuit In the top view, 9 is on the common source of the P-type or N-type substrate (N + (or P +)) (the N + (or P +) drain (7 7 2) and the drain on both sides (7 1 6 2) (6 1) (6 3) to) (or positive power supply VDD) connection point (I Ρ) »but in contact with the formation of two vaporized silicon gate vaporization layer (6 2) and the two sides connected to the 9S area 6 1 layer It contains a polycrystalline δ xi gate (the common source (6 2) is divided into SF ET anti-static protection circuit »2) on both sides. It is necessary to pull out the leads separately for VDD 丨 connection> and the above values Shown 1 Each contact area (6 1 (δ 1) (5 2) is outwardly ± nj m (I / Ρ) and connected to a negative power. The structure applied to the integrated circuit, the structure of the SFET is explained, it is the traditional N or P channel MOSFE and the cross-sectional view, in the cross-sectional view of the third figure 5) There is a bit in the central position 7 2) and symmetrical design In the left and right positions 1) (7 3), there is a contact area above the common source () (73) (respectively forming a negative power supply (the terminal of VSS and the input terminal area for input signal! 6 1) ~ (6 3) question is 8 0), and the second vaporized silicon insulation junction 5 1) (5 2) bounded between the common source () (6 3), so that the corresponding groups form two groups of N or Μ Ο of P channel, and each polycrystalline silicon gate (5 1) (5 negative power supply (VSS) (or positive power supply external lead is the top view as shown in the second figure) ~ (63) and two polycrystalline silicon dendrite poles are extended Point for the input source or positive power supply respectively. Under the design of the structure, each corresponding structure pretends to occupy excessively the area of the crystal H, so the author (please first,!;! 4 Note on the back side and then write this page) This paper scale is applicable to the Chinese National Standard (CNS) A 4 Specifications (210 X 297 mm) 218934 A6 _B6_ V. Description of the invention (}) SP thinks of reducing the area occupied by these anti-static protection circuits, but it is necessary to consider various steps such as structure when changing the structural design. After the change, it will not cause the reduction of the electrostatic protection effect and does not affect the organic energy. Therefore, it has been confirmed by many experiments in practice that after these MOSFET anti-static protection circuits are damaged by the static sky, the location of their failure or damage is concentrated on the The drain position of the input end point may be the contact area (6 i) (63) of the drain electrode pierced through the contact window to the position of the substrate (50) (contact spiking) and the polycrystalline silicon gate (5 1) (5 2 > Melt to form a short circuit (poly filament) with the substrate (50), the drain contact area (61) (63) and the polycrystalline silicon gate (51) (52) cause a short circuit (contact short to P 〇1 y) or drain (7 1) (7 3) and polycrystalline silicon gate (5 1) (5 2) due to the gate oxide breakdown of the gate chloride layer (8 0), and it is concluded that the above causes are not related to the shared source (7 2) and the source contact area (6 2), Therefore, the present inventors conducted research on the aspect that the shared source (72) and its contact area (62) did not cause the special anti-static change, that is, the occupied area of the relevant part of the source was reduced, and finally invented a Reduced electrostatic protection circuit. Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Labor Cooperatives (please read the precautions on the back and then fill out this page). The main purpose of the present invention is to provide a reduced electrostatic protection circuit, which mainly combines the two sides. The crystalline silicon dendrite is brought closer to the two sides of the source contact area and is in contact with each other, and at the same time the width of the source area is appropriately reduced. At this time, due to the two planed polycrystalline silicon gates being pulled closer to the source Under contact, the residence achieved a proper reduction in its occupied width and occupied area, and the paper size of the reduced cross-sectional area is applicable to the Chinese National Standard (CNS) A 4 specifications (210 X 297 mm). Printed by the cooperative. 218934 A6 _B6 5. Description of the invention (*) Advantages. The second objective of the present invention is to provide a reduced electrostatic protection circuit. After the two sides of the polycrystalline silicon dendrite electrodes are pulled closer to the source contact area, It can also directly eliminate the external connection of the two polycrystalline silicon dendrite poles, and can directly direct the voltage to the source and the two polycrystalline silicon gates through the source contact area, which has the advantage of simple layout complexity. Your review committee can further understand the structure, special purpose and other purposes of the present invention. The drawings are attached to explain in detail as follows: (1) ._Form part: The first picture: the equivalent circuit diagram of the pseudo anti-static protection circuit. Figure 2: The top view of the pseudo-learning anti-static protection circuit. Third figure: A cross-sectional view of the anti-static protection circuit. Fourth figure: a top view of the pseudo-present invention. Fifth figure: a cross-sectional view of the pseudo invention. (2) Part of drawing number: (10) t 5 Q) base (2 0) (8 0) vaporization layer (3 1) (3 3) (7 1) (7 3) drain (3 2) (7 2) Source (41) (42) (51) (5 2) Polycrystalline silicon gate (3 1 1) (3 2 1) (3 3 1) (6 1) ~ (6 3) contact area The structure of the present invention to reduce the actual width of the anti-static protection circuit (ESD) and reduce its occupied area is mainly to pull the polycrystalline silicon gates on both sides of the source contact area closer to the source Contact area (please read the precautions on the back and then fill out this page) 丨 installation. Order · i line-This paper standard is applicable to China National Standard (CNS) A 4 specifications (210 X 297 male cage) Ministry of Economy Central Standard Residence Staff Printed by the consumer cooperative 218934 A6 _B6 V. Description of the invention (:) When contacted, the structure is as shown in the top view and cross-sectional view of the fourth and fifth figures, and from the cross-sectional view of the fifth figure, the structure is as described above It is similar to the anti-static protection circuit (assuming that the channel length of the polycrystalline silicon gate is 1 contact area to the edge of the polycrystalline silicon gate is also 1 Am), and the difference is that the source electrode junction area (3 2 1) Side of the complex The silicon gates (4 1) (4 2) are pulled closer to the inside by about 1.5 am, and are in contact with the source junction area (3 2 1), and the source contact area (3 2 1) It is also appropriately widened to serve as the shared dysprosium region (3 2 1) of the source electrode (32) and the two polycrystalline silicon gates (41) (42), corresponding to the source contact region (3 2 1) The lower source electrode (3 2) is correspondingly reduced in width, so that the two close-coupled polycrystalline silicon dendrite electrodes (41) (42) respectively correspond to the source electrode (32) and the outer two drain electrodes (3 1) ) (33), and the two drain contact areas (3 1 1) (331) are connected to the input terminal (1 / P), and the source contact area (321) is connected to the negative power supply VSS (or positive power supply) VDD), which constitutes the anti-static protection circuit of the dual-input P-channel or N-channel SF ET. According to the above structural design, that is, after the polysilicon gates on both sides are pulled inwards by about 1.5 # πι, respectively, each of them has the same layout as the cell structure of the fifth figure, which can be reduced by about 3 layouts. The length, and taking the structure of six sets of units as an example, can reduce the layout length of 18 pm. When the effect of reducing the occupied area can be achieved, the remaining space after the reduction can be increased according to the actual needs. The distance from the window to the edge of the polycrystalline silicon gate is used to enhance the anti-static protection. (Please first -fr the precautions on the back and then write this page> This paper scale is applicable to the Chinese national standard (CNS> A 4 specifications (210 X 297 mm> Α6 Β6 V. Description of the invention (again) These trenches have the above-mentioned effect of reducing the occupied area and the space vacated after the reduction can be used to increase the area of the drain contact area to improve the anti-static protection ability and the heat dissipation surface. In particular, the design of the two polycrystalline silicon gates (4 1) (4 2) is set to interconnect with the source contact area (3 2 1), and the source contact area (32 1) can be used to supply two complexes at the same time. Crystal silicon gate (4 1) (42) The common end point of the Yuan source, so as to avoid the need to connect the wire or the wire layout outside the need to learn the polycrystalline silicon gate. This can be seen from the top view of the fourth figure to improve the protection circuit Density, shorten the distance between the pin and the cell 1 and reduce the complexity of the wire layout. And the trenches modified by the present invention can only be appropriately changed in the source part that does not damage and antistatic ability Its configuration type and corresponding relationship, and through experiments prove that there is no living He Yingbiao In addition, there are many advantages mentioned above. In addition, the structures of the present invention can be directly made into N or P channel antistatic protection circuits by changing the materials of the implanted well area and the source / drain as described above, and can also be applied For the purpose of the integrated circuit to reduce the occupied area and as a high-pin-count electrostatic protection circuit, you should apply for the patent application requirements and file the application according to the law (please read the precautions on the back before writing this page) —Installation. Ordering. The paper printed by the R & C Consumer Cooperative of the Central Standards Bureau of the Economy and Economy applies the Chinese National Standard (CNS) A4 specifications (210 X 297 public goods)