A7 B7 1414TWF.DOC/006 五、發明説明（/) 本發明是有關於一種靜電釋放（El ec t ros t at i e-Discharge ; ESD)保護元件及其製造方法，特別是關於—種只 再次摻雜一個源極/汲極區的ESD保護元件。 金屬氧化半導體（Metal-Oxide-Semiconductor ; M0S) 積體電路（Integrated Circuits ; 1C)的輸入信號是供給m〇s 電晶體的閘極的，如果供給閘極的電壓太高，則閘極氧化層 (Gate Oxide)會崩潰（Break Down)，已知二氧化矽的介電崩 潰強度爲約10X 106V/cm，舉例來說，若有一約15nm厚的閘極 氧化層，將無法承受大於約15V的電壓而崩潰，雖然，積體電 路的操作電壓都在約5V左右，不會產生崩潰的問題，但在人爲 操作或是機械的操作時，卻可能會產生一些高於此電壓的輸入 信號進入電路中。此種不良的電壓源通常來自磨擦生電 (Triboelectricity)，也就是兩物體互相磨擦所產生的靜 電，舉例來說，一個人只要走過房間，或是輕輕將一 1C從塑膠 包裝中取出，都會產生數百個到數千個伏特。假如此高壓不小 心通到1C包裝的接腳（Pms)上，會立刻產生崩潰現象而損壞 元件，使氧化層4法再正常參與元件的操作，而導致元件的失 敗（Device Failure) 〇 爲了防止M0S閘極的損壞，所有MOS 1C的接腳都有提供保 護的電路，通常此種保護電路也應用在超大型積體電路（Very Large Scale Integration ; VLSI)的兀件製作上，此種保 護電路都置於晶片上的輸出入墊（Input and Output Pads) 和與此墊相連的電晶體閘極之間，其設計爲可以導通或是承g 座遺J藉此提供一電性的接地，或是接到電源供應器的外殼 ____ 1 _ 本紙張尺度適用中國國家樣率（CNS ) A4規格（210X297公釐） ----^--1 裝---‘---訂-----^ 線 (讀先聞讀背面之注意事項再填寫本頁) 經濟部中央樣準局貝工消费合作社印策 Α7 Β7 1414TWF.DOC/006 五、發明説明（）） 上.。 習知提供有數種保護電路可避免ESD的損壞，請參閱第1A 圖和第1B圖，其所繪示的爲一種習知的MOS ESD保護元件，第 1A圖繪示的爲MOS ESD保護元件的俯視示意圖，第1B圖繪示的 爲MOS ESD保護元件沿著虛線AA’的側視示意圖，兩圖中相同 的部份係以相同的編號標示之，而有些部俯視圖看不到，只 有側視圖才看得到，相反的，有些部分側視圖看不到，只有俯 視圖才看得到。首先，一半導體基底10，其上有一周邊區 (Peripheral Region)，於此周邊區上，利用化學氣相沉積 法（Chemical Vapor Deposition ;CVD)或是熱成長方式， 形成一薄氧化層（Oxide Layer)，然後在薄氧化層上，形成一 多晶矽層（Polysilicon Layer) 〇將離子，例如磷離子，植 入（Implantation)多晶矽層中，或以擴散方式將磷離子滲入 多晶矽層中，以增加其導電性。接著，用傳統微影 (Photolithography)和蝕刻（Etching)的製程，在多晶砂層 和薄氧化層上形成圖案，用以形成一閘極，包括一閘極氧化層 12和一多晶矽閘il4，之後在半導體基底10上多晶矽閘極14 的周圍部分，摻入（Doping)離子，形成源極/汲極區16，到此 所述的方法，與一般形成一M0S胞的方法相同。而若要獲得一 NMOS ESD的保護元件，N型的離子，例如磷離子，可以被植入 源極/汲極區16，於是形成一ESD保護植入區18(Protection Implantation Regions)，在第1B圖之剖面圖中則爲區域 Π(用虛線表示）；另一方面，p型的離子，例如硼離子，亦可 以被植入源極/汲極區16中，形成一ESD保護植入區18(即區域 本紙張尺度適用中國困家橾準（CNS ) A4規格（210x297公釐） I--------ζ，‘装------.I 訂-----c..^ (請先閎讀背面之注$項再填寫本頁) 經濟部中央標準局貝工消費合作社印袋 A7 B7 I414TWF.DOC/006 五、發明説明（) 17)，就形成所謂的PMOS ESD的保護元件》 然而，習知的此種MOS ESD的保護元件有些缺點，由於在 源極/汲極區之間會有橫向的離子擴散，因此會產生短通道效 應（Short Channel Effect)，而且，由於電容的增加和兀件 的覆載(Load)增加，則電路的操作速度會降低。 因此，本發明的主要目的是提供一種半導體元件及其製造 方法，特別是關於一種MOS ESD保護元件，可以克服前述的問 題，減少習知所產生的短通道效應。 爲達上述目的，本發明提供一種半導體元件及其製造方 法，包括下列結構：一半導體基底，在此半導體基底之上有一 氧化層，在氧化層上有一閘極，以及二個源極/汲極區，其中 一個源極/汲極區爲一濃摻雜的源極/汲極區。 爲達上述目的，本發明提供一種半導體元件及其製造方 法，包括下列步驟：提供一半導體基底，在半導體基底上有一 周邊區；然後在周邊區上形成一閘極，接著，在周邊區上閘極 的兩側，形成二個源極/汲極區，以及進行雜質的摻雜，使得 該二個源極/汲極fc的其中一個源極/汲極區，成爲一濃摻雜的 源極/汲極區。 爲讓本發明之上述和其他目的、特徵、和優點能更明顯易 懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 圖式之簡單說明： 第1A圖繪示的爲習知MOS ESD保護元件的俯視示意圖； 第1B圖繪示的爲第1A圖中習知MOS ESD保護元件沿著AA’ _*___ — ^ _____ _ -------；—裝---l· (请先聞讀背面之注$項再填寫本頁) —.I訂-----C成 經濟部中央標準局貞工消费合作社印製 本紙張尺度逋用中國國家揉率< CNS ) A4規格（210X297公漦) A7 14I4TWF.DOC/006 五、發明説明（/ ) 虛線的側視示意圖； 第2A圖繪示根據本發明之一較佳實施例，一種MOS ESD保 護元件的俯視示意圖；以及 第2B圖繪示根據本發明之一較佳實施例，一種第2A圖p MOS ESD保護元件沿箸BB’虛線的側視示意圖。 實施例 本發明提供一種可避免ESD的損壞的保護電路，請參閱k 2A圖和第2B圖，其繪示根據本發明之一較佳實施例，爲一種 MOS ESD保護元件，第2A圖繪示的爲MOS ESD保護元件的俯視 示意圖，第2B圖繪示的爲第2A圖中MOS ESD保護元件沿著虛線 BB’的側視示意圖，兩圖中相同的部份係以相同的編號標示 之，而有些部分俯視圖看不到，只有側視圖才看得到，相反 的，有些部分側視圖看不到，只有俯視圖才看得到。 經濟部中央揉準局貝工消费合作社印製 (請先閲讀背面之注意事項再填寫本頁) 首先，一半導體基底20，其上有一周邊區，於此周邊區 上，利用化學氣相沉積法（CVD)或是熱成長方式，形成一薄氧 化層，然後在薄氧化層上，形成一多晶矽層。將離子，例如磷 離子，植入多晶#層中·，或以擴散方式將磷離子滲入多晶矽層 中，用以增加其導電性。接著，用傳統微影和蝕刻的製程，在 多晶矽層和薄氧化層上形成圖案，用以形成一閘極，包括一閘 極氧化層22和一多晶砂閘極24，之後在半導體基底20上多晶 矽閘極24的周圍部分，摻入離子，形成源極/汲極區26，若在 源極/汲極區26中，摻入N型的離子，即可形成NMOS元件；而若 在源極/汲極區26中，摻入P型的離子，即可形成PMOS元件，此 —在周邊區上所形成的結構，與傳統形成MOS元件的步驟是一 _—— ____6_____ 本紙張尺度適用中國國家標準（CNS) Α4规格（210Χ297公釐） 387138 A7 B7 1414TWF.DOC/006 五、發明説明（t) 1=._ I —! - 1= 11 I ---1 I (請先閲讀背面之注意事項再填寫本頁) 樣的。若是要形成一MOS ESD的保護元件，則需進一步包括下 列的植入步驟’例如若要獲得一NM0S ESD的保護元件，可以 在源極/汲極區26其中之一區中及其周緣，再次摻入N型的離 子’例如磷離子’若要獲得一PM〇S ESD的保護元件，則可以 在源極/汲極區26其中之一區中及其周緣，再次摻入p型的離 子，例如硼離子。 線 在此MOS ESD的保護元件上，本發明是在源極/汲極區26 之摻入的步驟上作改變，若要獲得一NMOS ESD的保護元件， 可以在源極/汲極區26的其中之一個源極/汲極區中及其周緣， 較佳的是在汲極區中，摻入N型的離子，例如磷離子，形成一N 型ESD保護植入區28。因此，本發明的此N型ESD保護植入區28 爲N型離子濃摻雜區（Heavily Doped Region);另一方面，P 型的離子，例如硼磷離子，亦可以被植入源極/汲極區26其中 之一及其周緣，較佳的是在汲極區中，摻入P型的離子，形成 一P型ESD保護植入區，就形成本發明的PMOS ESD的保護元 件。 經濟部中央標準局員工消費合作社印製 綜上所述，：ί發明之優點在於，進行離子植入的步驟，形 成Ν型ESD保護植入區28時，不需要額外的罩幕（Mask)，也就 是說，本發明所需的製程步驟與習知是一樣的，但是本發明卻 可具有更多的好處，因爲其源極/汲極區中離子的擴散只來自 一個方向，因此可以減少短通道效應，進而克服元件尺寸縮小 的阻礙，另一方面，由於源極區的接合電容降低，因此，元件 的操作速度可以增加。 雖然本發明已以一較佳實施例揭露如上’然其並非用以限 ______2______ — 本紙張尺度適用中國國家標率（CNS ) A4規格（210X 297公釐> 387138 A? 1414TWF.DOC/006 B7 五、發明説明（^ ) 定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍 內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後 附之申請專利範圍所界定者爲準。 -----I:---f、-裝---^--^丨訂-----^ 線 (請先聞讀背面之注意事項再填寫本頁) · 經濟部中央標準局貝工消费合作社印製 本紙張尺度適用中國囷家標率（CNS ) _A4規格（210X297公釐）A7 B7 1414TWF.DOC / 006 V. Description of the Invention (/) The present invention relates to an electrostatic discharge (El ec t ros t at i e-Discharge; ESD) protection element and a method for manufacturing the same, and in particular, to a kind of ESD protection element doped with a source / drain region. The input signal of Metal-Oxide-Semiconductor (M0S) integrated circuits (Integrated Circuits; 1C) is supplied to the gate of the m0s transistor. If the voltage supplied to the gate is too high, the gate oxide layer (Gate Oxide) will break down (Break Down). The dielectric breakdown strength of silicon dioxide is known to be about 10X 106V / cm. For example, if there is a gate oxide layer of about 15nm thick, it will not be able to withstand greater than about 15V. The voltage collapses. Although the operating voltage of the integrated circuit is about 5V, it does not cause a crash. However, when it is operated manually or mechanically, some input signals higher than this voltage may be entered. In the circuit. This kind of bad voltage source usually comes from triboelectricity, which is the static electricity generated by the friction between two objects. For example, if a person walks through a room or gently takes a 1C out of a plastic package, he will Hundreds to thousands of volts are generated. If such a high voltage is accidentally passed to the pins (Pms) of the 1C package, a breakdown phenomenon will immediately occur and the component will be damaged, so that the oxide layer 4 method will normally participate in the operation of the component again, resulting in the failure of the component (Device Failure). The gate of M0S is damaged. All the pins of MOS 1C have a circuit to provide protection. Usually, this protection circuit is also applied to the manufacturing of very large scale integration (VLSI) components. This type of protection circuit Are placed between the input and output pads on the chip and the transistor gates connected to this pad, and are designed to be conductive or to support the module J to provide an electrical ground, or It is the case connected to the power supply ____ 1 _ This paper size is applicable to China National Sample Rate (CNS) A4 specification (210X297 mm) ---- ^-1 Packing ---'--- Order --- -^ Line (read the notes on the back and read this page first, then fill out this page) Imprint A7 Β7 1414TWF.DOC / 006 The Central Samples Bureau of the Ministry of Economic Affairs, Pakong Consumer Cooperative, Ltd. There are several protection circuits that can be used to avoid ESD damage. Please refer to Figure 1A and Figure 1B, which show a conventional MOS ESD protection element, and Figure 1A shows a MOS ESD protection element. A schematic plan view. Figure 1B shows a schematic side view of the MOS ESD protection element along the dotted line AA '. The same parts in the two figures are labeled with the same numbers, and some parts are not visible in the top view, only the side view. Can only be seen, on the contrary, some parts can not be seen from the side view, only from the top view. First, a semiconductor substrate 10 has a peripheral region thereon. A thin oxide layer is formed on the peripheral region by using a chemical vapor deposition method (CVD) or thermal growth. ), And then form a polysilicon layer on the thin oxide layer 〇 implant ions, such as phosphorus ions, into the polycrystalline silicon layer, or diffuse the phosphorus ions into the polycrystalline silicon layer to increase its conductivity Sex. Next, a conventional photolithography and etching process is used to form a pattern on the polycrystalline sand layer and the thin oxide layer to form a gate, including a gate oxide layer 12 and a polycrystalline silicon gate il4. In the surrounding portion of the polycrystalline silicon gate 14 on the semiconductor substrate 10, doping ions are formed to form the source / drain region 16. The method described so far is the same as the general method of forming a MOS cell. To obtain an NMOS ESD protection element, N-type ions, such as phosphorus ions, can be implanted into the source / drain region 16, and an ESD protection implantation region 18 is formed. In Section 1B The cross-section of the figure is the area Π (represented by a dotted line); on the other hand, p-type ions, such as boron ions, can also be implanted into the source / drain region 16 to form an ESD-protected implanted region 18 (That is, the size of the paper in this region is applicable to China Standards for Standardization (CNS) A4 (210x297 mm) I -------- ζ, 'installation ------. I order ----- c .. ^ (Please read the note on the back before filling in this page) Printed bag A7 B7 I414TWF.DOC / 006 by the Central Bureau of Standards of the Ministry of Economy Shellfish Consumer Cooperative Fifth, the description of the invention () 17), so called PMOS ESD protection elements "However, the conventional MOS ESD protection elements have some disadvantages. Because there is lateral ion diffusion between the source / drain regions, a short channel effect occurs, and As the capacitance increases and the load of the component increases, the operating speed of the circuit will decrease. Therefore, the main object of the present invention is to provide a semiconductor device and a manufacturing method thereof, and more particularly, to a MOS ESD protection device, which can overcome the aforementioned problems and reduce the short-channel effect caused by the conventional method. To achieve the above object, the present invention provides a semiconductor device and a manufacturing method thereof, including the following structures: a semiconductor substrate, an oxide layer on the semiconductor substrate, a gate electrode on the oxide layer, and two source / drain electrodes Region, one of the source / drain regions is a heavily doped source / drain region. To achieve the above object, the present invention provides a semiconductor element and a method for manufacturing the same, including the following steps: providing a semiconductor substrate with a peripheral region on the semiconductor substrate; and then forming a gate on the peripheral region, and then gate on the peripheral region On both sides of the electrode, two source / drain regions are formed, and impurity doping is performed, so that one of the source / drain regions of the two source / drain fc becomes a heavily doped source. / Drain region. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1A Shown is a schematic plan view of a conventional MOS ESD protection element; FIG. 1B shows a conventional MOS ESD protection element in FIG. 1A along AA '_ * ___ — ^ _____ _ ----------; —Installation—-l · (please read the note $ on the back before filling out this page) —.I order ----- C Printed by the Chenggong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs and printed on paper in China National kneading rate < CNS) A4 specification (210X297 gong) A7 14I4TWF.DOC / 006 V. Description of the invention (/) Side view of dotted line; Figure 2A shows a MOS according to a preferred embodiment of the present invention A schematic top view of the ESD protection element; and FIG. 2B illustrates a schematic side view of the pMOS ESD protection element of FIG. 2A along the dashed line BB ′ according to a preferred embodiment of the present invention. Embodiments The present invention provides a protection circuit capable of preventing ESD damage. Please refer to FIG. 2A and FIG. 2B, which show a preferred embodiment of the present invention, which is a MOS ESD protection element. FIG. 2A shows The top view of the MOS ESD protection element is shown in Figure 2B. The side view of the MOS ESD protection element in Figure 2A along the dashed line BB 'is shown. The same parts in the two figures are marked with the same numbers. While some parts cannot be seen from the top view, only the side view can be seen. Conversely, some parts cannot be seen from the side view, only from the top view. Printed by the Central Government Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative (please read the precautions on the back before filling out this page). First, a semiconductor substrate 20 with a peripheral area on it. On this peripheral area, chemical vapor deposition is used. (CVD) or thermal growth, a thin oxide layer is formed, and then a polycrystalline silicon layer is formed on the thin oxide layer. Ions, such as phosphorus ions, are implanted into the polycrystalline silicon layer, or phosphorus ions are diffused into the polycrystalline silicon layer to increase its conductivity. Next, using a conventional lithography and etching process, a pattern is formed on the polycrystalline silicon layer and the thin oxide layer to form a gate, including a gate oxide layer 22 and a polycrystalline sand gate 24, and then on the semiconductor substrate 20 Around the upper polysilicon gate 24, ions are doped to form a source / drain region 26. If N-type ions are doped in the source / drain region 26, an NMOS element can be formed; In the electrode / drain region 26, P-type ions can be doped to form a PMOS device. This—the structure formed on the peripheral area and the traditional step for forming a MOS device—is the same as the one described in this paper. __6_____ This paper is applicable to China National Standard (CNS) A4 Specification (210 × 297 mm) 387138 A7 B7 1414TWF.DOC / 006 V. Description of the Invention (t) 1 = ._ I —!-1 = 11 I --- 1 I (Please read the Please fill out this page again). If it is to form a MOS ESD protection element, it needs to further include the following implantation steps. For example, to obtain a NMOS ESD protection element, it can be in one of the source / drain regions 26 and its periphery, again N-type ions such as phosphorus ions are doped to obtain a PMOS ESD protection element, and p-type ions can be doped again in one of the source / drain regions 26 and its periphery. For example boron ion. On the protection element of the MOS ESD, the present invention changes the step of incorporating the source / drain region 26. To obtain an NMOS ESD protection element, the One of the source / drain regions and its periphery is preferably doped with N-type ions, such as phosphorus ions, in the drain region to form an N-type ESD protection implanted region 28. Therefore, the N-type ESD protection implanted region 28 of the present invention is an N-type ion doped region (Heavily Doped Region); on the other hand, P-type ions, such as boron phosphorus ions, can also be implanted into the source / One of the drain regions 26 and its periphery is preferably doped with P-type ions in the drain region to form a P-type ESD protection implanted region to form the PMOS ESD protection element of the present invention. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. In summary: The advantage of the invention is that the steps of ion implantation to form the N-type ESD protection implanted area 28 do not require an additional mask. That is to say, the process steps required by the present invention are the same as the conventional ones, but the present invention can have more benefits because the diffusion of ions in the source / drain region comes from only one direction, so the short The channel effect overcomes the obstacle of the reduction in the size of the device. On the other hand, since the junction capacitance in the source region is reduced, the operation speed of the device can be increased. Although the present invention has been disclosed above in a preferred embodiment, it is not intended to limit ______2______ — this paper size is applicable to China National Standard (CNS) A4 specifications (210X 297 mm > 387138 A? 1414TWF.DOC / 006 B7 V. Explanation of the invention (^) Anyone who is familiar with this technology can make some modifications and retouching without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be regarded as the attached patent. The scope is subject to definition. ----- I: --- f, -install --- ^-^ 丨 order ----- ^ line (please read the precautions on the back before filling this page ) · The paper standard printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, is suitable for the Chinese standard (CNS) _A4 specification (210X297 mm)