TW217461B - - Google Patents

Info

Publication number
TW217461B
TW217461B TW082103072A TW82103072A TW217461B TW 217461 B TW217461 B TW 217461B TW 082103072 A TW082103072 A TW 082103072A TW 82103072 A TW82103072 A TW 82103072A TW 217461 B TW217461 B TW 217461B
Authority
TW
Taiwan
Application number
TW082103072A
Other languages
Chinese (zh)
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of TW217461B publication Critical patent/TW217461B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0191Manufacturing their doped wells
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401Combinations of FETs or IGBTs with BJTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85Complementary IGFETs, e.g. CMOS
    • H10D84/859Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub

Landscapes

  • Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
TW082103072A 1991-12-30 1993-04-22 TW217461B (enExample)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/814,547 US5252501A (en) 1991-12-30 1991-12-30 Self-aligned single-mask CMOS/BiCMOS twin-well formation with flat surface topography

Publications (1)

Publication Number Publication Date
TW217461B true TW217461B (enExample) 1993-12-11

Family

ID=25215385

Family Applications (1)

Application Number Title Priority Date Filing Date
TW082103072A TW217461B (enExample) 1991-12-30 1993-04-22

Country Status (4)

Country Link
US (1) US5252501A (enExample)
EP (1) EP0550021A3 (enExample)
JP (1) JPH06112420A (enExample)
TW (1) TW217461B (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0897163A (ja) 1994-07-28 1996-04-12 Hitachi Ltd 半導体ウエハの製造方法、半導体ウエハ、半導体集積回路装置の製造方法および半導体集積回路装置
US5583062A (en) * 1995-06-07 1996-12-10 Lsi Logic Corporation Self-aligned twin well process having a SiO2 -polysilicon-SiO2 barrier mask
US5770492A (en) * 1995-06-07 1998-06-23 Lsi Logic Corporation Self-aligned twin well process
US5763302A (en) * 1995-06-07 1998-06-09 Lsi Logic Corporation Self-aligned twin well process
US5670393A (en) * 1995-07-12 1997-09-23 Lsi Logic Corporation Method of making combined metal oxide semiconductor and junction field effect transistor device
KR0146080B1 (ko) * 1995-07-26 1998-08-01 문정환 반도체 소자의 트윈 웰 형성방법
US5547894A (en) * 1995-12-21 1996-08-20 International Business Machines Corporation CMOS processing with low and high-current FETs
US5670395A (en) * 1996-04-29 1997-09-23 Chartered Semiconductor Manufacturing Pte. Ltd. Process for self-aligned twin wells without N-well and P-well height difference
DE59813593D1 (de) * 1997-04-29 2006-07-27 Infineon Technologies Ag Verfahren zur Herstellung einer CMOS-Schaltungsanordnung
US5956583A (en) * 1997-06-30 1999-09-21 Fuller; Robert T. Method for forming complementary wells and self-aligned trench with a single mask
US6307230B1 (en) * 1999-01-05 2001-10-23 Texas Instruments Incorporated Transistor having an improved sidewall gate structure and method of construction
US6235568B1 (en) * 1999-01-22 2001-05-22 Intel Corporation Semiconductor device having deposited silicon regions and a method of fabrication
US6207538B1 (en) 1999-12-28 2001-03-27 Taiwan Semiconductor Manufacturing Company Method for forming n and p wells in a semiconductor substrate using a single masking step
DE10052680C2 (de) * 2000-10-24 2002-10-24 Advanced Micro Devices Inc Verfahren zum Einstellen einer Form einer auf einem Substrat gebildeten Oxidschicht
US6586296B1 (en) * 2001-04-30 2003-07-01 Cypress Semiconductor Corp. Method of doping wells, channels, and gates of dual gate CMOS technology with reduced number of masks
JP4982979B2 (ja) * 2005-07-19 2012-07-25 日産自動車株式会社 半導体装置の製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4050965A (en) * 1975-10-21 1977-09-27 The United States Of America As Represented By The Secretary Of The Air Force Simultaneous fabrication of CMOS transistors and bipolar devices
US4424621A (en) * 1981-12-30 1984-01-10 International Business Machines Corporation Method to fabricate stud structure for self-aligned metallization
US4527325A (en) * 1983-12-23 1985-07-09 International Business Machines Corporation Process for fabricating semiconductor devices utilizing a protective film during high temperature annealing
US4558508A (en) * 1984-10-15 1985-12-17 International Business Machines Corporation Process of making dual well CMOS semiconductor structure with aligned field-dopings using single masking step
JPH01161752A (ja) * 1987-12-18 1989-06-26 Toshiba Corp 半導体装置製造方法
US5070029A (en) * 1989-10-30 1991-12-03 Motorola, Inc. Semiconductor process using selective deposition
US5132241A (en) * 1991-04-15 1992-07-21 Industrial Technology Research Institute Method of manufacturing minimum counterdoping in twin well process

Also Published As

Publication number Publication date
EP0550021A2 (en) 1993-07-07
EP0550021A3 (en) 1996-12-27
US5252501A (en) 1993-10-12
JPH06112420A (ja) 1994-04-22

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