TW202428512A - Method for processing a polycrystalline silicon carbide wafer - Google Patents

Abstract

The invention relates to a method for processing a polycrystalline silicon carbide wafer, comprising: characterizing (R2) the surface condition of a front face of the polycrystalline silicon carbide wafer; when the characterized surface condition does not meet a predetermined specification for the bonding (C) of the polycrystalline silicon carbide wafer to a single-crystal silicon carbide substrate with the front face at the bonding interface, correcting (R3) the surface condition of the front face by removing material from the front face of the polycrystalline silicon carbide wafer.

Description

Method for processing polycrystalline silicon carbide wafers

The present invention relates to a polycrystalline silicon carbide wafer as a support for a single-crystal silicon carbide thin layer.

Silicon carbide (SiC) is increasingly being used in power electronics applications, especially to meet the growing demand for electronic products such as electric vehicles. Single-crystal SiC-based power devices and integrated power systems can actually manage higher power densities than conventional silicon devices, and do so with a smaller active area.

Despite this, substrates made of single-crystal silicon carbide for use in the microelectronics industry remain expensive and difficult to supply in large sizes. Therefore, it is advantageous to employ layer transfer solutions in order to produce composite structures, which typically comprise a thin layer made of single-crystal silicon carbide on a lower-cost support substrate. One well-known thin layer transfer solution is the Smart Cut™ process. This process can be used, for example, to produce a composite structure comprising a thin layer made of single-crystal silicon carbide, which has been taken from a donor substrate made of single-crystal silicon carbide (m-SiC) and is in contact with a recipient substrate made of polycrystalline silicon carbide (p-SiC).

The acceptor substrate is a p-SiC wafer, which is taken from a relatively thick p-SiC sheet (e.g., with a thickness of 0.6 to 3 mm). The p-SiC sheet is formed by deposition of the p-SiC on a growth substrate (e.g., a graphite substrate), typically by chemical vapor deposition at a temperature between 1100°C and 1400°C. After removal of the growth substrate, the p-SiC sheet is subjected to a process for forming one or more wafers (wafer slicing process), which includes various cleaning, etching, grinding and polishing stages, so that one or more p-SiC wafers of the desired form (especially bevel angles) and the desired thickness are obtained. Slicing may also be performed during this process, especially when several wafers have to be produced from the same sheet. According to SEMI standards, the thickness of the polycrystalline SiC wafers produced in this way is 350 μm +/- 25 μm (for a substrate with a diameter of 150 mm) or 500 μm +/- 25 μm (for a substrate with a diameter of 200 mm).

The SmartCut™ process for silicon carbide requires a specific surface preparation before the donor substrate (mSiC) and the acceptor substrate (pSiC) can be bonded together, which can be done using techniques such as ADB (Atomic Diffusion Bonding) or SAB (Surface Activation Bonding). This surface preparation aims to produce a specific surface condition in the spatial frequency range of 5x5μm to 150x150μm, characterized by its roughness.

However, this surface preparation does not seem to be perfectly repeatable, since a large number of p-SiC wafers prepared in this way are accompanied by the risk of incomplete transfer of the m-SiC layer during the Smart Cut™ process. In practice, therefore, p-SiC wafers prepared in this way are sorted in advance in order to exclude those that do not meet the required roughness specifications to comply with the bonding process. But it turns out that the rejection rate is high, the cost of p-SiC wafers is too high and their production requires a lot of energy.

One purpose of the present invention is to reduce such defect rate so as to reduce the cost of the Smart Cut ^™ process applied to silicon carbide and its impact on the environment.

To this end, the present invention provides a method for processing a polycrystalline silicon carbide wafer, which includes the following steps: - describing the surface roughness characteristics of the front side of the polycrystalline silicon carbide wafer; - when the described surface roughness characteristics meet the predetermined specifications for bonding the polycrystalline silicon carbide wafer to a single crystal silicon carbide substrate through its front side at the bonding interface: performing the bonding; - when the described surface roughness characteristics do not meet the predetermined specifications, reducing the surface roughness by removing material with a thickness between 3 µm and 10 µm from the front side of the polycrystalline silicon carbide wafer; repeating the characteristic description of the surface roughness of the front side of the polycrystalline silicon carbide wafer; and performing the bonding when the surface roughness characteristics after the repeated characteristic description steps meet the predetermined specifications.

The predetermined specifications correspond to predetermined standards, which, when met, result in a p-SiC wafer fully bonded to the m-SiC substrate through its front side at the bonding interface. The m-SiC substrate is considered fully bonded when it is bonded to the entire front side, but excluding an outer ring with a width of less than 10 mm, preferably less than 6 mm, and more preferably less than 5 mm at each point. The bonding step and the material removal step are the solutions adopted when the surface roughness characteristics of the surfaces to be bonded meet or do not meet the description, respectively. Therefore, according to the method of the invention, it is possible to identify polycrystalline silicon carbide wafers with a risk of incompletely transferred single-crystalline silicon carbide layers from a batch of wafers originating from the same wafer slicing process, so that these wafers can be corrected until the surface condition of the wafer allows satisfactory bonding, so as to avoid judging a large number of wafers as defective.

Some preferred but non-limiting aspects of the method are as follows: - Material removal is performed only on the front side of the polycrystalline silicon carbide wafer; - Removing material from the front side involves grinding; - Grinding includes a sequence of coarse grinding and fine grinding; - Coarse grinding is performed with a grinding wheel having an abrasive grit of less than 5000 mesh; - The thickness of material removed by coarse grinding is less than 10 µm; - Fine grinding is performed with a grinding wheel having an abrasive grit of greater than 5000 mesh; - The thickness of material removed by fine grinding is less than 3 µm; -- Removing material from the front side further involves polishing the front side after grinding; - Polishing is chemical polishing or chemical mechanical polishing; - The thickness of material removed by polishing is less than 1 µm; - The method further comprises forming a polycrystalline silicon carbide wafer from a polycrystalline silicon carbide sheet in advance, the said prior formation involves double-sided thinning (wafer slicing) of the polycrystalline silicon carbide sheet, the said double-sided wafer slicing sequentially comprising, for example, a coarse grinding, a rough grinding and a fine grinding; - The prior formation further comprises the steps of sawing, etching and/or polishing the back and/or front of the polycrystalline silicon carbide sheet; - Characterization of the surface condition of the front of the polycrystalline silicon carbide wafer involves a light-scattering haze measurement; - It comprises, when the surface roughness characteristics after repeated characterization steps do not meet the predetermined specifications, further reducing the surface roughness of the front by material removal; -The initial thickness of the polycrystalline SiC wafer is within an acceptable thickness range, and after the surface roughness of the front side has been reduced, the final thickness of the polycrystalline SiC wafer is within the same acceptable thickness range.

The present invention extends to a method for making a batch of polycrystalline silicon carbide wafers, each of which has a final thickness within an acceptable thickness range, the method comprising: - providing a group of polycrystalline silicon carbide wafers, each of which has an initial thickness within the same acceptable thickness range; - for each of the group of polycrystalline silicon carbide wafers, sequentially performing the following: ˙ describing the surface roughness characteristics of the front side of the wafer; ˙ when the described surface roughness characteristics meet predetermined specifications for bonding the wafer to a single crystal silicon carbide substrate via its front side at a bonding interface, adding the wafer to the batch; ˙ when the described surface roughness characteristics do not meet the predetermined specifications: removing a layer of polycrystalline silicon carbide wafer having a thickness of 3 µm to 10 µm from the front side of the polycrystalline silicon carbide wafer; µm to reduce the surface roughness; repeating the characterization of the surface roughness of the front side of the polycrystalline silicon carbide wafer; and adding the wafer to the batch when the surface roughness characteristics after the repeated characterization steps meet the predetermined specifications.

Finally, the invention extends to a method for making a batch of multi-layer structures, each multi-layer structure comprising a single crystal silicon carbide thin layer deposited on a polycrystalline silicon carbide wafer, the method comprising, for each polycrystalline silicon carbide wafer in the batch of polycrystalline silicon carbide wafers formed as described above, bonding a single crystal silicon carbide substrate to the front side of the polycrystalline silicon carbide wafer.

The invention relates to a method for processing a p-SiC wafer intended to serve as a support for a thin layer of m-SiC. The method may comprise a preliminary step of forming the wafer from a p-SiC plate. To this end, the p-SiC plate is subjected to a wafering process. The process involves in particular a double-sided thinning of the plate and a possible flattening of the plate in order to improve any curvature it may exhibit. The thinning may be carried out by grinding. Such grinding may comprise, in sequence, coarse grinding (which reduces the thickness to about 400 µm), rough grinding (which reduces the thickness to about 360 µm), and fine grinding (which removes the last few microns of material). The different grinding operations use different grinding wheel grit sizes, which become smaller and smaller through the successive grinding operations. Various grinding operations are performed on both the front and back sides of the polycrystalline silicon carbide sheets.

In addition to grinding, the wafer slicing process may involve one or more steps of cleaning, etching and/or polishing the front and/or back sides of the polycrystalline silicon carbide sheet. For example, polishing involves chemical mechanical polishing. Polishing reduces the surface roughness of the polycrystalline silicon carbide sheet and/or improves the flatness of the polycrystalline silicon carbide sheet. Cleaning can remove contaminants.

Finally, the wafer slicing process may involve sawing, especially when several polycrystalline SiC wafers are to be produced from the same polycrystalline SiC sheet.

For example, the preparation of p-SiC sheets on graphite by CVD means that a step of separating the graphite is performed before double-sided thinning of the p-SiC sheet.

The initial thickness of the polycrystalline silicon carbide wafer derived from the p-SiC sheet is preferably within an interval of acceptable thicknesses or a target thickness interval, which interval is selected so that once the surface roughness of the front side of the polycrystalline silicon carbide wafer is reduced by one or more sequential material removals as described below, the final thickness of the p-SiC wafer is still within the same interval of acceptable values, the initial thickness and final thickness being the average thickness of the p-SiC wafer before and after all material removal, respectively.

More specifically, the initial thickness and the final thickness of the polycrystalline silicon carbide wafer fall within intervals referred to as the initial thickness distribution and the final thickness distribution of the polycrystalline silicon carbide wafer, respectively. The initial thickness distribution of the polycrystalline silicon carbide wafer is selected to be within the acceptable thickness interval, and the median value of the initial thickness distribution is selected to be greater than the median value of the acceptable thickness interval, so that the final thickness distribution of the polycrystalline silicon carbide wafer is also within the acceptable thickness interval, wherein the median value of each interval means the average value of the lower end point and the upper end point of the interval. For example, the median value of the initial thickness distribution is 15 μm greater than the median value of the acceptable thickness interval.

Such an embodiment may advantageously result in a polycrystalline silicon carbide wafer that meets a thickness standard despite one or more sequential reductions in surface roughness through material removal. The thickness standard may correspond to an acceptable thickness range for semiconductor industry equipment. Alternatively or in addition, the thickness standard may meet specifications generally adopted in the semiconductor industry or be clearly defined by a semiconductor industry standard.

For example, the acceptable thickness range is the range defined by the SEMI standard for a p-SiC sheet with a diameter of 150 mm, which is 350 μm +/- 25 μm. As a further example, the acceptable thickness range is the range commonly adopted by most of the semiconductor industry for a p-SiC sheet with a diameter of 200 mm, which is 500 µm +/- 25 µm.

In this example, the initial thickness of the wafers from the 150 mm diameter p-SiC sheets is within an initial thickness distribution towards 365 µm, e.g. 365 µm +/- 10 µm, and the initial thickness of the wafers from the 200 mm diameter p-SiC sheets is within an initial thickness distribution towards 515 µm, e.g. 515 µm +/- 10 µm. This embodiment allows the final thickness of a 150 mm diameter p-SiC wafer to be maintained within a final thickness distribution range of 350 µm +/- 25 µm, thereby complying with SEMI standards, and allows the final thickness of a 200 mm diameter p-SiC wafer to be maintained within a final thickness distribution range of 500 µm +/- 25 µm, thereby complying with specifications generally adopted in the semiconductor industry, even if one or more operations of modifying the surface condition of the p-SiC wafer are performed according to the present invention described below to ensure a successful result of the Smart Cut™ process after the wafer has been bonded to an m-SiC substrate.

As shown in FIG. 1 , the method according to the invention may include a step R1 of supplying a p-SiC wafer. The method according to the invention further includes a step of characterizing the surface condition of the front side of the p-SiC wafer, typically characterizing the roughness of this front side (indicated by R2 in FIG. 1 ). This characterization may in particular involve light scattering haze measurement. Such haze measurement allows a characterization of the surface roughness of the front side of the p-SiC wafer. This haze is derived from a method using the optical reflectivity properties of the surface to be described, and due to the microroughness of the surface, the haze corresponds to the optical signal scattered by the surface. For example, the haze measurement can be performed using a KLA-Tencor Surfscan SP1 or SPA2 inspection system, or the haze measurement can be performed using a Lasertec SICA88 inspection system.

The method according to the invention then comprises a step of determining whether the described surface roughness characteristics meet predetermined specifications.

In certain embodiments, the determined specifications are predetermined standards that, when met, are sufficient to obtain complete bonding of the p-SiC wafer to the m-SiC substrate through its front side at the bonding interface. The m-SiC substrate is considered to be fully bonded when it is bonded to the entire front side, but excluding an outer peripheral ring whose width is less than 10 mm, preferably less than 6 mm and more preferably less than 5 mm at all points. In fact, it should be remembered that the bonding of the m-SiC substrate and the subsequent transfer of the m-SiC thin layer will occur over most of the surface of the p-SiC wafer, since the substrate usually has a bevel around its edge, but not in a peripheral ring extending from the edge of the wafer, and the width of the peripheral ring depends in particular on the geometry of the bevel.

The predetermined specification may involve an indirect measurement of the surface roughness. In a possible embodiment where the characterization of the surface roughness involves a haze measurement, the predetermined specification may be that the measured haze level must be below a predetermined threshold, in other words below a previously determined haze level limit, as a guarantee of successful bonding, in particular complete bonding as defined above.

If the surface roughness characterization complies with the predetermined specifications, the p-SiC wafer is then bonded (indicated by C in FIG. 1 ) via its front side at the bonding interface to a substrate made of m-SiC according to the method of the invention (e.g. using the ADB technique). The m-SiC substrate is then separated along the weakened plane previously formed therein by ion implantation according to the Smart Cut™ process in order to transfer the m-SiC thin layer to the p-SiC wafer, thereby forming a composite structure, this separation (indicated by D in FIG. 1 ) being achieved by thermal treatment, mechanical action or a combination of these. In this regard, FIG. 1 indicates the supply of the m-SiC substrate as D1 and uses D2 to indicate the ion implantation for weakening the m-SiC substrate. At the end of separation D and transfer of the m-SiC thin layer to the p-SiC wafer, the composite structure can be finished (indicated by F in FIG. 1 ) and the remaining m-SiC substrate can be recovered (R) for reuse.

If the surface condition of the front side of the p-SiC wafer does not meet the predetermined specifications, the method according to the present invention includes a step of removing material from the front side of the p-SiC wafer to correct the surface roughness of the front side of the p-SiC wafer (indicated by R3 in FIG. 1 ). Unlike previous double-sided thinning of p-SiC sheets, material removal can be performed only on the front side.

This material removal from the front side of the p-SiC wafer removes material thicknesses between 3 and 10 µm. It is achieved by grinding the front side. As mentioned before, the grinding of the p-SiC wafer is now only done on the front side, which is intended to be bonded to the m-SiC substrate. This grinding only on the front side is possible due to the double-sided grinding previously performed during the wafer slicing process, which balances the stresses between the front and back sides.

Grinding can include rough grinding and fine grinding in sequence. Rough grinding can be performed with a grinding wheel with an abrasive grain size of less than 5000 mesh. The thickness of material removed by rough grinding is preferably less than 10 µm, for example, 5 µm.

Fine grinding can be performed with a grinding wheel with a grit greater than 5000, for example between 8000 and 12000. The thickness of material removed by fine grinding is preferably less than 3 µm.

In one possible embodiment, the material removal from the front side of the p-SiC wafer may further involve polishing of the front side after grinding. Such polishing may be chemical polishing or chemical mechanical polishing. The thickness of the material removed by polishing is preferably less than 1 µm.

It should be understood that if a material thickness of, for example, 10 µm is removed in order to reduce the surface roughness of the front side to be bonded, the initial thickness of the p-SiC wafer is preferably greater than the thickness expected by the standard, for example 365 µm, so that after correction it still has the 350 µm thickness expected by the standard. Otherwise, several surface condition correction operations can be performed while maintaining the final thickness greater than the lower limit of 325 µm expected by the standard.

Specifically, after performing a first correction on the surface roughness of the front side to be bonded, the method of the present invention includes repeatedly performing a surface condition characteristic description of the front side, and when the surface condition characteristics after the repeated characteristic description meet the predetermined specifications, bonding is performed.

When the surface roughness characteristics after repeated characterization do not meet predetermined specifications, the method of the present invention may include further reducing the surface roughness of the front side by material removal.

The method according to the invention may include further reducing the surface roughness of the front side by one or more additional material removals, characterizing the surface condition before each additional removal. Preferably, each additional removal is of the same material as the first material removal. Each material removal removes 3 to 10 µm, and typically a first material removal and up to three additional material removals may be performed, while retaining a final thickness that complies with SEMI standards.

Furthermore, the method of the present invention can be repeated to process a set of wafers all originating from the same wafer slicing process and produce a batch of wafers, each of which is capable of being bonded to a single crystal silicon carbide substrate despite the lack of repeatability of the surface conditions of the wafers originating from the wafer slicing process. Therefore, the present invention can be extended to a method for making a batch of polycrystalline silicon carbide wafers, the method comprising: - providing a group of polycrystalline silicon carbide wafers; - for each of the group of polycrystalline silicon carbide wafers: ˙ describing the surface roughness characteristics of the front side of the wafer; ˙ when the described surface roughness characteristics meet the predetermined specifications for bonding the wafer to a single crystal silicon carbide substrate via its front side at the bonding interface, adding the wafer to the batch; ˙ when the described surface roughness characteristics do not meet the predetermined specifications, removing a 3 µm to 10 µm thick layer from the front side of the polycrystalline silicon carbide wafer; µm to reduce the surface roughness; repeat the characterization of the surface roughness of the front side of the polycrystalline silicon carbide wafer; and then, when the surface roughness characteristics after the repeated characterization steps meet the predetermined specifications, the wafer is added to the batch.

Batches of wafers formed in this way can then be individually bonded to a single crystal silicon carbide substrate.

The initial thickness of each polycrystalline silicon carbide wafer in the group of polycrystalline silicon carbide wafers is preferably within an acceptable thickness range, and the final thickness of each polycrystalline silicon carbide wafer after the surface roughness of each front side has been reduced is within the same acceptable thickness range.

In other words, the final thickness of each polycrystalline silicon carbide wafer derived from the polycrystalline silicon carbide wafer batch manufacturing method is within a target range, the initial thickness of each polycrystalline silicon carbide wafer in the group of polycrystalline silicon carbide wafers is within a narrow range of the target range, and the center value of the narrow range is higher than the center value of the target range.

As shown in the figure

Other aspects, objects, advantages and features of the present invention will become more apparent by reading the following detailed description of the preferred embodiments of the present invention, which is provided by way of non-limiting example and with reference to the accompanying drawings, in which FIG. 1 illustrates different steps of the Smart Cut ^TM process incorporating p-SiC wafer processing according to the present invention.

As shown in the picture.

Claims (19)

A method for processing a polycrystalline silicon carbide wafer, comprising the following steps: - describing the surface roughness characteristics (R2) of the front side of the polycrystalline silicon carbide wafer; - when the described surface roughness characteristics meet the predetermined specifications for bonding (C) the polycrystalline silicon carbide wafer to a single crystal silicon carbide substrate via its front side at the bonding interface: performing the bonding; - when the described surface roughness characteristics do not meet the predetermined specifications, reducing the surface roughness (R3) by removing material with a thickness between 3 µm and 10 µm from the front side of the polycrystalline silicon carbide wafer; repeating the description of the surface roughness characteristics of the front side of the polycrystalline silicon carbide wafer; and performing the bonding when the surface roughness characteristics after the repeated characterization steps meet the predetermined specifications. The method of claim 1, wherein the material removal is performed only on the front side of the polycrystalline silicon carbide wafer. A method as claimed in claim 1 or 2, wherein removing material from the front side involves grinding. A method as claimed in claim 3, wherein the grinding comprises a sequence of coarse grinding and fine grinding. A method as claimed in claim 4, wherein the rough grinding is performed using a grinding wheel with an abrasive grain size less than 5000 mesh. A method as claimed in claim 4 or 5, wherein the thickness of material removed by rough grinding is less than 10 µm. A method as claimed in any one of claims 4 to 6, wherein the fine grinding is performed using a grinding wheel with an abrasive grain size greater than 5000 mesh. A method as claimed in any one of claims 4 to 7, wherein the thickness of material removed by fine grinding is less than 3 µm. A method as in any one of claims 4 to 8, wherein removing material from the front side further involves polishing the front side after said grinding. The method of claim 9, wherein the polishing is chemical polishing or chemical mechanical polishing. The method of claim 9 or 10, wherein the thickness of material removed by polishing is less than 1 µm. A method as claimed in any one of claims 1 to 11, further comprising forming the polycrystalline silicon carbide wafer from a polycrystalline silicon carbide sheet in advance, wherein the prior formation involves double-sided thinning (wafer slicing) of the polycrystalline silicon carbide sheet, wherein the double-sided wafer slicing sequentially includes, for example, a coarse grinding, a rough grinding and a fine grinding. A method as claimed in claim 12, wherein the prior formation further comprises the steps of sawing, etching and/or polishing the back side and/or front side of the polycrystalline silicon carbide sheet. A method as in any one of claims 1 to 13, wherein characterizing the surface condition of the front side of the polycrystalline silicon carbide wafer involves a light scattering haze measurement. A method as claimed in any one of claims 1 to 14, comprising further reducing the surface roughness of the front side by removing material when the surface roughness characteristics after repeating the characterization step do not meet the predetermined specifications. A method as claimed in any one of claims 1 to 15, wherein the initial thickness of the polycrystalline silicon carbide wafer is within an acceptable thickness range, and after the surface roughness of the front side has been reduced, the final thickness of the polycrystalline silicon carbide wafer is within the same acceptable thickness range. A method for producing a batch of polycrystalline silicon carbide wafers, each of which has a final thickness within an acceptable thickness range, the method comprising: - providing a group of polycrystalline silicon carbide wafers, each of which has an initial thickness within the same acceptable thickness range; - for each of the group of polycrystalline silicon carbide wafers, sequentially performing the following: ˙ describing the surface roughness characteristics (R2) of the front side of the wafer; ˙ when the described surface roughness characteristics meet the predetermined specifications for bonding (C) the wafer to a single crystal silicon carbide substrate via its front side at the bonding interface, adding the wafer to the batch; ˙ when the described surface roughness characteristics do not meet the predetermined specifications: removing a layer of polycrystalline silicon carbide wafer having a thickness of 3 µm to 10 µm from the front side of the polycrystalline silicon carbide wafer; µm to reduce the surface roughness (R3); repeat the surface roughness characterization of the front side of the polycrystalline silicon carbide wafer; and when the surface roughness characteristics after the repeated characterization step meet the predetermined specifications, add the wafer to the batch. A method as claimed in claim 17, wherein the initial thickness of each silicon carbide wafer in the group of polycrystalline silicon carbide wafers is within a narrow range of the acceptable thickness range, and the center value of the narrow range is higher than the center value of the acceptable thickness range. A method for making a batch of multi-layer structures, each multi-layer structure comprising a single crystal silicon carbide thin layer deposited on a polycrystalline silicon carbide wafer, the method comprising bonding a single crystal silicon carbide substrate to the front side of each polycrystalline silicon carbide wafer in the batch of polycrystalline silicon carbide wafers formed in accordance with claim 18 or 19.