TW202427537A - Process kit for a substrate support - Google Patents

Abstract

Methods and apparatus for processing substrates are provided herein. In some embodiments, a process kit for a substrate support includes: an upper edge ring made of quartz and having an upper surface and a lower surface, wherein the upper surface is substantially planar and the lower surface includes a stepped lower surface to define a radially outermost portion and a radially innermost portion of the upper edge ring.

Description

Processing kit for substrate supports

Embodiments of the present disclosure relate generally to substrate processing apparatus and, more particularly, to processing kits for substrate supports and methods of using the same.

Substrate processing systems (e.g., plasma reactors) may be used to deposit, etch, or form layers on a substrate or to treat a substrate surface. One technique useful for controlling aspects of the substrate processing is to use radio frequency (RF) energy to control a plasma proximate to a substrate, such as by coupling RF energy to an electrode disposed below the substrate (disposed on a substrate support).

The inventors herein provide embodiments of a substrate processing system that can provide improved RF energy control of the substrate processing system and elastic control of the plasma sheath near the edge of the wafer.

In some embodiments, a processing kit for a substrate support includes an upper edge ring made of quartz and having an upper surface and a lower surface, wherein the upper surface is substantially planar and the lower surface includes a stepped lower surface to define a radially outermost portion and a radially innermost portion of the upper edge ring.

In some embodiments, a substrate support comprises: a lower edge ring, wherein the lower edge ring is conductive; and an upper edge ring, the upper edge ring having a wavy lower surface configured to intersect the lower edge ring, the upper edge ring further having an inner diameter smaller than the inner diameter of the lower edge ring and an outer diameter larger than the outer diameter of the lower edge ring, the upper edge ring further having an upper surface, the upper surface being substantially planar, wherein the upper edge ring is made of quartz.

In some embodiments, a substrate support comprises: a base supporting a substrate supporting surface configured to support a substrate having a given diameter; and a processing kit disposed on top of the substrate support and comprising: a lower edge ring having an upper surface disposed at a height greater than the upper surface of the base and less than the substrate supporting surface; and an upper edge ring disposed on top of the lower edge ring, the upper edge ring having an inner diameter less than the given diameter and an outer diameter greater than the outer diameter of the base, the upper edge ring further having an upper surface that is substantially planar.

Other and further embodiments of the disclosure are described below.

Methods and apparatus for processing substrates are disclosed herein. The disclosed methods and apparatus may advantageously facilitate more uniform plasma processing of substrates compared to conventional plasma processing apparatus. For example, embodiments of the present disclosure may improve processing uniformity, such as etch uniformity, between the edge of a substrate and the center of the substrate, thereby providing more uniform overall substrate processing.

For example, the inventors have discovered that during etching processes on certain substrates (e.g., semiconductor wafers), center-to-edge non-uniform etch amounts are discovered. Specifically, the inventors have discovered that the substrate edge acts like an RF antenna, causing the electric field in the processing chamber to be localized and attracted to the substrate edge during processing with an applied RF bias. As a result, the plasma strike on the substrate edge also becomes localized and stronger. The inventors have discovered an inventive edge ring design that includes two edge ring components: an upper edge ring and a lower edge ring, as discussed in more detail below. The upper edge ring is made of quartz, has a higher etch impedance and generates fewer defects/particles inside the chamber during processing. The lower edge ring can be made of a conductive material or a high dielectric constant material, such as aluminum. The conductive or high dielectric constant lower edge ring raises the RF conductive surface and changes the electric field near the edge of the substrate. This change in the electric field preferentially deflects plasma strikes from the substrate edge to the upper edge ring disposed above the lower edge ring.

FIG. 1 depicts a schematic side view of an inductively coupled plasma reactor (reactor 100) according to some embodiments of the present disclosure. Reactor 100 may be used alone or as a processing module for an integrated semiconductor substrate processing system, or cluster tool, such as the ^CENTURA® Integrated Semiconductor Wafer Processing System available from Applied Materials, Inc. of Santa Clara, California. Examples of suitable plasma reactors that may advantageously benefit from self-modification according to embodiments of the present disclosure include inductively coupled plasma etch reactors, such as the ^DPS® line of a semiconductor facility or other inductively coupled plasma reactors, such as the MESA ^™ also available from Applied Materials, Inc. The semiconductor facilities listed above are illustrative only, and other etching reactors and non-etching facilities (such as CVD reactors, or other semiconductor processing facilities) may also be suitable for modification according to the present teachings. For example, suitable non-limiting plasma reactors that may be modified according to the present disclosure may be found in U.S. Patent Application Publication No. 2011/009499 (published on April 28, 2011 by V. Todorow et al. and entitled “INDUCTIVELY COUPLED PLASMA APPARATUS”), U.S. Patent Application Publication No. 2011/0097901 (published on April 28, 2011 by S. Banna et al. and entitled “DUAL MODE INDUCTIVELY COUPLED PLASMA REACTOR WITH ADJUSTABLE PHASE COIL ASSEMBLY”), or U.S. Patent Application Publication No. 2015/0068682 (published on May 12, 2015 by S. Banna et al. and entitled “POWER DEPOSITION CONTROL IN INDUCTIVELY COUPLED PLASMA (ICP) REACTORS”).

The reactor 100 generally includes a processing chamber 104 having a conductive body (chamber walls 130) and a lid 120 (e.g., ceiling) that together define a content volume, a substrate support 116 (shown as supporting a substrate 115) disposed within the content volume, an inductively coupled plasma apparatus 102, and a controller 140. The chamber walls 130 are typically coupled to an electrical ground 134. In embodiments where the reactor 100 is configured as an inductively coupled plasma reactor, the lid 120 may include a dielectric material facing the content volume of the reactor 100. In other embodiments, other plasma sources may also or alternatively be used, such as capacitively coupled plasma sources, remote plasma sources, etc.

The substrate support 116 generally includes an upper portion having a support surface for supporting the substrate 115. In some embodiments, the support surface is formed of a dielectric material. FIG. 1 shows the upper portion of the substrate support 116, for example, as an electrostatic clamp 117. The substrate support 116 further includes a cathode 118 coupled to a bias source 122 via a matching network 124. The bias source 122 can illustratively be a source of RF energy up to about 1000 W (but not limited to about 1000 W), such as about 150 W for some applications, using a frequency such as about 13.56 MHz, although other frequencies and powers may be provided as desired for specific applications. The bias source 122 can generate one or both of continuous or pulsed power. In some embodiments, the bias source 122 can be a DC or pulsed DC source. In some embodiments, the bias source 122 can provide multiple frequencies, or one or more second bias sources (as illustrated in FIG. 2 ) can be coupled to the substrate support 116 via the same matching network 124 or via one or more additional matching networks (as illustrated in FIG. 2 ) to provide multiple frequencies. An insulating body layer 128 surrounds the cathode 118.

The processing kit 125 is disposed atop the substrate support 116 to protect the upper surface of the substrate support 116 that would otherwise be exposed. The processing kit 125 is further configured to improve substrate processing, as discussed in more detail below. In some embodiments, a plasma screen 129 may be disposed in the area between the substrate support 116 and the chamber wall 130 to limit or prevent the plasma from moving under the substrate support 116.

FIG. 2 depicts further details of the substrate support 116 according to some embodiments of the present disclosure. As shown in FIG. 2 , the substrate support 116 includes an electrode 200 (e.g., cathode 118) disposed within the substrate support 116. In some embodiments, the electrode 200 may be centrally disposed below a supporting surface 216 of the substrate support 116. The electrode 200 is formed of a conductive material, such as one or more of aluminum (Al), doped silicon carbide (SiC), or other suitable conductive materials that are compatible with the processing environment. In some embodiments, the electrode 200 may be disposed on or may be a base 205 that supports a dielectric supporting surface of the substrate support 116. The substrate 205 may have a peripheral edge 202 and an upper surface 204. In some embodiments, the substrate 205 may include a plurality of channels 207 disposed through the substrate 205 to flow a heat transfer medium through the channels 207. A heat transfer medium source 209 may be coupled to the plurality of channels 207 to provide the heat transfer medium to the plurality of channels 207. For example, the flow of the heat transfer medium through the plurality of channels 207 may be used to adjust the temperature of a substrate disposed on the substrate support 116.

The substrate support 116 further includes a substrate supporting surface 216 disposed above the upper surface 204 of the electrode 200. For example, the substrate supporting surface 216 can be part of an electrostatic chuck 117. The electrostatic chuck 117 is disposed above the electrode 200 and the substrate supporting surface 216 is an upper surface of the electrostatic chuck 117. The electrostatic chuck 117 can include a dielectric plate, such as a ceramic positioning plate 220. The ceramic positioning plate 220 includes one or more electrodes (electrode 222 shown) disposed in the ceramic positioning plate 220 to provide DC energy for clamping the substrate 115 to the electrostatic chuck 117. The electrode 222 is typically coupled to a DC power supply 226.

A processing kit (e.g., processing kit 125) is disposed atop substrate support 116 to protect the upper surface of substrate support 116 that would otherwise be exposed. For example, processing kit 125 includes a lower edge ring 206 and an upper edge ring 208. Lower edge ring 206 is made of a conductive or high dielectric constant process compatible material, such as aluminum or an aluminum alloy, such as Al6061. In some embodiments, and as shown in FIG. 4A , lower edge ring 206 may have an anodic oxide coating 410. In some embodiments, the coating of anodic oxide coating 410 completely surrounds lower edge ring 206. However, in some embodiments, the anodic oxide coating 410 does not completely surround the lower edge ring 206. For example, the anodic oxide coating 410 can be selectively formed on the lower edge ring 206. The anodic oxide coating 410 can help protect the metal surface of the lower edge ring 206 from chemical corrosion (e.g., fluorine corrosion), which may cause defects or contamination. The anodic oxide coating 410 can have a thickness of about 4 microns +/- 2 microns. The lower edge ring 206 is electrically coupled to the electrode 200 (e.g., substrate 205) so that the electrode 200 and the lower edge ring 206 can be coupled to a common RF power supply (e.g., bias source 122). In some embodiments, the lower edge ring 206 is made of the same conductive material as the substrate 205, in some embodiments Al6061. The lower edge ring 206 generally includes curved edges to avoid arcing. The upper edge ring 208 is made of an insulating process compatible material, such as quartz. An insulator layer 128 surrounding the cathode 118 (e.g., electrode 200, or substrate 205) is also disposed around the outer diameter surface of the lower edge ring 206. The upper edge ring 208 is disposed on the insulator layer 128, the lower edge ring 206, and a portion of the ceramic positioning plate 220, as will be discussed in more detail below.

The inventors have observed that during plasma processing, the edges of the substrate 115 can act like RF antennas, causing the electric field in the processing chamber to be localized and attracted to the substrate edges during processing with an applied RF bias. As a result, the plasma strike on the substrate edge also becomes localized and stronger, resulting in non-uniform substrate processing. For example, the inventors have discovered that during etching processes on certain substrates (e.g., semiconductor wafers), center-to-edge non-uniformity in etch volume is observed.

The conductive or high dielectric constant lower edge ring 206 raises the RF conductive surface and changes the electric field near the edge of the substrate 115. This change in the electric field advantageously deflects plasma strikes from the edge of the substrate 115 to the upper edge ring 208 disposed above the lower edge ring 206. The upper edge ring 208 is made of quartz, which advantageously has a higher etch resistance and generates fewer defects/particles inside the chamber during processing. Therefore, the inventors have discovered that providing a processing kit 125 (as discussed herein) can advantageously provide more uniform substrate processing (e.g., etching) while generating fewer defects/particles inside the chamber during processing. In embodiments of the lower edge ring 206 having an anodic oxide coating 410, the anodic oxide coating 410 is non-conductive. However, the anodic oxide coating 410 advantageously does not affect the ability of the conductive or high dielectric constant lower edge ring 206 to raise the RF conductive surface and change the electric field near the edge of the substrate 115.

FIG3 depicts a partial schematic side view of the substrate support 116 depicted in FIG2 , according to some embodiments of the present disclosure. For example, the electrostatic chuck 117 is configured to support a substrate having a given diameter, such as 300 mm (although other sizes and shapes may be used, such as 150 mm, 200 mm, 450 mm, etc.). The support surface 216 of the electrostatic chuck 117 has a diameter less than the given width, such that the peripheral edge of the substrate 115 slightly overhangs the support surface 216. For example, in a configuration for processing 300 mm wafers, the support surface 216 has a diameter slightly less than 300 mm. The electrostatic clamp 117 includes a wall 304 extending vertically or substantially vertically downward from the support surface 216 and terminating at an upper surface 306 of an outer peripheral protrusion 308 extending radially outward from the bottom of the wall 304.

The outer peripheral protrusion 308 of the electrostatic fixture 117 radially disposes the lower edge ring 206 outward. For example, the inner diameter of the lower edge ring 206 is larger than the inner diameter of the outer peripheral protrusion 308, and therefore, larger than the inner diameter of a given width of the substrate (e.g., 300 mm). As described above, the lower edge ring 206 is conductively coupled to the electrode 200. As depicted in FIG. 3, the lower edge ring 206 is conductively coupled to the electrode 200, for example, by being directly disposed on top of the substrate 205 (the substrate 205 forming the electrode 200). The lower edge ring 206 includes an upper surface 302 disposed above the upper surface 204 of the base 205 (eg, above the electrode 200 ) to locally elevate the RF conductive surface in a region disposed radially outward from the outer edge of the substrate 115 .

The inventors have discovered that placing the upper surface 302 of the lower edge ring 206 above the upper surface 204 of the electrode 200 advantageously provides more uniform substrate processing, as described above. For example, the inventors believe that the elevated upper surface 302 of the lower edge ring 206 attracts ions outside the diameter of the substrate 115, preventing or reducing the increase of process products at the edge of the substrate.

However, the inventors have further discovered that for some processes, placing the upper surface 302 of the lower edge ring 206 too close to or above the substrate 115 will drastically reduce the processing rate, such as the etching rate, near the edge of the substrate 115. Therefore, in some embodiments, the upper surface 302 of the lower edge ring 206 is further set at a height less than the upper surface 306 of the outer peripheral protrusion 308.

In some embodiments, the base 205 includes a cutout or recess 310 configured to receive the lower edge ring 206. In some embodiments, the radial inner wall of the recess 310 is substantially aligned with the outer wall of the outer peripheral protrusion 308. As depicted in FIG. 3 , the recess 310 and the lower edge ring 206 are sized to place the upper surface 302 of the lower edge ring 206 simultaneously above the upper surface 204 of the base 205 and below the upper surface 306 of the outer peripheral protrusion 308. In some embodiments, the lower edge ring 206 has an inner diameter that is larger than the inner diameter of the radial inner wall of the recess 310 so that the inner side wall of the lower edge ring does not contact the radial inner wall of the recess 310. In some embodiments, the lower edge ring 206 has an outer diameter that is equal to or smaller than the outer diameter of the base 205. In other words, the peripheral edge 312 of the lower edge ring is aligned with the peripheral edge 202 or is disposed radially inward.

In some embodiments, one or both of the lower edge ring 206 or the base 205 may include one or more alignment features to facilitate radial alignment of the lower edge ring 206 to the base 205. For example, as depicted in FIG3 , holes 314 may be provided in the recess 310 of the base 205 to receive corresponding protrusions or latches (not shown) of the lower edge ring 206 to facilitate radial alignment of the lower edge ring 206 to the base 205. Other alignment configurations are also contemplated.

The upper edge ring 208 is disposed on the insulator layer 128, the lower edge ring 206, and a portion of the outer peripheral protrusion 308 of the ceramic positioning plate 220. Specifically, the upper edge ring 208 has a lower surface configured to be disposed at least on the outer peripheral protrusion 308. The lower surface of the upper edge ring 208 is slightly spaced apart from the upper surface 302 of the lower edge ring 206. The lower surface of the upper edge ring 208 can also be disposed on the upper surface of the insulator layer 128.

In some embodiments, the lower edge ring 206 may include upper and outer peripheral notches 316 configured to intersect corresponding portions of the upper edge ring 208. The notches 316 facilitate alignment of the lower edge ring 206 and the upper edge ring 208. In some embodiments, the lower edge ring does not include upper and outer peripheral notches, such as described below with respect to FIGS. 6-6A.

In some embodiments, the insulator layer 128 may include upper and outer peripheral notches 318 configured to intersect corresponding portions of the upper edge ring 208. The upper edge ring 208 may include a wavy lower surface, such as a stepped lower surface. In some embodiments, the upper edge ring 208 includes a stepped lower surface having one or more steps to gradually reduce the thickness of the upper edge ring 208 from the thickest radially outermost portion (except for the rounded edge) to the thinnest radially innermost portion.

For example, in some embodiments, as depicted in FIG. 1 and FIGS. 7 and 7A, one step is provided, defining two portions having different thicknesses: a radially outermost portion (e.g., 720 in FIG. 7A) and a radially innermost portion (e.g., 710 in FIG. 7A). In some embodiments, as depicted in FIGS. 2-3 and FIGS. 5-5A, two steps are provided, defining three portions having different thicknesses: a radially outermost portion 320, a central portion 322, and a radially innermost portion 324. One or more steps may be positioned to intersect the upper edge ring 208 with the components disposed below the outer peripheral protrusion 308, the notch 316, and the notch 318.

The upper edge ring 208 includes an upper surface 326 and a rounded or curved upper peripheral edge to connect the upper surface 326 to the outer peripheral wall of the upper edge ring 208 or directly to the lower surface of the upper edge ring 208, depending on the nature of the bend. In some embodiments, the upper surface 326 is planar or substantially planar from the inner diameter of the upper edge ring 208 to near the outer diameter of the upper edge ring 208 (e.g., except for the curved upper peripheral edge of the upper edge ring).

The upper edge ring 208 has an inner diameter that is larger than the inner diameter of the support surface 216 and smaller than a given diameter of the substrate 115 (e.g., less than 300 mm for a configuration designed to process 300 mm wafers). A gap may be defined between the upper edge ring 208 and the wall 304. The upper edge ring 208 further has a thickness at a radially innermost portion 324 that is less than the height of the wall 304, such that when the upper edge ring 208 is disposed on the outer peripheral protrusion 308, an upper surface 326 of the upper edge ring 208 is lower than the support surface 216 of the electrostatic fixture 117. The inventors have discovered that placing the upper surface 326 at or above the level of the substrate 115 increases particle defects during certain processes (e.g., etching). Therefore, when the substrate 115 is disposed on the substrate support 116, the radially innermost portion 324 of the upper edge ring 208 extends below the outer peripheral edge of the substrate 115 and defines a gap between the upper edge ring 208 and the back surface of the substrate 115.

The upper edge ring 208 has an outer diameter that is larger than the outer diameter of the substrate support 116 such that the outer peripheral edge of the upper edge ring overhangs or extends beyond the substrate support 116 (including the insulator layer 128).

FIG4 depicts a side cross-sectional view of the lower edge ring 206 according to some embodiments of the present disclosure. FIG4A depicts a partial side cross-sectional view of the lower edge ring 206.

FIG5 depicts a side cross-sectional view of the upper edge ring 208 according to some embodiments of the present disclosure. FIG5A depicts a partial side cross-sectional view of the upper edge ring 208.

FIG. 6 depicts a side cross-sectional view of a lower edge ring 606 according to some embodiments of the present disclosure. FIG. 6A depicts a partial side cross-sectional view of the lower edge ring 606. A lower edge ring 606 similar to the lower edge ring described above may be used. Moreover, in some embodiments, the lower edge ring 606 may have an anodic oxide coating 610 similar to the anodic oxide coating 410 described above. For example, in some embodiments, the coating of the anodic oxide coating 610 completely surrounds the lower edge ring 606. However, in some embodiments, the anodic oxide coating 610 does not completely surround the lower edge ring 606. For example, an anodic oxide coating 610 may be selectively formed on the lower edge ring 606. The anodic oxide coating 610 may help protect the metal surface of the lower edge ring 606 from chemical corrosion (e.g., fluorine corrosion), which may cause defects or contamination. The anodic oxide coating 610 may have a thickness of about 4 microns +/- 2 microns. The lower edge ring 606 has an upper surface 602 and a peripheral sidewall 612. In some embodiments, the lower edge ring 608 has an outer diameter of about 13.2 inches to about 13.8 inches. In some embodiments, the lower edge ring 608 has an inner diameter of about 12.0 inches to about 12.5 inches. In some embodiments, lower edge ring 606 generally includes a curved edge.

FIG. 7 depicts a side cross-sectional view of an upper edge ring 708 according to some embodiments of the present disclosure. FIG. 7A depicts a partial side cross-sectional view of an upper edge ring 708. An upper edge ring 708 similar to the upper edge ring described above may be used. The upper edge ring 708 includes an upper surface 726 and a fillet or curved upper peripheral edge to connect the upper surface 726 to the outer peripheral wall 704 of the upper edge ring 708 or directly to the lower surface 702 of the upper edge ring 708, depending on the nature of the curvature. In some embodiments, the upper surface 726 is planar or substantially planar from the inner diameter of the upper edge ring 708 to approximately the outer diameter of the upper edge ring 708 (eg, except for the peripheral edge of the bend of the upper edge ring).

The upper edge ring 708 has an inner diameter that is larger than the inner diameter of the support surface 216 and smaller than a given diameter of the substrate 115. In some embodiments, the inner diameter of the upper edge ring 708 is about 11.5 inches to about 12.0 inches. In some embodiments, the outer diameter of the upper edge ring 708 is about 14.9 inches to about 15.4 inches. In some embodiments, the upper edge ring 708 has a width of about 1.5 inches to about 2.0 inches, defined by the distance between the inner diameter of the upper edge ring 708 and the outer diameter of the upper edge ring 708.

The upper edge ring 708 includes a wavy lower surface 702, such as a stepped lower surface. As depicted in FIG. 7 , the upper edge ring 708 includes a stepped lower surface to reduce the thickness of the upper edge ring 708 from a thicker radial outermost portion (except for the rounded edge) to a thinner radial innermost portion. In the embodiment of FIGS. 7-7A , a step is provided that defines two portions having different thicknesses: a radial outermost portion 720 and a radial innermost portion 710. In some embodiments, the radial innermost portion 710 has an outer diameter of about 13.5 inches to about 14.5 inches. The steps may be positioned to intersect the upper edge ring 708 with the outer peripheral protrusion 308 and the lower edge ring 206 or the lower edge ring 608.

Returning to FIG. 1 , in some embodiments, the lid 120 may be substantially flat. Other modifications of the processing chamber 104 may have other types of lids, such as a dome-shaped lid or other shapes. The inductively coupled plasma apparatus 102 is typically disposed above the lid 120 and is configured to inductively couple RF power into the processing chamber 104. The inductively coupled plasma apparatus 102 includes first and second coils 110, 112 disposed above the lid 120. Each of the relative position, the ratio of the diameters of each coil, and/or the number of turns in each coil may be adjusted as desired to control the profile or density of the plasma formed, for example, by controlling the inductance on each coil. Each of the first and second coils 110, 112 is coupled to the RF power supply 108 via the RF feed structure 106 via a matching network 114. RF power supply 108 may illustratively be capable of producing up to, but not limited to, approximately 4000 W at tunable frequencies in the range of 50 kHz to 13.56 MHz, although other frequencies and powers may be provided as desired for particular applications.

In some embodiments, a power divider 105 (e.g., a split capacitor) may be provided between the RF feed structure 106 and the RF power supply 108 to control the relative amount of RF power provided to each of the first and second coils. For example, as shown in FIG. 1 , the power divider 105 may be disposed in a line coupling the RF feed structure 106 to the RF power supply 108 to control the amount of RF power provided to each coil (thereby facilitating control of plasma characteristics in regions corresponding to the first and second coils). In some embodiments, the power divider 105 may be incorporated into the matching network 114. In some embodiments, after the power divider 105, the RF current flows to the RF feed structure 106 and then to the first and second coils 110, 112. Alternatively, a separate RF current may be fed directly to each of the individual first and second coils.

A heater element 121 may be disposed atop the lid 120 to facilitate heating the interior of the processing chamber 104. The heater element 121 may be disposed between the lid 120 and the first and second coils 110, 112. In some embodiments, the heater element 121 may include a resistive heating element and may be coupled to a power supply 123, such as an AC power supply, configured to provide sufficient energy to control the temperature of the heater element 121 between about 50 and about 100 degrees Celsius. In some embodiments, the heater element 121 may be an open-blocking heater. In some embodiments, the heater element 121 may include a non-blocking heater, such as a ring element, thereby facilitating uniform plasma formation within the processing chamber 104.

During operation, a substrate 115 (e.g., a semiconductor wafer or other substrate suitable for plasma processing) may be placed on a substrate support 116, and a process gas may be supplied from a gas panel 138 through one or more inlet ports 126 (disposed through the lid 120 and/or chamber wall 130) to form a gas mixture 150 within the processing chamber 104. For example, prior to introducing the process gas, the temperature of the surfaces within the chamber may be controlled by, for example, a heater 121 (as described above) to have a surface-facing volume at a temperature between about 100 and 200 degrees Celsius, or about 150 degrees Celsius. The gas mixture 150 may be ignited into a plasma 155 in the processing chamber 104 by applying power from the RF power supply 108 to the first and second coils 110, 112. In some embodiments, power from the bias source 122 may also be provided to the substrate support 116. The pressure within the interior of the processing chamber 104 may be controlled using a throttle valve 127 and a vacuum pump 136. In some embodiments, the pressure within the processing chamber 104 may be controlled using a gate valve, a butterfly valve, a swing valve, etc. The temperature of the chamber wall 130 may be controlled using a pipe (not shown) containing a liquid running through the chamber wall 130. One non-limiting specific application in which the present apparatus finds particular utility is in pre-cleaning applications, such as etching oxide (eg, silicon oxide) from a substrate (eg, a silicon substrate or wafer).

The controller 140 includes a central processing unit (CPU) 144, a memory 142, and support circuits 146 for the CPU 144 and facilitates control of the components of the reactor 100 and methods of forming a plasma, such as discussed herein. The controller 140 may be any form of general purpose computer processor that may be used in an industrial setting for controlling a variety of chambers and subprocessors. The memory, or computer readable medium 142 for the CPU 144 may be one or more readily accessible memories, such as random access memory (RAM), unique memory (ROM), a floppy disk, a hard disk, or any other form of digital storage, either locally or remotely. The support circuits 146 are coupled to the CPU 144 for supporting the processor in a conventional manner. Such circuits include caches, power supplies, clock circuits, input/output circuits and subsystems, etc. Memory 142 stores software (source or object code) that can be executed or called to control the operation of reactor 100 in the manner described herein. Software programs can also be stored and/or executed by a second CPU (not shown) that is located remotely from the hardware controlled by CPU 144.

Although the foregoing is an embodiment of the present disclosure, other and further embodiments of the present disclosure may be modified without departing from the basic scope thereof. For example, various sizes of processing kits 125 may be controlled for different RF frequencies, and/or different power levels of the RF bias applied to the electrode 200 to position the upper surface 302 (or 602) of the lower edge ring 206 (or 606). For example, in some embodiments, the upper surface 302 (or 602) of the lower edge ring 206 (or 606) may be placed closer to or further away from the support surface 216. In some embodiments, the inner and/or outer diameters of the lower edge ring 206 (or 606) may be selected or controlled to control the width of the upper surface 302 (or 602) and/or to control the radial position of the upper surface 302 (or 602) of the lower edge ring 206 (or 606).

100: Reactor 102: Inductively coupled plasma apparatus 104: Processing chamber 105: Power divider 106: RF feed structure 108: RF power supply 110: First coil 112: Second coil 114: Matching network 115: Substrate 116: Substrate support 117: Electrostatic fixture 118: Cathode 120: Cover 121: Heater element 122: Bias source 124: Matching network 125: Processing kit 126: Inlet port 127: Throttle valve 128: Insulator layer 129: Plasma screen 130: Chamber wall 134: electrical ground 136: vacuum pump 138: gas panel 140: controller 142: memory 144: CPU 146: support circuit 150: gas mixture 155: plasma 200: electrode 202: peripheral edge 204: upper surface 205: base 206: lower edge ring 207: channel 208: upper edge ring 209: heat transfer medium source 216: substrate support surface 220: ceramic positioning plate 222: electrode 226: DC power supply 302: upper surface 304: wall 306: upper surface 308: outer peripheral projection 310: notch 312: peripheral edge 314: hole 316: notch 318: notch 320: radial outermost portion 322: central portion 324: radial innermost portion 326: upper surface 410: anodic oxide coating 602: upper surface 606: lower edge ring 608: lower edge ring 610: anodic oxide coating 612: peripheral sidewall 702: lower surface 704: outer peripheral wall 708: upper edge ring 710: radial innermost portion 720: radial outermost portion 726: upper surface

The manner in which the above-described features of the present disclosure may be understood in detail may be understood by reference to the illustrative embodiments of the present disclosure depicted in the accompanying drawings (briefly summarized above and discussed in more detail below). However, the accompanying drawings illustrate only typical embodiments of the present disclosure and are not intended to limit the scope thereof, as the present disclosure may admit to other equally effective embodiments.

FIG. 1 depicts a schematic diagram of a plasma reactor according to some embodiments of the present disclosure.

FIG. 2 illustrates a schematic side view of a substrate support according to some embodiments of the present disclosure.

3 illustrates a partial schematic side view of a substrate support according to some embodiments of the present disclosure.

4 illustrates a side cross-sectional view of a lower edge ring for a substrate support according to some embodiments of the present disclosure.

FIG. 4A depicts a partial side cross-sectional view of the lower edge ring of FIG. 4 .

5 illustrates a side cross-sectional view of an upper edge ring for a substrate support according to some embodiments of the present disclosure.

FIG. 5A depicts a partial side cross-sectional view of the upper edge ring of FIG. 5 .

FIG. 6 depicts a side cross-sectional view of a lower edge ring according to some embodiments of the present disclosure.

FIG. 6A depicts a partial side cross-sectional view of the lower edge ring of FIG. 6 .

FIG. 7 depicts a side cross-sectional view of an upper edge ring according to some embodiments of the present disclosure.

FIG. 7A depicts a partial side cross-sectional view of the upper edge ring of FIG. 7 .

To facilitate understanding, the same element numbers are used as much as possible to designate common elements in the drawings. The drawings are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated into other embodiments without further description.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

115: Substrate

116: Baseboard support

117: Electrostatic clamp

118: cathode

125: Treatment Kit

128: Insulating layer

202: Peripheral edge

204: Upper surface

205: Base

206: Lower edge ring

208: Upper edge ring

216: Substrate support surface

302: Upper surface

304: Wall

306: Upper surface

308: Outer peripheral protrusion

310: Notch

312: Peripheral edge

314: Hole

316: Notch

318: Notch

320: radially outermost part

322: Central part

324: radial innermost part

326: Upper surface

Claims (20)

A processing kit for a substrate support, comprising: an upper edge ring, the upper edge ring being made of quartz and having an upper surface and a lower surface, wherein the upper surface is substantially planar and the lower surface comprises a stepped lower surface to define a radially outermost portion and a radially innermost portion of the upper edge ring; and a lower edge ring, wherein the lower edge ring is configured to intersect the stepped lower surface of the upper edge ring. A processing kit as described in claim 1, wherein the lower edge ring comprises aluminum or an aluminum alloy having an anodic oxidation coating. A processing kit as described in claim 1, wherein the lower edge ring has a notch along an upper and outer peripheral edge, and wherein the stepped lower surface of the upper edge ring is configured to intersect the notch. A processing kit as described in claim 1, wherein the upper edge ring has an inner diameter smaller than the inner diameter of the lower edge ring and an outer diameter larger than the outer diameter of the lower edge ring. The treatment kit of claim 1, wherein the lower edge ring is conductive. A processing kit as described in claim 1, wherein the radially outermost portion has a thickness greater than a thickness of the radially innermost portion. A processing kit as described in any one of claims 1 to 6, wherein the upper edge ring includes a curved upper peripheral edge connecting the upper surface to an outer peripheral wall of the upper edge ring or to the lower surface of the upper edge ring. A treatment kit as described in any of claims 1 to 6, wherein the upper edge ring has a width of about 1.5 inches to about 2.0 inches. A processing kit as described in any of claims 1 to 6, wherein the radial innermost portion of the upper edge ring has an outer diameter of about 13.5 inches to about 14.5 inches. A processing kit for a substrate support, comprising: a lower edge ring, wherein the lower edge ring is conductive; and an upper edge ring, the upper edge ring having a wavy lower surface configured to intersect the lower edge ring, the upper edge ring further having an inner diameter smaller than the inner diameter of the lower edge ring and an outer diameter larger than the outer diameter of the lower edge ring, the upper edge ring further having an upper surface, the upper surface being substantially planar, wherein the upper edge ring is made of quartz. A processing kit as described in claim 10, wherein the wavy lower surface of the upper edge ring includes a stepped lower surface, and the stepped lower surface generally decreases a thickness of the upper edge ring from a radially outermost portion to a radially innermost portion. A processing kit as described in claim 11, wherein the stepped lower surface includes a step to define the radial outermost portion and the radial innermost portion, wherein the radial innermost portion of the upper edge ring is configured to intersect with the lower edge ring. A processing kit as described in any one of claims 10 to 12, wherein the lower edge ring is made of aluminum or an aluminum alloy. A processing kit as described in any of claims 10 to 12, wherein the lower edge ring comprises aluminum or an aluminum alloy having an anodic oxidation coating. A processing kit as described in any of claims 10 to 12, wherein the lower edge ring has a notch along an upper and outer peripheral edge, wherein the undulating lower surface of the upper edge ring is configured to intersect the notch. A processing kit as described in any one of claims 10 to 12, wherein the upper edge ring includes a curved upper peripheral edge connecting the upper surface to an outer peripheral wall of the upper edge ring or to the wavy lower surface of the upper edge ring. A substrate support member includes: a substrate supporting a substrate support surface, the substrate support surface being configured to support a substrate having a given diameter; and a processing kit disposed on top of the substrate support member and including: a lower edge ring having an upper surface disposed at a height greater than the upper surface of the substrate and less than the substrate support surface; and an upper edge ring disposed on top of the lower edge ring, the upper edge ring having an inner diameter less than the given diameter and an outer diameter greater than the outer diameter of the substrate, the upper edge ring further having an upper surface that is substantially planar. The substrate support member as described in claim 17 further comprises: An upper portion of the substrate support member, the upper portion of the substrate support member is disposed above the base, wherein an upper surface of the upper portion of the substrate support member includes the substrate supporting surface. A substrate support as described in claim 18, wherein the upper portion of the substrate support includes an outer peripheral protrusion extending radially outward, and wherein the upper edge ring has a lower surface configured to be disposed on the outer peripheral protrusion. A substrate support as described in any of claims 17 to 19, wherein the lower edge ring comprises aluminum or an aluminum alloy having an anodic oxidation coating.