TW202423206A - Circuit board and semi-fabricated product of same - Google Patents

Abstract

Provided is a circuit board which makes it possible to improve heat dissipation. This circuit board 1 comprises: a circuit pattern 3 provided on a base 9 with an insulating material 11 interposed therebetween; a semiconductor chip 5 joined through a solder 13 onto the circuit pattern 3; and a heat dissipating frame 7 joined and fixed onto the circuit pattern 3 and disposed adjacent to the semiconductor chip 5, wherein when C [mm] is the clearance of the semiconductor chip 5 below the heat dissipating frame 7, A [mm2] is the surface area of the heat dissipating frame 7, and T [mm] is the thickness, the following equation is satisfied: 15.0 ≤ A0.5 * C -1.2 * T0.2 ≤ 600.

Description

Circuit substrates and semi-finished products

The present invention relates to a circuit substrate and a semi-finished product thereof with improved heat dissipation performance.

As a known circuit substrate, there is one described in Patent Document 1, for example. In this circuit substrate, a circuit pattern is formed on a base via an insulating material, and an upper layer circuit pattern is formed on the circuit pattern by cold spraying.

This known circuit substrate is considered to be excellent in heat dissipation by assembling electronic components such as power semiconductors on the upper layer circuit pattern, thereby reducing thermal resistance and dissipating heat.

However, since the upper layer of the multilayer circuit pattern is formed by cold spraying, there will be gaps in the internal structure, and the thermal conductivity will decrease due to the gaps, so the heat dissipation will be limited. [Known technical literature] [Patent literature]

[Patent Document 1] Japanese Patent Application Publication No. 2006-319146.

[The problem that the invention is trying to solve]

The problem we want to solve is that heat dissipation has its limits. [Technical means to solve the problem]

The present invention provides a circuit substrate, comprising: a circuit pattern arranged on an insulating substrate; an electronic component bonded to the circuit pattern; and a heat sink bonded to the circuit pattern and arranged adjacent to the electronic component, wherein when a gap between a lower portion of the heat sink frame and the electronic component is set to C [mm], an area of a lower surface of the heat sink frame is set to A [mm ² ], and a thickness of the heat sink frame relative to the circuit pattern is set to T [mm], 15.0≦A ^0.5 ×C ^{- 1.2} ×T ^0.2 ≦600 is satisfied.

Furthermore, the present invention provides a semi-finished product of a circuit substrate, comprising: a circuit pattern, which is arranged on an insulating substrate via an insulating material; and a heat sink, which is arranged adjacent to a configuration area of electronic components to be bonded to the circuit pattern, and when the gap between the lower part of the heat sink and the configuration area is set to C [mm], the area of the lower surface of the heat sink is set to A [mm ² ], and the thickness of the heat sink relative to the circuit pattern is set to T [mm], 15.0≦A ^0.5 ×C ^{- 1.2} ×T ^0.2 ≦600 is satisfied. [Effect of the invention]

In the present invention, the heat dissipation of the circuit substrate and its semi-finished product can be further improved.

The purpose of improving heat dissipation is achieved by providing a heat dissipation frame surrounding the electronic components on the circuit pattern.

As shown in the figure, the circuit substrate 1 has a circuit pattern 3, an electronic component 5, and a heat sink frame 7. The circuit pattern 3 is disposed on an insulating substrate 8. The electronic component 5 is bonded to the circuit pattern 3. The heat sink frame 7 is bonded to the circuit pattern 3 and disposed adjacent to the electronic component 5.

The heat dissipation frame 7 satisfies 15.0≦A 0.5 ×C - 1.2 ×T 0.2 ≦600 when the gap between the lower portion and the electronic component 5 is C [mm ^] , the area of the lower surface ^7a is A [mm ² ], and ^the thickness relative to the circuit pattern 3 is T [ ^mm ].

The heat dissipation frame 7 can be made of various conductive materials such as copper or aluminum.

The heat dissipation frame 7 may face the solder 13 in the surface direction of the circuit pattern 3 .

The heat dissipation frame 7 can be a positioning frame for the electronic component 5 .

The heat dissipation frame 7 may be formed in a frame shape in which the center of the electronic component 5 in a plan view is offset from the center of the outer shape of the heat dissipation frame 7, or may be formed in a frame shape containing a plurality of electronic components 5 therein, or may be formed in a frame shape in which the gap C is non-uniform in the circumferential direction, or may be formed in a ring-shaped frame shape. Furthermore, the thickness of the heat dissipation frame 7 may be different in the circumferential direction.

The semi-finished product of the circuit substrate 1 has the above-mentioned circuit pattern 3 and heat sink frame 7, and is a semi-finished product before the electronic components 5 are assembled. [Example 1]

FIG. 1(A) is a cross-sectional view of a circuit substrate with a heat sink frame according to Embodiment 1 of the present invention; FIG. 1(B) is a cross-sectional view of a circuit substrate without a heat sink frame according to Comparative Example 1.

The circuit board 1 of this embodiment includes a circuit pattern 3, a semiconductor chip 5, and a heat sink 7.

The circuit pattern 3 is provided on the insulating substrate 8. The insulating substrate 8 may be any insulating substrate such as a metal base substrate or a ceramic substrate on which the circuit pattern 3 can be formed. The insulating substrate 8 of this embodiment has an insulating material 11 provided on a base 9.

The base 9 is a metal base, for example, a plate-shaped member formed of copper. The insulating material 11 is a plate-shaped member bonded to the base 9. The material of the insulating material 11 is not particularly limited, but can be made of epoxy resin, cyanate resin, etc. The insulating material 11 may also contain an inorganic filler.

The circuit pattern 3 is a plate-shaped or foil-shaped member formed of a conductive material such as copper. In addition, the circuit pattern 3 may be made of materials other than copper as long as it is a conductive material. The circuit pattern 3 has an appropriate pattern corresponding to the circuit structure and includes an arrangement area R for the electronic component, i.e., the semiconductor chip 5. The arrangement area R refers to an area whose size in a plan view is the same as or larger than that of the semiconductor chip 5 and within which the semiconductor chip 5 is arranged.

The semiconductor chip 5 is bonded to the arrangement region R of the circuit pattern 3. The semiconductor chip 5 is bonded by solder 13, but can also be bonded by conductive glue such as silver glue or other conductive adhesives. The top view of the semiconductor chip 5 is a square plate. However, the shape of the semiconductor chip 5 can adopt various shapes.

The heat sink frame 7 is a member bonded to the circuit pattern 3 and disposed adjacent to the semiconductor chip 5. The heat sink frame 7 of the present embodiment is a frame-shaped member surrounding the semiconductor chip 5. However, the heat sink frame 7 does not need to surround the semiconductor chip 5, and may be partially open to surround the semiconductor chip 5 or may be disposed adjacent to only a portion of the periphery of the semiconductor chip 5.

The heat dissipation frame 7 is formed into a frame shape by a plate material. The material of the heat dissipation frame 7 is copper, the same as the circuit pattern 3 and the base 9. However, the material of the heat dissipation frame 7 is not limited to copper, and can be other metals or other materials.

The heat sink frame 7 of this embodiment is a square frame shape whose inner and outer shapes are similar to each other in accordance with the semiconductor chip 5. In addition, the inner and outer shapes of the heat sink frame 7 are not limited to similar shapes, and may be different shapes.

The circuit pattern 3 and the heat sink frame 7 are joined by ultrasonic bonding, which is a localized and instantaneous bonding with low heat input. Therefore, the warping of the circuit substrate 1 after bonding can be suppressed. In addition, the tool marks of ultrasonic bonding are left on the upper surface 7b of the heat sink frame 7, and no tool marks are left on the circuit pattern 3 on which the semiconductor chip 5 is mounted. Therefore, when joining with solder 13, the molten solder 13 will not accumulate on the tool marks, and the heat dissipation resistance caused by the solder 13 can be suppressed.

The heat sink frame 7 is provided with a gap C [mm] relative to the semiconductor chip 5 (arrangement area R) in a plan view. In this embodiment, the inner periphery of the heat sink frame 7 is similar to the outer periphery of the semiconductor chip 5, and the gap C is set to be uniform in the inner periphery of the heat sink frame 7 and the entire periphery of the semiconductor chip 5.

In addition, the gap C is a gap between the lower portion of the heat sink 7 and the semiconductor chip 5. The lower portion of the heat sink 7 is the lower portion of the heat sink 7 facing the semiconductor chip 5 in the surface direction, for example, the lower region bonded to the circuit pattern 3.

The heat dissipation frame 7 can also function as a positioning frame having a gap C to position the semiconductor chip 5. However, as described later, the gap C does not need to be uniform around the entire circumference of the semiconductor chip 5, and the heat dissipation frame 7 can also be set to be biased to one side relative to the semiconductor chip 5. Part of the heat dissipation frame 7 can also be in contact with the semiconductor chip 5.

The cross-sectional shape of the heat sink frame 7 is rectangular, but the upper surface 7b may be a curved surface or the cross-sectional shape may vary from the upper surface 7b to the lower surface 7a, such as the width varies from the upper surface 7b to the lower surface 7a. The lower surface 7a of the heat sink frame 7 of this embodiment is a plane divided by the inner periphery and the outer periphery of the heat sink frame 7 in the cross section. The area A [mm ² ] of the lower surface 7a is the area of the heat sink frame 7 in a top view.

In addition, in the case where the lower surface 7a of the heat dissipation frame 7 is curved in cross section or has concavo-convexity, etc., in the case other than a general plane, the area of the lower surface 7a can be set as the area in a plan view. The width of the heat dissipation frame 7 in cross section is obtained by considering the distance between the opposite sides of the inner periphery of the rectangle of the heat dissipation frame 7 as the inner diameter, the distance between the opposite sides of the outer periphery of the same rectangle as the same outer diameter, and the difference between the outer diameter and the inner diameter as the plate width W. In addition, if the heat dissipation frame 7 is annular, it becomes the original outer diameter and inner diameter.

The thickness T (mm) of the heat dissipation frame 7 is set so that the upper surface 7b of the heat dissipation frame 7 protrudes further than the front surface 5a of the semiconductor chip 5. The thickness T is the dimension from the front surface 3a of the circuit pattern 3 of the heat dissipation frame 7.

The heat dissipation frame 7 faces the solder 13 in the surface direction of the circuit pattern 3. Therefore, the heat dissipation frame 7 has the effect of preventing the solder from flowing during the soldering of the semiconductor chip 5. In addition, the so-called surface direction refers to the direction along the front surface of the circuit pattern 3.

In the above structures of the circuit board 1 of FIG. 1(A) and the circuit board 1 of Comparative Example 1 of FIG. 1(B), the thermal resistance related to heat dissipation relative to the heat generated by the semiconductor chip 5 shows a tendency as shown in FIG. 2 .

Fig. 2 is a graph showing the change rate of thermal resistance with respect to the area A [mm ² ], gap C [mm] and thickness T [mm] of the heat sink 7 of the circuit board 1 of Fig. 1 (A). The thermal resistance is shown in Fig. 5 between the point at the center of the front surface of the semiconductor chip 5 and the point on the back surface of the substrate 9 corresponding to this point.

In FIG. 2 , three graphs showing the change rate of thermal resistance are shown on the left, center, and right. The left graph shows the change relative to the area A (board width W) shown on the horizontal axis, the center shows the change relative to the same gap C, and the right shows the change relative to the thickness T.

The dashed line indicating "no Cu frame" is based on the circuit board 1 without a heat sink frame in Comparative Example 1 of Fig. 1(B). The materials and dimensions of each part in Comparative Example 1 of Fig. 1(B) are the same as those of Example 1 of Fig. 1(A).

As shown in FIG. 2 , relative to “no Cu frame” (no heat sink frame 7), in the circuit substrate 1 of the present embodiment, a heat sink frame 7 is provided, and when the gap C=0.5mm and the thickness T=1.0mm are set, the thermal resistance changes to -4.9% relative to “no Cu frame” by changing the area A relative to the board width W=2mm to 14mm.

When the plate width W = 4.0 mm and the thickness T = 1.0 mm, the thermal resistance changes to -5.0% with a change in the gap C of about 1 mm to 0.2 mm. When the plate width W = 4.0 mm and the gap C = 0.5 mm, the thermal resistance changes to -3.6% with a change in the thickness T of about 1 mm to 2 mm.

Therefore, we focused on the relationship between area A, gap C, thickness T, and the thermal resistance reduction effect, and obtained the results shown in Figures 3 and 4.

Fig. 3 is a graph showing the relationship between the area A, gap C and thickness T of the circuit board 1 of Fig. 1 (A) and the thermal resistance reduction rate and the heat dissipation effect size parameter together with the comparative example. Fig. 4 is a graph showing the relationship between the heat dissipation effect size parameter and the thermal resistance reduction rate of the circuit board of Fig. 1 (A) together with the comparative example.

Comparative Example 1 in Fig. 3 is a circuit board 1 without a heat sink frame in Fig. 1 (B). Embodiment 1 and Comparative Examples 2 to 4 in Fig. 3 are circuit boards 1 with a heat sink frame 7. Fig. 3 shows the results of varying the area, gap, and thickness of the heat sink frame 7.

As shown in FIG3 , in Comparative Examples 2 to 4, the thermal resistance reduction rate is less than -1.8 [%]. When the thermal resistance reduction rate is less than 2%, the thermal resistance reduction effect is low. Therefore, if the range of less than 2% where the thermal resistance reduction effect is low and including Comparative Examples 2 to 4 is specifically excluded, the heat dissipation effect dimension parameter becomes as shown in the following formula (1).

A ^0.5 × C ^{－ 1.2} × T ^0.2 ． ． ． Formula (1)

Regarding Comparative Examples 2 to 4 in FIG. 3 , if we look at the heat dissipation effect dimension parameters, they all become A ^0.5 × C ^{－ 1.2} × T ^0.2 ＜15.

On the other hand, Examples 1 to 6 (hereinafter, Examples 1-1 to 1-6) of Example 1 in FIG3 are examples whose heat dissipation effect size parameters all satisfy the following formula (2). In addition, the practical upper limit of the heat dissipation effect size parameter is 600.

15.0≦A ^0.5 ×C ^{－ 1.2} ×T ^0.2 ≦600 ． ． ． Formula (2)

If the results of Figure 3 are plotted as a graph, it becomes Figure 4.

The three data from the left in Fig. 4 are the thermal resistance reduction rates of Comparative Examples 2 to 4 relative to the heat dissipation effect size parameters in Fig. 3. The data other than Comparative Examples 2 to 4 in Fig. 4 are the thermal resistance reduction rates of Examples 1-1 to 1-5 relative to the heat dissipation effect size parameters.

The approximate line obtained from the data of Comparative Examples 2 to 4 is L1, and the approximate line obtained from the data of Example 1 is L2. There is an obvious critical point between the approximate lines L1 and L2 at the heat dissipation effect size parameter A ^0.5 ×C ^{- 1.2} ×T ^0.2 =15.

Furthermore, the bottom row of FIG3 shows the heat dissipation effect size parameter under area A: 64 mm ² , gap C: 0.5 mm, and thickness T: 0.08 mm as comparative example 5. This heat dissipation effect size parameter is 11.1. The thermal resistance reduction rate relative to this heat dissipation effect size parameter can be obtained along the approximate line L1.

Furthermore, the heat dissipation effect size parameter under the condition of area A: 873 mm ² , gap C: 0.1 mm, and thickness T: 3 mm is shown as Example 1-6 in Fig. 3. This heat dissipation effect size parameter can be obtained along the approximate line L2 and is 583.37 which is close to the upper limit value.

When manufacturing the circuit board 1, the circuit pattern 3 is formed on the insulating substrate 8. The heat sink frame 7 is bonded to the portion of the circuit pattern 3 surrounding the arrangement region R by ultrasonic bonding, thereby obtaining a semi-finished product of the circuit board 1.

The dimensions of the heat sink 7 are set to an area A and a thickness T, and the gap between the heat sink 7 and the semiconductor chip 5 is set to C. The relationship among C, A, and T related to heat dissipation is set to equation (2) using the heat sink 7.

For the semi-finished product of the circuit substrate 1, the semiconductor chip 5 is bonded to the circuit pattern 3 while using the heat sink frame 7 as a positioning frame. In this embodiment, the semiconductor chip 5 is bonded to the circuit pattern 3 by solder 13, and the heat sink frame 7 inhibits the solder from flowing out of the frame. Then, the semiconductor chip 5 is fixed to the circuit pattern 3 by the hardened solder 13.

The circuit board 1 of the present embodiment manufactured in this way has improved heat dissipation performance by means of the heat dissipation frame 7. In particular, the heat dissipation frame 7 is set to have a gap C with the semiconductor chip 5, an area A, and a thickness T, and the heat dissipation performance can be further improved by means of equation (2).

Figures 5 to 10 show the analysis results of the heat dissipation of Comparative Example 1 and Examples 1-1 to 1-5. Figures 5 (A) and 6 (A) are graphs showing the cross-sectional view of the circuit substrate of Comparative Example 1 and Example 1-1, together with the analysis results of the dimensions of each part, thermal conductivity, and thermal resistance; Figures 5 (B) and 6 (B) are top-view images showing the temperature distribution of the circuit substrate of Comparative Example 1 and Example 1-1, respectively.

FIG. 7(A), FIG. 8(A), FIG. 9(A) and FIG. 10(A) are graphs showing the analysis results of the thermal resistance of the circuit substrates of Examples 1-2 to 1-5, respectively; FIG. 7(B), FIG. 8(B), FIG. 9(B) and FIG. 10(B) are top-view images showing the temperature distribution of the circuit substrates of Examples 1-2 to 1-5, respectively.

The dimensions of the circuit board 1 of the comparative example 1 of FIG. 5 (A) are as follows. The thickness of the chip (semiconductor chip 5): 0.1 mm, the size in top view: 5×5 mm, and the thermal conductivity: 85 W/mK. The thickness of the solder (solder 13): 0.2 mm, and the thermal conductivity: 49 W/mK. The material of the copper circuit (circuit pattern 3): C1020, the thickness: 0.5 mm, the size: 20×20 mm, and the thermal conductivity: 390 W/mK. The material of the insulating material (insulating material 11): a resin (liquid crystal polymer) filled with aluminum oxide and boron nitride powder, the thickness: 0.12 mm, and the thermal conductivity: 7.5 W/mK. Material of copper substrate (substrate 9): C1921, thickness: 2 mm, thermal conductivity: 364 W/mK.

The analysis result of thermal resistance is T _Max at the point in the center of the front side of the semiconductor chip 5: 150.7°C, T at the point on the back side of the substrate 9 corresponding to this point _{under the copper substrate chip} : fixed 20.0°C, thermal resistance R: 0.654KW. In addition, the analysis of thermal resistance is performed under a heat of 200W. The temperature distribution at this time is shown in Figure 5 (B). Examples 1 to 5 of Example 1 are compared with this comparative example 1. In addition, in Figure 5 (B), the center is the highest temperature, and the temperature decreases toward the outside.

(Comparison between Example 1 and Comparative Example 1) Example 1 of FIG. 6 (A) is related to Example 1-1 of FIG. 3. Except for the copper plate (heat sink frame 7), the dimensions of this circuit substrate 1 are the same as those of Comparative Example 1 without a heat sink frame. Material of the copper plate (heat sink frame 7): C1020 (same as circuit pattern 3), thickness: 1.0 mm, size: 10×10 mm (hole 6×6 mm), thermal conductivity: 390 W/mK. The size of the hole indicates the size of the inner circumference of the heat sink frame 7. With the setting of the area A of the heat sink frame 7: 64 mm ² , the gap C: 0.5 mm, and the thickness T: 1 mm, the heat dissipation effect size parameter: 18.4 satisfies formula (2).

The analysis of thermal resistance was performed in the same manner as in Comparative Example 1, with a heat of 200W and a substrate bottom temperature T _{(under copper substrate wafer} ): fixed at 20.0°C. The analysis results showed that T _Max at the center point on the front surface of the semiconductor wafer 5 was 146.4°C, T _{(under copper substrate wafer)} : 20.0°C at the point on the back surface of the substrate 9 corresponding to this point, and thermal resistance R: 0.632KW. The rate of change of thermal resistance was ΔR: 0.022K/W, and the thermal resistance was reduced by 3.3% compared to Comparative Example 1. The temperature distribution at this time is as shown in Figure 6 (B).

It is obvious from FIG. 5 (A) and (B) and FIG. 6 (A) and (B) that the heat dissipation performance of Example 1-1 is improved by setting the heat dissipation frame 7 to satisfy equation (2).

The analysis result of the thermal resistance in FIG7 (A) is related to the embodiment 1-2 in FIG3. In this circuit substrate 1, the size of the copper plate (heat sink frame 7) is set to: 10×10 mm (hole 5.4×5.4 mm), and the gap is reduced compared with the embodiment 1-1 in FIG6. The area A of the heat sink frame 7 is increased to ⁷¹ mm2. The change of the gap C and the area A of the heat sink frame 7 results in a heat dissipation effect size parameter: 58.1, which satisfies the formula (2).

In this embodiment 1-2, T _Max : 144.2°C, T _{copper substrate wafer} : fixed at 20.0°C, thermal resistance R: 0.621KW. The change rate of thermal resistance is ΔR: 0.033K/W, and the thermal resistance is reduced by 5.0% compared with comparative example 1. The temperature distribution at this time is as shown in Figure 7 (B).

It is obvious from FIGS. 5(A) and (B) and FIGS. 7(A) and (B) that in Embodiment 1-2, the setting of the heat dissipation frame 7 satisfies equation (2), and the heat dissipation is further improved by reducing the gap.

The analysis result of the thermal resistance in FIG8 (A) is related to the embodiment 1-3 in FIG3. In this circuit board 1, the thickness T of the copper plate (heat dissipation frame 7) is increased to 2.0 mm compared with the embodiment 1-1 in FIG6. The change in the thickness T of the heat dissipation frame 7 results in a heat dissipation effect dimension parameter of 21.1, which satisfies the formula (2).

In this embodiment 1-3, T _Max : 146.0°C, T _{copper substrate wafer} : fixed at 20.0°C, thermal resistance R: 0.630KW. The change rate of thermal resistance is ΔR: 0.023K/W, and the thermal resistance is reduced by 3.6% compared with comparative example 1. The temperature distribution at this time is as shown in Figure 8 (B).

It is obvious from FIGS. 5(A) and (B) and FIGS. 8(A) and (B) that in Embodiment 1-3, the configuration of the heat dissipation frame 7 satisfies equation (2), and the heat dissipation performance is further improved by increasing the thickness.

The analysis result of the thermal resistance in FIG9 (A) is related to the embodiment 1-4 in FIG3. In this circuit board 1, the size of the copper plate (heat sink frame 7) is set to 20×20 mm (hole 6×6 mm) compared to the embodiment 1-1 in FIG6, and the outer diameter of the heat sink frame 7 is enlarged to increase the area. The change in the area A of the heat sink frame 7 results in a heat dissipation effect size parameter of 43.8, which satisfies the formula (2).

In this embodiment 1-4, T _Max : 144.3°C, T _{copper substrate wafer} : 20.0°C, and thermal resistance R: 0.622KW. The change rate of thermal resistance is ΔR: 0.032K/W, and the thermal resistance is reduced by 4.9% compared with comparative example 1. The temperature distribution at this time is the same as Figure 9 (B).

As can be clearly seen from FIGS. 5(A) and (B) and FIGS. 9(A) and (B), in Embodiments 1-4, the configuration of the heat dissipation frame 7 satisfies equation (2), and the heat dissipation is further improved by increasing the area toward the outer diameter.

The analysis result of the thermal resistance in FIG10 (A) is related to the embodiment 1-5 in FIG3. In this circuit board 1, the size of the copper plate (heat sink frame 7) is set to 20×20 mm (hole 5.4×5.4 mm) compared to the embodiment 1-1 in FIG6, and the outer diameter of the heat sink frame 7 is enlarged and the inner diameter is reduced to increase the area A to ³⁷¹ mm2. In addition, the gap C is reduced to 0.2 mm. The thickness T is increased to 2 mm. The heat dissipation effect size parameter 152.6 obtained by changing the area A, gap C, and thickness T of the heat sink frame 7 satisfies the formula (2).

In Example 5, T _Max : 140.1°C, T _{copper substrate wafer} : fixed at 20.0°C, thermal resistance R: 0.601K/W. The change rate of thermal resistance is ΔR: -0.031K/W, and the thermal resistance is reduced by 8.1% compared to Example 1. The temperature distribution at this time is as shown in Figure 10 (B).

It is obvious from FIG. 5 (A) and (B) and FIG. 10 (A) and (B) that due to the setting of the heat dissipation frame 7, the heat dissipation effect size parameter: 152.6 satisfies the formula (2), and the heat dissipation is further improved by increasing the area A, the thickness T, and reducing the gap C.

(Comparison between Comparison Example 1 and Comparison Examples 2 to 4) Next, compare Comparison Examples 2 to 4 with Comparison Example 1.

Figures 11 to 13 show the analysis results of the heat dissipation of Comparative Examples 2 to 4. Figures 11 (A), 12 (A) and 13 (A) are graphs showing the analysis results of the thermal resistance of the circuit substrates of Comparative Examples 2 to 4, respectively; Figures 11 (B), 12 (B) and 13 (B) show the temperature distribution of Comparative Examples 2 to 4, respectively.

The analysis result of thermal resistance in FIG11 (A) is related to the comparative example 2 in FIG3. In this circuit board 1, the size of the copper plate (heat sink frame 7) is set to 8×8 mm (hole 6×6 mm) compared to the example 1 in FIG6, and the outer diameter of the heat sink frame 7 is reduced to reduce the area A to ²⁸ mm2. Due to the change in the size of the heat sink frame 7, the heat dissipation effect size parameter: 12.2 does not satisfy the formula (2).

In this comparative example 2, T _Max : 148.4℃, T _{copper substrate wafer} : fixed at 20.0℃, thermal resistance R: 0.642K/W. The change rate of thermal resistance is ΔR: 0.010K/W, and the thermal resistance is only reduced by 1.8% compared with comparative example 1, as shown on the approximate line L1. The temperature distribution at this time is shown in Figure 11 (B).

It is obvious from FIG. 5 (A) and (B) and FIG. 11 (A) and (B) that in Comparative Example 2, due to the setting of the heat dissipation frame 7, the heat dissipation effect size parameter: 12.2 does not satisfy formula (2), and the heat dissipation performance is not improved.

The analysis result of the thermal resistance in FIG12 (A) is related to the comparative example 3 in FIG3. In this circuit board 1, the size of the copper plate (heat sink frame 7) is set to 10×10 mm (hole 7×7 mm) compared to the example 1 in FIG6, and the inner diameter of the heat sink frame 7 is enlarged to reduce the area A to ⁵¹ mm2. The gap C is enlarged to 1 mm. Due to the change in the size of the heat sink frame 7, the heat dissipation effect size parameter 7.1 obtained does not satisfy the formula (2).

In this comparative example 3, T _Max : 148.7℃, T _{copper substrate wafer} : fixed at 20.0℃, thermal resistance R: 0.643K/W. The change rate of thermal resistance is ΔR: 0.011K/W, and the thermal resistance is only reduced by 1.6% compared with comparative example 1, as shown on the approximate line L1. The temperature distribution at this time is shown in Figure 12 (B).

It is obvious from FIG. 5 (A) and (B) and FIG. 12 (A) and (B) that in Comparative Example 3, due to the setting of the heat dissipation frame 7, the heat dissipation effect size parameter: 7.1 does not satisfy formula (2), and the heat dissipation performance is not improved.

The analysis result of thermal resistance in FIG13 (A) is related to the comparative example 4 in FIG3. In this circuit board 1, the size of the copper plate (heat sink frame 7) is set to 8×8 mm (hole 6×6 mm) compared to the example 1 in FIG6, and the outer diameter of the heat sink frame 7 is reduced to reduce the area A to ²⁸ mm2. In addition, the thickness T is reduced to 0.5 mm. Due to the change in the size of the heat sink frame 7, the heat dissipation effect size parameter: 10.6 does not satisfy the formula (2).

In this comparative example 4, T _Max : 148.7℃, T _{copper substrate wafer} : fixed at 20.0℃, thermal resistance R: 0.644K/W. The change rate of thermal resistance is ΔR: 0.012K/W, and the thermal resistance is only reduced by 1.5% compared with comparative example 1, as shown on the approximate line L1. The temperature distribution at this time is shown in Figure 13 (B).

It is obvious from FIG. 5 (A) and (B) and FIG. 13 (A) and (B) that in Comparative Example 4, due to the setting of the heat dissipation frame 7, the heat dissipation effect size parameter: 10.6 does not satisfy formula (2), and the heat dissipation performance is not improved.

(Comparison of analysis results after changing heat dissipation conditions) Figure 14 (A) is a graph showing the cross-sectional view, dimensions, thermal conductivity, and analysis results of thermal resistance of the circuit substrate of Comparative Example 1 of Figure 1 (B) when the heat dissipation conditions are changed; Figure 14 (B) is a top view image showing the temperature distribution of the circuit substrate of Figure 14 (A). Figure 15 (A) is a graph showing the cross-sectional view, dimensions, thermal conductivity, and analysis results of thermal resistance of the circuit substrate of Example 1-1 of Figure 3 when the heat dissipation conditions are changed; Figure 15 (B) is a top view image showing the temperature distribution of the circuit substrate of Figure 15 (A).

Fig. 16 to Fig. 19 show the analysis results of the case where the heat dissipation conditions are changed in the circuit substrates of Examples 1-2 to 1-5 of Fig. 3. Fig. 16 (A), Fig. 17 (A), Fig. 18 (A) and Fig. 19 (A) are graphs showing the analysis results of the thermal resistance of the circuit substrates of Examples 1-2 to 1-5, respectively; Fig. 16 (B), Fig. 17 (B), Fig. 18 (B) and Fig. 19 (B) are plane images showing the temperature distribution of the circuit substrates of Examples 1-2 to 1-5, respectively.

The thermal resistance analysis in Figures 14 to 19 was performed at a heat load of 200W, and the heat dissipation conditions were that the heat transfer coefficient of the bottom surface of the substrate was h = 30000W/ ^m2.K and the heat was dissipated to 20℃.

The analysis results of thermal resistance in Comparative Example 1 are T _Max at the center point of the front surface of the semiconductor chip 5: 175.2°C, T at the point on the back surface of _{the metal substrate} 9 corresponding to this point: 53.7°C, and thermal resistance R: 0.607K/W. The temperature distribution at this time is shown in FIG14(B).

Examples 1 to 5 of Embodiment 1 were compared with Comparative Example 1 in which the heat dissipation conditions were changed as described above.

The embodiment 1-1 of Fig. 15 (A) is a circuit board 1 of the shape and size of the embodiment 1-1 of Fig. 3 with a different heat dissipation condition. The thickness and size of the heat dissipation frame 7 are set accordingly, and the heat dissipation effect dimension parameter: 18.4 and the temperature T of the bottom surface of the substrate: fixed at 20.0°C _{under the copper base chip} also satisfy the formula (2).

The analysis results of thermal resistance are T _Max at the center point of the front surface of the semiconductor chip 5: 169.6°C, T _{(copper-based chip)} at the point on the back surface of the metal substrate 9 corresponding to this point: 51.9°C, and thermal resistance R: 0.588K/W. The change rate of thermal resistance is ΔR: -0.019K/W, and the thermal resistance and the temperature of the bottom surface of the substrate T ( _{copper-based chip): fixed at} 20.0°C are similarly reduced compared to Comparative Example 1. The temperature distribution at this time is shown in FIG. 15 (B).

It is obvious from FIG. 14 (A) and (B) and FIG. 15 (A) and (B) that in Example 1-1, due to the setting of the heat dissipation frame 7, the heat dissipation effect size parameter: 18.4 satisfies the formula (2), and the heat dissipation is improved even if the heat dissipation conditions are changed.

FIG16 (A) shows a circuit board 1 of the shape and size of Example 1-2 of FIG3 with the heat dissipation conditions changed as described above. The gap C and area A of the heat dissipation frame 7 are changed relative to those of Example 1-1, and the heat dissipation effect dimension parameter: 58.1 and the temperature T of the bottom surface of the substrate: fixed at 20.0°C _{under the copper base chip} also satisfy equation (2).

The analysis results of thermal resistance are T _Max at the center point of the front surface of the semiconductor chip 5: 167.0°C, T _{(copper-based chip)} at the point on the back surface of the metal substrate 9 corresponding to this point: 51.3°C, and thermal resistance R: 0.578K/W. The change rate of thermal resistance is ΔR: -0.010K/W, and the thermal resistance and the temperature of the bottom surface of the substrate T ( _{copper-based chip): fixed at} 20.0°C are similarly reduced compared to Comparative Example 1. The temperature distribution at this time is shown in FIG. 16 (B).

It is obvious from FIG. 14 (A) and (B) and FIG. 16 (A) and (B) that in Example 1-2, due to the setting of the heat dissipation frame 7, the heat dissipation effect size parameter: 58.1 satisfies formula (2), and by reducing the gap C and increasing the area A, the heat dissipation is improved even if the heat dissipation conditions are changed.

Fig. 17 (A) is the analysis result after changing the heat dissipation conditions as described above for the circuit board 1 of the shape and size of Example 1-3 in Fig. 3. The thickness of the heat dissipation frame 7 is changed relative to that of Example 1-1, and the heat dissipation effect dimension parameter: 21.1 satisfies equation (2).

The analysis results of thermal resistance are T _Max at the center point of the front surface of the semiconductor chip 5: 169.1°C, T ( _copper-based chip) at the point on the back surface of the metal substrate 9 corresponding to this point: 51.8°C, and thermal resistance R: 0.587K/W. The change rate of thermal resistance is ΔR: -0.002K/W, and the thermal resistance and the temperature of the bottom surface of the substrate T _{(copper-based chip): fixed at} 20.0°C are similarly reduced compared to Comparative Example 1. The temperature distribution at this time is shown in FIG17 (B).

It is obvious from FIGS. 14(A) and (B) and FIGS. 17(A) and (B) that in Embodiment 1-3, due to the setting of the heat dissipation frame 7, the heat dissipation effect size parameter: 21.1 satisfies formula (2), and by increasing the thickness T, the heat dissipation is improved even if the heat dissipation conditions are changed.

FIG18(A) shows the analysis result after changing the heat dissipation conditions as described above for the circuit board 1 of the shape and size of Example 1-4 in FIG3. The area A of the heat dissipation frame 7 is changed relative to that of Example 1-1, and the heat dissipation effect size parameter: 43.8 satisfies equation (2).

The analysis results of thermal resistance are T _Max at the center point of the front surface of the semiconductor chip 5: 166.0°C, T ( _copper-based chip) at the point on the back surface of the metal substrate 9 corresponding to this point: 50.2°C, and thermal resistance R: 0.579K/W. The change rate of thermal resistance is ΔR: -0.009K/W, and the thermal resistance and the temperature of the bottom surface of the substrate T _{(copper-based chip)} : fixed at 20.0°C are similarly reduced compared to Comparative Example 1. The temperature distribution at this time is shown in FIG18 (B).

It is obvious from FIG. 14 (A) and (B) and FIG. 18 (A) and (B) that in Example 1-4, due to the setting of the heat dissipation frame 7, the heat dissipation effect size parameter: 43.8 satisfies the formula (2), and by increasing the area A, the heat dissipation is improved even if the heat dissipation conditions are changed.

FIG19 (A) is the analysis result after changing the heat dissipation conditions as described above for the circuit board 1 of the shape and size of Example 1-5 in FIG3. The area A, gap C, and thickness T of the heat dissipation frame 7 are changed relative to those of Example 1-1, and the heat dissipation effect dimensional parameter: 152.6 satisfies equation (2).

The analysis results of thermal resistance are T _Max at the center point of the front surface of the semiconductor chip 5: 160.7°C, T _{(copper-based chip)} at the point on the back surface of the metal substrate 9 corresponding to this point: 48.5°C, and thermal resistance R: 0.561K/W. The change rate of thermal resistance is ΔR: -0.027K/W, and the thermal resistance and the temperature of the bottom surface of the substrate T ( _{copper-based chip): fixed at} 20.0°C are similarly reduced compared to Comparative Example 1. The temperature distribution at this time is shown in FIG. 19 (B).

It is obvious from FIGS. 14 (A) and (B) and FIGS. 19 (A) and (B) that in Embodiment 1-5, due to the setting of the heat dissipation frame 7, the heat dissipation effect size parameter: 152.6 satisfies formula (2), and by increasing the area A and thickness T and reducing the gap C, the heat dissipation is improved even if the heat dissipation conditions are changed.

(Comparison of Comparative Examples 2 to 4 after changing the heat dissipation conditions with Comparative Example 1) Comparison of Comparative Examples 2 to 4 after changing the heat dissipation conditions as described above with Figure 14 (B) of Comparative Example 1 after changing the heat dissipation conditions as described above is performed.

Figs. 20 to 22 show the analysis results of the case where the heat dissipation conditions are changed in the circuit substrates of Comparative Examples 2 to 4 of Fig. 3. Figs. 20(A), 21(A) and 22(A) are graphs showing the analysis results of the thermal resistance of the circuit substrates of Comparative Examples 2 to 4, respectively; Figs. 20(B), 21(B) and 22(B) are top-view images showing the temperature distribution of the circuit substrates of Comparative Examples 2 to 4, respectively.

FIG20 (A) is the analysis result after changing the heat dissipation conditions as described above for the circuit board 1 of the shape and size of Comparative Example 2 in FIG3. The size of the heat dissipation frame 7 is changed relative to that of Example 1-1, and the heat dissipation effect size parameter: 12.2 and the temperature T of the bottom surface of the substrate: _{copper base wafer} : fixed at 20.0°C do not satisfy equation (2) in the same manner.

In the example where the heat dissipation conditions of Comparative Example 2 were changed as described above, T _Max : 172.3°C, T _{under copper substrate wafer} : 52.9°C, and thermal resistance R: 0.597K/W. The change rate of thermal resistance was ΔR: 0.009K/W, and the thermal resistance did not decrease compared to the example of FIG. 14 where the heat dissipation conditions of Comparative Example 1 were changed as described above. The temperature distribution at this time is shown in FIG. 20 (B).

It is obvious from FIG. 14 (A) and (B) and FIG. 20 (A) and (B) that in Comparative Example 2, due to the setting of the heat dissipation frame 7, the heat dissipation effect size parameter: 12.2 does not satisfy the formula (2), and even if the heat dissipation conditions are changed, the heat dissipation is not improved.

FIG21 (A) is the analysis result after changing the heat dissipation conditions as described above for the circuit board 1 of the shape and size of Comparative Example 3 in FIG3. The size of the heat dissipation frame 7 is changed relative to that of Example 1-1, and the heat dissipation effect size parameter: 7.1 and the temperature T of the bottom surface of the substrate: _{copper base chip: fixed at} 20.0°C do not satisfy equation (2) in the same way.

In the case where the heat dissipation conditions of Comparative Example 3 were changed as described above, T _Max : 172.4°C, T _{under copper substrate wafer} : 52.7°C, and thermal resistance R: 0.598K/W. The change rate of thermal resistance was ΔR: 0.010K/W, and the thermal resistance did not decrease compared to the case where the heat dissipation conditions of Comparative Example 1 were changed as described above. The temperature distribution at this time is shown in FIG. 21 (B).

It is obvious from FIG. 14 (A) and (B) and FIG. 21 (A) and (B) that in Comparative Example 3, due to the setting of the heat dissipation frame 7, the heat dissipation effect size parameter: 7.1 does not satisfy equation (2), and even if the heat dissipation conditions are changed, the heat dissipation is not improved.

FIG22 (A) is the analysis result after changing the heat dissipation conditions as described above for the circuit board 1 of the shape and size of Comparative Example 4 in FIG3. The size of the heat dissipation frame 7 is changed relative to that of Example 1-1, and the heat dissipation effect size parameter: 10.6 and the temperature T of the bottom surface of the substrate: _{copper base wafer} : fixed at 20.0°C do not satisfy equation (2) in the same way.

In the case where the heat dissipation conditions of Comparative Example 4 were changed as described above, T _Max : 172.7°C, T _{under copper substrate wafer} : 53.0°C, and thermal resistance R: 0.598K/W. The change rate of thermal resistance was ΔR: 0.010K/W, and the thermal resistance did not decrease compared to the case where the heat dissipation conditions of Comparative Example 1 were changed as described above. The temperature distribution at this time is shown in FIG. 22 (B).

It is obvious from FIG. 14 (A) and (B) and FIG. 22 (A) and (B) that in Comparative Example 4, due to the setting of the heat dissipation frame 7, the heat dissipation effect size parameter: 10.6 does not satisfy the formula (2), and even if the heat dissipation conditions are changed, the heat dissipation is not improved.

[Variation] Figures 23 to 26 are top views showing the relationship between the semiconductor chip and the heat sink of the circuit substrate of the variation of the first embodiment of Figure 1 (A). Figure 27 is a cross-sectional view of the circuit substrate of the variation of the first embodiment of Figure 1 (A) showing the thickness of the heat sink.

In the modification of FIG. 23 , the center of the semiconductor chip 5 is offset from the center of the outer shape of the heat sink frame 7 in a plan view. The widths of the sides of the heat sink frame 7 are B ₁ /2, B ₂ /2, B ₃ /2, and B ₄ /2. The area A of the heat sink frame 7 is the area of a square with one side B simplified based on the widths B ₁ , B ₂ , B ₃ , and B _4. The area A satisfies the equation (2) in relation to the thickness T and the gap C.

In the variation of FIG. 24 , the heat sink frame 7 has a frame shape that contains a plurality of, for example, two adjacent semiconductor chips 5. The width of each side of the heat sink frame 7 is set to B ₁ /2, B ₂ /2, B ₃ /2, B ₄ /2, B ₅ /2, B ₆ /2, B ₇ /2, and B ₈ /2. The area A of the heat sink frame 7 is the area of a square with one side B simplified based on the widths B ₁ , B ₂ , B ₃ , B ₄ , B ₅ , B ₆ , B ₇ , and B ₈ , and satisfies the formula (2) in relation to the thickness T and the gap C.

In the variation of FIG. 25 , the gap is set to be non-uniform in the circumferential direction. For example, the gap between each side of the heat sink frame 7 and each side of the semiconductor chip 5 is set to C ₄ <C ₁ <C ₂ <C ₃ . In addition, the size of the gaps C ₁ to C ₄ can be set arbitrarily, and C ₁ and C ₄ can be set to be the same, or C ₂ and C ₃ can be set to be the same. The gap C that satisfies the formula (2) is the average value C = _Cave {C ₁ , C ₂ , ...}.

In the modification of FIG26 , the heat sink frame 7 is provided in an annular frame shape relative to the semiconductor chip 5 which is rectangular in plan view. The gap C satisfying the equation (2) is the average value C=C _ave of the gaps C between each side of the semiconductor chip 5 and the inner periphery of the heat sink frame 7 .

In the variation of FIG. 27 , the thickness of the rectangular heat sink frame 7 is different in the circumferential direction, for example, the thickness of one of the facing sides is set to T ₁ > T ₂ . The thickness of the other facing side can be set to T ₁ or T ₂ . Furthermore, the thickness of the other facing side can be inclined or formed in a step-like manner in a manner connecting T ₁ and T ₂ .

In any case, the thickness T satisfying the formula (2) is an average value T=T _ave {T ₁ , T ₂ , ...}.

In addition, in Embodiment 1, the thickness T of the heat sink frame 7 is set to be larger than the thickness of the semiconductor chip 5, but as long as the heat sink effect dimension parameter satisfies the formula (2), the thickness T can be set freely.

The materials of the circuit pattern 3, the heat sink frame 7, and the base 9 are all copper, but as long as the heat dissipation effect dimension parameters satisfy formula (2) and the heat dissipation performance can be improved compared with that of comparative example 1, they can also be replaced with aluminum, aluminum alloy, or stainless steel. In this case, it is not necessary to make all of them with the same material, and the material of any one of the circuit pattern 3, the heat sink frame 7, and the base 9 can be changed relative to the other. [Example 2]

28 is a graph showing the relationship between the heat dissipation effect dimension parameter and the thermal resistance reduction rate in Example 2 when the material of the heat dissipation frame of the circuit substrate in FIG. 1 is replaced with aluminum, together with approximate lines of the comparative example and Example 1. FIG.

In addition, the basic structure of the second embodiment is the same as that of the first embodiment, and the same symbols are used to mark the same or corresponding components, and repeated descriptions are omitted.

The circuit board 1 of the second embodiment is obtained by replacing the material of the heat sink frame 7 of the first embodiment with pure aluminum (A1050). FIG. 28 shows the result.

FIG28 corresponds to FIG4 of Example 1. In FIG28, in addition to the data and approximate lines L1 and L2 of Example 1, data and approximate lines L3 and L4 of Example 2 are also shown. L3 is an approximate line of a comparative example of Example 2, and L4 is an approximate line of Example 2. The approximate lines L3 and L4 of Example 2 show the same inclination as the approximate lines L1 and L2 of Example 1.

FIG. 29(A) is a graph showing the cross-sectional view, dimensions, thermal conductivity, and analysis results of thermal resistance of the circuit substrate of Example 2-1; FIG. 29(B) is a top view showing the temperature distribution of the circuit substrate of FIG. 29(A).

The analysis result of the thermal resistance in FIG29 (A) is related to the data on the left side of the approximate line L4 in FIG28. As shown in FIG29 (A), the dimensions of the circuit substrate 1 of Example 2 are the same as those of Example 1. On the other hand, the pure aluminum plate (heat dissipation frame 7) is made of pure aluminum of material: A1050 (different from the circuit pattern 3), and the thermal conductivity is 220 W/mK. By setting the thickness and dimensions of the heat dissipation frame 7, the heat dissipation effect dimension parameter is 18.4 and satisfies formula (2).

The analysis of thermal resistance was performed with a heat of 200W and the temperature of the bottom surface _of the substrate was fixed at 20.0°C. The analysis results showed that the T _Max at the center point of the front surface of the semiconductor chip 5 was 147.7°C, the T at the back surface of _the substrate 9 corresponding to this point was 20.0°C, and the thermal resistance R was 0.638KW. The thermal resistance was reduced by 2.4% compared to the comparative example 1. The temperature distribution at this time is shown in Figure 29 (B).

It is obvious from FIGS. 5(A) and (B) and FIGS. 29(A) and (B) that even when the material of the heat dissipation frame 7 is replaced with pure aluminum, the heat dissipation performance is improved by satisfying equation (2).

FIG. 30(A) is a graph showing the analysis results of the thermal resistance of the circuit substrate of Example 2-2; FIG. 30(B) is a top view showing the temperature distribution of the circuit substrate of FIG. 30(A).

The analysis result of the thermal resistance in FIG30 (A) is related to the data on the right side of the approximate line L4 in FIG28. In this circuit board 1, the size of the pure aluminum plate (heat sink frame 7) is 20×20 mm (hole 5.4×5.4 mm), and the thickness is 2.0 mm. Compared with the example in FIG29, the gap is reduced and the area of the heat sink frame 7 is increased toward the outer diameter side and the thickness is increased. The change in the gap C, area A, and thickness T of the heat sink frame 7 results in a heat dissipation effect size parameter of 152.6, which satisfies equation (2).

In this example, T _Max : 143.0°C, T _{copper substrate wafer} : 20.0°C (fixed), and thermal resistance R: 0.615KW. The change rate of thermal resistance is ΔR: 0.023K/W, and the thermal resistance is reduced by 5.9% compared with comparative example 1. The temperature distribution at this time is shown in Figure 30 (B).

As is apparent from FIGS. 5(A) and (B) and FIGS. 30(A) and (B), in Example 2-2, even when the material of the heat dissipation frame 7 is replaced with pure aluminum, formula (2) is satisfied, and the heat dissipation is further improved by reducing the gap and increasing the area toward the outer diameter.

FIG. 31(A) is a graph showing the analysis results of the thermal resistance of the circuit substrate of Comparative Example 2-1 of Example 2; and FIG. 31(B) is a top view showing the temperature distribution of the circuit substrate of FIG. 31(A).

The analysis result of the thermal resistance in FIG31 (A) is related to the data of the comparative example on the approximate line L3 in FIG28. In this circuit board 1, the size of the pure aluminum plate (heat sink frame 7) is 10×10 mm (hole 7×7 mm) and the thickness is 1.0 mm. The gap is enlarged and the area of the heat sink frame 7 is reduced compared to the example in FIG29. The change in the gap C and the area A of the heat sink frame 7 results in a heat dissipation effect size parameter of 7.1, which does not satisfy the formula (2).

In this comparative example, T _Max : 149.3℃, T _{under copper substrate wafer} : 20.0℃ (fixed), and thermal resistance R: 0.647KW. The change rate of thermal resistance is ΔR: 0.008K/W, and the thermal resistance is only reduced by 1.0% compared with comparative example 1. The temperature distribution at this time is shown in Figure 31 (B).

As is apparent from FIGS. 5(A) and (B) and FIGS. 31(A) and (B), even when the material of the heat sink frame 7 is replaced with pure aluminum, if the gap is increased and the area is reduced, equation (2) is not satisfied and no improvement in heat dissipation is observed.

In this way, even if the material of the heat dissipation frame 7 is changed, the same effect can be obtained, and even if the material of the heat dissipation frame 7 is set to be different from that of the circuit pattern 3, the same effect can be obtained.

Fig. 32 to Fig. 34 correspond to Fig. 29 to Fig. 31, and show the embodiments 2-3, 2-4 and the comparative example 2-2. In the analysis of Fig. 32 to Fig. 34, the other shapes, structures, materials (pure aluminum of the heat sink frame 7) of the circuit board are not changed. The heat dissipation conditions are that the heat transfer coefficient of the bottom surface of the substrate is h = 30000 W/ ^m2.K and placed at 20℃.

If FIG. 29 (B) is compared with FIG. 32 (B), FIG. 30 (B) is compared with FIG. 33 (B), and FIG. 31 (B) is compared with FIG. 34 (B), the heat dissipation results of FIG. 32 and FIG. 33 for the comparison example of FIG. 34 correspond to the heat dissipation results of FIG. 29 and FIG. 30 for the comparison example of FIG. 31.

That is, the improvement in heat dissipation of Example 2 was achieved regardless of whether the bottom surface of the circuit board was fixed at 20°C or left at 20°C.

In addition, in this embodiment 2, the same effects as those in embodiment 1 can also be obtained.

1: Circuit board 3: Circuit pattern 3a: Front 5: Semiconductor chip, electronic components 5a: Front 7: Heat sink 7a: Lower surface 7b: Upper surface 8: Insulating substrate 9: Base, metal base 11: Insulating material 13: Solder A: Area B, B ₁ , B ₂ , B ₃ , B ₄ , B ₅ , B ₆ , B ₇ , B ₈ : Width C, C ₁ , C ₂ , C ₃ , C ₄ : Gap L1, L2, L3, L4: Approximate line R: Configuration area T, T ₁ , T ₂ : Thickness

FIG. 1 (A) is a cross-sectional view of a circuit substrate with a heat dissipation frame of Example 1 of the present invention; FIG. 1 (B) is a cross-sectional view of a circuit substrate without a heat dissipation frame of Comparative Example 1. FIG. 2 is a graph showing the rate of change of thermal resistance with respect to the area A [mm ² ], gap C [mm] and thickness T [mm] of the lower surface of the heat dissipation frame of the circuit substrate of FIG. 1 (A). FIG. 3 is a graph showing the relationship between the area A [mm ² ], gap C [mm] and thickness T [mm] of the circuit substrate of FIG. 1 (A) and the heat dissipation effect size parameter and the thermal resistance reduction rate together with the comparative example. FIG. 4 is a graph showing the relationship between the heat dissipation effect size parameter and the thermal resistance reduction rate of the circuit substrate of FIG. 1 (A) together with the comparative example. FIG. 5 (A) is a graph showing the cross-sectional view, dimensions, thermal conductivity, and analysis results of thermal resistance of the circuit substrate of the comparative example 1 without a heat sink of FIG. 1 (B); FIG. 5 (B) is a top view image showing the temperature distribution of the circuit substrate of FIG. 5 (A). FIG. 6 (A) is a graph showing the cross-sectional view, dimensions, thermal conductivity, and analysis results of thermal resistance of the circuit substrate of Example 1 of Example 1 of FIG. 3; FIG. 6 (B) is a top view image showing the temperature distribution of the circuit substrate of FIG. 6 (A). FIG. 7 (A) is a graph showing the analysis results of thermal resistance of the circuit substrate of Example 2 of Example 1 of FIG. 3; FIG. 7 (B) is a top view image showing the temperature distribution of the circuit substrate of FIG. 7 (A). FIG8(A) is a graph showing the analysis results of the thermal resistance of the circuit substrate of Example 3 of Example 1 of FIG3 ; FIG8(B) is a top view image showing the temperature distribution of the circuit substrate of FIG8(A) . FIG9(A) is a graph showing the analysis results of the thermal resistance of the circuit substrate of Example 4 of Example 1 of FIG3 ; FIG9(B) is a top view image showing the temperature distribution of the circuit substrate of FIG9(A) . FIG10(A) is a graph showing the analysis results of the thermal resistance of the circuit substrate of Example 5 of Example 1 of FIG3 ; FIG10(B) is a top view image showing the temperature distribution of the circuit substrate of FIG10(A) . FIG. 11 (A) is a graph showing the analysis results of the thermal resistance of the circuit substrate of Comparative Example 2 of FIG. 3 ; FIG. 11 (B) is a top view image showing the temperature distribution of the circuit substrate of FIG. 11 (A) . FIG. 12 (A) is a graph showing the analysis results of the thermal resistance of the circuit substrate of Comparative Example 3 of FIG. ; FIG. 12 (B) is a top view image showing the temperature distribution of the circuit substrate of FIG. 12 (A) . FIG. 13 (A) is a graph showing the analysis results of the thermal resistance of the circuit substrate of Comparative Example 4 of FIG. 3 ; FIG. 13 (B) is a top view image showing the temperature distribution of the circuit substrate of FIG. 13 (A) . FIG. 14 (A) is a graph showing the cross-sectional view, dimensions, thermal conductivity, and analysis results of thermal resistance when the heat dissipation conditions of the circuit substrate of Comparative Example 1 of FIG. 1 (B) are shown; FIG. 14 (B) is a top view image showing the temperature distribution of the circuit substrate of FIG. 14 (A). FIG. 15 (A) is a graph showing the cross-sectional view, dimensions, thermal conductivity, and analysis results of thermal resistance when the heat dissipation conditions of the circuit substrate of Example 1 of Embodiment 1 of FIG. 1 (A) and FIG. 3 are shown; FIG. 15 (B) is a top view image showing the temperature distribution of the circuit substrate of FIG. 15 (A). FIG. 16 (A) is a graph showing the analysis results of thermal resistance when the heat dissipation conditions are changed in the circuit substrate of Example 2 of Example 1 of FIG. 3 ; FIG. 16 (B) is a top view image showing the temperature distribution of the circuit substrate of FIG. 16 (A) . FIG. 17 (A) is a graph showing the analysis results of thermal resistance when the heat dissipation conditions are changed in the circuit substrate of Example 3 of Example 1 of FIG. 3 ; FIG. 17 (B) is a top view image showing the temperature distribution of the circuit substrate of FIG. 17 (A) . FIG. 18 (A) is a graph showing the analysis results of thermal resistance when the heat dissipation conditions are changed in the circuit substrate of Example 4 of Example 1 of FIG. 3 ; FIG. 18 (B) is a top view image showing the temperature distribution of the circuit substrate of FIG. 18 (A) . FIG. 19 (A) is a graph showing the analysis results of thermal resistance when the heat dissipation conditions are changed in the circuit substrate of Example 5 of Example 1 of FIG. 3 ; FIG. 19 (B) is a top view image showing the temperature distribution of the circuit substrate of FIG. 19 (A) . FIG. 20 (A) is a graph showing the analysis results of thermal resistance when the heat dissipation conditions are changed in the circuit substrate of Comparative Example 2 of FIG. 3 ; FIG. 20 (B) is a top view image showing the temperature distribution of the circuit substrate of FIG. 20 (A) . FIG. 21 (A) is a graph showing the analysis results of thermal resistance when the heat dissipation conditions are changed in the circuit substrate of Comparative Example 3 of FIG. 3 ; FIG. 21 (B) is a top view image showing the temperature distribution of the circuit substrate of FIG. 21 (A) . FIG. 22 (A) is a graph showing the analysis results of thermal resistance when the heat dissipation conditions are changed in the circuit substrate of Comparative Example 4 of FIG. 3 ; FIG. 22 (B) is a top view image showing the temperature distribution of the circuit substrate of FIG. 22 (A). FIG. 23 is a top view showing the relationship between the semiconductor chip and the heat dissipation frame of the circuit substrate of the modified example of Example 1 of FIG. 1 (A). FIG. 24 is a top view showing the relationship between the semiconductor chip and the heat dissipation frame of the circuit substrate of the modified example of Example 1 of FIG. 1 (A). FIG. 25 is a top view showing the relationship between the semiconductor chip and the heat dissipation frame of the circuit substrate of the modified example of Example 1 of FIG. 1 (A). FIG. 26 is a top view showing the relationship between the semiconductor chip and the heat dissipation frame of the circuit substrate of the modified example of Example 1 of FIG. 1 (A). FIG. 27 is a top view showing the relationship between the semiconductor chip and the heat sink of the circuit substrate of the variant of Example 1 of FIG. 1 (A). FIG. 28 is a graph showing the relationship between the heat dissipation effect dimension parameter and the thermal resistance reduction rate of the circuit substrate of Example 2, together with the approximate lines of the comparative example and Example 1. FIG. 29 (A) is a graph showing the cross-sectional view, dimensions, thermal conductivity, and analysis results of thermal resistance of the circuit substrate of Example 2; FIG. 29 (B) is a top view image showing the temperature distribution of the circuit substrate of FIG. 29 (A). FIG. 30 (A) is a graph showing the analysis results of the thermal resistance of the circuit substrate of Example 2; FIG. 30 (B) is a top view image showing the temperature distribution of the circuit substrate of FIG. 30 (A). FIG. 31 (A) is a graph showing the analytical results of the thermal resistance of the circuit substrate of the comparative example of Example 2; FIG. 31 (B) is a top view image showing the temperature distribution of the circuit substrate of FIG. 31 (A). FIG. 32 (A) is a graph showing the analytical results of the cross-sectional view, dimensions, thermal conductivity, and thermal resistance of the circuit substrate of Example 2 with changed heat dissipation conditions; FIG. 32 (B) is a top view image showing the temperature distribution of the circuit substrate of FIG. 32 (A). FIG. 33 (A) is a graph showing the analytical results of the thermal resistance of the circuit substrate of Example 2 with changed heat dissipation conditions; FIG. 33 (B) is a top view image showing the temperature distribution of the circuit substrate of FIG. 33 (A). FIG. 34(A) is a graph showing the analysis results of the thermal resistance of the circuit substrate of the comparative example of Example 2 in which the heat dissipation conditions are changed; and FIG. 34(B) is a top view image showing the temperature distribution of the circuit substrate of FIG. 34(A).

1: Circuit board

3: Circuit diagram

3a: Front

5: Semiconductor chips, electronic parts

5a: Front

7: Heat sink

7a: Lower surface

7b: Upper surface

8: Insulating substrate

9: Base, metal base

11: Insulation material

13: Solder

A: Area

C: Gap

R: Configuration area

T:Thickness

Claims (10)

A circuit substrate comprises: a circuit pattern disposed on an insulating substrate; an electronic component bonded to the circuit pattern; and a heat sink bonded to the circuit pattern and arranged adjacent to the electronic component, wherein when a gap between a lower portion of the heat sink frame and the electronic component is set to C [mm], an area of a lower surface of the heat sink frame is set to A [mm ² ], and a thickness of the heat sink frame relative to the circuit pattern is set to T [mm], 15.0≦A ^0.5 ×C ^{- 1.2} ×T ^0.2 ≦600 is satisfied. The circuit substrate as described in claim 1, wherein the heat sink frame is made of copper or aluminum. A circuit substrate as described in claim 1 or 2, wherein the electronic component is joined to the circuit pattern by solder, and the heat sink is facing the solder in the surface direction of the circuit pattern. A circuit substrate as described in claim 1 or 2, wherein the heat dissipation frame is a positioning frame for the electronic component. A circuit substrate as described in claim 1 or 2, wherein the heat sink frame is configured to have a frame shape in which the center of the electronic component in a plan view is offset relative to the center of the outer shape of the heat sink frame. A circuit substrate as described in claim 1 or 2, wherein the heat dissipation frame is configured to be in the shape of a frame containing a plurality of the electronic components therein. A circuit substrate as described in claim 1 or 2, wherein the heat sink frame is configured to have a frame shape that makes the gap non-uniform in the circumferential direction. A circuit substrate as described in claim 1 or 2, wherein the heat dissipation frame is configured to be an annular frame shape. A circuit substrate as described in claim 1 or 2, wherein the thickness of the heat sink frame is different in the circumferential direction. A semi-finished product of a circuit substrate, which is a semi-finished product of a circuit substrate as described in claim 1 or 2, and comprises: a circuit pattern, which is arranged on an insulating substrate through an insulating material; and a heat sink, which is arranged adjacent to a configuration area of electronic components to be joined to the circuit pattern, and when a gap between a lower portion of the heat sink frame and the configuration area is set to C [mm], an area of a lower surface of the heat sink frame is set to A [mm ² ], and a thickness of the heat sink frame relative to the circuit pattern is set to T [mm], 15.0≦A ^0.5 ×C ^{- 1.2} ×T ^0.2 ≦600 is satisfied.

Images