TW202422768A - Operation method of semiconductor substrate alignment apparatus, semiconductor substrate and menufacturing method of semiconductor substrate - Google Patents

Abstract

An operation method of a semiconductor substrate alignment apparatus includes using a rotary chuck to attach a semiconductor substrate, in which the semiconductor substrate has a flat edge and a roughening pattern adjacent to the flat edge; using a light source to send a light beam to the area adjacent to the flat edge of the semiconductor substrate, such that part of the light beam is reflected by the roughening pattern, in which the light source is located at a side of the rotary chuck and above the roughening pattern of the semiconductor substrate; and using a sensor below the light source to receive the other part of the light beam that is not reflected by the roughening pattern.

Description

Operating method of semiconductor substrate alignment equipment, semiconductor substrate and method for manufacturing semiconductor substrate

The present disclosure relates to an operating method of a semiconductor alignment device, a semiconductor substrate and a manufacturing method of the semiconductor substrate.

During the exposure or deposition process, the semiconductor substrate needs to be rotated to the corresponding direction in order to proceed correctly. In the past, the way to judge the semiconductor substrate was to use optical methods to judge whether the flat edge was rotated to the right position. However, for silicon carbide (SiC) substrates, because its energy gap is larger than that of silicon substrates, and the light transmittance of silicon carbide substrates is high, light can easily pass through the substrate to the optical detector under the substrate, making it impossible to judge whether the flat edge has been positioned. In the past, the only way to successfully judge whether the flat edge has been rotated to the right position was to adjust the sensitivity of the optical detector.

One technical aspect of the present disclosure is an operating method of a semiconductor substrate alignment device.

An operating method of a semiconductor substrate alignment device includes: using a rotating stage to adsorb a semiconductor substrate, wherein the semiconductor substrate has a flat edge and a roughened pattern adjacent to the flat edge; using a light source to emit light to an area adjacent to the flat edge of the semiconductor substrate so that part of the light is reflected by the roughened pattern, wherein the light source is located on one side of the rotating stage and above the roughened pattern of the semiconductor substrate; and using a detector located below the light source to receive the remaining part of the light that is not reflected by the roughened pattern.

In an embodiment of the present disclosure, the operating method of the semiconductor substrate alignment apparatus further includes overlapping the detector with the roughened pattern of the semiconductor substrate in a vertical direction.

In an embodiment of the present disclosure, the operating method of the semiconductor substrate alignment device further includes overlapping the light source with the roughened pattern of the semiconductor substrate in a vertical direction.

In an embodiment of the present disclosure, the operating method of the semiconductor substrate alignment device further includes overlapping the light source with the detector in a vertical direction.

In an embodiment of the present disclosure, the operating method of the semiconductor substrate alignment apparatus further includes disposing the detector so that it does not overlap with the rotating stage in the vertical direction.

In an embodiment of the present disclosure, the operating method of the semiconductor substrate alignment apparatus further includes arranging the light source so that it does not overlap with the rotating stage in the vertical direction.

In one embodiment of the present disclosure, the diameter of the rotating stage is smaller than the diameter of the semiconductor substrate, so that the flat edge and the roughened pattern of the semiconductor substrate protrude from the rotating stage and are suspended.

Another technical aspect of the present disclosure is a semiconductor substrate.

According to an embodiment of the present disclosure, a semiconductor substrate includes a flat edge and a roughened pattern. The flat edge is located at the edge of the semiconductor substrate. The roughening pattern is adjacent to the flat edge of the semiconductor substrate and is configured to reflect light, wherein the roughening pattern includes at least one convex portion and at least one concave portion surrounding the convex portion.

In an embodiment of the present disclosure, the roughening pattern has a square shape in top view.

In an embodiment of the present disclosure, the roughening pattern is circular in top view.

In an embodiment of the present disclosure, the roughening pattern is in the shape of a plurality of concentric circles in top view.

In an embodiment of the present disclosure, the top view shape of the roughening pattern is a plurality of squares, and the squares are arranged in an array.

In an embodiment of the present disclosure, the roughening pattern has a cross shape in top view.

In an embodiment of the present disclosure, the ratio of the distance between two opposite sidewalls of the roughening pattern to the length of the roughening pattern is between 0.1 and 0.6.

In one embodiment of the present disclosure, the ratio of the height to the length of the roughening pattern is between 0.15 and 0.65.

In one embodiment of the present disclosure, the length of the roughening pattern is in the range of 340 nm to 600 nm.

In one embodiment of the present disclosure, the material of the semiconductor substrate includes silicon carbide or sapphire so that the energy gap thereof is larger than the energy gap of silicon.

Another technical aspect of the present disclosure is a method for manufacturing a semiconductor substrate.

According to an embodiment of the present disclosure, a method for manufacturing a semiconductor substrate includes: coating a photoresist on a semiconductor substrate, wherein the semiconductor substrate has a flat edge; exposing the photoresist to form a patterned photoresist adjacent to the flat edge of the semiconductor substrate; etching the semiconductor substrate using the patterned photoresist to form a roughened pattern, wherein the roughened pattern is configured to reflect light; and removing the photoresist.

In one embodiment of the present disclosure, the photoresist is exposed using electron beam exposure.

In one embodiment of the present disclosure, etching a semiconductor substrate using a patterned photoresist is performed using focused ion beam etching or laser engraving.

In the above-mentioned embodiment of the present disclosure, since a roughening pattern is formed next to the flat edge of the semiconductor substrate, during alignment, light from a light source above the substrate can be effectively reflected back by the roughening pattern, thereby allowing an optical detector below the substrate to detect that part of the light is reflected back, thereby serving as a basis for determining whether the flat edge has reached the positioning.

The embodiments disclosed below provide many different embodiments, or examples, for implementing the different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these examples are only examples and are not intended to be limiting. In addition, the present invention may repeat component symbols and/or letters in each example. This repetition is for the purpose of simplicity and clarity, and does not itself specify the relationship between the various embodiments and/or configurations discussed.

Spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein for descriptive purposes to describe the relationship of one element or feature to another element or feature as illustrated in the accompanying figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

FIG. 1 shows a side view of a semiconductor substrate alignment device 100 according to an embodiment of the present disclosure. FIG. 2 shows a top view of the semiconductor substrate 120 of FIG. 1. Referring to FIG. 1 and FIG. 2 simultaneously, the semiconductor substrate alignment device 100 includes a rotating stage 110, a light source 130, and a detector 140. The rotating stage 110 is configured to adsorb a semiconductor substrate 120, wherein the semiconductor substrate 120 has a flat edge 121 and a roughened pattern 122 adjacent to the flat edge 121. The light source 130 is located on one side of the rotating stage 110 and above the roughened pattern 122 of the semiconductor substrate 120, and is configured to emit light L1 to an area adjacent to the flat edge 121 of the semiconductor substrate 120, wherein the roughened pattern 122 is configured to reflect a portion L2 of the light L1. The detector 140 is located below the light source 130 and is configured to receive the remaining portion of the light L1 that is not reflected by the roughened pattern 122 .

The operation method of the semiconductor substrate alignment device 100 may include the following steps. First, the semiconductor substrate 120 is adsorbed by the rotating stage 110. Then, the light source 130 is used to emit light L1 to the area of the flat edge 121 of the semiconductor substrate 120, so that a part L2 of the light L1 is reflected by the roughening pattern 122. Then, the detector 140 is used to receive the remaining part of the light L1 that is not reflected by the roughening pattern 122.

During operation, the detector 140 overlaps with the roughened pattern 122 of the semiconductor substrate 120 in the vertical direction. The light source 130 overlaps with the roughened pattern 122 of the semiconductor substrate 120 in the vertical direction. The light source 130 overlaps with the detector 140 in the vertical direction. In addition, the detector 140 can be set at a position that does not overlap with the rotating stage 110 in the vertical direction. The light source 130 can be set at a position that does not overlap with the rotating stage 110 in the vertical direction. The diameter of the rotating stage 110 is smaller than the diameter of the semiconductor substrate 120, so when the rotating stage 110 is used to absorb the semiconductor substrate 120, the flat edge 121 and the roughened pattern 122 of the semiconductor substrate 120 can protrude from the rotating stage 110 and be suspended.

In some embodiments, the material of the semiconductor substrate 120 includes silicon carbide (SiC) or sapphire, so that its energy gap is larger than that of silicon (Si), but it can also be other semiconductor materials with higher light transmittance. Such a design allows the light source 130 to directly illuminate the semiconductor substrate 120, and reflect a portion L2 of the light L1 back through the roughened pattern 122 adjacent to the flat edge 121 of the semiconductor substrate 120, so that the detector 140 can determine whether the flat edge 121 of the semiconductor substrate 120 is aligned. Since the material of the semiconductor substrate 120 has high light transmittance, the light L1 will directly penetrate the semiconductor substrate 120 before the flat edge 121 of the semiconductor substrate 120 is aligned. Only when the flat edge 121 is aligned, the roughened pattern 122 adjacent to the flat edge 121 of the semiconductor substrate 120 will reflect the light L1 of the largest portion L2. The detector 140 located below the semiconductor substrate 120 can determine whether the flat edge 121 of the semiconductor substrate 120 is aligned based on the amount of light transmittance. In this embodiment, the detector 140 can be a charge coupled device (CCD), but this is not intended to limit the present disclosure.

Specifically, since the roughened pattern 122 is formed next to the flat edge 121 of the semiconductor substrate 120, during alignment, the light L1 from the light source 130 above the semiconductor substrate 120 can be effectively reflected back by the roughened pattern 122, thereby allowing the detector 140 below the substrate to detect that part L2 of the light L1 is reflected back, thereby serving as a basis for determining whether the flat edge 121 has reached the positioning.

It should be understood that the connection relationship and function of the components described above will not be repeated, and it is better to explain them first. In the following description, various roughening patterns of semiconductor substrates will be described.

FIG. 3 and FIG. 4 illustrate three-dimensional views of roughening patterns 122, 122a according to different implementations of the present disclosure. Referring to FIG. 2, FIG. 3 and FIG. 4, the semiconductor substrate 120 includes a flat edge 121 and a roughening pattern 122. The flat edge 121 is located at the edge of the semiconductor substrate 120. The roughening pattern 122 is adjacent to the flat edge 121 of the semiconductor substrate 120 and is configured to reflect light L1 (see FIG. 1), wherein the roughening pattern 122 includes at least one convex portion 123 and at least one concave portion 124 surrounding the convex portion 123. In FIG. 3, the convex portion 123 and the concave portion 124 can define a cube, so that the top view shape of the roughening pattern 122 is a square. In FIG. 4 , the roughening pattern 122a includes at least one convex portion 123a and at least one concave portion 124a surrounding the convex portion 123a. The convex portion 123a and the concave portion 124a may define a cylinder, so that the roughening pattern 122a is circular in top view.

FIG. 5 and FIG. 6 show top views of roughening patterns 122b and 122c according to different embodiments of the present disclosure. Referring to FIG. 5, the roughening pattern 122b includes a plurality of convex portions 123b and a plurality of concave portions 124b surrounding the convex portions 123b, and the convex portions 123b and the concave portions 124b can make the top view shape of the roughening pattern 122b a plurality of concentric circles. Referring to FIG. 6, the roughening pattern 122c includes a plurality of convex portions 123c and a plurality of concave portions 124c surrounding the convex portions 123c, and the convex portions 123c and the concave portions 124c can make the top view shape of the roughening pattern 122c a plurality of squares, and the squares are arranged in an array. In some implementations, the three-dimensional image of each of the array-arranged protrusions 123c may be the protrusion 123 of FIG. 3 .

FIG. 7 shows a three-dimensional diagram of a roughening pattern 122d according to another embodiment of the present disclosure. FIG. 8 and FIG. 9 show the reflectivity distribution diagram of the roughening pattern 122d of FIG. 7 at a specific length L according to the ratio of the distance W between the two opposite side walls to the length L to the ratio of the height H to the length L. Refer to FIG. 7 to FIG. 9 simultaneously. The roughening pattern 122d includes a convex portion 123d and at least one concave portion 124d surrounding the convex portion 123d, and the top view shape of the roughening pattern 122d is a cross. The ratio of the distance W between the two opposite side walls of the roughening pattern 122d to the length L of the roughening pattern is between 0.1 and 0.6. The ratio of the height H to the length L of the roughening pattern 122d is between 0.15 and 0.65. Within this range, the reflectivity of the roughened pattern 122d can be increased to close to 1, and can almost completely reflect back a portion L2 of the light L1 directly incident on the roughened pattern 122d (see FIG. 1 ), so that the detector 140 can determine that a portion L2 of the light L1 is reflected, and use this as a basis for determining whether the flat edge 121 of the semiconductor substrate 120 is aligned.

FIG. 10 shows the reflectivity distribution diagram of the roughened pattern 122d of FIG. 7 at a specific ratio of height H to length L, according to different ratios of length L to the distance W between the two opposite side walls and length L. Referring to FIG. 7 and FIG. 10 at the same time, the length L of the roughened pattern 122d is in the range of 340 nm to 600 nm. In this range, the reflectivity of the roughened pattern 122d can be increased to nearly 1, and the portion L2 (see FIG. 1) of the light L1 directly incident on the roughened pattern 122d can be almost completely reflected back, so that the detector 140 can determine that a portion L2 of the light L1 is reflected, thereby serving as a basis for determining whether the flat edge 121 of the semiconductor substrate 120 is aligned.

In the following description, a method for manufacturing a semiconductor substrate will be described.

FIG. 11 to FIG. 14 are cross-sectional views of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure at an intermediate stage. Referring to FIG. 11 , the method for manufacturing a semiconductor substrate 120 includes coating a photoresist 150 on the semiconductor substrate 120, wherein the semiconductor substrate 120 has a flat edge 121 (see FIG. 1 ). The purpose of coating the photoresist 150 is to form a roughening pattern 122 (see FIG. 1 ) adjacent to the flat edge 121 of the semiconductor substrate 120 in the subsequent etching.

12 , after the photoresist 150 is coated, the photoresist 150 is exposed to form a patterned photoresist 150 adjacent to the flat edge 121 of the semiconductor substrate 120. The photoresist 150 may be exposed using electron beam lithograph exposure, but is not limited to this method.

Referring to FIG. 13 , after forming the patterned photoresist 150, the semiconductor substrate 120 is etched using the patterned photoresist 150 to form a roughened pattern 122, wherein the roughened pattern 122 is configured to reflect the light L1 (see FIG. 1 ). The etching of the semiconductor substrate 120 using the patterned photoresist 150 may use focused ion beam etching (FIB etching) or laser engraving.

Referring to FIG. 1, FIG. 2 and FIG. 14 at the same time, the photoresist 150 is then removed. After this step is completed, the semiconductor substrate 120 of FIG. 2 is manufactured. Since the roughening pattern 122 is formed by etching next to the flat edge 121 of the semiconductor substrate 120, the light L1 from the light source 130 above the semiconductor substrate 120 can be effectively reflected back by the roughening pattern 122 during alignment, so that the detector 140 below the substrate can only detect the remaining unreflected light L1, which serves as a basis for judging whether the flat edge 121 has reached the position. The roughening pattern 122 can have shapes and arrangements such as those shown in FIG. 3 to FIG. 7 according to different wavelengths of the light L1, depending on the design requirements.

In summary, since the roughened pattern 122 is formed by etching next to the flat edge 121 of the semiconductor substrate 120, during alignment, the light L1 from the light source 130 above the semiconductor substrate 120 can be effectively reflected back by the roughened pattern 122, thereby allowing the detector 140 below the substrate to detect that a portion L2 of the light L1 is reflected back, thereby serving as a basis for determining whether the flat edge 121 has reached the positioning. By measuring the reflectivity, the ratio of the distance W between the two opposite side walls of the roughened pattern 122d to the length L, the ratio of the height H to the length L, and the most suitable size range of the length L are defined, so that the reflectivity of the roughened pattern 122d can be increased to close to 1, and almost all of the part L2 of the light L1 directly hitting the roughened pattern 122d can be reflected back.

The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and/or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications here without departing from the spirit and scope of the present disclosure.

100: semiconductor substrate alignment equipment 110: rotating stage 120: semiconductor substrate 121: flat edge 122: roughening pattern 123, 123a, 123b, 123c, 123d: convex part 124, 124a, 124b, 124c, 124d: concave part 130: light source 140: detector 150: photoresist L1: light L2: part W: distance H: height L: length

The disclosure is best understood from the following embodiments when read in conjunction with the accompanying illustrations. Note that various features are not drawn to scale, in accordance with standard practice in the industry. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 illustrates a side view of a semiconductor substrate alignment apparatus according to one embodiment of the disclosure. FIG. 2 illustrates a top view of the semiconductor substrate of FIG. 1. FIG. 3 and FIG. 4 illustrate three-dimensional views of roughening patterns according to different embodiments of the disclosure. FIG. 5 and FIG. 6 illustrate top views of roughening patterns according to different embodiments of the disclosure. FIG. 7 illustrates a three-dimensional view of a roughening pattern according to another embodiment of the disclosure. FIG. 8 and FIG. 9 show the reflectivity distribution diagram of the roughening pattern of FIG. 7 at a specific length according to the ratio of the distance between the two opposite side walls to the length to the ratio of the height to the length. FIG. 10 shows the reflectivity distribution diagram of the roughening pattern of FIG. 7 at a specific height to length ratio according to the ratio of the distance between the two opposite side walls to the length. FIG. 11 to FIG. 14 show cross-sectional views of the manufacturing method of a semiconductor substrate according to one embodiment of the present disclosure in the middle process.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

100: Semiconductor substrate alignment equipment

110: Rotating stage

120:Semiconductor substrate

122: Roughening pattern

130: Light source

140: Detector

L1: Light

L2: Partial

Claims (20)

A method for operating a semiconductor substrate alignment device comprises: Using a rotating stage to absorb a semiconductor substrate, wherein the semiconductor substrate has a flat edge and a roughened pattern adjacent to the flat edge; Using a light source to emit a light to an area adjacent to the flat edge of the semiconductor substrate, so that a part of the light is reflected by the roughened pattern, wherein the light source is located on one side of the rotating stage and above the roughened pattern of the semiconductor substrate; and Using a detector located below the light source to receive the remaining part of the light that is not reflected by the roughened pattern. The method for operating the semiconductor substrate alignment device as described in claim 1 further includes: Overlapping the detector with the roughened pattern of the semiconductor substrate in the vertical direction. The operating method of the semiconductor substrate alignment device as described in claim 1 further includes: Overlapping the light source with the roughened pattern of the semiconductor substrate in the vertical direction. The operating method of the semiconductor substrate alignment device as described in claim 1 further includes: Overlapping the light source with the detector in the vertical direction. The operating method of the semiconductor substrate alignment device as described in claim 1 further includes: The detector is arranged so that it does not overlap with the rotating stage in the vertical direction. The operating method of the semiconductor substrate alignment device as described in claim 1 further includes: The light source is arranged so that it does not overlap with the rotating stage in the vertical direction. An operating method for a semiconductor substrate alignment device as described in claim 1, wherein the diameter of the rotating stage is smaller than the diameter of the semiconductor substrate, and the rotating stage is used to adsorb the semiconductor substrate so that the flat edge and the roughened pattern of the semiconductor substrate protrude from the rotating stage and are suspended. A semiconductor substrate comprises: a flat edge located at the edge of the semiconductor substrate; and a roughening pattern adjacent to the flat edge of the semiconductor substrate, configured to reflect light, wherein the roughening pattern comprises at least one convex portion and at least one concave portion surrounding the convex portion. A semiconductor substrate as described in claim 8, wherein the top view shape of the roughening pattern is a square. A semiconductor substrate as described in claim 8, wherein the top view shape of the roughening pattern is circular. A semiconductor substrate as described in claim 8, wherein the top view shape of the roughening pattern is a plurality of concentric circles. A semiconductor substrate as described in claim 8, wherein the top-view shape of the roughening pattern is a plurality of squares, and the squares are arranged in an array. A semiconductor substrate as described in claim 8, wherein the top view shape of the roughening pattern is a cross. A semiconductor substrate as described in claim 13, wherein the ratio of the distance between two opposite side walls of the roughening pattern to the length of the roughening pattern is between 0.1 and 0.6. A semiconductor substrate as described in claim 14, wherein the ratio of the height to the length of the roughening pattern is between 0.15 and 0.65. A semiconductor substrate as described in claim 15, wherein the length of the roughening pattern is in the range of 340 nm to 600 nm. The semiconductor substrate as described in claim 8, wherein the material includes silicon carbide or sapphire so that its energy gap is larger than the energy gap of silicon. A method for manufacturing a semiconductor substrate comprises: coating a photoresist on a semiconductor substrate, wherein the semiconductor substrate has a flat edge; exposing the photoresist to form a patterned photoresist adjacent to the flat edge of the semiconductor substrate; etching the semiconductor substrate using the patterned photoresist to form a roughened pattern, wherein the roughened pattern is configured to reflect light; and removing the photoresist. A method for manufacturing a semiconductor substrate as described in claim 18, wherein the photoresist is exposed using electron beam exposure. A method for manufacturing a semiconductor substrate as described in claim 18, wherein etching the semiconductor substrate using the patterned photoresist uses ion beam focused etching or laser engraving.

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