TW202422698A - Method of manufacturing semiconductor device - Google Patents

Abstract

The present disclosure provides a method of manufacturing a semiconductor device. The method includes: providing a semiconductor layer stack, in which the semiconductor layer stack includes a substrate, a metal layer disposed on the substrate, and a dielectric layer disposed on the metal layer; forming a hardmask layer on the semiconductor layer stack, in which the hardmask layer has a plurality of first hollowed portions; forming a plurality of second hollowed portions in the dielectric layer and exposing the metal layer through the first hollowed portions by an etching process, and a first intermediate product formed on an upper surface of the metal layer; oxidizing the first intermediate product to form a second intermediate product on the upper surface of the metal layer through the second hollowed portions by an ashing process; and removing the second intermediate product by a cleaning process, such that a plurality of recessed portions are formed on the upper surface of the metal layer.

Description

Method for manufacturing semiconductor device

The present disclosure relates to a method for manufacturing a semiconductor device.

Generally speaking, the process of semiconductor structure uses a defined patterned hard mask to transfer the pattern of the hard mask to the target metal layer. In order to improve the uniformity of the wafer, more recesses are required in the dielectric layer. However, when etching the dielectric layer, it is actually easy to damage more metal layers due to over-etching and form byproducts on the wafer due to different etching selectivities between the dielectric layer and the metal layer. For example, the above-mentioned byproducts can be metal oxides or metal chlorides. These byproducts will accumulate on the surface of the metal layer in solid form. This makes the electrical performance of the finally manufactured semiconductor device unsatisfactory.

Therefore, how to come up with a method for manufacturing semiconductor components to improve electrical performance is one of the problems that the industry is eager to invest research and development resources to solve.

In view of this, one purpose of the present disclosure is to provide a method for manufacturing a semiconductor device that can solve the above-mentioned problems.

In order to achieve the above-mentioned purpose, according to one embodiment of the present disclosure, a method for manufacturing a semiconductor element includes: providing a semiconductor layer stack, the semiconductor layer stack including a substrate, a metal layer disposed on the substrate, and a dielectric layer disposed on the metal layer; forming a hard mask layer on the semiconductor layer stack, wherein the hard mask layer has a plurality of first hollow portions; using the first hollow portions to form a plurality of second hollow portions in the dielectric layer and expose the metal layer by an etching process, and forming a first intermediate product on the upper surface of the metal layer; using the second hollow portions to oxidize the first intermediate product by an ashing process to form a second intermediate product on the upper surface of the metal layer; and removing the second intermediate product by a cleaning process, so that a plurality of recesses are formed on the upper surface of the metal layer.

In one or more embodiments of the present disclosure, the ashing process uses a first reaction gas, a second reaction gas, or a third reaction gas. The first reaction gas is composed of oxygen and a hydrogen/nitrogen mixture, the second reaction gas is composed of oxygen and ammonia, and the third reaction gas is composed of a hydrogen/nitrogen mixture.

In one or more embodiments of the present disclosure, the first reaction gas is composed of 90% by volume oxygen and 10% by volume hydrogen/nitrogen mixture.

In one or more embodiments of the present disclosure, the second reaction gas is composed of 60% by volume oxygen and 40% by volume ammonia.

In one or more embodiments of the present disclosure, the process time of the ashing process is in the range between 90 seconds and 110 seconds.

In one or more embodiments of the present disclosure, the process time of the cleaning process is in the range between 115 seconds and 135 seconds.

In one or more embodiments of the present disclosure, an etching process uses an etching gas, which includes sulfur hexafluoride, carbon tetrafluoride, or chloride.

In one or more embodiments of the present disclosure, the step of oxidizing the first intermediate product using the second hollow portion through an ashing process oxidizes a portion of the first intermediate product into a second intermediate product, and the step of removing the second intermediate product through a cleaning process leaves the remaining portion of the first intermediate product on the upper surface of the metal layer.

In one or more embodiments of the present disclosure, the step of oxidizing the first intermediate product by utilizing the second hollow portion through an ashing process is performed before the step of removing the second intermediate product through a cleaning process.

In one or more embodiments of the present disclosure, the step of oxidizing the first intermediate product by utilizing the second hollow portion through an ashing process is performed after the step of forming the second hollow portion in the dielectric layer by utilizing the first hollow portion through an etching process and exposing the metal layer.

In summary, in the manufacturing method of the semiconductor element disclosed in the present invention, since the hard mask layer has a first hollow portion, the first hollow portion defines the pattern of the dielectric layer. In the manufacturing method of the semiconductor element disclosed in the present invention, since the dielectric layer is etched and patterned to have a second hollow portion, the metal layer can be exposed and a first intermediate product can be formed on its surface. In the manufacturing method of the semiconductor element disclosed in the present invention, since the ashing process is performed after the etching process, an intermediate product that can be easily removed by a subsequent cleaning process can be formed. In the manufacturing method of the semiconductor element disclosed in the present invention, since the ashing process is performed before the cleaning process, the cleaning process can remove the intermediate product located on the upper surface of the metal layer. In an embodiment of the present disclosure, a method for manufacturing a semiconductor device improves its electrical performance by reducing the amount of residual intermediate products remaining on the upper surface of a metal layer.

The above description is only used to explain the problem to be solved by the present disclosure, the technical means for solving the problem, and the effects produced, etc. The specific details of the present disclosure will be introduced in detail in the following implementation method and related drawings.

The following will disclose multiple embodiments of the present disclosure with drawings. For the purpose of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present disclosure. In other words, in some embodiments of the present disclosure, these practical details are not necessary. In addition, in order to simplify the drawings, some commonly used structures and components will be depicted in the drawings in a simple schematic manner. The same reference numerals will be used to represent the same or similar components in all drawings.

Please refer to FIG. 1. FIG. 1 is a flow chart of a method M for manufacturing the semiconductor device 100 shown in FIG. 5 according to an embodiment of the present disclosure. The method M shown in FIG. 1 includes step S101, step S102, step S103, step S104, and step S105. Please refer to FIG. 1 and FIG. 2 for a better understanding of step S101 and step S102, please refer to FIG. 1 and FIG. 3 for a better understanding of step S103, please refer to FIG. 1 and FIG. 4 for a better understanding of step S104, and please refer to FIG. 1 and FIG. 5 for a better understanding of step S105.

The following describes step S101, step S102, step S103, step S104 and step S105 in detail.

In step S101, a semiconductor layer stack SS is provided.

Please refer to FIG. 2. FIG. 2 is a schematic diagram of an intermediate stage of manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. As shown in FIG. 2, a semiconductor layer stack SS is provided. In this embodiment, the semiconductor layer stack SS includes a substrate 110, a metal layer 120, and a dielectric layer 130, as shown in FIG. 2. The metal layer 120 is formed above the substrate 110. The dielectric layer 130 is formed above the metal layer 120.

In some embodiments, the substrate 110 may be a silicon substrate. In some embodiments, the substrate 110 may include monocrystalline silicon, polycrystalline silicon, amorphous silicon, or other similar materials. However, any suitable material may be used.

In some embodiments, the substrate 110 may be formed by any suitable method, such as a CVD (chemical vapor deposition) process, a PECVD (plasma enhanced chemical vapor deposition) process, a PVD (physical vapor deposition) process, an ALD (atomic layer deposition) process, a PEALD (plasma enhanced atomic layer deposition) process, an ECP (electrochemical plating) process, a chemical plating process, or other similar methods. The present disclosure is not intended to limit the method of forming the substrate 110.

In some embodiments, the metal layer 120 may include a metal material such as tungsten (W), aluminum (Al), copper (Cu), or other similar materials. However, any suitable material may be used.

In some embodiments, the metal layer 120 can be formed by any suitable method, such as a CVD (chemical vapor deposition) process, a PECVD (plasma enhanced chemical vapor deposition) process, a PVD (physical vapor deposition) process, an ALD (atomic layer deposition) process, a PEALD (plasma enhanced atomic layer deposition) process, an ECP (electrochemical plating) process, a chemical plating process, or other similar methods. The present disclosure is not intended to limit the method of forming the metal layer 120.

In some embodiments, the dielectric layer 130 may include nitride, oxide, carbide, or other similar materials. However, any suitable material may be used.

In some embodiments, the dielectric layer 130 can be formed by any suitable method, such as a CVD (chemical vapor deposition) process, a PECVD (plasma enhanced chemical vapor deposition) process, a PVD (physical vapor deposition) process, an ALD (atomic layer deposition) process, a PEALD (plasma enhanced atomic layer deposition) process, an ECP (electrochemical plating) process, a chemical plating process, or other similar methods. The present disclosure is not intended to limit the method of forming the dielectric layer 130.

In step S102, a hard mask layer HM is formed on the semiconductor layer stack SS, wherein the hard mask layer HM has a plurality of first hollow portions O1.

Please continue to refer to FIG. 2. As shown in FIG. 2, the hard mask layer HM is formed on the semiconductor layer stack SS. In some embodiments, as shown in FIG. 2, the hard mask layer HM is formed on the dielectric layer 130. Specifically, as shown in FIG. 2, the hard mask layer HM is formed on the upper surface 130a of the dielectric layer 130.

In some embodiments, as shown in FIG. 2 , the hard mask layer HM has a plurality of first hollow portions O1. In some embodiments, the hard mask layer HM is a patterned mask. In some embodiments, the first hollow portions O1 penetrate the hard mask layer HM.

In some embodiments, the hard mask layer HM may include a material such as polysilicon. However, any suitable material may be used.

In some implementations, the hard mask layer HM having the first hollow portion O1 may be formed by any suitable method, such as a lithography process, etc. The present disclosure is not intended to limit the method for forming the hard mask layer HM.

In step S103 , a plurality of second hollow portions O2 are formed in the dielectric layer 130 by using the first hollow portion O1 through an etching process to expose the metal layer 120 , and a first intermediate product 122 is formed on the upper surface 120 a of the metal layer 120 .

Please refer to FIG. 2 and FIG. 3. In the present embodiment, an etching process may be performed in the middle stage of manufacturing the semiconductor device 100 as shown in FIG. 2 to transfer the pattern of the hard mask layer HM onto the dielectric layer 130. As shown in FIG. 2 and FIG. 3, the dielectric layer 130 may be patterned using the hard mask layer HM having the first hollow portion O1 by performing the above etching process. Specifically, as shown in FIG. 2 and FIG. 3, the etching process uses the first hollow portion O1 to form a plurality of second hollow portions O2 in the dielectric layer 130. In some embodiments, as shown in FIG. 3, the second hollow portion O2 penetrates the dielectric layer 130, so that the metal layer 120 is exposed.

Please continue to refer to FIG. 3. In the present embodiment, the etching process is substantially over-etching. As shown in FIG. 3, the dielectric layer 130 is over-etched, so that the second hollow portion O2 penetrates the dielectric layer 130 and forms the first intermediate product 122 on the upper surface 120a of the metal layer 120. Specifically, since the etching process has different etching selectivity ratios for the dielectric layer 130 and the metal layer 120, it is easy to form byproducts such as the first intermediate product 122 on the upper surface 120a of the metal layer 120 and around the second hollow portion O2. In some embodiments, the first intermediate product 122 is formed directly below the second hollow portion O2, and the first intermediate product 122 is formed by the reaction of the etching gas with the metal layer 120. Specifically, the first intermediate product 122 is formed due to the incomplete reaction of the etching gas with the metal layer 120.

In some embodiments, the dielectric layer 130 having the second hollow portion O2 can be formed by any suitable etching method, such as an anisotropic etching process (eg, dry etching) or other similar processes. The present disclosure is not intended to limit the method for forming the dielectric layer 130 having the second hollow portion O2.

In some embodiments, the dielectric layer 130 having the second hollow portion O2 may be formed by an etching process using any suitable etching gas, such as fluorine, chloride, or other suitable components. In some embodiments, the etching gas may include sulfur hexafluoride (SF ₆ ), carbon tetrafluoride (CF ₄ ), carbon tetrachloride (CCl ₄ ), or any suitable gas. The present disclosure is not intended to limit the components of the etching gas.

In some embodiments, the first intermediate product 122 is a solid residue.

In step S104 , the first intermediate product 122 is oxidized by the second hollow portion O2 through an ashing process to form a second intermediate product 124 on the upper surface 120 a of the metal layer 120 .

Please refer to FIG. 3 and FIG. 4. In the present embodiment, an ash process may be performed in the middle stage of manufacturing the semiconductor device 100 as shown in FIG. 3 to convert the first intermediate product 122 into the second intermediate product 124. Specifically, as shown in FIG. 3 and FIG. 4, the ash process utilizes the second hollow portion O2 to oxidize the first intermediate product 122. Then, the first intermediate product 122 is oxidized to form the second intermediate product 124. In some embodiments, as shown in FIG. 4, the second intermediate product 124 is formed on the upper surface 120a of the metal layer 120. Specifically, the second intermediate product 124 is formed directly below the second hollow portion O2, and the second intermediate product 124 is formed by the reaction of the reaction gas with the metal layer 120.

In some embodiments, the second intermediate product 124 can be formed by any suitable ashing method, such as a plasma ashing process or other similar processes. The present disclosure is not intended to limit the method for forming the second intermediate product 124.

In some embodiments, any suitable reaction gas may be used to form the second intermediate product 124 by the ashing process. In some embodiments, the reaction gas includes oxygen (O ₂ ), hydrogen (H ₂ ), nitrogen (N ₂ ), ammonia (NH ₃ ) or other suitable components. In some embodiments, the reaction gas is composed of oxygen and a hydrogen/nitrogen (H ₂ /N ₂ ) mixture. In some embodiments, the reaction gas is composed of oxygen and ammonia. In some embodiments, the reaction gas is composed of a hydrogen/nitrogen mixture. The present disclosure is not intended to limit the composition of the second intermediate product 124.

In some embodiments where the reaction gas is composed of oxygen and a hydrogen/nitrogen mixture, the volume percentage of oxygen is 90% and the volume percentage of the hydrogen/nitrogen mixture is 10%.

In some embodiments where the reaction gas is composed of oxygen and ammonia, the volume percentage of oxygen is 60% and the volume percentage of ammonia is 40%.

In some embodiments, the ashing process has a process time in the range of 90 seconds to 110 seconds. In some embodiments, the ashing process has a process time in the range of 95 seconds to 105 seconds. In some embodiments, the ashing process has a process time of 100 seconds. However, any suitable process time may be used.

In some embodiments, the second intermediate product 124 may include an oxide. In some embodiments, the second intermediate product 124 is, for example, a metal oxide or other similar oxide. In some embodiments, the second intermediate product 124 may include tungsten trioxide (WO ₃ ), tungsten dioxide (WO ₂ ), aluminum oxide (Al ₂ O ₃ ), copper oxide (CuO) or other similar materials.

In some embodiments, the second intermediate product 124 is a solid residue.

In some embodiments, since the second intermediate product 124 is formed by oxidizing the first intermediate product 122 by the second hollow portion O2 through the ashing process in step S104 after the second hollow portion O2 is formed in the dielectric layer 130 by the first hollow portion O1 through the etching process in step S103 and the metal layer 120 is exposed, the second intermediate product 124 can be formed on the upper surface 120a of the metal layer 120 to be in a form that is easy to remove. How the second intermediate product 124 is removed will be described in detail below.

In step S105 , the second intermediate product 124 is removed by a cleaning process, so that a plurality of recesses R are formed on the upper surface 120 a of the metal layer 120 .

Please refer to FIG. 4 and FIG. 5. In the present embodiment, an ash process may be performed in the middle stage of manufacturing the semiconductor device 100 as shown in FIG. 4 to remove the second intermediate product 124. Specifically, as shown in FIG. 4 and FIG. 5, the ash process removes the second intermediate product 124 using a cleaning agent. Specifically, the cleaning agent at least rinses the upper surface 120a of the metal layer 120 so that the second intermediate product 124 can be removed from the upper surface 120a of the metal layer 120. Then, as shown in FIG. 5, the second intermediate product 124 is removed by the ash process, so that a plurality of recesses R are formed on the upper surface 120a of the metal layer 120.

In some embodiments, as shown in FIG. 5 , the recess R is recessed relative to the upper surface 120 a of the metal layer 120 toward the substrate 110 .

In some embodiments, the second intermediate product 124 can be removed by any suitable cleaning method, such as a wet cleaning process or other similar processes. The present disclosure is not intended to limit the method for removing the second intermediate product 124.

In some embodiments, any suitable cleaning agent may be used to remove the second intermediate product 124 by the cleaning process. In some embodiments, the cleaning agent may be, for example, an acid or other suitable compound. In some embodiments, the cleaning agent may be dilute hydrofluoric acid (dHF). The present disclosure is not intended to limit the composition of the cleaning agent.

In some embodiments where the cleaning agent is dilute hydrofluoric acid, the volume percent concentration of the dilute hydrofluoric acid is 1%. However, any suitable concentration may be used.

In some embodiments, the process time of the cleaning process is in the range of 115 seconds to 135 seconds. In some embodiments, the process time of the cleaning process is preferably in the range of 120 seconds to 130 seconds. In some embodiments, the process time of the cleaning process is preferably 125 seconds. However, any suitable process time may be used.

In some embodiments, since the oxidizing of the first intermediate product 122 to form the second intermediate product 124 by using the second hollow portion O2 through an ashing process in step S104 is performed before the removal of the second intermediate product 124 through a cleaning process in step S105, the second intermediate product 124 can be removed from the upper surface 120a of the metal layer 120.

By executing the method M including step S101, step S102, step S103, step S104 and step S105, a semiconductor device 100 with better electrical performance can be manufactured.

The semiconductor device 100, the semiconductor device 100A or the semiconductor device 100B formed by different implementation methods will be described in detail below.

Please refer to FIGS. 6 to 8. FIGS. 6 to 8 are top views of semiconductor device 100, semiconductor device 100A, or semiconductor device 100B according to different embodiments of the present disclosure. In some embodiments, FIGS. 6 to 8 are wafer defect maps of semiconductor device 100, semiconductor device 100A, or semiconductor device 100B. In this embodiment, semiconductor device 100, semiconductor device 100A, or semiconductor device 100B can be formed by executing method M including step S101, step S102, step S103, step S104, and step S105. The difference between the semiconductor device 100, the semiconductor device 100A, or the semiconductor device 100B is that the semiconductor device 100, the semiconductor device 100A, or the semiconductor device 100B uses different reaction gases in step S104. As shown in FIG. 6, the semiconductor device 100 uses a reaction gas composed of oxygen and a hydrogen/nitrogen mixture in step S104. As shown in FIG. 7, the semiconductor device 100A uses a reaction gas composed of an oxygen and an ammonia mixture in step S104. As shown in FIG. 8, the semiconductor device 100B uses a reaction gas composed of a hydrogen/nitrogen mixture in step S104. As shown in FIGS. 6 to 8 , in some embodiments, the first intermediate product 122, the first intermediate product 122A, and the first intermediate product 122B remain on the semiconductor device 100, the semiconductor device 100A, or the semiconductor device 100B, respectively. Specifically, the first intermediate product 122, the first intermediate product 122A, and the first intermediate product 122B remain on the upper surface 120a of the metal layer 120 of the semiconductor device 100, the semiconductor device 100A, or the semiconductor device 100B, respectively.

Therefore, it can be seen that in step S104, the ashing process only oxidizes part of the first intermediate product 122, the first intermediate product 122A and the first intermediate product 122B, so in step S105, the remaining part of the first intermediate product 122, the first intermediate product 122A and the first intermediate product 122B remains on the upper surface 120a of the metal layer 120, as shown in Figures 6 to 8.

Please continue to refer to Figures 6 to 8. In some embodiments, as shown in Figures 6 to 8, the residue of the first intermediate product 122 is lower than the residue of the first intermediate product 122A or the residue of the first intermediate product 122B. In some embodiments, the residue of the first intermediate product 122A is lower than the residue of the first intermediate product 122B. Based on the above description, regardless of whether the ashing process in step S104 uses a reaction gas composed of oxygen and a hydrogen/nitrogen mixture, a reaction gas composed of oxygen and ammonia, or a reaction gas composed of a hydrogen/nitrogen mixture, the intermediate product is effectively removed to reduce the residue of the intermediate product.

By executing method M including step S101, step S102, step S103, step S104 and step S105, the amount of solid residues (for example, the first intermediate product 122, the first intermediate product 122A and the first intermediate product 122B) can be reduced compared to the prior art, thereby manufacturing a semiconductor device 100, a semiconductor device 100A or a semiconductor device 100B with better electrical performance.

Based on the above discussion, it can be seen that the method M of the present disclosure provides advantages. However, it should be understood that other embodiments may also provide additional advantages, and not all advantages must be disclosed herein, and not all embodiments require specific advantages.

Through the above detailed description of the specific implementation of the present disclosure, it can be clearly seen that in the manufacturing method of the semiconductor element disclosed in the present disclosure, since the hard mask layer has a first hollow portion, the first hollow portion defines the pattern of the dielectric layer. In the manufacturing method of the semiconductor element disclosed in the present disclosure, since the dielectric layer is etched and patterned to have a second hollow portion, the metal layer can be exposed and a first intermediate product can be formed on its surface. In the manufacturing method of the semiconductor element disclosed in the present disclosure, since the ashing process is performed after the etching process, an intermediate product that can be easily removed by a subsequent cleaning process can be formed. In the manufacturing method of the semiconductor element disclosed in the present disclosure, since the ashing process is performed before the cleaning process, the cleaning process can remove the intermediate product located on the upper surface of the metal layer. In an embodiment of the present disclosure, a method for manufacturing a semiconductor device improves its electrical performance by reducing the amount of residual intermediate products remaining on the upper surface of a metal layer.

Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained in the present disclosure.

It is obvious to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. In view of the foregoing, the present disclosure is intended to cover modifications and variations of the present disclosure as long as they fall within the scope of the attached patent application.

100, 100A, 100B: semiconductor element 110: substrate 120: metal layer 120a, 130a: upper surface 122, 122A, 122B: first intermediate product 124: second intermediate product 130: dielectric layer HM: hard mask layer M: method O1: first hollow part O2: second hollow part R: recessed part S101, S102, S103, S104, S105: steps SS: semiconductor layer stacking

In order to make the above and other purposes, features, advantages and implementation methods of the present disclosure more clearly understandable, the attached drawings are described as follows: Figure 1 is a flow chart showing a method for manufacturing a semiconductor element according to an implementation method of the present disclosure. Figure 2 is a schematic diagram showing an intermediate stage of manufacturing a semiconductor element according to an implementation method of the present disclosure. Figure 3 is a schematic diagram showing an intermediate stage of manufacturing a semiconductor element according to an implementation method of the present disclosure. Figure 4 is a schematic diagram showing an intermediate stage of manufacturing a semiconductor element according to an implementation method of the present disclosure. Figure 5 is a schematic diagram showing an intermediate stage of manufacturing a semiconductor element according to an implementation method of the present disclosure. Figure 6 is a top view showing an intermediate stage of manufacturing a semiconductor element according to an implementation method of the present disclosure. FIG. 7 is a top view showing an intermediate stage of manufacturing a semiconductor device according to another embodiment of the present disclosure. FIG. 8 is a top view showing an intermediate stage of manufacturing a semiconductor device according to yet another embodiment of the present disclosure.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

M: Method

S101, S102, S103, S104, S105: Steps

Claims (10)

A method for manufacturing a semiconductor element comprises: providing a semiconductor layer stack, the semiconductor layer stack comprising a substrate, a metal layer disposed on the substrate, and a dielectric layer disposed on the metal layer; forming a hard mask layer on the semiconductor layer stack, wherein the hard mask layer has a plurality of first hollow portions; forming a plurality of second hollow portions in the dielectric layer and exposing the metal layer by an etching process using the first hollow portions, and forming a first intermediate product on an upper surface of the metal layer; oxidizing the first intermediate product by an ashing process using the second hollow portions to form a second intermediate product on the upper surface of the metal layer; and The second intermediate product is removed by a cleaning process, so that a plurality of recesses are formed on the upper surface of the metal layer. A method as described in claim 1, wherein the ashing process uses a first reaction gas, a second reaction gas or a third reaction gas, the first reaction gas is composed of oxygen and a hydrogen/nitrogen mixture, the second reaction gas is composed of oxygen and ammonia, and the third reaction gas is composed of a hydrogen/nitrogen mixture. The method as described in claim 2, wherein the first reaction gas is composed of 90 volume % oxygen and 10 volume % hydrogen/nitrogen mixture. The method as described in claim 2, wherein the second reaction gas is composed of 60% by volume of oxygen and 40% by volume of ammonia. The method of claim 1, wherein the process time of the ashing process is in a range between 90 seconds and 110 seconds. The method of claim 1, wherein the process time of the cleaning process is in a range between 115 seconds and 135 seconds. A method as described in claim 1, wherein the etching process uses an etching gas, and the etching gas contains sulfur hexafluoride, carbon tetrafluoride or chloride. A method as described in claim 1, wherein the step of oxidizing the first intermediate product using the second hollow portions through the ashing process is to oxidize part of the first intermediate product into the second intermediate product, and the step of removing the second intermediate product through the cleaning process is to leave the remaining part of the first intermediate product on the upper surface of the metal layer. The method as described in claim 1, wherein the step of oxidizing the first intermediate product using the second hollow portions through the ashing process is performed before the step of removing the second intermediate product through the cleaning process. The method as described in claim 1, wherein the step of oxidizing the first intermediate product by utilizing the second hollow portions through the ashing process is performed after the step of forming the second hollow portions in the dielectric layer by utilizing the first hollow portions through the etching process and exposing the metal layer.

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