TW202422670A - Semiconductor process for reducing micro scratch defect in chemical mechanical polishing - Google Patents

Abstract

A semiconductor process for reducing micro scratch defect in chemical mechanical polishing (CMP) is provided in the present invention, including performing a pre-CMP cleaning step in a cleaning tool, performing a wafer bevel treatment in a bevel treatment device immediately after the pre-CMP cleaning step, wherein the wafer bevel treatment includes cleaning or polishing wafer bevels, and performing a CMP process in a CMP tool immediately after the wafer bevel treatment.

Description

Semiconductor Process for Reducing Micro-Scratch Defects in Chemical Mechanical Polishing

The present invention generally relates to a semiconductor process, and more particularly, to a semiconductor process for cleaning or grinding the edge of a wafer.

Chemical-Mechanical Polishing (CMP) is a common process used in semiconductor device manufacturing. In the process, abrasive and corrosive polishing fluids are used in combination with polishing pads to remove unnecessary or irregular structures on the surface of silicon wafers or other substrate materials to achieve the purpose of flattening. The flattened silicon wafer has a flat process surface, which makes it easier to form patterns in dry etching, and can form smaller semiconductor patterns, thereby improving the integration of components.

However, the chemical mechanical polishing process often produces micro scratch defects on the polished surface due to the presence of hard impurity particles in the process, which in turn affects the reliability of subsequent processes and final components. For example, the pre-cleaning step before polishing is not thorough, resulting in impurity particles remaining, or silicon crystal particles falling off the bevel of the wafer during the process. Therefore, general technicians in this field still need to improve the existing chemical mechanical polishing process to avoid the above problems.

In view of the above problems encountered in the prior art, the present invention proposes a novel semiconductor manufacturing process, which is characterized in that a crystal edge treatment step is added between the pre-cleaning step before chemical mechanical polishing and the polishing step to remove impurity particles on the crystal edge to prevent these impurity particles from scratching the polished surface in the subsequent polishing process to form micro-scratch defects.

The purpose of the present invention is to provide a semiconductor process that can reduce micro-scratch defects in chemical mechanical polishing, and the steps include: performing a pre-cleaning step before polishing in a cleaning machine, immediately entering a wafer edge processing device to perform a wafer edge processing step after the pre-cleaning step before polishing, and immediately entering a chemical mechanical polishing machine to perform a wafer polishing step after the wafer edge processing step.

These and other objects of the present invention will become more apparent after the reader has read the following detailed description of the preferred embodiments described in various figures and drawings.

Now, the following will describe in detail exemplary embodiments of the present invention, which will refer to the attached drawings to illustrate the described features so that the reader can understand and achieve the technical effects. The reader will understand that the description herein is only by way of example and is not intended to limit the present invention. Various embodiments of the present invention and various features that do not conflict with each other in the embodiments can be combined or reset in various ways. Without departing from the spirit and scope of the present invention, modifications, equivalents or improvements to the present invention are understandable to those skilled in the art and are intended to be included in the scope of the present invention.

As used herein, the term "substrate" refers to the material onto which subsequent materials are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a wide range of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

Readers can further understand that when the words "include" and/or "contain" are used in this specification, they specify the existence of the described features, regions, wholes, steps, operations, elements and/or components, but do not exclude the possibility of the existence or addition of one or more other features, regions, wholes, steps, operations, elements, components and/or combinations thereof.

Please refer to FIG. 1, which is a top view schematic diagram of the machine used in the process of the present invention. In the semiconductor process of the present invention, a pre-grinding pre-cleaning step is first performed. The pre-grinding pre-cleaning step is performed in a cleaning machine 100. The cleaning machine 100 can be a wet cleaning machine, not limited to a tank type or a single-wafer type. It uses a specific chemical solution and deionized water to clean the wafer surface without damage, such as RCA wet cleaning, ultrasonic cleaning, etc. The chemical solution used in the pre-cleaning step depends on the previous process, such as SC1, SC2, sulfuric acid and hydrogen peroxide mixture (SPM), tetramethylammonium hydroxide (TMAH), ozone deionized water (DIO ₃ ), diluted hydrofluoric acid (DHF), hydrofluoric acid buffer (BHF), etc., but not limited to these. The pre-cleaning step before polishing can remove various impurities and contaminants left on the wafer surface in the previous process, such as natural oxide layer, organic matter, metal ions, sacrificial layer, etc., to provide a clean process surface.

Still refer to Figure 1. After the above-mentioned pre-cleaning step before grinding, the cleaned wafer will be immediately transferred by a transfer mechanism to a bevel processing device 200 connected to the cleaning machine 100 for a bevel processing step. This bevel processing step can remove impurities and defects on the bevel area that cannot be cleaned in the above-mentioned pre-cleaning step before grinding. In the embodiment of the present invention, the bevel processing step includes cleaning the bevel of the wafer and/or grinding the bevel of the wafer to remove impurities or defects located at the bevel area. It should be noted that this bevel processing step is different from the subsequent chemical mechanical polishing (CMP) step, and the area to be processed is the bevel of the wafer, not the surface or process surface of the wafer.

Please refer to FIG. 2, which is a cross-sectional schematic diagram of the crystal edge processing step in an embodiment of the present invention. In the crystal edge processing step, the crystal edge portion of the wafer 10 to be processed in the crystal edge processing device 200 will be set in a groove 203 of the processing mechanism 202, and the wafer 10 can be rotated so that different crystal edge portions are located in the groove 203. Deionized water can be introduced into the groove 203 to rinse the crystal edge of the wafer 10 to remove impurity particles at the crystal edge. Furthermore, a sponge or a grinding pad 204 can be set in the groove 203, and a grinding liquid can be introduced to grind the crystal edge. The polishing liquid used in the embodiment can be a polishing liquid used in a general CMP process, such as an aluminum oxide polishing liquid, a silicon oxide polishing liquid or a bismuth oxide polishing liquid, etc., especially a polishing liquid for silicon materials. The above-mentioned polishing action can further remove the inferior layer or fragile layer structure at the crystal edge to prevent its impurity particles from falling off and scratching the polishing surface in the subsequent CMP process.

Refer to FIG. 1 again. After the above-mentioned wafer edge processing step, the processed wafer will be immediately transferred to a CMP machine 300 connected to the wafer edge processing device 200 through a transfer mechanism for a wafer polishing step. The operations previously performed in the cleaning machine 100 and the wafer edge processing device 200 are all pre-cleaning and pre-processing operations for the CMP process of the wafer. At this time, the main CMP process is performed in the CMP machine 300. The CMP machine 300 can be any type of polishing machine, such as a machine for different materials or processes such as silicon oxide, shallow trench isolation structure, tungsten, copper, etc. In the CMP process, polishing liquids such as aluminum oxide polishing liquid, silicon oxide polishing liquid or tael oxide polishing liquid are used together with polishing pads to remove unnecessary or irregular structures on the surface of silicon wafers or other substrate materials to achieve the purpose of planarization.

In the embodiment of the present invention, the edge processing device 200 is preferably located between the cleaning machine 100 and the CMP machine 300, and the two are connected. In this way, after the wafer completes the pre-cleaning step in the cleaning machine 100, it can be immediately and directly transferred to the edge processing device 200 through the conveying mechanism for edge processing, and after the edge processing, it can be immediately and directly transferred to the CMP machine 300 through the conveying mechanism for CMP process. Such a setting can avoid the additional edge processing action from having too much impact on the output of the overall process. The above is only a preferred embodiment of the present invention. All equal changes and modifications made according to the scope of the patent application of the present invention should be covered by the present invention.

10: Wafer 100: Cleaning machine 200: Wafer edge processing device 202: Processing mechanism 203: Groove 204: Sponge (polishing pad) 300: Chemical mechanical polishing (CMP) machine

FIG. 1 is a top view schematic diagram of the machine used in the process of the present invention; and FIG. 2 is a cross-sectional schematic diagram of the crystal edge processing step according to an embodiment of the present invention. It should be noted that all the diagrams in this specification are of a legend nature. For the sake of clarity and convenience of illustration, the size and proportion of each component in the diagram may be exaggerated or reduced. Generally speaking, the same reference symbols in the figure will be used to indicate corresponding or similar component features after modification or in different embodiments.

100: Cleaning machine

200: Crystal edge processing device

300: Chemical Mechanical Polishing (CMP) Machine

Claims (6)

A semiconductor process for reducing micro-scratch defects in chemical mechanical polishing, comprising: performing a pre-polishing step in a cleaning machine; immediately entering a wafer edge treatment device to perform a wafer edge treatment step after the pre-polishing step; and immediately entering a chemical mechanical polishing machine to perform a wafer polishing step after the wafer edge treatment step. A semiconductor process for reducing micro-scratch defects in chemical mechanical polishing as described in claim 1, wherein the crystal edge processing step includes cleaning the crystal edge of the wafer. A semiconductor process for reducing micro-scratch defects in chemical mechanical polishing as described in claim 2, wherein deionized water is used to clean the edge of the wafer. A semiconductor process for reducing micro-scratch defects in chemical mechanical polishing as described in claim 1, wherein the crystal edge processing step includes polishing the crystal edge of the wafer. A semiconductor process for reducing micro-scratch defects in chemical mechanical polishing as described in item 4 of the patent application scope, wherein a polishing liquid is used to polish the edge of the wafer. A semiconductor process for reducing micro-scratch defects in chemical mechanical polishing as described in item 1 of the patent application scope, wherein the crystal edge processing device is located between the cleaning machine and the chemical mechanical polishing machine and connects the two.