TW202420415A - Photodiode structure and manufacturing method thereof - Google Patents

Photodiode structure and manufacturing method thereof Download PDF

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TW202420415A
TW202420415A TW111141908A TW111141908A TW202420415A TW 202420415 A TW202420415 A TW 202420415A TW 111141908 A TW111141908 A TW 111141908A TW 111141908 A TW111141908 A TW 111141908A TW 202420415 A TW202420415 A TW 202420415A
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semiconductor layer
manufacturing
present
reflection layer
coating process
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TW111141908A
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TWI818792B (en
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林駿杰
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台亞半導體股份有限公司
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Priority claimed from TW111141908A external-priority patent/TWI818792B/en
Priority to CN202310897917.5A priority patent/CN117995937A/en
Priority to KR1020230123900A priority patent/KR20240062935A/en
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Priority to US18/495,100 priority patent/US20240145605A1/en
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Abstract

The present invention provides a manufacturing method of a photodiode structure. The method includes the following steps: providing a substrate; performing an epitaxial process to form a first semiconductor layer on the substrate; performing an active area patterning and etching process to forming a recessed portion on the first semiconductor layer; performing a first coating process to form a first anti-reflection layer on the first semiconductor layer; and performing an ion implantation process to form a second semiconductor layer in the recessed portion pass through the first anti-reflection layer.

Description

光電二極體結構及其製造方法Photodiode structure and manufacturing method thereof

本發明係關於一種光電二極體結構之製造方法,尤指一種可維持高線性度之光電二極體結構之製造方法。The present invention relates to a method for manufacturing a photodiode structure, and more particularly to a method for manufacturing a photodiode structure capable of maintaining high linearity.

光電二極體用於接收外來光線,並輸出相應之類比電訊號或者執行電路中不同狀態之切換。目前光電二極體廣泛應用在有光學測量需求之產品上,例如許多智慧型穿戴裝置會使用光電二極體來執行相應脈博或/及血氧量測等功能。Photodiodes are used to receive external light and output corresponding analog electrical signals or switch between different states in the circuit. Currently, photodiodes are widely used in products that require optical measurement. For example, many smart wearable devices use photodiodes to perform corresponding pulse and/or blood oxygen measurement functions.

習知光電二極體在製造過程中,會先形成所需之N型及P型半導體層,再於該些半導體層表面上塗佈抗反射層。由於各抗反射層所使用之材料及厚度並不相同,部分抗反射層之製程可能需要在高溫環境下執行,以利於形成相應之抗反射層。然而,該些半導體層受到製程之高溫影響可能產生材質變化,容易出現線性度下降等問題,進而影響光電二極體之感測效能。It is known that in the manufacturing process of photodiodes, the required N-type and P-type semiconductor layers are first formed, and then the anti-reflection layer is coated on the surface of these semiconductor layers. Since the materials and thicknesses used in each anti-reflection layer are different, the process of some anti-reflection layers may need to be performed in a high temperature environment to facilitate the formation of the corresponding anti-reflection layer. However, these semiconductor layers may undergo material changes due to the high temperature of the process, which may easily cause problems such as linearity degradation, thereby affecting the sensing performance of the photodiode.

因此,如何設計出能改善前述問題之光電二極體結構之製造方法,實為一個值得研究之課題。Therefore, how to design a manufacturing method for a photodiode structure that can improve the above-mentioned problems is indeed a topic worthy of research.

本發明之目的在於提供一種可維持高線性度之光電二極體結構之製造方法。The purpose of the present invention is to provide a method for manufacturing a photodiode structure that can maintain high linearity.

為達上述目的,本發明之光電二極體結構之製造方法包括以下步驟:提供一基材;執行磊晶製程以於基材上形成第一半導體層;執行主動區圖形化蝕刻製程以於第一半導體層上形成凹陷部;執行第一塗佈製程以於第一半導體層上形成第一抗反射層;以及執行離子佈值製程以穿過第一抗反射層並於凹陷部內形成第二半導體層。To achieve the above-mentioned object, the manufacturing method of the photodiode structure of the present invention includes the following steps: providing a substrate; performing an epitaxial process to form a first semiconductor layer on the substrate; performing an active region patterning etching process to form a recessed portion on the first semiconductor layer; performing a first coating process to form a first anti-reflection layer on the first semiconductor layer; and performing an ion dotting process to penetrate the first anti-reflection layer and form a second semiconductor layer in the recessed portion.

在本發明之一實施例中,第一塗佈製程為高溫LPCVD製程。In one embodiment of the present invention, the first coating process is a high temperature LPCVD process.

在本發明之一實施例中,第一塗佈製程之製程溫度不低於800℃。In one embodiment of the present invention, the process temperature of the first coating process is not less than 800°C.

在本發明之一實施例中,第一抗反射層之厚度介於25nm至XX之間。In one embodiment of the present invention, the thickness of the first anti-reflection layer is between 25 nm and XX.

在本發明之一實施例中,第一抗反射層係以XXX製程。In one embodiment of the present invention, the first anti-reflection layer is formed by XXX process.

在本發明之一實施例中,更包括以下步驟:執行第二塗佈製程以於第一抗反射層上形成第二抗反射層;執行第一金屬化製程以形成電性連接基材之第一電極;以及執行第二金屬化製程以形成電性連接第二半導體層之第二電極。In one embodiment of the present invention, the following steps are further included: performing a second coating process to form a second anti-reflection layer on the first anti-reflection layer; performing a first metallization process to form a first electrode electrically connected to the substrate; and performing a second metallization process to form a second electrode electrically connected to the second semiconductor layer.

在本發明之一實施例中,第二塗佈製程為PVD製程,且第二塗佈製程之製程溫度低於第一塗佈製程之製程溫度。In one embodiment of the present invention, the second coating process is a PVD process, and the process temperature of the second coating process is lower than the process temperature of the first coating process.

在本發明之一實施例中,第二塗佈製程之製程溫度不高於200℃。In one embodiment of the present invention, the process temperature of the second coating process is not higher than 200°C.

在本發明之一實施例中,第二抗反射層之厚度介於XX至XX之間。In one embodiment of the present invention, the thickness of the second anti-reflection layer is between XX and XX.

在本發明之一實施例中,第一半導體層為N型半導體層,第二半導體層為P型半導體層,第一電極為負極,且第二電極為正極。In one embodiment of the present invention, the first semiconductor layer is an N-type semiconductor layer, the second semiconductor layer is a P-type semiconductor layer, the first electrode is a negative electrode, and the second electrode is a positive electrode.

本發明還包括一種使用前述製造方法製程之光電二極體結構。The present invention also includes a photodiode structure using the aforementioned manufacturing method and process.

據此,藉由將形成第一反射層之高溫塗佈製程執行於形成第二半導體層之前,可避免製程之高溫影響已成型之第二半導體層,減少第二半導體層之線性度下降之可能性,進而維持本發明之光電二極體結構之原有感測效能。Accordingly, by performing the high temperature coating process for forming the first reflective layer before forming the second semiconductor layer, the high temperature of the process can be prevented from affecting the formed second semiconductor layer, reducing the possibility of linearity degradation of the second semiconductor layer, thereby maintaining the original sensing performance of the photodiode structure of the present invention.

由於各種態樣與實施例僅為例示性且非限制性,故在閱讀本說明書後,具有通常知識者在不偏離本發明之範疇下,亦可能有其他態樣與實施例。根據下述之詳細說明與申請專利範圍,將可使該等實施例之特徵及優點更加彰顯。Since the various aspects and embodiments are only exemplary and non-restrictive, after reading this specification, a person with ordinary knowledge may also have other aspects and embodiments without departing from the scope of the invention. According to the following detailed description and patent application scope, the features and advantages of these embodiments will be more prominent.

於本文中,係使用「一」或「一個」來描述本文所述的元件和組件。此舉只是為了方便說明,並且對本發明之範疇提供一般性的意義。因此,除非很明顯地另指他意,否則此種描述應理解為包括一個或至少一個,且單數也同時包括複數。In this document, "a" or "an" is used to describe the elements and components described herein. This is only for convenience of explanation and to provide a general meaning for the scope of the present invention. Therefore, unless it is obvious that it is otherwise intended, such description should be understood to include one or at least one, and the singular also includes the plural.

於本文中,用語「第一」或「第二」等類似序數詞主要是用以區分或指涉相同或類似的元件或結構,且不必然隱含此等元件或結構在空間或時間上的順序。應了解的是,在某些情形或組態下,序數詞可以交換使用而不影響本創作之實施。In this article, the terms "first" or "second" and similar ordinal numbers are mainly used to distinguish or refer to the same or similar elements or structures, and do not necessarily imply the order of these elements or structures in space or time. It should be understood that in some cases or configurations, ordinal numbers can be used interchangeably without affecting the implementation of the present invention.

於本文中,用語「包括」、「具有」或其他任何類似用語意欲涵蓋非排他性之包括物。舉例而言,含有複數要件的元件或結構不僅限於本文所列出之此等要件而已,而是可以包括未明確列出但卻是該元件或結構通常固有之其他要件。As used herein, the terms "include," "have," or any other similar terms are intended to cover a non-exclusive inclusion. For example, a component or structure having plural elements is not limited to those elements listed herein but may include other elements that are not expressly listed but are generally inherent to the component or structure.

本發明之光電二極體結構可應用於智慧型穿戴裝置。智慧型穿戴裝置會使用光電二極體作為光學感測器以量測脈膊或/及血氧濃度等身體參數,為了保持訊號感測之穩定性以及後續運算處理之精準度,因此光電二極體需要維持高線性度。前述線性度是指所接收之光源強度與光電二極體本身產生之光電流之比值為常數,當比值越小代表線性度越高,在此先行說明。The photodiode structure of the present invention can be applied to smart wearable devices. Smart wearable devices use photodiodes as optical sensors to measure body parameters such as pulse and/or blood oxygen concentration. In order to maintain the stability of signal sensing and the accuracy of subsequent calculation processing, the photodiode needs to maintain high linearity. The aforementioned linearity refers to the ratio of the intensity of the received light source to the photocurrent generated by the photodiode itself as a constant. The smaller the ratio, the higher the linearity. This is explained in advance.

以下請一併參考圖1至圖2B,其中圖1為本發明之光電二極體結構之製造方法之流程圖,圖2A為本發明之光電二極體結構於形成第二半導體層前之結構示意圖,圖2B為本發明之光電二極體結構於形成第二半導體層後之結構示意圖。如圖1至圖2B所示,本發明之光電二極體結構之製造方法包括以下步驟:Please refer to Figures 1 to 2B below, where Figure 1 is a flow chart of the manufacturing method of the photodiode structure of the present invention, Figure 2A is a schematic diagram of the structure of the photodiode structure of the present invention before the second semiconductor layer is formed, and Figure 2B is a schematic diagram of the structure of the photodiode structure of the present invention after the second semiconductor layer is formed. As shown in Figures 1 to 2B, the manufacturing method of the photodiode structure of the present invention includes the following steps:

步驟S1:提供一基材。Step S1: providing a substrate.

首先,本發明藉由提供一基材10以作為本發明之光電二極體結構1之基礎結構件。基材10可利用半導體材料製程,例如高摻雜之N型半導體(即N+半導體),但前述半導體材料之選用會依設計需求不同而改變。First, the present invention provides a substrate 10 as a basic structural member of the photodiode structure 1 of the present invention. The substrate 10 can be made of semiconductor material, such as highly doped N-type semiconductor (i.e., N+ semiconductor), but the selection of the aforementioned semiconductor material will vary depending on different design requirements.

步驟S2:執行磊晶製程以於該基材上形成第一半導體層。Step S2: performing an epitaxial process to form a first semiconductor layer on the substrate.

於前述步驟S1提供基材10之後,接著本發明可針對基材10之一側之表面執行磊晶(epitaxy,簡稱EPI)製程,以於基材10上形成第一半導體層20。第一半導體層20可利用低摻雜之N型半導體(即N-半導體)製程,但前述半導體材料之選用會依設計需求不同而改變。After providing the substrate 10 in the aforementioned step S1, the present invention can then perform an epitaxy (EPI) process on a surface of one side of the substrate 10 to form a first semiconductor layer 20 on the substrate 10. The first semiconductor layer 20 can utilize a low-doped N-type semiconductor (i.e., N-semiconductor) process, but the selection of the aforementioned semiconductor material will vary depending on different design requirements.

一般而言,在第一半導體層20形成後,會針對第一半導體層20之裸露側之表面執行初始氧化製程,以於該表面形成氧化層作為絕緣層使用,在本發明之光電二極體結構之製造方法中亦可於第一半導體層20形成後執行相同製程,但本發明不以此為限。Generally speaking, after the first semiconductor layer 20 is formed, an initial oxidation process is performed on the surface of the exposed side of the first semiconductor layer 20 to form an oxide layer on the surface to be used as an insulating layer. In the manufacturing method of the photodiode structure of the present invention, the same process can also be performed after the first semiconductor layer 20 is formed, but the present invention is not limited thereto.

步驟S3:執行主動區圖形化蝕刻製程以於第一半導體層上形成凹陷部。Step S3: performing an active region patterning etching process to form a recessed portion on the first semiconductor layer.

於前述步驟S2形成第一半導體層20後,接著本發明可針對第一半導體層20之裸露側之表面執行主動區圖形化蝕刻製程,例如採用微影製程(photolithography)於第一半導體層20上形成必要之主動區幾何圖形結構。在本發明中,第一半導體層20藉由執行主動區圖形化蝕刻製程後至少可形成凹陷部21,用以供設置後述之第二半導體層40(請參閱圖2B)。After forming the first semiconductor layer 20 in the aforementioned step S2, the present invention can then perform an active region patterning etching process on the surface of the exposed side of the first semiconductor layer 20, for example, using a photolithography process to form a necessary active region geometric structure on the first semiconductor layer 20. In the present invention, the first semiconductor layer 20 can at least form a recessed portion 21 after performing the active region patterning etching process, for providing the second semiconductor layer 40 described later (see FIG. 2B ).

步驟S4:執行第一塗佈製程以於第一半導體層上形成第一抗反射層。Step S4: performing a first coating process to form a first anti-reflection layer on the first semiconductor layer.

於前述步驟S3後,接著本發明可針對第一半導體層20之裸露側之表面執行第一塗佈製程,以於第一半導體層20上形成第一抗反射層30。第一抗反射層30可完全覆蓋第一半導體層20之凹陷部21。在本發明中,第一塗佈製程採用低壓化學氣相沉積(Low-pressure chemical vapor deposition,簡稱LPCVD)製程,且前述LPCVD製程係於高溫環境下執行。第一塗佈製程之製程溫度不低於800℃,例如在本發明之一實施例中,第一塗佈製程之製程溫度約為800℃,但本發明不以此為限。此外,在本發明之一實施例中,第一抗反射層主要係以需經由高溫成形之氮化矽製程,且藉由第一塗佈製程所形成之第一抗反射層30之厚度介於20至30nm之間。例如在本發明之一實施例中,第一抗反射層30之厚度約為25 nm,但第一抗反射層30之厚度可隨著選用材料不同或設計需求不同而改變。After the aforementioned step S3, the present invention can then perform a first coating process on the surface of the exposed side of the first semiconductor layer 20 to form a first anti-reflection layer 30 on the first semiconductor layer 20. The first anti-reflection layer 30 can completely cover the recessed portion 21 of the first semiconductor layer 20. In the present invention, the first coating process adopts a low-pressure chemical vapor deposition (LPCVD) process, and the aforementioned LPCVD process is performed in a high temperature environment. The process temperature of the first coating process is not less than 800°C. For example, in one embodiment of the present invention, the process temperature of the first coating process is about 800°C, but the present invention is not limited thereto. In addition, in one embodiment of the present invention, the first anti-reflection layer is mainly formed by a silicon nitride process that needs to be formed by high temperature, and the thickness of the first anti-reflection layer 30 formed by the first coating process is between 20 and 30 nm. For example, in one embodiment of the present invention, the thickness of the first anti-reflection layer 30 is about 25 nm, but the thickness of the first anti-reflection layer 30 can be changed with different materials or design requirements.

步驟S5:執行離子佈值製程以穿過第一抗反射層並於凹陷部內形成第二半導體層。Step S5: performing an ion distribution process to penetrate the first anti-reflection layer and form a second semiconductor layer in the recessed portion.

於前述步驟S4形成第一抗反射層30後,本發明可針對第一半導體層20之凹陷部21之所在位置執行離子佈值製程,以於該凹陷部21內形成第二半導體層40。因離子佈值製程具有較高功率,可將形成第二半導體層40之材料穿過第一抗反射層30而抵達凹陷部21,進而於凹陷部21內形成第二半導體層40。After forming the first anti-reflection layer 30 in the aforementioned step S4, the present invention can perform an ion dosing process on the location of the recessed portion 21 of the first semiconductor layer 20 to form the second semiconductor layer 40 in the recessed portion 21. Since the ion dosing process has a higher power, the material forming the second semiconductor layer 40 can pass through the first anti-reflection layer 30 and reach the recessed portion 21, thereby forming the second semiconductor layer 40 in the recessed portion 21.

由此可知,第二半導體層40因形成於需經高溫處理之第一抗反射層30後,使得第二半導體層40不會受到第一塗佈製程之高溫影響,以確保第二半導體層40本身之材料特性,進而維持本發明之光電二極體結構可提供之高線性度。Therefore, it can be seen that since the second semiconductor layer 40 is formed after the first anti-reflection layer 30 that needs to be treated at a high temperature, the second semiconductor layer 40 will not be affected by the high temperature of the first coating process, thereby ensuring the material properties of the second semiconductor layer 40 itself, and further maintaining the high linearity that the photodiode structure of the present invention can provide.

以下請一併參考圖3及圖4,其中圖3為本發明之光電二極體結構之製造方法之另一流程圖,圖4為本發明之光電二極體結構之整體示意圖。如圖3及圖4所示,本發明之光電二極體結構之製造方法還包括以下步驟:Please refer to FIG. 3 and FIG. 4 together below, where FIG. 3 is another flow chart of the manufacturing method of the photodiode structure of the present invention, and FIG. 4 is an overall schematic diagram of the photodiode structure of the present invention. As shown in FIG. 3 and FIG. 4, the manufacturing method of the photodiode structure of the present invention also includes the following steps:

步驟S6:執行第二塗佈製程以於第一抗反射層上形成第二抗反射層。Step S6: performing a second coating process to form a second anti-reflection layer on the first anti-reflection layer.

於前述步驟S5形成第二半導體層40後,接著本發明可針對第一抗反射層30之裸露側之表面執行第二塗佈製程,以於第一抗反射層30上形成第二抗反射層50。在本發明中,第二塗佈製程採用物理氣相沈積(physical vapor deposition,簡稱PVD)製程,且前述PVD製程之製程溫度低於第一塗佈製程之製程溫度,其中第二塗佈製程之製程溫度為不影響第二半導體層40本身之材料特性之溫度。第二塗佈製程之製程溫度不高於200℃,例如在本發明之一實施例中,第二塗佈製程之製程溫度約為200℃,但本發明不以此為限。此外,在本發明之一實施例中,第二抗反射層50主要係以PVD製程。據此,即使第二塗佈製程執行於第二半導體層40形成後,第二半導體層40也不會受到第二塗佈製程之製程溫度影響而改變本身之材料特性。After forming the second semiconductor layer 40 in the aforementioned step S5, the present invention can then perform a second coating process on the surface of the exposed side of the first anti-reflection layer 30 to form the second anti-reflection layer 50 on the first anti-reflection layer 30. In the present invention, the second coating process adopts a physical vapor deposition (PVD) process, and the process temperature of the aforementioned PVD process is lower than the process temperature of the first coating process, wherein the process temperature of the second coating process is a temperature that does not affect the material properties of the second semiconductor layer 40 itself. The process temperature of the second coating process is not higher than 200°C. For example, in one embodiment of the present invention, the process temperature of the second coating process is about 200°C, but the present invention is not limited thereto. In addition, in one embodiment of the present invention, the second anti-reflection layer 50 is mainly formed by PVD process. Therefore, even if the second coating process is performed after the second semiconductor layer 40 is formed, the second semiconductor layer 40 will not be affected by the process temperature of the second coating process and change its material properties.

一般而言,在第二抗反射層50形成後,可視設計需求不同選擇執行其他單一或複數塗佈製程,以於第二抗反射層50之裸露側表面進一步形成更多層之抗反射層,且該些抗反射層之使用材料及製程也不同於前述第一塗佈製程及第二塗佈製程;但該些抗反射層之製程溫度同樣為不影響第二半導體層40本身之材料特性之溫度。Generally speaking, after the second anti-reflection layer 50 is formed, other single or multiple coating processes can be selected to be executed according to different design requirements to further form more layers of anti-reflection layers on the exposed side surface of the second anti-reflection layer 50, and the materials and processes used for these anti-reflection layers are also different from the aforementioned first coating process and second coating process; however, the process temperature of these anti-reflection layers is also a temperature that does not affect the material properties of the second semiconductor layer 40 itself.

步驟S7:執行第一金屬化製程以形成電性連接基材之第一電極。Step S7: Perform a first metallization process to form a first electrode electrically connected to the substrate.

於前述步驟S6形成第二抗反射層50後,接著本發明可針對基材10之另一裸露側表面執行第一金屬化製程,以於基材10之另一側形成第一電極60。也就是說,在結構上,第一電極60會形成於基材10之下方。在本發明中,第一電極60為負極,但本發明不以此為限。After forming the second anti-reflection layer 50 in the aforementioned step S6, the present invention can then perform a first metallization process on the other exposed side surface of the substrate 10 to form a first electrode 60 on the other side of the substrate 10. In other words, in terms of structure, the first electrode 60 is formed below the substrate 10. In the present invention, the first electrode 60 is a negative electrode, but the present invention is not limited thereto.

步驟S8:執行第二金屬化製程以形成電性連接第二半導體層之第二電極。Step S8: Perform a second metallization process to form a second electrode electrically connected to the second semiconductor layer.

於前述步驟S7形成第二半導體層40後,本發明可針對第二抗反射層50之裸露側表面執行第二金屬化製程,以於第二抗反射層50上形成第二電極70。在結構之實際製作上,會先於第二半導體層40上方之適當位置,針對已形成第一抗反射層30及第二抗反射層50產生穿孔,再藉由執行第二金屬化製程來形成第二電極70,使得第二電極70電性連接第二半導體層40。在本發明中,第一電極60為正極,但本發明不以此為限。After forming the second semiconductor layer 40 in the aforementioned step S7, the present invention can perform a second metallization process on the exposed side surface of the second anti-reflection layer 50 to form a second electrode 70 on the second anti-reflection layer 50. In the actual fabrication of the structure, a through hole is first generated at an appropriate position above the second semiconductor layer 40 for the formed first anti-reflection layer 30 and the second anti-reflection layer 50, and then the second electrode 70 is formed by performing a second metallization process, so that the second electrode 70 is electrically connected to the second semiconductor layer 40. In the present invention, the first electrode 60 is a positive electrode, but the present invention is not limited thereto.

本發明還包括一種使用如前所述之製造方法製程之光電二極體結構1。本發明之光電二極體結構1之結構特徵如圖2或圖4所示,且各細部結構之形成方式已於前述說明中揭露,在此不多加贅述。The present invention also includes a photodiode structure 1 using the manufacturing method and process described above. The structural features of the photodiode structure 1 of the present invention are shown in FIG. 2 or FIG. 4, and the formation method of each detailed structure has been disclosed in the above description, and will not be elaborated here.

以上實施方式本質上僅為輔助說明,且並不欲用以限制申請標的之實施例或該等實施例的應用或用途。此外,儘管已於前述實施方式中提出至少一例示性實施例,但應瞭解本發明仍可存在大量的變化。同樣應瞭解的是,本文所述之實施例並不欲用以透過任何方式限制所請求之申請標的之範圍、用途或組態。相反的,前述實施方式將可提供本領域具有通常知識者一種簡便的指引以實施所述之一或多種實施例。再者,可對元件之功能與排列進行各種變化而不脫離申請專利範圍所界定的範疇,且申請專利範圍包含已知的均等物及在本專利申請案提出申請時的所有可預見均等物。The above embodiments are essentially only for auxiliary explanation and are not intended to limit the embodiments of the application subject or the application or use of such embodiments. In addition, although at least one exemplary embodiment has been proposed in the aforementioned embodiments, it should be understood that the present invention can still exist in a large number of variations. It should also be understood that the embodiments described herein are not intended to limit the scope, use or configuration of the claimed application subject in any way. On the contrary, the aforementioned embodiments will provide a simple guide for those with ordinary knowledge in the field to implement one or more of the embodiments described. Furthermore, various changes can be made to the function and arrangement of the components without departing from the scope defined by the scope of the patent application, and the scope of the patent application includes known equivalents and all foreseeable equivalents at the time of filing the present patent application.

1:光電二極體結構 10:基材 20:第一半導體層 21:凹陷部 30:第一抗反射層 40:第二半導體層 50:第二抗反射層 60:第一電極 70:第二電極 S1~S8:步驟 1: Photodiode structure 10: Substrate 20: First semiconductor layer 21: Recess 30: First anti-reflection layer 40: Second semiconductor layer 50: Second anti-reflection layer 60: First electrode 70: Second electrode S1~S8: Steps

圖1為本發明之光電二極體結構之製造方法之流程圖。 圖2A為本發明之光電二極體結構於形成第二半導體層前之結構示意圖。 圖2B為本發明之光電二極體結構於形成第二半導體層後之結構示意圖。 圖3為本發明之光電二極體結構之製造方法之另一流程圖。 圖4為本發明之光電二極體結構之整體示意圖。 FIG. 1 is a flow chart of the manufacturing method of the photodiode structure of the present invention. FIG. 2A is a schematic diagram of the structure of the photodiode structure of the present invention before the second semiconductor layer is formed. FIG. 2B is a schematic diagram of the structure of the photodiode structure of the present invention after the second semiconductor layer is formed. FIG. 3 is another flow chart of the manufacturing method of the photodiode structure of the present invention. FIG. 4 is an overall schematic diagram of the photodiode structure of the present invention.

S1~S5:步驟 S1~S5: Steps

Claims (12)

一種光電二極體結構之製造方法,該方法包括以下步驟: 提供一基材; 執行一磊晶製程以於該基材上形成一第一半導體層; 執行一主動區圖形化蝕刻製程以於該第一半導體層上形成一凹陷部; 執行一第一塗佈製程以於該第一半導體層上形成一第一抗反射層;以及 執行一離子佈值製程以穿過該第一抗反射層並於該凹陷部內形成一第二半導體層。 A method for manufacturing a photodiode structure, the method comprising the following steps: Providing a substrate; Performing an epitaxial process to form a first semiconductor layer on the substrate; Performing an active region patterning etching process to form a recess on the first semiconductor layer; Performing a first coating process to form a first anti-reflection layer on the first semiconductor layer; and Performing an ion distribution process to pass through the first anti-reflection layer and form a second semiconductor layer in the recess. 如請求項1所述之製造方法,其中該第一塗佈製程為一高溫LPCVD製程。A manufacturing method as described in claim 1, wherein the first coating process is a high temperature LPCVD process. 如請求項2所述之製造方法,其中該第一塗佈製程之製程溫度不低於800℃。A manufacturing method as described in claim 2, wherein the process temperature of the first coating process is not lower than 800°C. 如請求項1所述之製造方法,其中該第一抗反射層之厚度介於20至30nm之間。The manufacturing method as described in claim 1, wherein the thickness of the first anti-reflection layer is between 20 and 30 nm. 如請求項1所述之製造方法,其中該第一抗反射層係以LPCVD製程。A manufacturing method as described in claim 1, wherein the first anti-reflection layer is formed by a LPCVD process. 如請求項1所述之製造方法,更包括以下步驟: 執行一第二塗佈製程以於該第一抗反射層上形成一第二抗反射層; 執行一第一金屬化製程以形成電性連接該基材之一第一電極;以及 執行一第二金屬化製程以形成電性連接該第二半導體層之一第二電極。 The manufacturing method as described in claim 1 further includes the following steps: Performing a second coating process to form a second anti-reflection layer on the first anti-reflection layer; Performing a first metallization process to form a first electrode electrically connected to the substrate; and Performing a second metallization process to form a second electrode electrically connected to the second semiconductor layer. 如請求項6所述之製造方法,其中該第二塗佈製程為一PVD製程,且該第二塗佈製程之製程溫度低於該第一塗佈製程之製程溫度。A manufacturing method as described in claim 6, wherein the second coating process is a PVD process, and the process temperature of the second coating process is lower than the process temperature of the first coating process. 如請求項7所述之製造方法,其中該第二塗佈製程之製程溫度不高於200℃。A manufacturing method as described in claim 7, wherein the process temperature of the second coating process is not higher than 200°C. 如請求項6所述之製造方法,其中該第二抗反射層之厚度介於100至150nm之間。A manufacturing method as described in claim 6, wherein the thickness of the second anti-reflection layer is between 100 and 150 nm. 如請求項6所述之製造方法,其中該第二抗反射層係以PVD製程。A manufacturing method as described in claim 6, wherein the second anti-reflection layer is formed by a PVD process. 如請求項6所述之製造方法,其中該第一半導體層為N型半導體層,該第二半導體層為P型半導體層,該第一電極為負極,且該第二電極為正極。A manufacturing method as described in claim 6, wherein the first semiconductor layer is an N-type semiconductor layer, the second semiconductor layer is a P-type semiconductor layer, the first electrode is a negative electrode, and the second electrode is a positive electrode. 一種使用請求項1至11中任一項所述之製造方法製程之光電二極體結構。A photodiode structure manufactured using the manufacturing method described in any one of claims 1 to 11.
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