TW202419825A - Evaluation circuit for a sensor, and sensor system - Google Patents

Abstract

The invention relates to an evaluation circuit for a capacitive sensor and to a sensor system having such an evaluation circuit. The evaluation circuit comprises an amplifier stage with a transconductance amplifier for converting a voltage signal from the sensor into an electrical current, followed by an integration of the electrical current from the amplifier stage.

Description

Evaluation circuit for sensor and sensor system

The present invention relates to an evaluation circuit for a sensor and a sensor system. In particular, the present invention relates to an evaluation circuit for a capacitive sensor and a sensor system having the capacitive sensor.

The sensor can be used, for example, to provide an output signal corresponding to an actual variable. For example, a voltage signal corresponding to the monitored actual variable can be provided as the output variable. As developments progress, sensors with microelectromechanical systems (MEMS) are increasingly being used.

Document DE 10 2012 200 929 B4 describes, for example, a micro-electromechanical acceleration sensor and a corresponding production method.

In order to detect sensor variables such as acceleration, a capacitance change in the sensor can be detected. For example, a voltage change at a node between two capacitive elements can be monitored and used to determine the sensor value. For this purpose, an evaluation circuit can be connected specifically to the node, which provides an output signal corresponding to the capacitance change and therefore to the voltage change.

The invention discloses an evaluation circuit for a sensor and a sensor system having the features of the independent claims. Advantageous embodiments are furthermore the subject of the dependent claims.

Therefore, the following is proposed: an evaluation circuit for a capacitive sensor, which includes an input terminal, an amplifier stage, and an integrator. The input terminal is designed to be electrically coupled to the output terminal of the capacitive sensor. The amplifier stage is electrically coupled to the input terminal. In addition, the amplifier stage is designed to provide an output current corresponding to the voltage at the input terminal. The integrator includes an operational amplifier. The integrator in this case is designed to integrate the output current of the amplifier stage during a predetermined time. Furthermore, the integrator is designed to provide an electrical output voltage corresponding to the integrated current.

Also proposed is a sensor system comprising a capacitive sensor and an evaluation circuit according to the invention. The sensor in this case is designed to provide a voltage corresponding to the sensor variable.

Advantages of the present invention

The invention is based on the finding that the preparation of the signal provided by the sensor for subsequent processing is extremely important. The usually quite weak signal of the sensor must be amplified with sufficient bandwidth and as low noise as possible without being further affected. Furthermore, it is desirable to provide an output signal with sufficient output power in a form suitable for further processing. For this purpose, corresponding evaluation circuits are usually connected to the sensor terminals of the sensor.

One concept of the invention therefore takes this finding into account and provides an evaluation circuit for a sensor, in particular a capacitive sensor, which meets the above requirements and provides a corresponding signal as an output signal. The output signal provided by the sensor will on the one hand be amplified with as little noise as possible and without any or at least as little external influence as possible. Furthermore, the intention is to provide an output signal that can meet the requirements for any desired further processing, both in terms of power and signal form, i.e. current or voltage.

In particular, sensors or sensor systems with sensor components based on microelectronic systems often initially provide sensor signals which have to be amplified or preprocessed. For example, acceleration can be detected by a sensor element, wherein the sensor element comprises a mass element between two capacitive elements. This mass element can be deflected under the effect of acceleration, so that the capacitance of the capacitive element changes. This also changes the voltage at the node of the series circuit of the two capacitive elements. By using a suitable evaluation circuit, this voltage change can be detected and processed in order to provide an output signal corresponding thereto.

Conventional evaluation circuits may be limited with respect to their noise characteristics and/or their frequency response. It would therefore be desirable to create an evaluation circuit that is optimized for use with such sensor elements.

According to the invention, the signal provided by the sensor (in particular a voltage) is first converted into a corresponding current by means of an amplifier stage (in particular an amplifier stage with a transconductance amplifier). This current can then be integrated in an integrator downstream of an operational amplifier. As a result, the integrator delivers an output signal corresponding to the total current provided by the transconductance amplifier during a specified integration time.

A transconductance amplifier may be understood to mean essentially any kind of circuit configuration which, from an electrical input voltage, supplies an electrical output current corresponding to the electrical input voltage.

An integrator is considered to be a circuit configuration that continuously totals or integrates the current output from the amplifier stage, especially during a predetermined time period, and outputs a signal corresponding thereto, for example: a voltage corresponding to the sum or integration. At the end of the totalization or integration period, the corresponding output signal may be continuously output. This fixed output signal may be continuously output during another predetermined time period. Thereafter, a new totalization or integration period may be executed. If necessary, the previous integration value may be reset, possibly at the beginning of this new totalization or integration period. Alternatively, the previous integration value may also be retained and used as a starting value for the next totalization or integration. In other words, the integrator of the evaluation circuit is not only implemented by a capacitor charged by the output current of the transconductance amplifier, but also by an electronic circuit, in particular a circuit with an operational amplifier. The integrator thus comprises at least one operational amplifier and possibly other components. In the circuit configuration, for example, a capacitor can be provided between the input terminal of the operational amplifier and the output terminal of the operational amplifier. The above configuration of the integrator with the operational amplifier can reduce noise, so that amplification with significantly lower noise can be achieved.

According to one embodiment, the amplifier stage may comprise a two-stage amplifier arrangement having an input amplifier and a downstream transconductance amplifier. This means that any offset of the amplifier stage can be compensated without necessarily having to provide coupling capacitors or the like, which has a beneficial effect on the noise performance.

According to one embodiment, the transconductance amplifier and/or the integrator of the amplifier stage may be designed to operate with correlated double sampling (CDS). For example, using the correlated double sampling technique allows unwanted offsets to be compensated.

According to one embodiment, the evaluation circuit comprises a control device. The control device can be designed to cyclically continuously adjust a plurality of phases in the evaluation circuit. In particular, at least one integration phase and one readout phase can be cyclically adjusted in the evaluation circuit. This means that the current output from the amplifier stage can be initially summed or integrated during the integration phase. The result can then be provided for the duration of the readout phase at the end of this integration phase.

According to one embodiment, the evaluation circuit is designed to integrate the output current of the amplifier stage during an integration phase. After the integration phase is completed, an output signal corresponding to the integrated current can be provided. The value of the previous integration phase can then be reset before another integration phase begins. Alternatively, it is also possible that the subsequent integration phase uses the value of the previous integration phase as a starting value.

According to one embodiment, the evaluation circuit is designed to provide, during the readout phase, an output voltage corresponding to the integrated current at the end of the previous integration phase. Thus, during this readout phase, a fixed value is available, which corresponds to the integrated current at the end of the integration phase.

According to one embodiment, the evaluation circuit includes a sample-and-hold (S&H) element. The S&H element can be designed to sample the voltage provided by the integrator at a predetermined time and provide an output signal corresponding to the sampled voltage. Therefore, the value sampled by the S&H element can be used continuously as a readout value for a specified time period.

According to one embodiment, the control means are designed to set a reset phase before each integration phase. In this reset phase, the amplifier stage can be coupled to the reference potential on the input side. In this way, a kind of initialization can be carried out to compensate for an existing offset or the like if necessary or to reset the value integrated up to that point in time.

Where practical, the above-described embodiments and extensions may be combined with each other in any desired manner. Further embodiments, extensions and implementations of the invention also include combinations of features of the invention described previously or below with respect to the exemplary embodiments, which are not explicitly described. In particular, a person skilled in the art will also be able to add individual ideas as improvements or additions to each of the basic forms of the invention.

FIG. 1 shows a schematic diagram of a block diagram of a sensor system according to an embodiment. The sensor system comprises a sensor 2 and an evaluation circuit 1 connected to the sensor 2. The sensor 2 can be formed, for example, by an acceleration sensor. In this case, for example, a series circuit consisting of two capacitor elements C1 and C2 can be implemented so that a mass element at a node K between the two capacitor elements C1 and C2 deflects under the action of acceleration and the capacitance of the capacitor elements C1 and C2 changes accordingly. As a result, the potential at the node K also changes. This voltage change at the node K can be detected by the connected evaluation circuit 1 and a corresponding output signal can be generated. The sensor 2 can be implemented, for example, by a microelectromechanical system (MEMS). Besides accelerometers, any other sensors operating on a similar capacitive sensor principle are also possible.

For this purpose, the sensor terminal S electrically coupled to the node K can be electrically coupled to the input terminal E of the evaluation circuit 1. For example, an electrical connection can be produced between the sensor terminal S and the input terminal E. Thus, at the input terminal E of the evaluation circuit 1, a voltage exists which corresponds to the voltage of the node K between the two capacitive elements C1 and C2.

The voltage present at the input terminal E can be fed to the amplifier stage 10. If necessary, optional components such as capacitors can be provided between the input terminal E and the amplifier stage 10.

The amplifier stage 10 generates an electrical output current which corresponds to the voltage at the input of the amplifier stage 10 and thus to the voltage at the input terminal E. The amplifier stage 10 may comprise, for example, a transconductance amplifier or something similar for this purpose. The current is provided at the output of the amplifier stage 10.

The output current of the amplifier stage 10 is fed to an integrator 20. This integrator 20 integrates or sums the current output by the amplifier stage 10 and outputs an output signal corresponding to the integration or sum. In particular, an integrator 20 having an operational amplifier or the like can be provided for this purpose. This output signal can be a voltage, for example, whose magnitude corresponds to the sum or integration of the currents provided at the input. This output signal of the integrator 20 can be provided at an output terminal A of the evaluation circuit 1.

The operation of the evaluation circuit 1 can be divided into at least two phases. In the first phase, the integrator 20 can first integrate the output current from the amplifier stage 10. In the second phase, this integration can be stopped or interrupted and the output signal can be provided as a result corresponding to the integration up to this point in time. For this purpose, a switch S2 can be provided between the amplifier stage 10 and the integrator 20. This switch S2 can be closed during the integration phase to connect the output of the amplifier stage 10 to the input of the integrator 20. During the output phase, this switch S2 is opened so that no further integration of the current occurs and a fixed value is output at the output of the integrator 20. During this output phase, in which the switch S2 is opened, another switch S1 is closed, which is arranged between the output of the amplifier stage 10 and, for example, a reference potential. Therefore, the current output from the amplifier stage 10 can flow away through this switch S1 during the output phase.

FIG2 shows a timing diagram for illustrating the integration and readout times of the process in the above configuration including the evaluation circuit 1. In the first time period II of the integration phase, the switch S2 between the output of the amplifier stage 10 and the input of the integrator 20 is closed, so that the current output by the amplifier stage 10 is totaled or integrated by the integrator 20. The switch S1 is opened during this process. In the subsequent output phase of the time period I, the switch S2 is opened and the switch S1 is closed. Therefore, no further integration of the current output by the amplifier stage 10 occurs during this time period, so that a fixed signal is output at the output of the integrator 20. Thus, a signal waveform U_out corresponding to the voltage U_in at the input terminal E of the evaluation circuit 1 is obtained at the output terminal A of the evaluation circuit 1. The transition between the integration phase and the output phase can be made periodically, for example, for a period T. For example, the integration can take place in half a period T/2 and the output phase in the remaining half a period T/2. In principle, however, other relationships between the integration phase and the output phase are also possible.

As shown in Figure 2, the integration value is not reset at the beginning of the integration or between individual integration phases. In other words, the integration adds the input signal to the final value of the previous integration. However, the integration value can be reset if necessary. For example, such a reset can prevent the integration value from reaching the maximum possible value, thus making no further totalization/integration possible.

FIG3 shows a schematic diagram of a block diagram of a sensor system with an evaluation circuit 1 according to a further embodiment. For this embodiment, all statements made above apply in general. The embodiment according to FIG3 differs from the previously described embodiment according to FIG1 in particular in that the integrator 20 is also followed by a sample-and-hold element 30. This sample-and-hold element 30 detects the output value of the integrator 20 at a predetermined time and then provides a fixed output signal which corresponds to the value received at the input.

Furthermore, individual components such as amplifier stage 10, integrator 20 and, if applicable, sample-and-hold element 30 can be implemented as components with correlated double sampling (CDS). An input signal is processed in a first stage and a corresponding output signal is output by the individual components. In a further stage, the inverted output signal can be fed back to the input. This feedback of the output signal to the input side can, for example, compensate for any input offset. This operation can be performed periodically, for example, cyclically.

Finally, Fig. 4 shows a schematic diagram of an example circuit diagram of a sensor system with an evaluation circuit 1 according to an embodiment. Here again, all statements relating to the previous exemplary embodiments generally apply.

In this embodiment, the amplifier stage 10 is designed by way of example as an upstream voltage amplifier 11 and a downstream transconductance amplifier 12 for converting the output voltage of the voltage amplifier 11 into a corresponding current.

Coupling capacitors C_k may be provided between the input terminal E and the amplifier stage 10, as well as between other components of the evaluation circuit 1. The values of the coupling capacitors C_k between the individual stages may be individually selected depending on the design.

In this embodiment, the amplifier stage 10 is designed, for example, as a voltage amplifier 11 and a transconductance amplifier 12 downstream for current-to-voltage conversion.

The evaluation circuit 1 of this embodiment can be operated in, for example, three phases. In a first reset phase, individual components can be reset or initialized. In the directly subsequent measurement and integration phase, the previously described integration of the current output from the amplifier stage 10 is carried out. Finally, during the readout phase 3, a fixed signal value is output, which corresponds to the value at the end of the integration phase. In the readout phase 3, this value can be captured by the sample-and-hold element 30, i.e. received, and then provided as an output value at the output of the sample-and-hold element 30.

The switching times of the individual switching elements are indicated by the markings displayed on the respective switching elements, φ1 for the first time period of the reset phase, φ2 for the second time period of the integration phase, and φ3 for the readout phase. Correspondingly, for example, φ12 indicates a switching operation during the reset phase and the integration phase. Subsequent markings such as "d" or "dd" represent delays in the switching sequence.

In summary, the invention relates to an evaluation circuit for a capacitive sensor and a sensor system having such an evaluation circuit. The evaluation circuit comprises a preferably two-stage amplifier stage with a transconductance amplifier to convert a voltage signal from the sensor into a current, followed by integration of the current from the amplifier stage.

1: Evaluation circuit 2: Sensor 10: Amplifier stage 11: Voltage amplifier 12: Transconductance amplifier 20: Integrator 30: Sample and hold element A: Output terminal C1: Capacitor element C2: Capacitor element E: Input terminal K: Node S: Sensor terminal S1: Switch S2: Switch

Further features and advantages of the present invention are discussed below based on the drawings. In the drawings:

[FIG. 1] is a schematic diagram showing a block diagram of a sensor system having an evaluation circuit according to an embodiment;

[FIG. 2] shows a timing diagram for illustrating integration and readout time according to one embodiment;

[FIG. 3] is a schematic diagram showing a block diagram of a sensor system having an evaluation circuit according to yet another embodiment; and

[FIG. 4] A schematic diagram showing an exemplary block diagram of an evaluation circuit according to an embodiment.

In the drawings, identical reference numerals designate identical or functionally identical components, unless otherwise indicated.

1:Evaluation circuit

2: Sensor

10: Amplifier stage

20: Integrator

A: Output terminal

C1: Capacitor element

C2: Capacitor element

E: Input terminal

K: Node

S: Sensor terminal

S1: switch

S2: switch

Claims (10)

An evaluation circuit (1) for a capacitive sensor (2) having: an input terminal (E) designed to be electrically coupled to an output terminal (S) of the capacitive sensor (2); an amplifier stage (10) electrically coupled to the input terminal (E) and designed to provide an output current corresponding to a voltage at the input terminal (E); and an integrator (20) comprising an operational amplifier, wherein the integrator (20) is designed to integrate the output current of the amplifier stage (10) during a predetermined time period and provide an electrical output voltage corresponding to the integrated current. An evaluation circuit (1) as claimed in claim 1, wherein the amplifier stage (10) comprises an input amplifier (11) and a downstream transconductance amplifier (12). An evaluation circuit (1) as claimed in claim 1 or 2, wherein the transconductance amplifier (12) and/or the integrator (20) of the amplifier stage (10) are designed to operate with correlated double sampling. An evaluation circuit (1) as claimed in claim 1 or 2, comprising a control device which is designed to cyclically adjust at least one integration phase and one readout phase of the evaluation circuit (1). An evaluation circuit (1) as claimed in claim 4, wherein the evaluation circuit (1) is designed to integrate the output current of the amplifier stage (10) in the integration phase. As in the evaluation circuit (1) of claim 4, the evaluation circuit (1) is designed to provide, in the readout phase, an output voltage corresponding to the integrated current at the end of the previous integration phase. An evaluation circuit (1) as claimed in claim 1 or 2, having a sample-and-hold element designed to sample the voltage provided by the integrator at a predetermined time and provide an output signal corresponding to the sampled voltage. An evaluation circuit (1) as claimed in claim 1 or 2, wherein before each integration phase a reset phase is provided, wherein the amplifier stage (10) is coupled to a reference potential on the input side. A sensor system having: a capacitive sensor (2) designed to provide a voltage corresponding to a sensor variable; and an evaluation circuit (1) as claimed in any one of claims 1 to 8. A sensor system as claimed in claim 9, wherein the capacitive sensor (2) comprises a micro-electromechanical sensor.

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