TW202416365A - Semiconductor device, semiconductor package and manufacturing method the same - Google Patents

Abstract

A semiconductor device, a semiconductor package, and a manufacturing method the same are provided. The manufacturing method includes the following steps: (a) providing a wafer, the wafer including: an active surface and a back surface; a semiconductor element region and dicing street region, wherein the dicing street region has a plurality of conductive pillars disposed therein, and the conductive pillars are electrically connected to the semiconductor elements in the semiconductor element region, wherein the conductive pillars do not penetrate to the back surface of the wafer; (b) dicing the wafer with a dicing tool to remove part of the wafer and the conductive pillars in the dicing street region, wherein a width of the dicing tool is smaller than a width of the dicing street region; (c) grinding the back surface of the wafer to expose the conductive pillars; and (d) separating the wafer into a plurality of semiconductor chips from the portion of the wafer that is removed from the dicing street region.

Description

Semiconductor element, semiconductor package and manufacturing method thereof

The present invention relates to a semiconductor element and a manufacturing method thereof, and in particular to a semiconductor element and a manufacturing method thereof applied to a three-dimensional stacking package.

At present, the through silicon via (TSV) process is mainly used in the stacking package of dynamic random access memory (DRAM) and complementary metal oxide semiconductor field effect transistor (CMOS), which can reduce the package size. Its process is mainly divided into front-end (FEOL), back-end (BEOL), and packaging (OSAT). The front-end is responsible for etching through holes in silicon wafers and copper plating to form silicon vias, the back-end is grinding and plating solder balls, and the packaging is responsible for testing and solder packaging.

However, the IC size design required by the application side has reached 3nm and is about to break through to 2nm. Therefore, the requirements for available area must also be increased.

Therefore, it is necessary to provide a highly integrated semiconductor device and a manufacturing method thereof to solve the problems existing in the conventional technology.

One purpose of the present invention is to provide a highly integrated semiconductor device and a manufacturing method thereof, which can save area and facilitate packaging or increase transistor design to speed up computing speed.

Another object of the present invention is to provide a highly integrated semiconductor device and a method for manufacturing the same, which can increase the number of transistor designs and thereby speed up computing speed.

To achieve the above-mentioned object, the present invention provides a method for manufacturing a semiconductor device, comprising the following steps: (a) providing a wafer, the wafer comprising: an active surface and a back surface, the back surface being arranged relative to the active surface; a semiconductor device region and a scribe line region, the scribe line region having a plurality of conductive pillars arranged therein, and the conductive pillars being electrically connected to a plurality of semiconductor devices in the semiconductor device region, wherein the conductive pillars do not penetrate into the wafer; (a) cutting the wafer with a cutter to remove a portion of the wafer and a portion of the conductive pillars in the cutting path area, so that the sides of the conductive pillars are exposed after cutting, wherein the width of the cutter is smaller than the width of the cutting path area; (c) grinding the back side of the wafer to expose the conductive pillars; and (d) separating the wafer into a plurality of semiconductor chips through the wafer portion removed in the cutting path area.

In one embodiment of the present invention, the conductive pillars are entirely disposed in the scribe line region but not in the semiconductor device region.

In one embodiment of the present invention, step (a) further includes: performing laser drilling on the wafer to remove a portion of the material of the wafer to form a plurality of through holes, wherein the through holes do not penetrate to the back side of the wafer; and filling a conductive material into the through holes to form the conductive pillars.

In one embodiment of the present invention, the semiconductor device region has a metal layer extending to the cutting path region, wherein when the wafer is laser drilled, the laser simultaneously removes a portion of the metal layer, so that when the conductive material is filled into the through holes, the conductive pillars are electrically connected to the metal layer.

In one embodiment of the present invention, step (a) further includes: disposing a plurality of first conductive elements on the conductive pillars.

In an embodiment of the present invention, the step (a) further includes: disposing a protective film on the wafer and covering the first conductive elements.

In one embodiment of the present invention, step (c) further comprises: disposing a plurality of second conductive elements on the conductive pillars exposed from the back side of the wafer through grinding.

In one embodiment of the present invention, step (d) further comprises: removing the protective film so that the wafer is separated into the semiconductor chips through the wafer portion cut off in the scribe line area.

In one embodiment of the present invention, the width of the cutting road area is 40 micrometers to 60 micrometers, and the width of the tool is 20 micrometers to 40 micrometers.

The present invention also provides a wafer used in the method for manufacturing semiconductor elements as described above, wherein the wafer comprises: an active surface and a back surface, the back surface being arranged relative to the active surface; a semiconductor element region and a cutting path region, the cutting path region having a plurality of conductive pillars arranged therein, and the conductive pillars being electrically connected to the semiconductor elements in the semiconductor element region, wherein the conductive pillars do not penetrate to the back surface of the wafer.

The present invention also provides a semiconductor package, comprising: a substrate, wherein the substrate is provided with a controller chip and at least one passive element, and the substrate has a plurality of connection pads; a first semiconductor chip manufactured by the above-mentioned semiconductor element manufacturing method is stacked on the substrate, wherein the first semiconductor chip is electrically connected to the connection pads through the conductive pillars located on the side of the first semiconductor chip; and a second semiconductor chip manufactured by the above-mentioned semiconductor element manufacturing method is stacked on the first semiconductor chip, wherein the second semiconductor chip is electrically connected to the conductive pillars located on the side of the first semiconductor chip through the conductive pillars located on the side of the second semiconductor chip.

In order to make the above and other purposes, features and advantages of the present invention more clearly understood, the preferred embodiments of the present invention are specifically cited below and described in detail with reference to the attached drawings. Furthermore, the directional terms mentioned in the present invention, such as up, down, top, bottom, front, back, left, right, inside, outside, side, periphery, center, horizontal, transverse, vertical, longitudinal, axial, radial, topmost or bottommost, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to explain and understand the present invention, but not to limit the present invention.

As used herein, reference to a numerical range for a variable is intended to mean that the variable is equal to any value within the range. Thus, for a variable that is itself discontinuous, the variable is equal to any integer value within the numerical range, including the endpoints of the range. Similarly, for a variable that is itself continuous, the variable is equal to any real value within the numerical range, including the endpoints of the range. As an example, and not a limitation, a variable described as having a value between 0-2 takes on a value of 0, 1, or 2 if the variable is itself discontinuous, and takes on a value of 0.0, 0.1, 0.01, 0.001, or any other real value ≥0 and ≤2 if the variable is itself continuous.

Please refer to FIG. 1, which shows a schematic flow diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention. The method for manufacturing a semiconductor device (S100) comprises the following steps: (S101) providing a wafer, the wafer comprising: an active surface and a back surface, the back surface being arranged relative to the active surface; a semiconductor device region and a scribe line region, the scribe line region having a plurality of conductive posts arranged therein, and the conductive posts being electrically connected to a plurality of semiconductor devices in the semiconductor device region, wherein the conductive posts do not penetrate to the back surface of the wafer; (S102) 102) using a cutter to cut the wafer to remove part of the wafer and part of the conductive pillars in the cutting path area, so that the side surfaces of the conductive pillars are exposed after cutting, wherein the width of the cutter is smaller than the width of the cutting path area; (S103) grinding the back side of the wafer to expose the conductive pillars; and (S104) separating the wafer into a plurality of semiconductor chips through the wafer portion removed in the cutting path area.

Please refer to Figures 2 to 10, which show the structural schematic diagrams of the manufacturing method of the semiconductor element of the embodiment of the present invention. First, please refer to Figure 2, a wafer 100 includes: an active surface 101, a back surface 102, a semiconductor element area 103 and a cutting path area 104. The back surface 102 is arranged relative to the active surface 101. Optionally, the wafer is a silicon wafer. The wafer 100 includes a substrate 106, on which a plurality of semiconductor elements 105 are arranged, and the semiconductor elements 105 are connected to a metal layer 107 to connect the semiconductor elements to the outside world. The semiconductor elements 105 and the metal layer 107 are covered with an insulating layer 108 to protect the semiconductor elements 105 and the metal layer 107.

First, please refer to FIG. 3 and FIG. 4 , the dicing area 104 has a plurality of conductive posts 110 disposed therein, and the conductive posts 110 are electrically connected to a plurality of semiconductor elements 105 in the semiconductor element area 103, wherein the conductive posts 110 do not penetrate to the back side 102 of the wafer 100. It is worth noting that the conductive posts 110 are disposed entirely in the dicing area 104 and are not disposed in the semiconductor element area 103. In addition, the conductive posts 110 may be formed by laser drilling the wafer 100 to remove a portion of the material of the wafer 100 to form a plurality of through holes 109. It should be noted that the through holes 109 do not penetrate to the back side 102 of the wafer 100. Next, a conductive material is filled into the through holes 109 to form the conductive pillars 110. The conductive pillars 110 do not penetrate to the back side 102 of the wafer 100.

In this embodiment, the semiconductor device region 103 has a metal layer 107 extending to the cutting path region 104, wherein when the wafer 100 is laser drilled, the laser simultaneously removes a portion of the metal layer 107, so that when the conductive material is filled into the through holes 109, the conductive pillars 110 form an electrical connection with the metal layer 107.

Next, as shown in FIG. 5 , a cutter 120 is used to cut the wafer 100 to remove a portion of the wafer 100 and a portion of the conductive pillars 110 in the cut zone area 104 , so that the sides of the conductive pillars 110 are exposed after cutting, wherein the width W1 of the cutter 120 is smaller than the width W2 of the cut zone area.

Optionally, as shown in FIG6 , the present embodiment further includes: disposing a plurality of first conductive elements 130 on the conductive pillars 110. In addition, as shown in FIG7 , a protective film 140 is disposed on the wafer 100 and covers the first conductive elements 130. It should be noted that the step of disposing the first conductive elements 130 on the conductive pillars 110 shown in FIG6 can be performed before or after the step in FIG5 .

Next, as shown in FIG. 8 , the back surface 102 of the wafer 100 is ground to expose the conductive pillars 110 .

Optionally, as shown in FIG. 9 , a plurality of second conductive elements 150 are disposed on the conductive pillars 110 exposed from the back side 102 of the wafer 100 by grinding.

Finally, as shown in FIG. 10 , the protective film 140 is removed, so that the wafer 100 is separated into a plurality of semiconductor chips 200 through the portion of the wafer 100 cut away in the scribe line region 104 .

In one embodiment of the present invention, the width of the scribe line region is 40 microns to 60 microns, and the width of the tool is 20 microns to 40 microns.

As shown in FIG. 11 , FIG. 11 shows a schematic diagram of a top view of a semiconductor chip 200 manufactured according to the method for manufacturing a semiconductor device of the present invention. The semiconductor chip 200 includes: a semiconductor device region 203 and a saw street residual region 204. The saw street residual region 204 has a plurality of conductive pillars 210 disposed at the edge of the semiconductor chip 200. It should be noted that the conductive pillars 210 are not completely cylindrical (e.g., semi-cylindrical) after being cut.

It should be noted that, in general, under the requirement of integration, a silicon via with a diameter of 10 microns on a chip is very large for DRAM, and it takes up a lot of space if a large number of I/Os need to be designed. This design is to design the aperture on the cutting path, which can reduce the chip size and save space, and can be completed in the later stage. In the case of a cutting path of 40 to 60 microns, the present invention can set a silicon via structure with a diameter of about 10 microns at both ends of the cutting path, and the total aperture of the two ends is about 20 microns. In addition to the silicon via, there is still 20 to 40 microns of space reserved for cutting, so there is still enough space for cutting. The present invention moves the location of the silicon via structure to the cutting path to save area, thereby facilitating packaging, or increasing the number of transistor designs, thereby speeding up the computing speed of electronic devices. For example, if there are 100 I/Os, the area occupied is about 0.1 mm ² . With TSMC's 5-nanometer process, the design of the present invention can increase the number of transistors by 15,000,000 transistors, or reduce the size of the chip.

As described above, the present invention also provides a wafer 100 for the method of manufacturing a semiconductor device as described above. As shown in FIG. 4 , the wafer 100 includes: an active surface 101 and a back surface 102, the back surface 102 being arranged relative to the active surface 101; a semiconductor device region 103 and a scribe line region 104, the scribe line region 104 having a plurality of conductive posts 110 arranged therein, and the conductive posts 110 are electrically connected to the semiconductor devices 105 in the semiconductor device region 103, wherein the conductive posts 110 do not penetrate to the back surface 102 of the wafer 100.

The present invention also provides a semiconductor package, comprising: a substrate, wherein the substrate is provided with a controller chip and at least one passive element, and the substrate has a plurality of connection pads; a first semiconductor chip manufactured by the above-mentioned semiconductor element manufacturing method is stacked on the substrate, wherein the first semiconductor chip is electrically connected to the connection pads through the conductive pillars located on the side of the first semiconductor chip; and a second semiconductor chip manufactured by the above-mentioned semiconductor element manufacturing method is stacked on the first semiconductor chip, wherein the second semiconductor chip is electrically connected to the conductive pillars located on the side of the first semiconductor chip through the conductive pillars located on the side of the second semiconductor chip.

Please refer to Fig. 12, which shows a front view of the semiconductor package of the first embodiment of the present invention. The semiconductor package 30 comprises: a substrate 310, wherein the substrate 310 is provided with a controller chip 311 and at least one passive component 312, and the substrate 310 has a plurality of connection pads 313.

In one embodiment, the controller chip 311 is a microcontroller (MCU). Optionally, the passive components 312 may be resistors or capacitors and are electrically connected to the controller chip 311 .

Optionally, the controller chip 311 is connected to the pads on the surface of the substrate 310 by flip chip connection. The passive components 312 are connected to the circuits on the surface of the substrate 310 by surface mounting technology.

A first semiconductor chip 320 is stacked on the substrate 310, and the first semiconductor chip 320 is manufactured by the manufacturing method of the semiconductor device as described above. The first semiconductor chip 320 is stacked on a surface of the substrate 310, wherein the first semiconductor chip 320 is electrically connected to the connection pads 313 through the first conductive pillars 321 located on the side of the first semiconductor chip 320. Optionally, the first semiconductor chip 320 conducts the first conductive pillars 321 of the first semiconductor chip 320 with the connection pads 313 through a plurality of first conductive bumps 322.

Optionally, the first semiconductor chip 320 may be a flash memory chip. The first semiconductor chip 320 may be controlled by the controller chip 311.

It is worth noting that the first semiconductor chip 320 has a similar structure as shown in FIG. 11 , that is, the first conductive pillars 321 are in an incomplete cylindrical shape (eg, a semi-cylindrical shape) after being cut.

A second semiconductor chip 330 is stacked on the first semiconductor chip 320. The second semiconductor chip 330 is manufactured by the semiconductor device manufacturing method described above.

The second semiconductor chip 330 is stacked on a surface of the first semiconductor chip 320 , wherein the second semiconductor chip 330 is electrically connected to the first semiconductor chip 320 via the second conductive pillars 331 located on the side of the second semiconductor chip 330 .

Optionally, the second semiconductor chip 330 conducts the second conductive pillars 331 of the second semiconductor chip 330 with the first conductive pillars 321 of the first semiconductor chip 320 through a plurality of second conductive bumps 332. The second semiconductor chip 330 can be controlled by the controller chip 311.

It is worth noting that the second semiconductor chip 330 also has a similar structure as shown in FIG. 11 , that is, the second conductive pillars 331 are in an incomplete cylindrical shape (eg, a semi-cylindrical shape) after being cut.

In addition, in some embodiments of the present invention, a plurality of third conductive pillars 341 , such as copper pillars, are disposed on the connection pads 313 , and the first semiconductor chip 320 conducts electricity between the first conductive pillars 321 of the first semiconductor chip 320 and the third conductive pillars 341 through the first conductive bumps 322 .

It is worth noting that the third conductive posts 341 are different from the first conductive posts 321 and the second conductive posts 331 , that is, the third conductive posts 341 are not cut and present a complete cylindrical shape.

Please refer to FIG. 13, which shows a front view of the semiconductor package of the second embodiment of the present invention. The semiconductor package of the second embodiment of the present invention shown in FIG. 13 is substantially the same as the semiconductor package of the first embodiment of the present invention shown in FIG. 12, except that the substrate 310 and the first semiconductor chip 320 are electrically connected through the second substrate 450 and the third substrate 460. The semiconductor package of the second embodiment of the present invention will be described in detail below with reference to FIG. 13.

The semiconductor package 40 includes a first substrate 410 , wherein the first substrate 410 is provided with a controller chip 411 and at least one passive component 412 , and the first substrate 410 has a plurality of first connection pads 413 .

In one embodiment, the controller chip 411 is a microcontroller (MCU). Optionally, the passive components 412 may be resistors or capacitors and are electrically connected to the controller chip 411 .

Optionally, the controller chip 411 is connected to the pads on the surface of the first substrate 410 by flip chip connection. The passive components 412 are connected to the circuits on the surface of the first substrate 410 by surface mounting technology.

A second substrate 450 is stacked on the first substrate 410. Optionally, the second substrate 450 is electrically connected to the first substrate 410 through a plurality of conductive members (eg, solder balls, conductive bumps, copper pillars, etc.).

The second substrate 450 has a hollowed-out area (eg, in a square shape when viewed from top to bottom) for arranging the controller chip 411 and the at least one passive component 412. Optionally, the second substrate 450 has a plurality of circuit layers therein.

A third substrate 460 is stacked on the second substrate 450. The third substrate 460 may have a plurality of circuit layers, and a plurality of second connection pads 463 are disposed on a surface of the third substrate 460. Optionally, the third substrate 460 is electrically connected to the second substrate 450 through a plurality of conductive members (e.g., solder balls, conductive bumps, copper pillars, etc.).

Alternatively, the first substrate 410 , the second substrate 450 , and the third substrate 460 may be electrically connected to each other by eutectic bonding.

A first semiconductor chip 420 is stacked on the third substrate 460. The first semiconductor chip 420 is manufactured by the semiconductor device manufacturing method described above. The first semiconductor chip 420 is stacked on a surface of the third substrate 460, wherein the first semiconductor chip 420 is electrically connected to the second connection pads 463 on the third substrate 460 through the first conductive pillars 421 located on the side of the first semiconductor chip 420.

Optionally, the first semiconductor chip 420 conducts electricity between the first conductive pillars 421 of the first semiconductor chip 420 and the second connection pads 463 through a plurality of first conductive members 422 (eg, solder balls, conductive bumps, copper pillars, etc.).

Optionally, the first semiconductor chip 420 may be a flash memory chip. The first semiconductor chip 420 may be controlled by the controller chip 411.

It is worth noting that the first semiconductor chip 420 has a similar structure as shown in FIG. 11 , that is, the first conductive pillars 421 are in an incomplete cylindrical shape (eg, a semi-cylindrical shape) after being cut.

A second semiconductor chip 430 is stacked on the first semiconductor chip 420. The second semiconductor chip 430 is manufactured by the semiconductor device manufacturing method described above.

The second semiconductor chip 430 is stacked on a surface of the first semiconductor chip 420 , wherein the second semiconductor chip 430 is electrically connected to the first semiconductor chip 420 via the second conductive pillars 431 located on the side of the second semiconductor chip 430 .

Optionally, the second semiconductor chip 430 conducts electricity to the second conductive pillars 431 of the second semiconductor chip 430 and the first conductive pillars 421 of the first semiconductor chip 420 through a plurality of second conductive members 432 (e.g., solder balls, conductive bumps, copper pillars, etc.), so that the second semiconductor chip 430 can be controlled by the controller chip 411.

It is worth noting that the second semiconductor chip 430 also has a similar structure as shown in FIG. 11 , that is, the second conductive pillars 431 are in an incomplete cylindrical shape (eg, a semi-cylindrical shape) after being cut.

Although the present invention has been disclosed with preferred embodiments, they are not intended to limit the present invention. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined in the attached patent application.

S100: Method for manufacturing semiconductor element S101~S104: Steps 100: Wafer 101: Active surface 102: Back surface 103: Semiconductor element region 104: Cutting path region 105: Semiconductor element 106: Substrate 107: Metal layer 108: Insulating layer 109: Through hole 110: Conductive column 120: Cutter 130: First conductive element 140: Protective film 150: Second conductive element 200: Semiconductor chip 203: Semiconductor element region 204: Cutting path residual region 210: Conductive column 30: Semiconductor package 310: Substrate 311: Controller chip 312: Passive element 313: connection pad 320: first semiconductor chip 321: first conductive column 322: first conductive bump 330: second semiconductor chip 331: second conductive column 332: second conductive bump 341: third conductive column 40: semiconductor package 410: first substrate 411: controller chip 412: passive element 413: first connection pad 420: first semiconductor chip 421: first conductive column 422: first conductive element 430: second semiconductor chip 431: second conductive column 432: second conductive element 441: third conductive column 450: second substrate 460: third substrate 463: second connection pad W1: tool width W2: Cutting area width

[Figure 1]: Schematic diagram of the process of the method for manufacturing a semiconductor element of an embodiment of the present invention. [Figure 2] to [Figure 10]: Schematic diagram of the structure of the method for manufacturing a semiconductor element of an embodiment of the present invention. [Figure 11]: Schematic diagram of the top view of the structure of a semiconductor chip manufactured by the method for manufacturing a semiconductor element of an embodiment of the present invention. [Figure 12]: Schematic diagram of the front view of the structure of the semiconductor package of the first embodiment of the present invention. [Figure 13]: Schematic diagram of the front view of the structure of the semiconductor package of the second embodiment of the present invention.

S100: Method for manufacturing semiconductor components

S101~S104: Steps

Claims (10)

A method for manufacturing a semiconductor device comprises the following steps: (a) providing a wafer, the wafer comprising: an active surface and a back surface, the back surface being arranged relative to the active surface; a semiconductor device region and a cutting path region, the cutting path region having a plurality of conductive pillars arranged therein, and the conductive pillars being electrically connected to a plurality of semiconductor devices in the semiconductor device region, wherein the conductive pillars do not penetrate to the back surface of the wafer; (b) using a cutter to cut the wafer to remove a portion of the wafer and a portion of the conductive pillars in the cutting path region, so that the side surfaces of the conductive pillars after cutting are exposed, wherein the width of the cutter is smaller than the width of the cutting path region; (c) grinding the back surface of the wafer to expose the conductive pillars; and (d) The wafer is separated into a plurality of semiconductor chips by cutting off the wafer portion in the dicing area. A method for manufacturing a semiconductor device as described in claim 1, wherein the conductive pillars are entirely disposed in the scribe line region but not in the semiconductor device region. A method for manufacturing a semiconductor element as described in claim 1, wherein step (a) further includes: laser drilling the wafer to remove a portion of the wafer material to form a plurality of through holes, wherein the through holes do not penetrate to the back side of the wafer; and filling a conductive material into the through holes to form the conductive pillars. A method for manufacturing a semiconductor element as described in claim 3, wherein the semiconductor element region has a metal layer extending to the cutting path region, wherein when the wafer is laser drilled, the laser simultaneously removes a portion of the metal layer, so that when the conductive material is filled into the through holes, the conductive pillars form an electrical connection with the metal layer. The method for manufacturing a semiconductor device as described in claim 1, wherein step (a) further comprises: disposing a plurality of first conductive elements on the conductive pillars. The method for manufacturing a semiconductor element as described in claim 5, wherein step (a) further includes: providing a protective film on the wafer and covering the first conductive elements. The method for manufacturing a semiconductor device as described in claim 6, wherein step (c) further comprises: disposing a plurality of second conductive elements on the conductive pillars exposed from the back side of the wafer by grinding. A method for manufacturing a semiconductor device as described in claim 7, wherein step (d) further comprises: removing the protective film so that the wafer is separated into the semiconductor chips through the wafer portion cut off in the cutting path area. A method for manufacturing a semiconductor device as described in claim 1, wherein the width of the cutting road area is 40 microns to 60 microns, and the width of the tool is 20 microns to 40 microns. A semiconductor package comprises: a substrate, wherein the substrate is provided with a controller chip and at least one passive element, and the substrate has a plurality of connection pads; a first semiconductor chip manufactured by the method for manufacturing a semiconductor element as described in claim items 1 to 9 is stacked on the substrate, wherein the first semiconductor chip is electrically connected to the connection pads through the conductive pillars located on the side of the first semiconductor chip; and a second semiconductor chip manufactured by the method for manufacturing a semiconductor element as described in claim items 1 to 9 is stacked on the first semiconductor chip, wherein the second semiconductor chip is electrically connected to the conductive pillars located on the side of the first semiconductor chip through the conductive pillars located on the side of the second semiconductor chip.

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