CN109671680A - The chip packaging piece of tube core structure and forming method thereof with different height - Google Patents
The chip packaging piece of tube core structure and forming method thereof with different height Download PDFInfo
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- CN109671680A CN109671680A CN201810789422.XA CN201810789422A CN109671680A CN 109671680 A CN109671680 A CN 109671680A CN 201810789422 A CN201810789422 A CN 201810789422A CN 109671680 A CN109671680 A CN 109671680A
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- chip stack
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The present invention provides structures of chip packaging piece and forming method thereof.Chip packaging piece includes substrate, is attached to the first chip stack of substrate and is attached to the second chip stack of substrate.First chip stack and the second chip stack are attached to the same side of substrate.Chip packaging piece further includes the molding compound around the first chip stack and the second chip stack.Molding compound covers the most top surface of the first chip stack.The most top surface of molding compound and the most top surface of the second chip stack are substantially coplanar.The embodiment of the present invention further relates to have chip packaging piece of tube core structure of different height and forming method thereof.
Description
Technical field
The embodiment of the present invention is related to having chip packaging piece of tube core structure of different height and forming method thereof.
Background technique
Semiconductor devices is used in the various electronic applications of such as PC, mobile phone, digital camera and other electronic equipments
In.It is sequentially depositing insulation or dielectric layer, conductive layer and semiconductor layer by side on a semiconductor substrate, and uses photoetching and erosion
Carving technology patterns each material layer and manufactures these semiconductor devices to form circuit unit and element on a semiconductor substrate.
Semiconductor industry continually refines each electronic building brick by the continuous reduction of minimal parts size (for example, brilliant
Body pipe, diode, resistor, capacitor etc.) integration density, this allows to integrate more components in a given area.?
In some applications, these lesser electronic building bricks are also using the lesser packaging part using less area and lesser height.
New encapsulation technology has been developed to improve the density and function of semiconductor devices.For this of semiconductor devices
A little relatively new encapsulation technologies face manufacture challenge.
Summary of the invention
The embodiment provides a kind of packaging parts, comprising: substrate；First chip stack is attached to the lining
Bottom；Second chip stack, is attached to the substrate, and first chip stack and second chip stack are attached to
The same side of the substrate；And molding compound, first chip stack and second chip stack are surrounded, it is described
Molding compound covers the most top surface of first chip stack, and the most top surface of the molding compound and second chip stack
The most top surface of part is coplanar.
Another embodiment of the present invention provides a kind of packaging part, comprising: substrate, the substrate have first surface and the
Two surfaces, the second surface are opposite with the first surface；First chip stack is bonded to the first table of the substrate
Face；Second chip stack, is bonded to the first surface of the substrate adjacent with first chip stack, and described second
Chip stack is higher than first chip stack；And molding compound, along the most top surface of first chip stack
Extend, the most top surface of first chip stack is the farthest surface of substrate described in the distance of first chip stack.
Another embodiment of the present invention provides a kind of packaging part, comprising: substrate；First chip stack is bonded to institute
State substrate；Second chip stack is bonded to the substrate；Underfill layer, in first chip stack and the lining
Extend between bottom and between second chip stack and the substrate, the Underfill layer at least partially along
The side wall of first chip stack and the side wall of second chip stack extend；And encapsulated layer, it is located at the bottom
Above portion's filled layer, the encapsulated layer extends along the most top surface of first chip stack, the Underfill layer and institute
The interface between encapsulated layer is stated to be located on the lowest surfaces of first chip stack and be located at first chip stack
Most top surface below.
Detailed description of the invention
When reading in conjunction with the accompanying drawings, various aspects of the invention are best understood from described in detail below.It should
Note that according to the standard practices in industry, all parts are not drawn on scale.In fact, in order to clearly discuss, various parts
Size can be arbitrarily increased or decreased.
Figure 1A-Fig. 1 F is the section in each stage of the technique in accordance with some embodiments for being used to form chip packaging piece
Figure.
Fig. 2 is the sectional view of chip packaging piece in accordance with some embodiments.
Fig. 3 A- Fig. 3 E is the section in each stage of the technique in accordance with some embodiments for being used to form chip packaging piece
Figure.
Fig. 4 is the sectional view of chip packaging piece in accordance with some embodiments.
Fig. 5 is the sectional view of chip packaging piece in accordance with some embodiments.
Fig. 6 is the sectional view of chip packaging piece in accordance with some embodiments.
Fig. 7 is the sectional view of chip packaging piece in accordance with some embodiments.
Fig. 8 is the sectional view of chip packaging piece in accordance with some embodiments.
Fig. 9 is the sectional view of chip packaging piece in accordance with some embodiments.
Figure 10 is the sectional view of chip packaging piece in accordance with some embodiments.
Figure 11 is the sectional view of chip packaging piece in accordance with some embodiments.
Figure 12 is the sectional view of chip packaging piece in accordance with some embodiments.
Figure 13 is the sectional view of chip packaging piece in accordance with some embodiments.
Specific embodiment
Following disclosure provides the different embodiments or example of many different characteristics for realizing provided theme.
The specific example of component and arrangement is described below to simplify the present invention.Certainly, these are only example, are not intended to limit this
Invention.For example, in the following description, above second component or the upper formation first component may include the first component and second
The embodiment that component is formed in a manner of directly contacting, and also may include can be with shape between the first component and second component
At additional component, so that the embodiment that the first component and second component can be not directly contacted with.In addition, the present invention can be
Repeat reference numerals and/or character in each example.The repetition is that for purposes of simplicity and clarity, and itself is not indicated
The relationship between each embodiment and/or configuration discussed.
Moreover, for ease of description, can be used herein such as " in ... lower section ", " ... below ", " lower part ", " ...
On ", the spatially relative terms such as " top " to be to describe an element or component and another (or other) member as shown in the figure
The relationship of part or component.Other than the orientation shown in figure, spatially relative term is intended to include device in use or operation
Different direction.Device can otherwise orient (be rotated by 90 ° or in other directions), and space phase as used herein
Corresponding explanation can similarly be made to descriptor.
Some embodiments of the present invention are described.Figure 1A-Fig. 1 F is in accordance with some embodiments to be used to form chip packaging piece
Technique each stage sectional view.Volume can be provided before, during and/or after the stage described in Figure 1A-Fig. 1 F
Outer operation.For different embodiments, described some stages can be replaced or eliminated.Additional component can be added
To semiconductor device structure.For different embodiments, some components described below can be replaced or eliminated.Although with specific
The operation that sequence is implemented discusses some embodiments, but can implement these operations with another logical order.
As shown in Figure 1A, according to some embodiments, semiconductor chip 10 and chip stack 20 are engaged above substrate 180
With 30.In some embodiments, semiconductor chip 10 is higher than chip stack 20 or 30.In some embodiments, semiconductor core
Piece 10 includes the interconnection structure (not shown) of semiconductor substrate 100 and formation on a semiconductor substrate 100.For example, in semiconductor
Interconnection structure is formed on the bottom surface of substrate 100.Interconnection structure includes multiple interlayer dielectric layers and is formed in interlayer dielectric layer
Multiple conductive components.These conductive components include conducting wire, conductive through hole and conductive contact piece.The some parts of conductive component can be with
As conductive welding disk.
In some embodiments, various components are formed in semiconductor substrate 100.The example packet of various components
Transistor is included (for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET), complementary metal oxide semiconductor (CMOS)
Transistor, bipolar junction transistor (BJT), high voltage transistor, high frequency transistor, p-channel and/or n-channel field effect transistor
(PFET/NFET)), diode or other suitable elements such as.
By interconnection structure interconnection devices element to form integrated circuit device.Integrated circuit device include logical device,
Memory device (for example, static random access memory, SRAM), radio frequency (RF) device, input/output (I/O) device, on chip
The device or their combination of system (SoC) device, other application types.In some embodiments, semiconductor chip 10 is packet
Include system on chip (SoC) chip of multiple functions.
In some embodiments, each of chip stack 20 and 30 includes the multiple semiconductor elements stacked.Such as figure
Shown in 1A, chip stack 20 include semiconductor element 200,202A, 202B, 202C, 202D, 202E, 202F, 202G and
202H.In some embodiments, chip stack 20 includes the molding compound 210 for sealing and protecting these semiconductor elements.Mould
Plastic layer 210 may include the epoxy for being wherein dispersed with filler.Filler may include non-conductive fibre, insulated particle, its
His suitable element or their combination.
In some embodiments, semiconductor element 202A, 202B, 202C, 202D, 202E, 202F, 202G and 202H is to deposit
Memory die.Memory dice may include such as static random access memory (SRAM) device, dynamic random access memory
(DRAM) memory device of device, other suitable devices or their combination.In some embodiments, semiconductor element 200
It is electrically connected to stack the control tube core of memory dice on it.Chip stack 20 may be used as high bandwidth memory
(HBM).In some embodiments, chip stack 30 is also the high bandwidth memory of the memory dice including multiple stackings.
Can to the embodiment of the present invention many modifications may be made and/or modification.In some embodiments, chip stack 20
It only include one single chip with one in 30.In these cases, reference number 20 or 30 can be used for specified semiconductor chip.
As shown in Figure 1A, in some embodiments, these semiconductor elements 200,202A, 202B, 202C, 202D,
Conductive bond structure 206 is formed between 202E, 202F, 202G and 202H so that they to be bonded together.In some embodiments,
Each of conductive bond structure 206 includes metal column and/or solder projection.In some embodiments, the formation of underfill element 208
To surround and protect conductive bond structure 206 between these semiconductor elements.In some embodiments, underfill element
208 include the epoxy for being wherein dispersed with filler.Filler may include non-conductive fibre, insulated particle, other suitable members
Element or their combination.In some embodiments, size and/or the density for being dispersed in the filler in underfill element 208 are small
In the size and/or density of the filler being dispersed in molding compound 210.
As shown in Figure 1A, in some embodiments, it is formed in some semiconductor elements being located in chip stack 20
Multiple conductive components 282.Each conductive component 282 pass through semiconductor element 200,202A, 202B, 202C, 202D, 202E,
One in 202F, 202G and 202H and it is electrically connected to a conductive bond structure 206.Conductive component 282 is logical as substrate
Hole (TSV).Electric signal can be transmitted between the semiconductor element of these vertical stackings by conductive component 282.
As shown in Figure 1A, conductive bond is passed through according to some embodiments, semiconductor chip 10 and chip stack 20 and 30
Structure 106 is joined on substrate 180.In some embodiments, conductive bond structure 106 include solder projection, metal column convex block,
Other suitable structures or their combination.As shown in Figure 1A, in some embodiments, each conductive bond structure 106 includes
Metal column convex block 102, solder element 104 and metal column convex block 184.For example, metal column convex block 102 and 184 is substantially made of copper.
In some embodiments, multiple metals are formed above the bottom surface of semiconductor chip 10 and chip stack 20 and 30
Column convex block 102.In some embodiments, before being engaged with semiconductor chip 10 and chip stack 20 and 30, in substrate 180
Top forms multiple metal column convex blocks 184.
In some embodiments, the solder material of such as soldering paste is applied to 102 He of metal column convex block before joint technology
On one or two of 184.Later, metal column convex block 102 and 184 is bonded together by solder material.Solder material exists
Solder element 104 is formed between metal column convex block 102 and 184.As a result, as shown in Figure 1A, forming conductive bond structure 106.?
In some embodiments, solder material is the alloy material for including tin (Sn).Solder material further includes another element.Element can be with
Including lead, silver, copper, nickel, bismuth, another suitable element or their combination.In some embodiments, solder material does not include
Lead.
In some embodiments, substrate 180 include semiconductor material, it is ceramic material, insulating materials, polymer material, another
One suitable material or their combination.In some embodiments, substrate 180 is semiconductor substrate.Semiconductor substrate can be
The semiconductor crystal wafer of such as Silicon Wafer.In some embodiments, substrate 180 may include silicon-on-insulator (SOI) substrate.SOI
Substrate may include the semiconductor material layer (for example, silicon, germanium etc.) being formed in above insulating layer (for example, buried oxide etc.),
Wherein, insulating layer is formed on a silicon substrate.
As shown in Figure 1A, according to some embodiments, multiple conductive components 182 are formed in substrate 180.In some embodiments
In, conductive component 182 is formed before forming metal column convex block 184.In some embodiments, each conductive component 182 is electrically connected
It is connected to a metal column convex block 184.Interconnection structure (not shown) including such as redistributing layer can be used in conductive component 182
Electrical connection is formed between metal column convex block 184.In some embodiments, it is formed between conductive component 182 and substrate 180 exhausted
Edge element (not shown) is to prevent the short circuit between different conductive components 182.
In some embodiments, conductive component 182 by copper, aluminium, titanium, tungsten, cobalt, gold, platinum, another suitable material or they
Combination be made.In some embodiments, insulation component is by silica, silicon nitride, silicon oxynitride, silicon carbide, another suitable
Material or their combination are made.In some embodiments, it is led using one or more photoetching and etch process to form restriction
Multiple openings of the position of electrical components 182.Later, insulating layer and conductive layer are sequentially depositing above substrate 180 to fill opening.
Then implement flatening process to remove the part of insulating layer and conductive layer being located at outside opening.As a result, insulating layer and conductive layer
Be located at opening in remainder be respectively formed insulation component and conductive component 182.
As shown in Figure 1B, according to some embodiments, Underfill layer 108 is formed to surround and protect conductive bond structure
106.In some embodiments, Underfill layer 108 is directly contacted with conductive bond structure 106.In some embodiments, pass through
Capillarity is distributed liquid bottom packing material and is solidified to form Underfill layer 108.In some embodiments, bottom
Portion's filled layer 108 includes the epoxy for being wherein dispersed with filler.Filler may include fiber, particle, other suitable members
Element or their combination.
As shown in Figure 1 C, according to some embodiments, encapsulated layer 110 is formed above substrate 180 with sealing semiconductor chips
10 and chip stack 20 and 30.In some embodiments, 110 filling semiconductor chip 10 of encapsulated layer and chip stack 20 or
Gap between 30.In some embodiments, encapsulated layer 110 is directly contacted with Underfill layer 108.In some embodiments,
Encapsulated layer 110 does not contact directly with conductive bond structure 106.In some embodiments, encapsulated layer 110 and chip stack 20 and
30 molding compound 210 directly contacts.
In some embodiments, encapsulated layer 110 includes polymer material.In some embodiments, encapsulated layer 110 is molding
The bed of material.Molding compound may include the epoxy for being wherein dispersed with filler.Filler may include non-conductive fibre, insulation
Grain, other suitable elements or their combination.In some embodiments, be dispersed in the filler in encapsulated layer 110 size and/
Or density is greater than the size and/or density for the filler being dispersed in Underfill layer 108.
In some embodiments, apply liquid molding compound material, and apply heating operation then with solidify liquid morphotype plastics
Material.As a result, liquid molding compound material is hardened and is transformed into encapsulated layer 110.In some embodiments, Celsius from about 200
Degree implements heat operation at a temperature of in the range of about 230 degrees Celsius.The operating time of heat operation can be from about 1 hour to about
In the range of 3 hours.
As shown in figure iD, according to some embodiments, planarized package layer 110, so that exposing semiconductor chip 10
Top surface.In some embodiments, the top surface of semiconductor chip 10 and encapsulated layer 110 is substantially coplanar with each other.In some embodiments,
Carry out planarized package layer using grinding technics, chemically mechanical polishing (CMP) technique, another applicable technique or their combination
110.In some embodiments, the top surface of chip stack 20 or 30 is covered still through encapsulated layer 110.In some embodiments
In, chip stack 20 and 30 is protected by encapsulated layer 110 during flatening process.Do not grind core during flatening process
Piece stack 20 and 30.It is therefore prevented that damaging chip stack 20 and 30 during flatening process.Chip stack is improved significantly
The q&r of overlapping piece 20 and 30.
As shown in figure iD, in some embodiments, encapsulated layer 110 covers top and the side wall of chip stack 20 and 30.
In some embodiments, the top surface of semiconductor chip 10 is not covered by encapsulated layer 110.In some embodiments, encapsulated layer 110
Top surface it is substantially coplanar with the top surface of semiconductor chip 10, this is conducive to subsequent technique.
As referring to figure 1E, according to some embodiments, skiving substrate 180 is to expose conductive component 182.In some embodiments
In, each conductive component 182 penetrates substrate 180.In some embodiments, each conductive component 182 is electrically connected to a conduction
Connected structure 106.In some embodiments, structure shown in Fig. 1 D is overturned.Later, using flatening process skiving substrate 180
To expose conductive component 182.Flatening process may include CMP process, grinding technics, etch process, other applicable techniques
Or their combination.
Later, as referring to figure 1E, according to some embodiments, conducting element is formed above substrate 180.As referring to figure 1E,
In some embodiments, conducting element includes metal column 114 and solder element 116.However, it is possible to the embodiment of the present invention into
The many variations of row and/or modification.In some other embodiments, conducting element has different structures.For example, conducting element is not
Including metal column.Conducting element can only include solder projection.In some embodiments, buffer layer 112 is formed to protect conduction
Element.In some embodiments, each metal column 114 is electrically connected to a conductive component 182.As referring to figure 1E, in some realities
It applies in example, buffer layer 112 extends along the part of the side wall of metal column 114.In some embodiments, buffer layer 112 is by nitrogenizing
Silicon, silicon oxynitride, silica, polyimides, epoxy resin, polybenzoxazoles (PBO), another suitable material or their group
Conjunction is made.
It as shown in fig. 1F, will be in the engagement to substrate 118 of structure shown in Fig. 1 E according to some embodiments.In some implementations
In example, substrate 118 is the circuit board of such as printed circuit board.In some other embodiments, substrate 118 is ceramic substrate.Such as
Shown in Fig. 1 F, in some embodiments, conducting element 120 and 124 is formed on the apparent surface of substrate 118.In some implementations
In example, conducting element 120 and 124 is the weldering of such as controlled collapse chip connection (C4) convex block and/or ball grid array (BGA) convex block
Expect convex block.As shown in fig. 1F, in some embodiments, reflowing conductive element 120 and solder element 116 and they are bonded on one
It rises.
In some embodiments, each conducting element 120 is electric by the conductive component (not shown) being formed in substrate 118
It is connected to a conducting element 124.Conductive component may include conducting wire and conductive through hole.In some embodiments, it is then serving as a contrast
Underfill layer 122 is formed between bottom 118 and substrate 180 to protect the conductive bond structure between them.
Can to the embodiment of the present invention many modifications may be made and/or modification.Fig. 2 is chip envelope in accordance with some embodiments
The sectional view of piece installing.In some embodiments, Underfill layer 108 is not formed.In some embodiments, encapsulated layer 110 is filled
Substrate 180 and including the interval between semiconductor chip 10 and chip stack 20 and 30 semiconductor chip.Encapsulated layer 110 encloses
Around conductive bond structure 106.In some embodiments, due to not formed Underfill layer 108, so encapsulated layer 110 and conduction
Connected structure 106 directly contacts.
In some embodiments, substrate 180 is used as interpolater.In some embodiments, interpolater does not include being located therein
Active device.In some other embodiments, interpolater includes one or more active devices formed therein.Some
In embodiment, substrate 180 is silicon interpolater.Substrate 180 can be used for improving the structural strength and reliability of chip packaging piece.So
And the embodiment of the present invention is not limited to this.Can to the embodiment of the present invention many modifications may be made and/or modification.Some
In embodiment, substrate 180 is not formed.
Fig. 3 A- Fig. 3 E is the section in each stage of the technique in accordance with some embodiments for being used to form chip packaging piece
Figure.As shown in Figure 3A, carrier substrates 300 are attached at according to some embodiments, semiconductor chip 10 and chip stack 20 and 30
On.Adhesive layer (not shown) can be used semiconductor chip 10 and chip stack 20 and 30 are attached in carrier substrates 300.
In some embodiments, carrier substrates 300 include glass substrate, ceramic substrate, semiconductor substrate, polymer substrate, Ling Yihe
Suitable substrate or their combination.In some embodiments, carrier substrates 300 are that semiconductor core is used to support during subsequent technique
The temporary substrates of piece 10 and chip stack 20 and 30.Later, carrier substrates 300 can be removed.
As shown in Figure 3B, according to some embodiments, encapsulated layer 310 is formed in 300 top of carrier substrates with sealing semiconductor
Chip 10 and chip stack 20 and 30.In some embodiments, 310 filling semiconductor chip 10 of encapsulated layer and chip stack
Gap between 20 or 30.In some embodiments, encapsulated layer 310 and the molding compound 210 of chip stack 20 and 30 are direct
Contact.
In some embodiments, encapsulated layer 310 includes polymer material.In some embodiments, encapsulated layer 310 is molding
The bed of material.Molding compound may include the epoxy for being wherein dispersed with filler.Filler may include non-conductive fibre, insulation
Grain, other suitable elements or their combination.
In some embodiments, apply liquid molding compound material, and apply heating operation then with solidify liquid morphotype plastics
Material.As a result, liquid molding compound material is hardened and is transformed into encapsulated layer 310.In some embodiments, Celsius from about 200
Degree implements heat operation at a temperature of in the range of about 230 degrees Celsius.The operating time of heat operation can be from about 1 hour to about
In the range of 3 hours.
As shown in Figure 3 C, according to some embodiments, planarized package layer 310, so that exposing semiconductor chip 10
Top surface.In some embodiments, using grinding technics, chemically mechanical polishing (CMP) technique, another applicable technique or they
Combination carry out planarized package layer 310.In some embodiments, chip stack 20 or 30 is covered still through encapsulated layer 310
Top surface.In some embodiments, chip stack 20 and 30 is protected by encapsulated layer 310 during flatening process.Flat
Smoothization process devices not grinding chip stack 20 and 30.It is therefore prevented that damaging chip stack 20 during flatening process
With 30.The q&r of chip stack 20 and 30 can be significantly improved.
As shown in Figure 3 C, in some embodiments, encapsulated layer 310 covers top and the side wall of chip stack 20 and 30.
In some embodiments, the top surface of semiconductor chip 10 is not covered by encapsulated layer 310.In some embodiments, encapsulated layer 310
Top surface is substantially coplanar with the top surface of semiconductor chip 10, this is conducive to subsequent technique.
As shown in Figure 3D, according to some embodiments, carrier substrates 300 are removed, so that exposure semiconductor chip 10, core
The bottom surface of piece stack 20 and 30 and encapsulated layer 310.In some embodiments, semiconductor chip 10,20 and of chip stack
30 and encapsulated layer 310 bottom surface it is substantially coplanar with each other.
Later, as shown in Figure 3D, according to some embodiments, in the bottom surface of semiconductor chip 10 and chip stack 20 and 30
Top forms conducting element.As shown in Figure 3D, in some embodiments, conducting element includes metal column 314 and solder element
316.In some other embodiments, conducting element includes other configurations.In some embodiments, buffer layer (not shown) is formed
To protect conducting element.
It as shown in FIGURE 3 E, will be in the engagement to substrate 318 of structure shown in Fig. 3 D according to some embodiments.In some implementations
In example, substrate 318 is the circuit board of such as printed circuit board.In some other embodiments, substrate 318 is ceramic substrate.Such as
Shown in Fig. 3 E, in some embodiments, conducting element 320 and 324 is formed on the apparent surface of substrate 318.In some implementations
In example, conducting element 320 and 324 is the weldering of such as controlled collapse chip connection (C4) convex block and/or ball grid array (BGA) convex block
Expect convex block.As shown in FIGURE 3 E, in some embodiments, reflowing conductive element 320 and solder element 316 and they are bonded on one
It rises.
In some embodiments, each conducting element 320 is electric by the conductive component (not shown) being formed in substrate 318
It is connected to a conducting element 324.Conductive component may include conducting wire and conductive through hole.In some embodiments, it is then serving as a contrast
Bottom 318 and including between semiconductor chip 10 and chip stack 20 and 30 chip formed Underfill layer 322 with guard bit
In the conductive bond structure between them.In some embodiments, encapsulated layer 310 not with the conductive bond knot between them
Structure directly contacts.
In some embodiments, it due to the protection of encapsulated layer 310, prevents from damaging chip stack 20 during manufacturing process
With 30.For example, the stress that planarization of the buffering from encapsulated layer 310 and the joint technology to substrate 318 generate.Improve chip
The quality of packaging part.
Can to the embodiment of the present invention many modifications may be made and/or modification.Fig. 4 is chip envelope in accordance with some embodiments
The sectional view of piece installing.In some embodiments, Underfill layer 108 is not only about conductive bond structure 106, but also is partly leading
Extend on the side wall of body chip 10.The part of the side wall of semiconductor chip 10 is covered by Underfill layer 108.In some implementations
In example, Underfill layer 108 extends in chip stack 20 and 30.Chip stack 20 is covered by Underfill layer 108
With the part of 30 side wall.
Can to the embodiment of the present invention many modifications may be made and/or modification.Fig. 5 is chip envelope in accordance with some embodiments
The sectional view of piece installing.Structure shown in fig. 5 is similar to structure shown in Fig. 1 F.In some embodiments, semiconductor chip 10
Between chip stack 20 and semiconductor chip 40.In some embodiments, semiconductor chip 10 is higher than chip stack 20
Or semiconductor chip 40.In some embodiments, the height of semiconductor chip 40 and chip stack 20 is different from each other.Some
In embodiment, semiconductor chip 40 is higher than chip stack 20.
In some embodiments, semiconductor chip 40 includes semiconductor substrate 400 and is formed in semiconductor substrate 400
Interconnection structure (not shown).For example, forming interconnection structure on the bottom surface of semiconductor substrate 400.Interconnection structure includes multiple layers
Between dielectric layer and the multiple conductive components being formed in interlayer dielectric layer.These conductive components include conducting wire, conductive through hole and lead
Electric contact piece.The some parts of conductive component may be used as conductive welding disk.
In some embodiments, it is similar to semiconductor substrate 100, forms various components in semiconductor substrate 400.
The example of various components includes transistor (for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET), complementary gold
Belong to oxide semiconductor (CMOS) transistor, bipolar junction transistor (BJT), high voltage transistor, high frequency transistor, p-channel and/or
N-channel field effect transistor (PFET/NFET) etc., diode or other suitable elements.
By interconnection structure interconnection devices element to form integrated circuit device.Integrated circuit device include logical device,
Memory device (for example, static random access memory, SRAM), radio frequency (RF) device, input/output (I/O) device, on chip
Other application types or their combination of system (SoC) device, device.In some embodiments, semiconductor chip 40 is packet
Include system on chip (SoC) chip of multiple functions.In some embodiments, one or more function of semiconductor chip 10 and 40
It can be different from each other.
Can to the embodiment of the present invention many modifications may be made and/or modification.Fig. 6 is chip envelope in accordance with some embodiments
The sectional view of piece installing.Structure shown in fig. 6 is similar to structure shown in Fig. 1 F.In some embodiments, planarized package layer 110
With semiconductor chip 10 so that exposure chip stack 20 and 30 top surface.In some embodiments, semiconductor chip 10
Top surface, encapsulated layer 110 top surface and chip stack 20 and 30 top surface it is substantially coplanar with each other.In some embodiments, make
With grinding technics, CMP process, etch process, another applicable technique, their combination etc. come 110 and of planarized package layer
Semiconductor chip 10.In some embodiments, surface mount device (SMD) 602 is bonded to the top surface and/or bottom surface of substrate 118.
SMD 602 may include discrete passive and/or active device, and can provide to chip packaging piece shown in fig. 6 additional
Function.
Can to the embodiment of the present invention many modifications may be made and/or modification.Fig. 7 is chip envelope in accordance with some embodiments
The sectional view of piece installing.Structure shown in Fig. 7 is similar to structure shown in Fig. 1 F.In some embodiments, skiving substrate 180 it
Afterwards and before forming metal column 114 and solder element 116, the redistribution structure being in electrical contact with conductive component 182 is formed
702.In some embodiments, redistribution structure 702 including multiple insulating layers 704 (not separately shown) and is located at multiple insulating layers
In 704 and/or between multiple redistributing layers (RDL) 706.In some embodiments, RDL 706 includes conducting wire and conductive through hole
(not separately labeled).
In other embodiments, insulating layer 704 may include such as polybenzoxazoles (PBO), polyimides (PI), benzo
The photo-patterned insulating materials of cyclobutane (BCB), their combination etc., and spin coating proceeding etc. can be used to be formed.
For example, the photolithography method similar with Other substrate materials can be used to pattern this photo-patterned insulating materials.In this reality
It applies in example, the first RDL forming method can be used to form RDL 706.In some embodiments, the first RDL forming method can
Opening is formed wherein to include the insulating layer of patterned insulation layer 704.On the insulating layer side and form blanket in the opening
Seed layer.In some embodiments, seed layer may include one or more layers of copper, titanium, nickel, gold, manganese or their combination etc.,
And it can be formed by atomic layer deposition (ALD), physical vapor deposition (PVD), sputtering, their combination etc..In crystal seed
Layer top formed sacrificial layer (such as, for example, photoresist layer), and sacrificial patterned with expose seed layer be located at insulating layer in
Opening in part and seed layer the top face positioned at insulating layer part.By opening in patterned insulating layer
Conductive material is formed in the combined openings that opening in mouth and patterned sacrificial layer is formed.In some embodiments, conduction material
Material may include copper, tungsten, aluminium, silver, gold, their combination etc., and can be used electrochemical plating technique, chemical plating process,
ALD, PVD, their combination etc. are formed.After forming conductive material, sacrificial layer is removed.Subsequently, using for example etching
The expose portion of the removal seed layer such as method.In some embodiments, the technique can be repeated to form additional RDL, until
Form required amount of RDL.
In other embodiments, multiple insulating layers 704 may include such as silicon nitride, silica, phosphosilicate glass
(PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), their combination etc. is not photo-patterned
Insulating materials, and chemical vapor deposition (CVD), ALD, spin coating proceeding, their combination can be used etc. and is formed.This
In embodiment, the 2nd RDL forming method can be used to form RDL 706.2nd RDL forming method may include single bed setter
Skill, dual-damascene technics, their combination etc..
Also in other embodiments, the first insulating layer of the insulating layer 704 adjacent with the bottom surface of substrate 180 may include not
Photo-patterned insulating materials, and the second insulating layer of the insulating layer 704 adjacent with metal column 114 may include can light pattern
The insulating materials of change.In such an embodiment, using the 2nd RDL forming method in the first insulating layer and/or between form RDL
706, and using the first RDL forming method in second insulating layer and/or between formed RDL 706.
In the embodiment shown in fig. 7, the top surface of semiconductor chip 10 and the top surface of encapsulated layer 110 are substantially coplanar with each other.
In other embodiments, it is all as described with reference to figure 6, the top surface of semiconductor chip 10, the top surface of encapsulated layer 110 and chip stack
The top surface of part 20 and 30 is substantially coplanar with each other.
Can to the embodiment of the present invention many modifications may be made and/or modification.Fig. 8 is chip envelope in accordance with some embodiments
The sectional view of piece installing.Structure shown in Fig. 8 is similar to structure shown in Fig. 1 F.In some embodiments, semiconductor chip 10 wraps
Include Multi-core stack.In the shown embodiment, semiconductor chip 10 includes two integrated circuit dies 802A and 802B.At it
In his embodiment, the quantity of integrated circuit die can be changed according to the design requirement of chip packaging piece.In some embodiments
In, the material and method similar with the semiconductor chip 40 for example described above with reference to Fig. 5 can be used to form tube core 802A
And 802B, and not repeated description herein.In some embodiments, using the direct joint method of mixing joint method etc.
Tube core 802A and 802B are engaged with each other.In such an embodiment, the insulating layer 804A of tube core 802A is spliced directly to tube core
The insulating layer 804B of 802B, and the landing pad 806A of tube core 802A is spliced directly to the landing pad 806B of tube core 802B.
It in some embodiments, can be before tube core 802A be bonded to tube core 802B, to the exposure table of insulating layer 804A and 804B
The exposed surface of face and landing pad 806A and 806B implement process of surface treatment.In some embodiments, by tube core
802A is bonded to after tube core 802B, and implementable annealing process is to reinforce the engagement between tube core 802A and tube core 802B.One
In a little embodiments, the engagement between landing pad 806A and 806B provides the electrical connection between tube core 802A and tube core 802B.
In some embodiments, landing pad 806A and 806B may include copper, tungsten, aluminium, silver, gold, their combination etc..In some realities
It applies in example, landing pad 806A and 806B may include identical material.In other embodiments, landing pad 806A and 806B
It may include different materials.In some embodiments, it can be used similar with the insulating layer 704 described above with reference to Fig. 7
Material and method form insulating layer 804A and 804B, and not repeated description herein.In some embodiments, insulating layer 804A
It may include identical material with 804B.In other embodiments, insulating layer 804A and 804B may include different material.
In the embodiment shown in fig. 8, the top surface of semiconductor chip 10 and the top surface of encapsulated layer 110 are substantially coplanar with each other.
In other embodiments, it is all as described with reference to figure 6, the top surface of semiconductor chip 10, the face of encapsulated layer 110 and chip stack 20
Top surface with 30 is substantially coplanar with each other.In some embodiments, Fig. 1 F, Fig. 2, Fig. 3 E, Fig. 4 and semiconductor chip shown in fig. 5
10 be the Multi-core stack above with reference to described in Fig. 8.
Can to the embodiment of the present invention many modifications may be made and/or modification.Fig. 9 is chip envelope in accordance with some embodiments
The sectional view of piece installing.Structure shown in Fig. 9 is similar to structure shown in Fig. 1 F.In some embodiments, substrate 180 may include
One or more passive devices 902 and one or more active devices 904.Passive device 902 may include resistor, capacitor
(such as, for example, deep-trench capacitor), inductor, fuse, their combination etc..Active device 904 may include transistor,
Diode, photodiode, photo-coupler, modulator, their combination etc..In some embodiments, active device 904 can be with
Conductive bond structure 106 is electrically connected to by interconnection piece 906 (such as conducting wire and through-hole) and contact pad 908.In some implementations
In example, interconnection piece 906 and contact pad 908 may include copper, tungsten, aluminium, silver, gold, their combination etc..In other embodiments
In, it is convenient to omit one in passive device 902 and active device 904.
In the embodiment shown in fig. 9, the top surface of semiconductor chip 10 and the top surface of encapsulated layer 110 are substantially coplanar with each other.
In other embodiments, it is all as described with reference to figure 6, the top surface of semiconductor chip 10, the top surface of encapsulated layer 110 and chip stack
20 and 30 top surface is substantially coplanar with each other.
Can to the embodiment of the present invention many modifications may be made and/or modification.Figure 10 is chip in accordance with some embodiments
The sectional view of packaging part.Structure shown in Fig. 10 is similar to structure shown in Fig. 1 F.In some embodiments, chip packaging piece packet
Include the redistribution structure 702 between substrate 180 and metal column 114.Redistribution structure is described by reference to Fig. 7 above
702, and not repeated description herein.In some embodiments, semiconductor chip 10 include have integrated circuit die 802A and
The Multi-core stack of 802B.Multi-core stack, and not repeated description herein are described by reference to Fig. 8 above.
In the embodiment shown in fig. 10, the top surface of semiconductor chip 10 and the top surface of encapsulated layer 110 are substantially coplanar with each other.
In other embodiments, it is all as described with reference to figure 6, the top surface of semiconductor chip 10, the top surface of encapsulated layer 110 and chip stack
20 and 30 top surface is substantially coplanar with each other.
Can to the embodiment of the present invention many modifications may be made and/or modification.Figure 11 is chip in accordance with some embodiments
The sectional view of packaging part.Structure shown in Figure 11 is similar to structure shown in Fig. 1 F.In some embodiments, chip packaging piece packet
Include the redistribution structure 702 between substrate 180 and metal column 114.Redistribution structure 702 is described by reference to Fig. 7 above,
And not repeated description herein.In some embodiments, substrate 180 may include one or more passive devices 902 and one
Or multiple active devices 904.One or more passive devices 902 are described by reference to Fig. 9 above and one or more is active
Device 904, and be not repeated to describe herein.
In the embodiment shown in fig. 11, the top surface of semiconductor chip 10 and the top surface of encapsulated layer 110 are substantially coplanar with each other.
In other embodiments, it is all as described with reference to figure 6, the top surface of semiconductor chip 10, the top surface of encapsulated layer 110 and chip stack
20 and 30 top surface is substantially coplanar with each other.
Can to the embodiment of the present invention many modifications may be made and/or modification.Figure 12 is chip in accordance with some embodiments
The sectional view of packaging part.Structure shown in Figure 12 is similar to structure shown in Fig. 1 F.In some embodiments, semiconductor chip 10
Including the Multi-core stack with integrated circuit die 802A and 802B.Multi-core is described by reference to Fig. 8 above to stack
Part, and not repeated description herein.In some embodiments, substrate 180 may include one or more passive devices 902 and one
A or multiple active devices 904.Describing one or more passive devices 902 and one or more by reference to Fig. 9 above has
Source device 904, and not repeated description herein.
In the embodiment shown in fig. 12, the top surface of semiconductor chip 10 and the top surface of encapsulated layer 110 are substantially coplanar with each other.
In other embodiments, it is all as described with reference to figure 6, the top surface of semiconductor chip 10, the top surface of encapsulated layer 110 and chip stack
20 and 30 top surface is substantially coplanar with each other.
Can to the embodiment of the present invention many modifications may be made and/or modification.Figure 13 is chip in accordance with some embodiments
The sectional view of packaging part.Structure shown in Figure 13 is similar to structure shown in Fig. 1 F.In some embodiments, chip packaging piece packet
Include the redistribution structure 702 between substrate 180 and metal column 114.Redistribution structure is described by reference to Fig. 7 above
702, and not repeated description herein.In some embodiments, semiconductor chip 10 include have integrated circuit die 802A and
The Multi-core stack of 802B.Multi-core stack, and not repeated description herein are described by reference to Fig. 8 above.One
In a little embodiments, substrate 180 may include one or more passive devices 902 and one or more active devices 904.Above
One or more passive devices 902 and one or more active devices 904 are described through reference Fig. 9, and are not repeated herein
Description.
In the embodiment shown in fig. 13, the top surface of semiconductor chip 10 and the top surface of encapsulated layer 110 are substantially coplanar with each other.
In other embodiments, it is all as described with reference to figure 6, the top surface of semiconductor chip 10, the top surface of encapsulated layer 110 and chip stack
20 and 30 top surface is substantially coplanar with each other.
What the embodiment of the present invention formation can be chip stack includes the first semiconductor chip and the second semiconductor core
The chip packaging piece of piece.The height of first semiconductor chip and the second semiconductor chip is different.Form the envelope of such as molding compound
Layer is filled to seal the first semiconductor chip and the second semiconductor chip.Skiving encapsulated layer is with the first semiconductor chip of exposure.It is cutting
During thin technique, the second semiconductor chip is protected by encapsulated layer without directly being ground.Due in the thinning process phase
Between encapsulated layer protection, prevent the second semiconductor chip (or chip stack) to be adversely affected.Core is improved significantly
The Performance And Reliability of chip package.
According to some embodiments, chip packaging piece is provided.Chip packaging piece includes the core with multiple semiconductor elements
Piece stack.Chip packaging piece further includes semiconductor chip, and semiconductor chip is higher than chip stack.Chip packaging piece is also
The encapsulated layer of the side wall at top and side wall and semiconductor chip including covering chip stack.
According to some embodiments, chip packaging piece is provided.Chip packaging piece includes the first semiconductor chip and the second half
Conductor chip.Chip packaging piece further includes the molding compound around the first semiconductor chip and the second semiconductor chip.Moulding compound
The top surface of layer the first semiconductor chip of covering, and the top surface of molding compound is substantially coplanar with the top surface of the second semiconductor chip.
According to some embodiments, the method for being used to form chip packaging piece is provided.This method, which is included in above substrate, to be connect
Close the first semiconductor chip and the second semiconductor chip.This method further include on substrate it is rectangular at encapsulated layer to seal the first half
Conductor chip and the second semiconductor chip.This method further includes planarized package layer, so that the second semiconductor chip of exposure
Top surface, and pass through encapsulated layer cover the first semiconductor chip top surface.
According to some embodiments, a kind of packaging part is provided.The packaging part includes substrate and the first core for being bonded to substrate
Piece stack.The packaging part further includes the second chip stack for being bonded to the substrate adjacent with the first chip stack.The envelope
Piece installing further includes the molding compound extended along the first side of the first chip stack, and the first side of the first chip stack is the
The side farthest apart from substrate of one chip stack.
According to some embodiments, a kind of packaging part is provided.The packaging part includes substrate and is attached to the first the half of substrate
Conductor chip.The packaging part further includes the second semiconductor chip for being attached to substrate, the first semiconductor chip and the second semiconductor
Chip is attached to the same side of substrate.The packaging part further includes the molding around the first semiconductor chip and the second semiconductor chip
The bed of material, molding compound cover the top surface of the first semiconductor chip.
According to some embodiments, a kind of packaging part is provided.The packaging part includes substrate, the semiconductor core for being bonded to substrate
Piece and the first chip stack for being bonded to substrate.The packaging part further includes between semiconductor chip and substrate and
The Underfill layer extended between one chip stack and substrate, the side at least partially along semiconductor chip of Underfill layer
Wall and along the side wall of the first chip stack extend.The packaging part further includes the encapsulated layer above Underfill layer,
Encapsulated layer extends along the most top surface of the first chip stack, and the interface between Underfill layer and encapsulated layer is located at the first chip
On the most bottom surface of stack and it is located at below the most top surface of first chip stack.
According to some embodiments, a kind of packaging part is provided.The packaging part includes substrate, the first chip for being attached to substrate
Stack and the second chip stack for being attached to substrate.First chip stack and the second chip stack are attached to substrate
Same side.The packaging part further includes the molding compound around the first chip stack and the second chip stack.Molding compound covers
The most top surface of the first chip stack of lid.The most top surface of molding compound and the most top surface of the second chip stack are substantially coplanar.
In above-mentioned packaging part, wherein pass through molding compound exposure second chip stack.
In above-mentioned packaging part, wherein second chip stack has bigger than first chip stack
Highly.
It further include around the bottom of first chip stack and second chip stack in above-mentioned packaging part
Filled layer, the interface between the Underfill layer and the molding compound be located at first chip stack most bottom surface and
On the lowest surfaces of second chip stack.
In above-mentioned packaging part, wherein second chip stack includes be bonded to the second integrated circuit die
One integrated circuit die, the first insulating layer on the first side of first integrated circuit die collect with being located at described second
At the second insulating layer physical contact in second side of circuit die.
It further include redistribution structure in above-mentioned packaging part, the substrate is plugged on the redistribution structure and described
Between two chip stacks.
In above-mentioned packaging part, wherein the substrate includes at least one of passive device and active device.
According to some embodiments, a kind of packaging part is provided.The packaging part includes substrate, the substrate have first surface and
Second surface, second surface is opposite with first surface, and the first chip stack is bonded to the first surface of substrate.The encapsulation
Part further includes the second chip stack for being bonded to the first surface of the substrate adjacent with the first chip stack, the second chip stack
Overlapping piece is higher than the first chip stack, and the molding compound of the most top surface extension along the first chip stack, the first chip
The most top surface of stack is the surface farthest apart from substrate of the first chip stack.
It further include the Underfill layer being plugged between the substrate and the molding compound in above-mentioned packaging part.
It further include the Underfill layer being plugged between the substrate and the molding compound in above-mentioned packaging part,
In, the most top surface of the Underfill layer be located at first chip stack most bottom surface and second chip stack
On most bottom surface.
In above-mentioned packaging part, wherein the most top surface of the molding compound and the most top surface of the second chip stack are coplanar.
It further include the redistribution structure on the second surface of the substrate, the redistribution in above-mentioned packaging part
Structure passes through the substrate electrical connection to first chip stack and second chip stack.
In above-mentioned packaging part, wherein the substrate includes at least one of passive device and active device.
In above-mentioned packaging part, wherein second chip stack includes be bonded to the second integrated circuit die
The second of one integrated circuit die, the first landing pad of first integrated circuit die and second integrated circuit die
Landing pad physical contact.
According to some embodiments, a kind of packaging part is provided.The packaging part includes substrate, is bonded to the first chip of substrate
Stack is bonded to the second chip stack of substrate, and between the first chip stack and substrate and in the second core
The Underfill layer extended between piece stack and substrate.The side at least partially along the first chip stack of Underfill layer
Wall and along the side wall of the second chip stack extend.The packaging part further includes the encapsulated layer above Underfill layer.It should
Encapsulated layer extends along the most top surface of the first chip stack.Interface between Underfill layer and encapsulated layer is located at the first chip
On the most bottom surface of stack and it is located at below the most top surface of the first chip stack.
In above-mentioned packaging part, wherein first chip stack includes: multiple integrated circuit dies；And sealing
Agent extends and along the side wall of the multiple integrated circuit die across between the Underfill layer and the encapsulated layer
Interface.
In above-mentioned packaging part, wherein first chip stack includes: multiple integrated circuit dies；And sealing
Agent extends and along the side wall of the multiple integrated circuit die across between the Underfill layer and the encapsulated layer
Interface, wherein the sealant along at least one integrated circuit die in the multiple integrated circuit die most top surface
Extend, and is physically contacted with the most top surface of at least one integrated circuit die in the multiple integrated circuit die.
In above-mentioned packaging part, wherein second chip stack includes: the first integrated circuit die, and described first
Integrated circuit die includes the first landing pad being embedded into the first insulating layer；And second integrated circuit die, it is bonded to
First integrated circuit die, second integrated circuit die include the second landing pad being embedded in second insulating layer,
First insulating layer and the second insulating layer are physically contacted, first landing pad and the second landing pad physics
Contact.
In above-mentioned packaging part, wherein the most top surface of second chip stack and the most top surface of the encapsulated layer are neat
It is flat.
It further include the redistribution structure with substrate electrical contact in above-mentioned packaging part, the substrate is plugged on described
Between first chip stack and the redistribution structure.
Foregoing has outlined the feature of several embodiments so that those skilled in the art may be better understood it is of the invention each
Aspect.It should be appreciated by those skilled in the art that they can easily be used for using based on the present invention to design or modify
Implement and other process and structures in the identical purpose of this introduced embodiment and/or the identical advantage of realization.Art technology
Personnel it should also be appreciated that this equivalent constructions without departing from the spirit and scope of the present invention, and without departing substantially from of the invention
In the case where spirit and scope, they can make a variety of variations, replace and change herein.
Claims (10)
1. a kind of packaging part, comprising:
Substrate；
First chip stack is attached to the substrate；
Second chip stack is attached to the substrate, first chip stack and second chip stack attachment
To the same side of the substrate；And
Molding compound, around first chip stack and second chip stack, described in the molding compound covering
The most top surface of first chip stack, the most top surface of the molding compound are coplanar with the most top surface of second chip stack.
2. packaging part according to claim 1, wherein pass through molding compound exposure second chip stack.
3. packaging part according to claim 1, wherein second chip stack has to be stacked than first chip
The bigger height of part.
4. packaging part according to claim 1 further includes around first chip stack and second chip stack
The Underfill layer of overlapping piece, the interface between the Underfill layer and the molding compound are located at first chip stack
Most bottom surface and second chip stack lowest surfaces on.
5. packaging part according to claim 1, wherein second chip stack includes being bonded to the second integrated circuit
First integrated circuit die of tube core, the first insulating layer on the first side of first integrated circuit die be located at institute
State the second insulating layer physical contact in second side of the second integrated circuit die.
6. packaging part according to claim 1 further includes redistribution structure, the substrate is plugged on the redistribution structure
Between second chip stack.
7. packaging part according to claim 1, wherein the substrate includes at least one in passive device and active device
Kind.
8. a kind of packaging part, comprising:
Substrate, the substrate have first surface and second surface, and the second surface is opposite with the first surface；
First chip stack is bonded to the first surface of the substrate；
Second chip stack, is bonded to the first surface of the substrate adjacent with first chip stack, and described
Two chip stacks are higher than first chip stack；And
Molding compound extends along the most top surface of first chip stack, and the most top surface of first chip stack is
The farthest surface of substrate described in the distance of first chip stack.
9. packaging part according to claim 8 further includes the bottom being plugged between the substrate and the molding compound
Filled layer.
10. a kind of packaging part, comprising:
Substrate；
First chip stack is bonded to the substrate；
Second chip stack is bonded to the substrate；
Underfill layer, between first chip stack and the substrate and in second chip stack and institute
State and extend between substrate, the Underfill layer at least partially along the side wall of first chip stack and described second
The side wall of chip stack extends；And
Encapsulated layer, is located above the Underfill layer, and the encapsulated layer prolongs along the most top surface of first chip stack
It stretches, the interface between the Underfill layer and the encapsulated layer is located on the lowest surfaces of first chip stack and position
Below the most top surface of first chip stack.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/784,807 US10319699B2 (en) | 2015-07-02 | 2017-10-16 | Chip package having die structures of different heights |
| US15/784,807 | 2017-10-16 | ||
| US15/966,873 US10535633B2 (en) | 2015-07-02 | 2018-04-30 | Chip package having die structures of different heights and method of forming same |
| US15/966,873 | 2018-04-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109671680A true CN109671680A (en) | 2019-04-23 |
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| CN201810789422.XA Pending CN109671680A (en) | 2017-10-16 | 2018-07-18 | The chip packaging piece of tube core structure and forming method thereof with different height |
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| CN (1) | CN109671680A (en) |
| TW (1) | TWI693645B (en) |
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| US20230317671A1 (en) * | 2022-03-30 | 2023-10-05 | Taiwan Semiconductor Manufacturing Company Limited | Substrate trench for controlling underfill fillet area and methods of forming the same |
| TWI822387B (en) * | 2022-10-11 | 2023-11-11 | 廖富江 | Semiconductor device, semiconductor package and manufacturing method the same |
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| CN106328608A (en) * | 2015-07-02 | 2017-01-11 | 台湾积体电路制造股份有限公司 | Structure and formation method for chip package |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024050911A1 (en) * | 2022-09-05 | 2024-03-14 | 长鑫存储技术有限公司 | Semiconductor structure and forming method therefor, and memory |
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| Publication number | Publication date |
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| TW201946163A (en) | 2019-12-01 |
| TWI693645B (en) | 2020-05-11 |
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