TW202416357A - Treatments to enhance material structures - Google Patents
Treatments to enhance material structures Download PDFInfo
- Publication number
- TW202416357A TW202416357A TW112148679A TW112148679A TW202416357A TW 202416357 A TW202416357 A TW 202416357A TW 112148679 A TW112148679 A TW 112148679A TW 112148679 A TW112148679 A TW 112148679A TW 202416357 A TW202416357 A TW 202416357A
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- Prior art keywords
- processing chamber
- dielectric layer
- processing
- substrate
- nitridation
- Prior art date
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- 239000000463 material Substances 0.000 title description 15
- 238000011282 treatment Methods 0.000 title description 2
- 238000000034 method Methods 0.000 claims abstract description 108
- 230000008569 process Effects 0.000 claims abstract description 88
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000000151 deposition Methods 0.000 claims abstract description 12
- 125000004433 nitrogen atom Chemical group N* 0.000 claims abstract description 10
- 239000000126 substance Substances 0.000 claims abstract description 8
- 238000012545 processing Methods 0.000 claims description 132
- 238000000137 annealing Methods 0.000 claims description 30
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 28
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 18
- 239000007789 gas Substances 0.000 claims description 16
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 claims description 14
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 13
- 239000001301 oxygen Substances 0.000 claims description 13
- 229910052760 oxygen Inorganic materials 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 10
- 229910052757 nitrogen Inorganic materials 0.000 claims description 10
- 229910021529 ammonia Inorganic materials 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 229910052786 argon Inorganic materials 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 239000001272 nitrous oxide Substances 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 14
- 238000004140 cleaning Methods 0.000 abstract description 6
- 238000012546 transfer Methods 0.000 description 35
- 235000012431 wafers Nutrition 0.000 description 23
- 239000003989 dielectric material Substances 0.000 description 18
- 239000002243 precursor Substances 0.000 description 9
- 230000015654 memory Effects 0.000 description 8
- 238000010405 reoxidation reaction Methods 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000003860 storage Methods 0.000 description 5
- MDBGGTQNNUOQRC-UHFFFAOYSA-N Allidochlor Chemical compound ClCC(=O)N(CC=C)CC=C MDBGGTQNNUOQRC-UHFFFAOYSA-N 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000010348 incorporation Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 3
- 239000011148 porous material Substances 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 229910052727 yttrium Inorganic materials 0.000 description 3
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 3
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 235000011114 ammonium hydroxide Nutrition 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000006185 dispersion Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- PDPJQWYGJJBYLF-UHFFFAOYSA-J hafnium tetrachloride Chemical group Cl[Hf](Cl)(Cl)Cl PDPJQWYGJJBYLF-UHFFFAOYSA-J 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- -1 halogen (Hf) Chemical class 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000003032 molecular docking Methods 0.000 description 2
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 2
- 239000007800 oxidant agent Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910000859 α-Fe Inorganic materials 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
- 229910003865 HfCl4 Inorganic materials 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910052784 alkaline earth metal Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- WYEMLYFITZORAB-UHFFFAOYSA-N boscalid Chemical compound C1=CC(Cl)=CC=C1C1=CC=CC=C1NC(=O)C1=CC=CN=C1Cl WYEMLYFITZORAB-UHFFFAOYSA-N 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 238000013480 data collection Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 125000002887 hydroxy group Chemical group [H]O* 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000877 morphologic effect Effects 0.000 description 1
- 150000002831 nitrogen free-radicals Chemical class 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- UZLYXNNZYFBAQO-UHFFFAOYSA-N oxygen(2-);ytterbium(3+) Chemical compound [O-2].[O-2].[O-2].[Yb+3].[Yb+3] UZLYXNNZYFBAQO-UHFFFAOYSA-N 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- 229910052761 rare earth metal Inorganic materials 0.000 description 1
- 150000002910 rare earth metals Chemical class 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052712 strontium Inorganic materials 0.000 description 1
- CIOAGBVUUVVLOB-UHFFFAOYSA-N strontium atom Chemical compound [Sr] CIOAGBVUUVVLOB-UHFFFAOYSA-N 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
- 150000003624 transition metals Chemical class 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
- 229910003454 ytterbium oxide Inorganic materials 0.000 description 1
- 229940075624 ytterbium oxide Drugs 0.000 description 1
Classifications
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/40—Oxides
- C23C16/405—Oxides of refractory metals or yttrium
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/56—After-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
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- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02189—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing zirconium, e.g. ZrO2
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02192—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium
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- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
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- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
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- H01L21/02301—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment in-situ cleaning
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
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- H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
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- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
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Abstract
Description
本文描述的多個實施方式一般涉及半導體元件製造,尤其是,涉及在半導體結構中形成高品質高κ介電材料層的系統和方法。Various embodiments described herein relate generally to semiconductor device fabrication and, more particularly, to systems and methods for forming high-quality high-κ dielectric material layers in semiconductor structures.
隨著金屬氧化物半導體場效應電晶體(MOSFET)已經為了實現高元件性能和低功耗而減小尺寸,傳統的二氧化矽(SiO 2)閘極介電質的厚度已經減小到它的物理極限(physical limit)。因此,為了實現進一步的縮小(scaling),用高κ介電材料替代二氧化矽閘極介電質已經是在所難免的。在各種高κ介電材料中,自45nm MOSFET技術節點開始,已經應用了氧化鉿(HfO 2),這是因為氧化鉿(HfO 2)有高介電常數和在矽基板上優越的熱穩定性。但是,對於32nm MOSFET技術節點及以後的技術節點的等效氧化物厚度(equivalent oxide thickness,EOT)的進一步縮小而言,簡單地減小高κ介電材料層的厚度是成問題的,因為流過高κ介電材料層的漏電流增加了。 As metal oxide semiconductor field effect transistors (MOSFETs) have been reduced in size to achieve high device performance and low power consumption, the thickness of the traditional silicon dioxide (SiO 2 ) gate dielectric has been reduced to its physical limit. Therefore, in order to achieve further scaling, it is inevitable to replace the silicon dioxide gate dielectric with high-κ dielectric materials. Among various high-κ dielectric materials, ferrite (HfO 2 ) has been used since the 45nm MOSFET technology node because ferrite (HfO 2 ) has a high dielectric constant and excellent thermal stability on a silicon substrate. However, for further reduction of the equivalent oxide thickness (EOT) at the 32nm MOSFET technology node and beyond, simply reducing the thickness of the high-κ dielectric material layer is problematic because leakage current flowing through the high-κ dielectric material layer increases.
因此,需要能夠用來形成薄的(例如EOT小於1nm)高κ介電材料層的系統和方法,這種材料層具有能夠受控以確保期望的結構特性和電氣特性的化學結構。Therefore, there is a need for systems and methods that can be used to form thin (eg, EOT less than 1 nm) high-κ dielectric material layers having a chemical structure that can be controlled to ensure desired structural and electrical properties.
本揭示內容的多個實施方式提供一種形成半導體結構的方法。該方法包括以下步驟:預清潔基板的表面;在所述基板的預清潔後的表面上形成介面層(interfacial layer);在所述介面層上沉積高κ介電層;執行電漿氮化(plasma nitridation)製程以在所沉積的高κ介電層中插入氮原子;和執行氮化後退火(post-nitridation anneal)製程以鈍化電漿氮化後的高κ介電層中的化學鍵。Various embodiments of the present disclosure provide a method for forming a semiconductor structure. The method includes the following steps: pre-cleaning a surface of a substrate; forming an interfacial layer on the pre-cleaned surface of the substrate; depositing a high-κ dielectric layer on the interfacial layer; performing a plasma nitridation process to insert nitrogen atoms in the deposited high-κ dielectric layer; and performing a post-nitridation anneal process to passivate chemical bonds in the plasma nitrided high-κ dielectric layer.
本揭示內容的多個實施方式還提供一種形成半導體結構的方法。該方法包括以下步驟:預清潔基板的表面;在所述基板上沉積高κ介電層;和執行電漿氮化製程以在所沉積的高κ介電層中插入氮原子。Various embodiments of the present disclosure also provide a method for forming a semiconductor structure, which includes the following steps: pre-cleaning a surface of a substrate; depositing a high-κ dielectric layer on the substrate; and performing a plasma nitridation process to insert nitrogen atoms into the deposited high-κ dielectric layer.
本揭示內容的多個實施方式進一步提供一種處理系統。處理系統包括第一處理腔室、第二處理腔室、第三處理腔室、第四處理腔室、第五處理腔室和系統控制器。該系統控制器被構造成:在所述第一處理腔室中預清潔基板的表面;在所述第二處理腔室中,在所述基板的預清潔後的表面上形成介面層;在所述第三處理腔室中,在所述介面層上沉積高κ介電層;在所述第四處理腔室中,將所沉積的高κ介電層暴露給氮電漿;和在所述第五處理腔室中,對電漿氮化後的高κ介電層進行退火。在所述第一處理腔室、所述第二處理腔室、所述第三處理腔室、所述第四處理腔室和所述第五處理腔室之間傳送所述基板而不破壞所述處理系統中的真空環境。Multiple embodiments of the present disclosure further provide a processing system. The processing system includes a first processing chamber, a second processing chamber, a third processing chamber, a fourth processing chamber, a fifth processing chamber, and a system controller. The system controller is configured to: pre-clean the surface of a substrate in the first processing chamber; form an interface layer on the pre-cleaned surface of the substrate in the second processing chamber; deposit a high-κ dielectric layer on the interface layer in the third processing chamber; expose the deposited high-κ dielectric layer to nitrogen plasma in the fourth processing chamber; and anneal the plasma-nitrided high-κ dielectric layer in the fifth processing chamber. The substrate is transferred between the first processing chamber, the second processing chamber, the third processing chamber, the fourth processing chamber, and the fifth processing chamber without destroying the vacuum environment in the processing system.
隨著閘極結構縮到更小的尺寸,一直在尋求新的材料結構來提供改進。相較於利用諸如氧化矽之類材料的傳統閘極結構,高κ介電材料的使用增大了閘極結構的介電常數。然而,類似於氧化矽,隨著閘極結構的厚度減小,漏電流增加。例如,閘極洩漏(gate leakage)隨著有效氧化物厚度減小而增加。因此,閘極洩漏與有效氧化物厚度之間的反比關係可能形成對所生產的元件和電晶體性能的限制。As gate structures shrink to smaller dimensions, new material structures are sought to provide improvements. The use of high-κ dielectric materials increases the dielectric constant of the gate structure compared to traditional gate structures utilizing materials such as silicon oxide. However, similar to silicon oxide, as the thickness of the gate structure decreases, the leakage current increases. For example, gate leakage increases as the effective oxide thickness decreases. Therefore, the inverse relationship between gate leakage and effective oxide thickness can form a limitation on the performance of the components and transistors produced.
相較於類似厚度的氧化矽,高κ介電材料可以提供更大的溝道遷移率(channel mobility)。隨著本行業繼續尋求在不增加閘極洩漏的情況下更低的有效氧化物厚度,由於形態學特徵(morphological characteristics)的緣故,對已知的高κ材料的介電常數(也稱為「κ值」)最大化的努力將要達到極限。傳統的技術已經在努力克服高κ材料的固有特性(這可能設定κ值的上限),以及隨後的元件改造以嘗試結合新的膜。High-κ dielectric materials can provide greater channel mobility than silicon oxide of similar thickness. As the industry continues to seek lower effective oxide thickness without increasing gate leakage, efforts to maximize the dielectric constant (also known as the "κ value") of known high-κ materials are reaching their limits due to morphological characteristics. Traditional techniques have struggled to overcome the inherent properties of high-κ materials (which may set an upper limit on the κ value), and subsequent device modifications have attempted to incorporate new films.
本文描述的多個實施方式提供用於改善高κ介電材料的特性的系統和方法。通過生產呈現特定形態或者晶粒結構的高κ介電材料,可以實現更高的介電常數和隨之改進的元件性能。為了控制示例性元件中的晶粒形成,可以進行處理(treatment)以提供能夠引起特定晶粒生長的活化基板表面(activated substrate surface),以及在形成後對膜進行穩定化,這可以造成更高的介電常數。Various embodiments described herein provide systems and methods for improving the properties of high-κ dielectric materials. By producing high-κ dielectric materials that exhibit a specific morphology or grain structure, higher dielectric constants and consequently improved device performance can be achieved. In order to control grain formation in exemplary devices, treatments can be performed to provide an activated substrate surface that can induce specific grain growth, as well as stabilizing the film after formation, which can result in a higher dielectric constant.
圖1是根據本揭示內容的一些示例的多腔室處理系統100的示例的示意性俯視圖。該處理系統100一般包括:工廠介面102;裝載鎖定腔室104、106;具有相應的傳送機械手112、114的傳送腔室108、110;保持腔室116、118;和處理腔室120、122、124、126、128、130。如本文所詳述的那樣,可以在各種腔室中處理在處理系統100中的晶圓和在各種腔室之間傳送這些晶圓而不將這些晶圓暴露給處理系統100外部的周圍環境(例如,諸如可能存在於晶圓廠(fab)中的大氣環境)。例如,可以在低壓(例如,小於或等於約300托)或真空環境中在各種腔室中處理這些晶圓和在各種腔室之間傳送這些晶圓,而不破壞處理系統100中對晶圓執行的各種製程之間的低壓或真空環境。因此,處理系統100可以為晶圓的一些處理提供整合的解決方案。1 is a schematic top view of an example of a multi-chamber processing system 100 according to some examples of the present disclosure. The processing system 100 generally includes: a factory interface 102; load lock chambers 104, 106; transfer chambers 108, 110 with corresponding transfer robots 112, 114; holding chambers 116, 118; and processing chambers 120, 122, 124, 126, 128, 130. As described in detail herein, wafers in the processing system 100 can be processed in the various chambers and transferred between the various chambers without exposing the wafers to an ambient environment external to the processing system 100 (e.g., an atmospheric environment such as may exist in a wafer fab). For example, the wafers may be processed in various chambers and transferred between the various chambers in a low pressure (e.g., less than or equal to about 300 Torr) or vacuum environment without disrupting the low pressure or vacuum environment between various processes performed on the wafers in the processing system 100. Thus, the processing system 100 may provide an integrated solution for a number of processing of wafers.
可以根據本文提供的教導適當修改的處理系統的示例包括可以從位於美國加利福尼亞州聖塔克拉拉的應用材料公司商業獲得的Endura®、 Producer®或者Centura®整合處理系統或者其他適當的處理系統。預期其他處理系統(包括來自其他製造商的那些處理系統)可適於受益於本文所述的多個態樣。Examples of processing systems that may be suitably modified in accordance with the teachings provided herein include the Endura®, Producer®, or Centura® integrated processing systems commercially available from Applied Materials, Inc., located in Santa Clara, Calif., or other suitable processing systems. It is contemplated that other processing systems, including those from other manufacturers, may be adapted to benefit from the various aspects described herein.
在圖1的圖示示例中,工廠介面102包括塢站(docking station)140和工廠介面機械手142以説明傳送晶圓。塢站140被構造成接納一個或者多個前開式標準艙(FOUP)144。在一些示例中,每個工廠介面機械手142一般包括葉片148,葉片148設置在相應工廠介面機械手142的一端上,被構造成將晶圓從工廠介面102傳送至裝載鎖定腔室104、106。1 , the fab 102 includes a docking station 140 and a fab robot 142 to facilitate wafer transfer. The docking station 140 is configured to receive one or more front opening unmanned units (FOUPs) 144. In some examples, each fab robot 142 generally includes a blade 148 disposed on one end of the corresponding fab robot 142 and configured to transfer wafers from the fab 102 to the load lock chambers 104, 106.
裝載鎖定腔室104、106具有耦接到工廠介面102的相應埠150、152和耦接到傳送腔室108的相應埠154、156。傳送腔室108還有耦接到保持腔室116、118的相應埠158、160和耦接到處理腔室120、122的相應埠162、164。類似地,傳送腔室110具有耦接到保持腔室116、118的相應埠166、168和耦接到處理腔室124、126、128、130的相應埠170、172、174、176。埠154、156、158、160、162、164、166、168、170、172、174、176可以是例如帶有狹縫閥的狹縫閥開口,用於借助傳送機械手112、114使晶圓從中通過並用於在相應的腔室之間提供密封以防止氣體在各腔室之間通過。通常,任何埠開放以用於傳送晶圓從中通過。否則,埠被關閉。The load lock chambers 104, 106 have corresponding ports 150, 152 coupled to the factory interface 102 and corresponding ports 154, 156 coupled to the transfer chamber 108. The transfer chamber 108 also has corresponding ports 158, 160 coupled to the holding chambers 116, 118 and corresponding ports 162, 164 coupled to the processing chambers 120, 122. Similarly, the transfer chamber 110 has corresponding ports 166, 168 coupled to the holding chambers 116, 118 and corresponding ports 170, 172, 174, 176 coupled to the processing chambers 124, 126, 128, 130. Ports 154, 156, 158, 160, 162, 164, 166, 168, 170, 172, 174, 176 may be, for example, slit valve openings with slit valves for passing wafers therethrough by means of transfer robots 112, 114 and for providing a seal between the respective chambers to prevent gas from passing between the chambers. Typically, any port is open for passing a wafer therethrough. Otherwise, the port is closed.
裝載鎖定腔室104、106、傳送腔室108、110、保持腔室116、118和處理腔室120、122、124、126、128、130可以流體耦接到氣體和壓力控制系統(未具體圖示出)。氣體和壓力控制系統可以包括一個或多個氣泵(例如,渦輪泵、低溫泵(cryo-pump)、低真空泵(roughing pump))、氣源、各種閥和流體耦接到各種腔室的導管。在操作中,工廠介面機械手142通過埠150或152將晶圓從FOUP 144傳送到裝載鎖定腔室104或106。然後氣體和壓力控制系統泵空(pump down)裝載鎖定腔室104或106。氣體和壓力控制系統進一步將傳送腔室108、110和保持腔室116、118保持在內部低壓或真空環境(該環境可包括惰性氣體)。因此,裝載鎖定腔室104或106的泵空便於在例如工廠介面102的大氣環境與傳送腔室108的低壓或真空環境之間傳遞晶圓。The load lock chambers 104, 106, transfer chambers 108, 110, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130 may be fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system may include one or more gas pumps (e.g., a turbo pump, a cryo-pump, a roughing pump), gas sources, various valves, and conduits that are fluidly coupled to the various chambers. In operation, the factory interface robot 142 transfers wafers from the FOUP 144 to the load lock chamber 104 or 106 via port 150 or 152. The gas and pressure control system then pumps down the load lock chamber 104 or 106. The gas and pressure control system further maintains the transfer chambers 108, 110 and the holding chambers 116, 118 within an internal low pressure or vacuum environment (which may include an inert gas). Thus, pumping of the load lock chamber 104 or 106 facilitates the transfer of wafers between, for example, the atmospheric environment of the fab interface 102 and the low pressure or vacuum environment of the transfer chamber 108.
帶著已經被泵空的裝載鎖定腔室104或106中的晶圓,傳送機械手112通過埠154或156將晶圓從裝載鎖定腔室104或106傳送到傳送腔室108中。傳送機械手112然後能夠將晶圓傳送到處理腔室120、122和保持腔室116、118中的任何腔室和/或在這些腔室中的任何腔室之間傳送晶圓,通過相應埠162、164將晶圓傳送到用於處理的處理腔室120、122,通過相應埠158、160將晶圓傳送到用於保持以等待進一步傳送的保持腔室116、118。類似地,傳送機械手114能夠通過埠166或168接取保持腔室116或118中的晶圓,並且能夠將晶圓傳送到處理腔室124、126、128、130和保持腔室116、118中的任何腔室和/或在這些腔室中的任何腔室之間傳送晶圓,通過相應埠170、172、174、176將晶圓傳送到用於處理的處理腔室124、126、128、130,通過相應埠166、168將晶圓傳送到用於保持以等待進一步傳送的保持腔室116、118。晶圓在各個腔室內和之間的傳送和保持能夠在由氣體和壓力控制系統提供的低壓或真空環境中進行。With the wafer in the load lock chamber 104 or 106 now pumped empty, the transfer robot 112 transfers the wafer from the load lock chamber 104 or 106 to the transfer chamber 108 via the port 154 or 156. The transfer robot 112 can then transfer the wafer to and/or between any of the processing chambers 120, 122 and the holding chambers 116, 118, transferring the wafer to the processing chamber 120, 122 for processing via the corresponding ports 162, 164 and transferring the wafer to the holding chamber 116, 118 for holding to await further transfer via the corresponding ports 158, 160. Similarly, the transfer robot 114 can access wafers in the holding chamber 116 or 118 through the port 166 or 168 and can transfer the wafers to and/or between any of the processing chambers 124, 126, 128, 130 and the holding chambers 116, 118, transfer the wafers to the processing chambers 124, 126, 128, 130 for processing through the corresponding ports 170, 172, 174, 176, and transfer the wafers to the holding chambers 116, 118 for holding to await further transfer through the corresponding ports 166, 168. The transfer and holding of wafers within and between the various chambers can be performed in a low pressure or vacuum environment provided by a gas and pressure control system.
處理腔室120、122、124、126、128、130可以是用於處理晶圓的任何合適的腔室。在一些示例中,處理腔室122可以能夠執行清潔製程,處理腔室120可以能夠執行蝕刻製程,而處理腔室124、126、128、130可以能夠執行相應的磊晶生長製程。處理腔室122可以是能夠從美國加利福尼亞州的聖塔克拉拉的應用材料公司獲得的SiCoNi ™預清潔腔室。處理腔室120可以是能夠從美國加利福尼亞州的聖塔克拉拉的應用材料公司獲得的Selectra ™蝕刻腔室。 Processing chambers 120, 122, 124, 126, 128, 130 may be any suitable chamber for processing wafers. In some examples, processing chamber 122 may be capable of performing a cleaning process, processing chamber 120 may be capable of performing an etching process, and processing chambers 124, 126, 128, 130 may be capable of performing a corresponding epitaxial growth process. Processing chamber 122 may be a SiCoNi ™ pre-clean chamber available from Applied Materials, Inc. of Santa Clara, California, USA. Processing chamber 120 may be a Selectra ™ etch chamber available from Applied Materials, Inc. of Santa Clara, California, USA.
系統控制器190耦接到處理系統100,用於控制處理系統100或者處理系統100的部件。例如,系統控制器190可以使用對處理系統100的腔室104、106、108、116、118、110、120、122、124、126、128、130的直接控制來控制處理系統100的操作,或者通過控制與腔室104、106、108、116、118、110、120、122、124、126、128、130相關聯的控制器來控制處理系統100的操作。在操作中,系統控制器190能夠實現資料收集和來自相應腔室的回饋以協調處理系統100的運行。The system controller 190 is coupled to the processing system 100 for controlling the processing system 100 or components of the processing system 100. For example, the system controller 190 can control the operation of the processing system 100 using direct control of the chambers 104, 106, 108, 116, 118, 110, 120, 122, 124, 126, 128, 130 of the processing system 100, or by controlling controllers associated with the chambers 104, 106, 108, 116, 118, 110, 120, 122, 124, 126, 128, 130. In operation, the system controller 190 can enable data collection and feedback from the corresponding chambers to coordinate the operation of the processing system 100.
系統控制器190一般包括中央處理單元(CPU)192、記憶體194和支援電路196。CPU 192可以是能夠在工業設置中使用的任何形式的通用處理器之一。記憶體194或非暫時性電腦可讀媒體能夠由CPU 192存取並且可以是諸如隨機存取記憶體(RAM)、唯讀記憶體(ROM)、軟碟、硬碟或任何其他形式的本地或遠端數位存儲裝置之類的一個或多個記憶體。支援電路196耦接到CPU 192並且可以包括快取記憶體、時鐘電路、輸入/輸出子系統、電源和類似裝置等。本文揭示的各種方法通常可以在CPU 192的控制下通過CPU 192執行存儲在記憶體194(或特定製程腔室的記憶體)中作為例如軟體常式的電腦指令代碼來實施。當電腦指令代碼由CPU 192執行時,CPU 192控制這些腔室以根據各種方法執行製程。The system controller 190 generally includes a central processing unit (CPU) 192, a memory 194, and support circuits 196. The CPU 192 can be one of any form of general purpose processor capable of use in an industrial setting. The memory 194 or non-transitory computer readable medium can be accessed by the CPU 192 and can be one or more memories such as random access memory (RAM), read-only memory (ROM), a floppy disk, a hard disk, or any other form of local or remote digital storage device. The support circuits 196 are coupled to the CPU 192 and can include cache memory, clock circuits, input/output subsystems, power supplies, and the like. The various methods disclosed herein may generally be implemented by the CPU 192 executing computer instruction codes stored in the memory 194 (or the memory of a particular process chamber) as, for example, software routines, under the control of the CPU 192. When the computer instruction codes are executed by the CPU 192, the CPU 192 controls the chambers to perform processes according to the various methods.
其他處理系統可以採用其他配置。例如,更多或更少的處理腔室可以耦接到傳送設備。在圖示的示例中,傳送設備包括傳送腔室108、110和保持腔室116、118。在其他示例中,更多或更少的傳送腔室(例如,一個傳送腔室)和/或更多或更少的保持腔室(例如,沒有保持腔室)可以作為處理系統中的傳送設備來實現。Other processing systems may employ other configurations. For example, more or fewer processing chambers may be coupled to the transfer device. In the illustrated example, the transfer device includes transfer chambers 108, 110 and holding chambers 116, 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and/or more or fewer holding chambers (e.g., no holding chambers) may be implemented as a transfer device in a processing system.
圖2是根據本揭示內容的一個或多個實施方式的形成半導體結構300的方法200的製程流程圖。圖3A和圖3B是對應於方法200的各種狀態的半導體結構300的一部分的截面圖。應當理解,圖3A和圖3B僅示出了半導體結構300的局部示意圖,而半導體結構300可以包含任意數量的電晶體部分和具有如圖所示多個態樣的附加材料。還應該注意的是,雖然圖2中所示的方法步驟是按順序描述的,但包括一個或多個已被省略和/或添加的、和/或已按另一所需順序重新排列的一個或多個方法步驟的其他製程順序也落入本文提供的本揭示內容的多個實施方式的範圍內。FIG. 2 is a process flow diagram of a method 200 of forming a semiconductor structure 300 according to one or more embodiments of the present disclosure. FIG. 3A and FIG. 3B are cross-sectional views of a portion of the semiconductor structure 300 corresponding to various states of the method 200. It should be understood that FIG. 3A and FIG. 3B only show partial schematic views of the semiconductor structure 300, and the semiconductor structure 300 may include any number of transistor portions and additional materials having multiple states as shown. It should also be noted that although the method steps shown in FIG. 2 are described in sequence, other process sequences including one or more method steps that have been omitted and/or added, and/or rearranged in another desired order also fall within the scope of the various embodiments of the present disclosure provided herein.
方法200始於方框210中的預清潔製程,以預清潔基板302的表面。該預清潔製程可以包括:通過幹蝕刻製程或者使用蝕刻溶液的濕蝕刻製程來蝕刻基板302的表面,蝕刻溶液諸如是包含NH 4OH(氫氧化銨(ammonium hydroxide))、H 2O 2(過氧化氫(hydrogen peroxide))和H 2O(水)的標準清潔1(Standard Clean 1, SC1)蝕刻溶液,幹蝕刻製程例如是SiConi ™遠端電漿輔助幹蝕刻製程,其中基板302的表面被暴露於N 2、NF 3和NH 3電漿副產物。可以在諸如圖1中所示的處理腔室122或者120之類的預清潔腔室中執行該預清潔製程。 The method 200 begins with a pre-cleaning process in block 210 to pre-clean the surface of the substrate 302. The pre-cleaning process may include etching the surface of the substrate 302 by a dry etching process or a wet etching process using an etching solution, such as a Standard Clean 1 (SC1) etching solution containing NH4OH (ammonium hydroxide), H2O2 (hydrogen peroxide), and H2O (water), the dry etching process being, for example , a SiConi ™ remote plasma assisted dry etching process, in which the surface of the substrate 302 is exposed to N2 , NF3 , and NH3 plasma byproducts. The pre-clean process may be performed in a pre-clean chamber such as the processing chamber 122 or 120 shown in FIG. 1 .
在方框220中,執行介面形成製程,以在基板302的預清潔後的表面上形成介面層304,如圖3A中所示。介面形成製程可以包括適當的熱氧化製程,諸如是利用一氧化二氮(N 2O)氣體的增強型原位蒸汽生成(enhanced in-situ steam generation, eISSG)製程。在方框220中形成的介面層304是一種薄的非晶氧化矽(SiO 2)層,具有介於約3Å與約10Å之間的厚度,例如約5Å,對應於氧化矽的一個或多個單層(monolayer)。在一些實施方式中,可以通過利用H 2和O 2氣體的原位蒸汽生成(ISSG)製程或者通過利用NH 3和O 2氣體的快速熱氧化(rapid thermal oxidation, RTO)製程來形成介面層304。介面層304可以作為待沉積在介面層304上的高κ介電材料層的成核層(nucleation layer),並提高基板302與高κ介電材料層之間介面的品質(例如,諸如介面態密度(interface state density)、累積電容(accumulation capacitance)、頻散(frequency dispersion)和漏電流之類)。可以在諸如圖1中所示的處理腔室120、122、124、126、128或者130之類的處理腔室中執行該介面形成製程。 In block 220, an interface formation process is performed to form an interface layer 304 on the pre-cleaned surface of the substrate 302, as shown in FIG3A. The interface formation process may include a suitable thermal oxidation process, such as an enhanced in-situ steam generation (eISSG) process using nitrous oxide ( N2O ) gas. The interface layer 304 formed in block 220 is a thin amorphous silicon oxide ( SiO2 ) layer having a thickness between about 3Å and about 10Å, such as about 5Å, corresponding to one or more monolayers of silicon oxide. In some embodiments, the interface layer 304 may be formed by an in-situ steam generation (ISSG) process using H 2 and O 2 gases or by a rapid thermal oxidation (RTO) process using NH 3 and O 2 gases. The interface layer 304 may serve as a nucleation layer for a high-κ dielectric material layer to be deposited on the interface layer 304 and improve the quality of the interface between the substrate 302 and the high-κ dielectric material layer (e.g., such as interface state density, accumulation capacitance, frequency dispersion, and leakage current). The interface formation process may be performed in a processing chamber such as the processing chamber 120, 122, 124, 126, 128, or 130 shown in FIG. 1 .
在一些實施方式中,省去了方框220中的介面形成製程,在高κ介電材料層沉積在基板302上之前不形成介面層304。這種情況下,通過下面描述的方框250或者方框290中的熱氧化製程來形成介面層304,該製程經由沉積在基板302上的高κ介電材料層熱氧化基板302。具有介於約0.3nm與約 1nm之間的厚度,例如,約0.5nm的厚度,通過方框250或者方框290中的熱氧化製程形成的介面層304可以厚得足以確保可靠的元件特性(例如,諸如介面態密度、累積電容、頻散和漏電流之類)並且減少從高κ介電材料層向基板302的原子擴散(atomic diffusion)。In some embodiments, the interface formation process in block 220 is omitted, and the interface layer 304 is not formed before the high-κ dielectric material layer is deposited on the substrate 302. In this case, the interface layer 304 is formed by a thermal oxidation process in block 250 or block 290 described below, which thermally oxidizes the substrate 302 via the high-κ dielectric material layer deposited on the substrate 302. With a thickness between about 0.3 nm and about 1 nm, for example, a thickness of about 0.5 nm, the interface layer 304 formed by the thermal oxidation process in block 250 or block 290 can be thick enough to ensure reliable device characteristics (e.g., such as interface state density, cumulative capacitance, dispersion, and leakage current) and reduce atomic diffusion from the high-κ dielectric material layer to the substrate 302.
在方框230中,執行沉積製程,以在半導體結構300的暴露表面上(即,在方框220中形成介面層304的情況下在介面層304上,如圖3B所示,和在方框220中不形成介面層304的情況下在基板302上)沉積高κ介電層306。高κ介電層306可以由高κ介電材料形成,諸如二氧化鉿(HfO 2)、二氧化鋯(ZrO 2)、氧化鐿(ytterbium oxide,Y 2O 3)或者氧化鋁(Al 2O 3)之類的材料。該沉積製程可以包括原子層沉積(ALD)製程,其中將含金屬前驅物和含氧前驅物交替遞送至半導體結構300的暴露表面。在一些實施方式中,在遞送含氧前驅物之前,清除(purge)含金屬前驅物。金屬可以是諸如鉿(Hf)、鋯(Zr)或者鈦(Ti)之類的過渡金屬、諸如鑭(La)、鐿(Yb)或者釔(Y)之類的稀土金屬、諸如鍶(Sr)之類的鹼土金屬或者諸如鋁(Al)之類的其他金屬。對於氧化劑來說,可以使用可以與金屬反應的任何含氧前驅物。例如,含氧前驅物可以是或者包含水、雙原子氧(diatomic oxygen)、臭氧、含羥基的前驅物(hydroxyl-containing precursor)或者酒精、含氮和氧的前驅物、包含本地或者遠端增強的氧的電漿增強氧、或者可以與金屬結合以在基板302之上產生金屬的氧化物的層的含氧的任何其他材料。在一個示例中,含金屬前驅物是四氯化鉿(hafnium tetrachloride, HfC l4)並且氧化劑是水(H 2O),以形成二氧化鉿(HfO 2)層。可以在介於約200°C與約400°C之間的溫度(例如,約270°C)執行ALD製程。如由ALD製程所沉積的那樣,高κ介電層306可以是非晶的並且具有介於約10Å與約30Å之間的厚度。可以在諸如圖1中所示的處理腔室120、122、124、126、128或者130之類的處理腔室中執行該沉積製程。 In block 230, a deposition process is performed to deposit a high-κ dielectric layer 306 on the exposed surface of the semiconductor structure 300 (i.e., on the interface layer 304 if the interface layer 304 is formed in block 220, as shown in FIG. 3B, and on the substrate 302 if the interface layer 304 is not formed in block 220 ). The high-κ dielectric layer 306 may be formed of a high -κ dielectric material, such as HfO2 , ZrO2 , ytterbium oxide ( Y2O3 ), or Al2O3 . The deposition process may include an atomic layer deposition (ALD) process, in which a metal-containing precursor and an oxygen-containing precursor are alternately delivered to the exposed surface of the semiconductor structure 300. In some embodiments, the metal-containing precursor is purged before the oxygen-containing precursor is delivered. The metal may be a transition metal such as halogen (Hf), zirconium (Zr), or titanium (Ti), a rare earth metal such as yttrium (La), yttrium (Yb), or yttrium (Y), an alkali earth metal such as strontium (Sr), or other metals such as aluminum (Al). For the oxidant, any oxygen-containing precursor that can react with the metal may be used. For example, the oxygen-containing precursor can be or contain water, diatomic oxygen, ozone, a hydroxyl-containing precursor or alcohol, a nitrogen and oxygen-containing precursor, plasma-enhanced oxygen containing local or remote enhanced oxygen, or any other material containing oxygen that can combine with a metal to produce a layer of metal oxide on the substrate 302. In one example, the metal-containing precursor is hafnium tetrachloride ( HfCl4 ) and the oxidant is water ( H2O ) to form a hafnium dioxide ( HfO2 ) layer. The ALD process can be performed at a temperature between about 200°C and about 400°C, for example, about 270°C. As deposited by an ALD process, the high-κ dielectric layer 306 may be amorphous and have a thickness between about 10 Å and about 30 Å. The deposition process may be performed in a processing chamber such as processing chambers 120, 122, 124, 126, 128, or 130 as shown in FIG. 1 .
在方框240中,執行可選的沉積後退火製程,以硬化和緻密化(densify)所沉積的高κ介電層306。可能發生所沉積的高κ介電層306的結晶化(crystallization)。該沉積後退火製程可以包括在一種快速熱處理(RTP)腔室中執行的惰性環境中(諸如在氮(N2)和氬(Ar)環境中)的熱退火製程,這種快速熱處理(RTP)腔室諸如是可以從位於美國加利福尼亞州聖塔克拉拉的應用材料公司獲得的RADOX ™腔室。這種RTP腔室可以是圖1中所示的處理腔室120、122、124、126、128和130中的任意腔室。這種沉積後退火製程可以用熱的方法硬化和緻密化介面層304和高κ介電層306。 In block 240, an optional post-deposition annealing process is performed to harden and densify the deposited high-κ dielectric layer 306. Crystallization of the deposited high-κ dielectric layer 306 may occur. The post-deposition annealing process may include a thermal annealing process in an inert environment (such as a nitrogen (N2) and argon (Ar) environment) performed in a rapid thermal processing (RTP) chamber, such as a RADOX ™ chamber available from Applied Materials, Inc., Santa Clara, California. The RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG. 1. This post-deposition annealing process can thermally harden and densify the interface layer 304 and the high-κ dielectric layer 306.
可以在介於約500°C與約800°C之間的溫度和介於約0.01Torr與10Torr之間的壓力執行沉積後退火製程達約1秒與約60秒之間的時間。The post-deposition annealing process may be performed at a temperature between about 500° C. and about 800° C. and a pressure between about 0.01 Torr and 10 Torr for a time between about 1 second and about 60 seconds.
在方框250中,替代方框240中的沉積後退火製程,執行可選的再氧化製程,以熱氧化基板302。該再氧化製程可以包括在一種快速熱處理(RTP)腔室中執行的在氧(O 2)、一氧化二氮(N 2O)和H 2環境中的熱退火製程,這種快速熱處理(RTP)腔室諸如是可以從位於美國加利福尼亞州聖塔克拉拉的應用材料公司獲得的RADOX ™腔室。這種RTP腔室可以是圖1中所示的處理腔室120、122、124、126、128和130中的任意腔室。方框250中的再氧化製程可以經由高κ介電層306熱氧化下面的層,因而在方框220中形成介面層304的情況下將介面層304增厚到介於約3Å與約10Å之間的厚度,而在方框220中不形成介面層304的情況下在與高κ介電層306的交界附近在基板302中形成介面層304。 In block 250, an optional reoxidation process is performed to thermally oxidize the substrate 302 in place of the post-deposition anneal process in block 240. The reoxidation process may include a thermal annealing process in an oxygen ( O2 ), nitrous oxide ( N2O ), and H2 environment performed in a rapid thermal processing (RTP) chamber, such as a RADOX ™ chamber available from Applied Materials, Inc., Santa Clara, California. The RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG. 1 . The reoxidation process in box 250 can thermally oxidize the underlying layers through the high-κ dielectric layer 306, thereby thickening the interface layer 304 to a thickness between about 3Å and about 10Å if the interface layer 304 is formed in box 220, and forming the interface layer 304 in the substrate 302 near the junction with the high-κ dielectric layer 306 if the interface layer 304 is not formed in box 220.
可以在介於約400°C與約900°C之間的溫度和介於約0.01Torr與100Torr之間的壓力執行再氧化製程達約1秒與約30秒之間的時間。The reoxidation process may be performed at a temperature between about 400° C. and about 900° C. and a pressure between about 0.01 Torr and 100 Torr for a time between about 1 second and about 30 seconds.
在方框260中,執行電漿氮化製程,以將氮原子插入到高κ介電層306中的孔隙和缺陷中。該電漿氮化製程可以是在一種去耦電漿氮化(decoupled plasma nitridation, DPN)腔室中執行的DPN製程,這種DPN腔室諸如是可以從位於美國加利福尼亞州聖塔克拉拉的應用材料公司獲得的CENTURA® DPN腔室。這種DPN腔室可以是圖1中所示的處理腔室120、122、124、126、128和130中的任意腔室。該電漿氮化製程將高κ介電層306暴露於氮電漿,這可以在高κ介電層306的整個厚度上使氮自由基(radicals)或者氮原子能夠被結合到高κ介電層306內。在該電漿氮化製程期間,氮原子可以形成與氧(O)的亞穩態鍵(metastable bond)。可以在該電漿製程中使用的氣體包括含氮氣體,諸如氮氣(N 2)、氨氣(NH 3)或者這些氣體的混合物。在一個示例中,這種含氮氣體是混合有約3%至約8%的氮氣(N 2)的氨氣(NH 3)。作為氮結合到所沉積的高κ介電層306的孔隙和缺陷中的結果,該電漿氮化製程可以不改變高κ介電層306的厚度。 In block 260, a plasma nitridation process is performed to insert nitrogen atoms into pores and defects in the high-κ dielectric layer 306. The plasma nitridation process may be a decoupled plasma nitridation (DPN) process performed in a DPN chamber, such as a CENTURA® DPN chamber available from Applied Materials, Inc., Santa Clara, California. The DPN chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG. 1 . The plasma nitridation process exposes the high-κ dielectric layer 306 to nitrogen plasma, which can enable nitrogen radicals or nitrogen atoms to be bonded into the high-κ dielectric layer 306 throughout the thickness of the high-κ dielectric layer 306. During the plasma nitridation process, the nitrogen atoms can form metastable bonds with oxygen (O). Gases that can be used in the plasma process include nitrogen-containing gases, such as nitrogen ( N2 ), ammonia ( NH3 ), or mixtures of these gases. In one example, the nitrogen-containing gas is ammonia ( NH3 ) mixed with about 3% to about 8% nitrogen ( N2 ). As a result of nitrogen incorporation into pores and defects in the deposited high-κ dielectric layer 306 , the plasma nitridation process may not change the thickness of the high-κ dielectric layer 306 .
可以在介於約0°C與約500°C之間的溫度執行氮化製程達約10秒與約300秒之間的時間。The nitridation process may be performed at a temperature between about 0°C and about 500°C for a time between about 10 seconds and about 300 seconds.
在方框270中,執行可選的熱氮化製程,以進一步將氮原子插入到電漿氮化後的高κ介電層306中的孔隙和缺陷中。該熱氮化製程可以包括在一種快速熱處理(RTP)腔室中執行的氨(NH 3)環境中的熱退火製程,這種快速熱處理(RTP)腔室諸如是可以從位於美國加利福尼亞州聖塔克拉拉的應用材料公司獲得的RADOX ™腔室。這種RTP腔室可以是圖1中所示的處理腔室120、122、124、126、128和130中的任意腔室。 In block 270, an optional thermal nitridation process is performed to further insert nitrogen atoms into pores and defects in the plasma nitrided high-κ dielectric layer 306. The thermal nitridation process may include a thermal annealing process in an ammonia (NH 3 ) environment performed in a rapid thermal processing (RTP) chamber, such as a RADOX ™ chamber available from Applied Materials, Inc., Santa Clara, California, USA. The RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG. 1 .
可以在介於約700°C與約900°C之間的溫度和介於約10Torr與740Torr之間的壓力執行熱氮化製程達約10秒與約300秒之間的時間。The thermal nitridation process may be performed at a temperature between about 700° C. and about 900° C. and a pressure between about 10 Torr and 740 Torr for a time between about 10 seconds and about 300 seconds.
在方框280中,執行氮化後退火製程,以鈍化電漿氮化後的高κ介電層306中剩餘的化學鍵。該氮化後退火製程可以包括在一種快速熱處理(RTP)腔室中執行的氮(N 2)和氬(Ar)環境中的尖峰熱退火(spike thermal anneal)製程,這種快速熱處理(RTP)腔室諸如是可以從位於美國加利福尼亞州聖塔克拉拉的應用材料公司獲得的RADOX ™腔室。這種RTP腔室可以是圖1中所示的處理腔室120、122、124、126、128和130中的任意腔室。該氮化後退火製程可以鈍化在方框240中的電漿氮化製程中形成的亞穩態氮鍵,並且可能發生非晶高κ介電層306的結晶化。 In block 280, a post-nitridation annealing process is performed to passivate the chemical bonds remaining in the high-κ dielectric layer 306 after plasma nitridation. The post-nitridation annealing process may include a spike thermal annealing process in a nitrogen ( N2 ) and argon (Ar) environment performed in a rapid thermal processing (RTP) chamber, such as a RADOX ™ chamber available from Applied Materials, Inc., Santa Clara, California. The RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG. 1 . The post-nitridation annealing process may passivate metastable nitrogen bonds formed during the plasma nitridation process in block 240 and may cause crystallization of the amorphous high-κ dielectric layer 306 to occur.
可以在介於約700°C與約850°C之間的溫度和介於約10Torr與740Torr之間的壓力執行尖峰熱退火製程達約1秒與約30秒之間的時間。The spike thermal annealing process may be performed at a temperature between about 700° C. and about 850° C. and a pressure between about 10 Torr and 740 Torr for a time between about 1 second and about 30 seconds.
在方框290中,替代方框280中的氮化後退火製程,執行氮化後退火和再氧化製程,以同時如方框280中那樣鈍化高κ介電層306中剩餘的化學鍵和如方框250中那樣熱氧化基板302。方框290中的氮化後退火和再氧化製程與方框250中的再氧化製程相同。因此,這裡省略方框290中的氮化後退火和再氧化製程的細節。In block 290, instead of the post-nitridation annealing process in block 280, a post-nitridation annealing and reoxidation process is performed to simultaneously passivate the remaining chemical bonds in the high-κ dielectric layer 306 as in block 280 and thermally oxidize the substrate 302 as in block 250. The post-nitridation annealing and reoxidation process in block 290 is the same as the reoxidation process in block 250. Therefore, the details of the post-nitridation annealing and reoxidation process in block 290 are omitted here.
在本文描述的多個實施方式中,提供了形成高品質薄的高κ介電材料層的系統和方法。這樣的高κ介電材料層的特性可以得到很好的控制。例如,方框260和270中的氮化製程可以受到控制以提供介於約3原子%與約20原子%之間的高κ介電層306中的氮結合,從而實現與更高氮結合的情況相比更高的κ值,和與更低氮結合的情況相比更好的結構穩定性。方框240、270、280和290中的退火製程也可以受到控制以在高κ介電層306中提供具有大於約20Å的尺寸的晶粒(grain),從而減少流過高κ介電層306的漏電流。In various embodiments described herein, systems and methods for forming high-quality thin high-κ dielectric material layers are provided. The properties of such high-κ dielectric material layers can be well controlled. For example, the nitridation processes in blocks 260 and 270 can be controlled to provide nitrogen incorporation in the high-κ dielectric layer 306 between about 3 atomic % and about 20 atomic %, thereby achieving a higher κ value compared to a higher nitrogen incorporation, and better structural stability compared to a lower nitrogen incorporation. The annealing processes in blocks 240, 270, 280, and 290 can also be controlled to provide grains having a size greater than about 20Å in the high-κ dielectric layer 306, thereby reducing leakage current flowing through the high-κ dielectric layer 306.
儘管前述內容涉及本揭示內容的多個實施方式,但在不脫離本揭示內容的基本範圍的情況下可以設計本揭示內容的其他和進一步的實施方式,並且本揭示內容的範圍由隨附的申請專利範圍來確定。Although the foregoing relates to multiple embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the appended claims.
100:多腔室處理系統 102:工廠介面 104:裝載鎖定腔室 106:裝載鎖定腔室 108:傳送腔室 110:傳送腔室 112:傳送機械手 114:傳送機械手 116:保持腔室 118:保持腔室 120:處理腔室 122:處理腔室 124:處理腔室 126:處理腔室 128:處理腔室 130:處理腔室 140:塢站 142:工廠介面機械手 144:FOUP 148:葉片 150:埠 152:埠 154:埠 156:埠 158:埠 160:埠 162:埠 164:埠 166:埠 168:埠 170:埠 172:埠 174:埠 176:埠 190:系統控制器 192:CPU 194:記憶體 196:支援電路 200:方法 210:方框 220:方框 230:方框 240:方框 250:方框 260:方框 270:方框 280:方框 290:方框 300:半導體結構 302:基板 304:介面層 306:高κ介電層 100: Multi-chamber processing system 102: Factory interface 104: Load lock chamber 106: Load lock chamber 108: Transfer chamber 110: Transfer chamber 112: Transfer robot 114: Transfer robot 116: Holding chamber 118: Holding chamber 120: Processing chamber 122: Processing chamber 124: Processing chamber 126: Processing chamber 128: Processing chamber 130: Processing chamber 140: Dockyard 142: Factory interface robot 144: FOUP 148: Blade 150: Port 152: Port 154: Port 156: Port 158: Port 160: port 162: port 164: port 166: port 168: port 170: port 172: port 174: port 176: port 190: system controller 192: CPU 194: memory 196: support circuit 200: method 210: box 220: box 230: box 240: box 250: box 260: box 270: box 280: box 290: box 300: semiconductor structure 302: substrate 304: interface layer 306: high-κ dielectric layer
為了能夠詳細理解本揭示內容的上述特徵的方式,可以通過參考多個實施方式來對以上簡要概括的本揭示內容進行更具體的描述,在附圖中圖示出這些實施方式中的一些實施方式。但是,應注意的是,附圖僅圖示出本揭示內容的典型實施方式,因此不應視為對本揭示內容的範圍的限制,因為本揭示內容可以允許有其他等效的實施方式。In order to understand in detail the manner in which the above features of the present disclosure are described, the present disclosure briefly summarized above may be described in more detail by reference to a number of embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only typical embodiments of the present disclosure and should not be considered as limiting the scope of the present disclosure, as the present disclosure may admit of other equivalent embodiments.
圖1是根據一個實施方式的示例多腔室處理系統的示意性俯視圖。FIG. 1 is a schematic top view of an example multi-chamber processing system according to one embodiment.
圖2是根據一個實施方式的形成半導體結構的方法的製程流程圖。FIG. 2 is a process flow diagram of a method for forming a semiconductor structure according to an embodiment.
圖3A和圖3B是根據一個實施方式的半導體結構的示意圖。3A and 3B are schematic diagrams of a semiconductor structure according to an embodiment.
為了便於理解,只要可能,就用相同的參考標記指代各圖共有的相同元件。考慮到的是,一個實施方式的元件和特徵可以有益地結合到其他實施方式中而無需進一步聲明。To facilitate understanding, identical reference numerals have been used, wherever possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無 Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None
200:方法 200:Methods
210:方框 210: Box
220:方框 220: Box
230:方框 230: Box
240:方框 240: Box
250:方框 250: Box
260:方框 260: Box
270:方框 270: Box
280:方框 280: Box
290:方框 290: Box
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