JP4931939B2 - Method for forming a semiconductor device - Google Patents

Description

Background of the Invention

Field of Invention
[0001] Embodiments of the present invention generally relate to methods and apparatus for forming a high-k dielectric layer. More particularly, embodiments of the present invention relate to a method for forming a gate dielectric layer.

Explanation of related technology
[0002] Integrated circuits are composed of many, for example, millions of devices such as transistors, capacitors, resistors. Transistors such as field effect transistors typically include a source, a drain, and a gate stack. A gate stack typically includes a silicon substrate, a substrate such as a gate dielectric, and a gate electrode such as polycrystalline silicon on the gate dielectric. The gate dielectric layer may be a dielectric material such as silicon dioxide (SiO ₂ ), or SiON, SiN, hafnium oxide (HfO ₂ ), hafnium silicate (HfSiO ₂ ), hafnium oxynitride silicon (HfSiON), zirconium oxide (ZrO). ₂ ), high-k dielectric having a dielectric constant exceeding 4.0, such as zirconium silicate (ZrSiO ₂ ), barium strontium titanate (BaSrTiO ₃ or BST), lead zirconate titanate (Pb (ZrTi) O ₃ or PZT) Formed from material. However, it should be noted that the film stack can include layers formed from other materials.

  FIG. 1A is a cross-sectional view showing a field effect transistor (FET) incorporating a gate dielectric layer 14. The drawing shows a substrate 12 on which a gate dielectric layer 14 and a gate electrode 16 are disposed. Sidewall spacers 18 are shown adjacent to the vertical sidewalls of gate dielectric layer 14 and gate electrode 16. The source / drain junction 13 is formed in the substrate 12 substantially adjacent to the opposing vertical sidewalls of the gate electrode 16.

  [0004] As the integrated circuit size and the size of the transistors above it have decreased, the gate drive current required to increase the speed of the transistors has increased. The drive current increases as the gate capacitance increases. Capacitance = kA / d, where k is the dielectric constant of the gate, d is the thickness of the dielectric, and A is the area of the device. A way to increase gate capacitance and drive current is to decrease the dielectric thickness and increase the dielectric constant of the gate dielectric.

[0005] Attempts have been made to reduce the thickness of the SiO ₂ gate dielectric to less than 20 angstroms. However, it has been found that the use of SiO ₂ gate dielectrics less than 20 angstroms often has undesirable effects on gate performance and durability. For example, boron from a boron-doped gate electrode can penetrate the underlying silicon substrate through the thin SiO ₂ gate dielectric. Also, in thin dielectrics where the amount of power consumed by the gate increases, typically the gate leakage current, i.e. tunneling current, increases. Thin SiO ₂ gate dielectrics are susceptible to NMOS hot carrier degradation, and high energy carriers traveling throughout the dielectric can damage or destroy the channel. Thin SiO ₂ gate dielectrics are also susceptible to PMOS negative bias temperature instability (NBTI), where the threshold voltage or drive current drifts with the operation of the gate.

  [0006] A method of forming a dielectric layer suitable for use as a gate dielectric layer in a MOSFET (metal oxide semiconductor field effect transistor) includes nitriding a silicon oxide thin film of a nitrogen-containing plasma. Increasing the net nitrogen content of the gate oxide to increase the dielectric constant is desirable for several reasons. For example, most oxide dielectrics can easily incorporate nitrogen during the plasma nitridation process, reducing oxide equivalent film thickness (EOT) over the starting oxide. This can result in reduced gate leakage due to tunneling during FET operation with the same EOT as the non-nitrided oxide dielectric. At the same time, such an increase in nitrogen content is induced by the Fowler-Nordheim (FN) tunneling current during subsequent processing operations, assuming that the dielectric thickness is in the FN tunneling current range. Damage can be reduced. Another advantage of increasing the net nitrogen content of the gate oxide is that the nitrided gate dielectric is more tolerant of gate etch undercut issues, reducing gate edge defect states and leakage currents.

  [0007] In US Pat. No. 6,610,615, issued August 26, 2003, referred to as “Plasma Nitride For Reduced Leakage GateDielectric Layers”, McFadden et al. Describe the nitrogen profile of a silicon oxide film for both thermal and plasma nitridation processes. Comparison is made (see FIG. 1B). The nitrided oxide film is disposed on the silicon substrate. FIG. 1B further shows the nitrogen profile of crystalline silicon under the oxide film. The nitrogen profile data 22 of the thermally nitrided oxide includes a first nitrogen concentration at the top surface of the oxide layer, a deeper, substantially lower nitrogen concentration in the oxide, and a nitrogen junction at the oxide-silicon junction. It shows a nitrogen concentration gradient that is decreasing with accumulation, and finally with distance to the substrate. In contrast, it can be seen that the plasma nitridation process results in a nitrogen profile 24 that is essentially monotonically decreasing from the top surface of the oxide layer through the oxide-silicon junction to the substrate. The undesirable nitrogen junction buildup seen in the thermal nitridation process does not occur with ion bombardment of the nitrogen plasma. Furthermore, the nitrogen concentration of the substrate is lower than that achieved with the thermal nitridation process at all depths.

  [0008] As noted above, the increased nitrogen concentration advantage at the gate electrode-gate oxide junction is the advantage of dopants such as boron from the polycrystalline silicon gate electrode to the gate oxide or through the gate oxide. The outward diffusion is reduced. This improves device reliability, for example, by reducing defects in most of the gate oxide caused by boron diffused inward from a boron-doped polycrystalline silicon gate electrode. Another advantage of reducing the nitrogen content at the gate oxide-silicon channel junction is a reduction in fixed charge density and junction state density. This improves channel mobility and transconductance. The plasma nitrogen process is therefore advantageous over the thermal nitridation process.

  [0009] As semiconductor devices have become smaller, the size of silicon nitride gate oxide layers has reached a practical limit. However, with the reduction of nitrided silicon dioxide gate dielectrics to smaller physical thicknesses (from 10 angstroms), gate leakage has further increased to an unacceptable level for practical device applications. As there is still a need to reduce device size, new gate dielectric materials and / or processes are required.

[0010] The substitution with high k dielectric type material silicon dioxide (SiO _2), there is a problem. For example, high-k dielectric materials typically tend to be incorporated into films deposited with carbon-containing precursors and other contaminants, chemical vapor deposition (CVD) or atomic layer deposition (ALD) techniques. It is deposited using. Carbon and other contaminants adversely affect the dielectric properties of the gate dielectric layer. Also, the quality of the junction between the chemical vapor deposition (CVD) or atomic layer deposition (ALD) deposition high-k film and the channel region is not as robust as the silicon dioxide layer.

  [0011] Therefore, there is a need in the art for a method and apparatus for forming a gate dielectric layer with improved dielectric properties and smaller EOT.

Summary of the Invention

  [0012] The present invention is generally a method of forming a semiconductor device, comprising forming a dielectric layer having a desired thickness on a surface of a substrate, and low energy sputtering in the dielectric layer. Depositing an amount of a first material that forms a concentration gradient through at least a portion of the thickness of a dielectric layer formed using the process, wherein a low energy sputtering process includes a first RF frequency and a first RF The step of depositing a second material over the dielectric layer, wherein the first material of the target can be disposed in the dielectric layer so as to supply RF energy of power to the processing region of the low energy sputtering chamber; The method is provided.

  [0013] Embodiments of the present invention are further apparatus for forming a high-k dielectric layer, comprising a transfer chamber having one or more walls forming a transfer region and a transfer robot positioned in the transfer region A plasma nitridation chamber coupled to the transfer chamber and configured to form nitride on the surface of the substrate in the first processing region of the nitridation chamber, wherein the plasma nitridation chamber is electrically connected to the first processing region. A first low energy coupled to a transfer chamber in communication with the robot; and an RF source in communication with the first processing region and a nitrogen-containing gas source in selective communication with the first processing region. A plasma processing chamber (where the first low energy plasma processing chamber comprises one or more walls forming a second processing region) and a surface having a surface exposed to the second processing region; (Where the target includes a first material), a first RF generator adapted to supply energy at a first RF frequency, and a substrate support positioned in a second processing region. The apparatus is provided.

  [0014] Embodiments of the present invention further include an apparatus for forming a high-k dielectric layer, one or more walls forming a processing region, a target having a surface exposed to the processing region, a processing region A substrate support having at least one substrate facing the substrate (wherein the substrate support is adapted to support a substrate having a dielectric layer formed on the surface of the substrate) and an electrical target and A first generator configured to maintain a capacitively coupled plasma in the processing region by distributing a first amount of energy to the target at a frequency of about 1 MHz to about 200 MHz, wherein the first generator is Configured to create a bias on the surface of the target so that material can be sputtered from it) and the frequency distributed to the target by the first generator And a controller configured to control, to provide the apparatus.

  [0015] Embodiments of the present invention further provide an apparatus for forming a high-k dielectric layer having one or more walls forming a processing region, a surface exposed to the processing region, and a DC A target in communication with the power source and a first coil in electrical communication with the processing region and the first generator (where the first coil and the first generator generate plasma in the processing region adjacent to the surface of the target). The apparatus comprising a substrate support positioned in the processing region.

  [0016] Embodiments of the present invention further provide a method for forming a high-k dielectric layer using a low energy sputtering process, wherein the low energy sputtering process is a dielectric layer in a processing region of a plasma processing chamber. Positioning a substrate formed thereon and disposing a first material in the dielectric layer using a low energy sputtering process, wherein the low energy sputtering process generates a plurality of RF energy pulses. Distributing from a single RF generator to a target comprising a first material, wherein the RF energy of each pulse is distributed at a first RF frequency, and the steps from the DC source assembly to a plurality of DC pulses. Distributing to a plurality of RF energy pulses and a plurality of RF energy pulses DC pulses are synchronized, comprising the steps, to provide the method.

  [0017] Embodiments of the present invention are further methods of forming a high-k dielectric layer using a low-energy sputtering process, the step of forming the high-k dielectric layer using a low-energy sputtering process. The low energy sputtering process includes positioning a substrate having a dielectric layer formed thereon in a processing region of the plasma processing chamber, and the step of forming a first layer in the dielectric layer using the low energy sputtering process. Disposing a material, wherein the low energy sputtering process includes distributing a plurality of RF energy pulses from a first RF generator to a coil in electrical communication with the processing region, wherein RF energy Are distributed at a first RF frequency and a first power, and a plurality of DC pulses Comprising the steps of dispensing a target containing a first material from the DC source assembly, a plurality of RF energy pulses and a plurality of DC pulses are synchronized, comprising the steps, to provide the method.

  [0018] Embodiments of the present invention further comprise forming a high-k dielectric layer using a low-energy sputtering process, wherein the low-energy sputtering process includes the dielectric layer in the processing region of the plasma processing chamber. Positioning the first material in the dielectric layer using a low energy sputtering process, the method comprising positioning a substrate formed thereon, the low energy sputtering process comprising: Distributing a plurality of RF energy pulses at a second frequency from a first RF generator at a first frequency to a coil in electrical communication with the processing region, and the second plurality of RF energy pulses at a second frequency Distributing from a first RF generator to a target in electrical communication with the processing region There, a plurality of RF energy pulses and a plurality of DC pulses are synchronized, comprising the steps, to provide the method.

  [0019] In order that the above features of the present invention may be understood in detail, a more particular description of the invention briefly summarized above may be referred to by embodiments, some of which are illustrated in the accompanying drawings. Is shown in However, the accompanying drawings are merely illustrative of exemplary embodiments of the invention and should not be considered as limiting the scope of the invention, which is not limited to other equally effective embodiments. It should be noted that is acceptable.

Detailed description

  [0043] The present invention generally provides methods and apparatus adapted to form a high quality dielectric gate layer on a substrate. Embodiments contemplate a method for forming a high dielectric constant layer on a substrate using a metal plasma treatment process instead of a standard nitridation process. Embodiments further “inject” relatively low energy metal ions to reduce ion bombardment damage to the gate dielectric layer, such as silicon dioxide, and avoid contamination of the underlying silicon with metal atoms. Contemplates an apparatus adapted to the above. Embodiments of the present invention are useful for forming semiconductor devices such as logic devices or memory devices.

Manufacturing method of high dielectric constant transistor gate
[0044] In the current state of the art of device manufacturing processes, it is difficult to manufacture a gate dielectric layer with 5-10 Angstrom EOT with low leakage current. Plasma nitridation processes are used in the current state of the art of 10-16 angstrom EOT processes for transistor nodes from 65 nm to 90 nm. However, as the nitrided silicon dioxide gate dielectric layer is reduced to thinner physical thicknesses, eg, 10 angstroms, gate leakage may increase to a level that is unacceptable for practical device applications. In order to solve the gate leakage problem with smaller dielectric layer thicknesses, hafnium (Hf), lanthanum (La) are used to replace the plasma nitridation process with a deposition process that forms a high-k dielectric oxide or silicate. ), Aluminum (Al), titanium (Ti), zirconium (Zr), strontium (Sr), lead (Pb), yttrium (Y), or barium (Ba) using the following process Can do.

  [0045] The present invention is for fabricating a gate dielectric in a field effect transistor for logic type applications having a (gate) equivalent oxide thickness (EOT) of a thin gate dielectric thickness of about 5-10 Angstroms. Contemplates the method. The present invention also provides a method for manufacturing a gate dielectric layer in a field effect transistor for memory type applications wherein the gate dielectric layer has an (electrical) equivalent oxide thickness (EOT) of about 10 angstroms to 30 angstroms. Is intended. This process can be used to manufacture integrated semiconductor devices and circuits.

Method and apparatus for forming gate oxide layer
[0046] Efforts to solve common gate performance problems found in sub 45 nanometer (nm) MOS type devices to reduce and / or eliminate defects such as Fermi level pinning or threshold voltage pinning A new process has been created. In general, the process includes forming a high-k derivative and then terminating the surface of the deposited high-k material to form a good junction between the gate electrode and the high-k dielectric material. . Embodiments of the present invention also form a high-k dielectric material, terminate the surface of the high-k dielectric material, perform one or more post-processing steps, and form a polycrystalline silicon and / or metal gate layer. Providing a cluster tool adapted to.

  [0047] FIG. 2A is a diagram illustrating a process sequence 251 containing a series of method steps used to fabricate the gate dielectric of a field effect transistor according to one embodiment of the present invention. Process sequence 251 generally includes processing steps performed on the substrate to form the gate structure of an exemplary MOS type device. 3A-3F are diagrams illustrating regions of the substrate 401 where the gate oxide layer and gate are formed using the steps in the process sequence 251 illustrated in FIG. 2A. The images of FIGS. 3A-3F are not shown to scale and are simplified for illustration. At least a portion of the process sequence 251 can be performed using a processing reactor in an integrated semiconductor substrate processing system (ie, a cluster tool) such as that shown in FIG.

[0048] The process sequence 251 begins at step 252 and proceeds to step 268. In step 252, a silicon (Si) substrate 401 (eg, 200 mm wafer, 300 mm semiconductor wafer) is prepared and a native oxide layer 401A (eg, silicon dioxide (SiO ₂ )) is removed from the surface of the substrate (FIG. 3A). Expose to cleaning solution. In one embodiment, the native oxide layer 401A is removed using a cleaning liquid that includes hydrogen fluoride (HF) and deionized (DI) water. In one embodiment, the cleaning liquid is an aqueous solution containing about 0.1 to about 10% by weight HF maintained at a temperature of about 20 to about 30 ° C. In one example, the cleaning solution includes about 0.5 wt% HF maintained at a temperature of about 25 ° C. In step 252, the substrate 401 can be immersed in a cleaning solution and then rinsed with deionized water. Step 252 can be performed in a single substrate processing chamber or a multiple substrate batch type processing chamber that can include the distribution of ultrasonic energy during processing. Alternatively, step 252 can be performed using the single substrate wet cleaning reactor of integrated processing system 600 (FIG. 7). In other embodiments, the native oxide layer 401A can be removed using an RCA cleaning method. Upon completion of step 252, the substrate 401 is placed in an environment purged with a vacuum loadlock or nitrogen (N ₂ ). Alternatively, step 252 can be performed using the single substrate wet cleaning reactor of integrated processing system 600 (FIG. 7).

[0049] At step 254, a thermal oxide (SiO ₂ ) layer 402 is grown on the cleaned surface 401B of the substrate 401 (FIG. 3B). In general, the thickness of the thermal oxide layer 402 is from about 3 to about 35 Angstroms. In logic type applications, the thermal oxide layer 402 may have a thickness of about 6 to about 15 angstroms, and in memory type applications, the thermal oxide layer 402 may have a thickness of about 15 to about 40 angstroms. There should be. Embodiments of the present invention can be used in applications where the thermal oxide layer thickness may be greater than 35 angstroms. The thermal oxidation step 254 will form a sub-layer of silicon dioxide (SiO ₂ ) that forms on the silicon dielectric junction. Step 254 improves the quality and reliability of the dielectric / silicon junction over the deposited dielectric layer (eg, high-k dielectric layer 404 in FIG. 3D) and charges the channel region under surface 401B. It is thought that the mobility of the carrier is also increased. Step 254 may be performed using a rapid thermal processing (RTP) reactor positioned in one of the substrate processing chambers 614A-614F in the integrated processing system 600 shown in FIG. One suitable RTP chamber is a RADIANCE® RTP chamber available from Applied Materials, Inc., Santa Clara, California. In one example, a 6 Å silicon dioxide (SiO ₂ ) film is formed on the surface 401B of the substrate 401 using an 18 second, 750 ° C., 2 Torr process with an oxygen (O ₂ ) gas flow rate of ₂ slm. In this example, the reactive gas injected into the process chamber in forming the thermal oxide layer 402 is oxygen, but in some cases an inert carrier gas can be added to the process chamber to obtain the desired chamber pressure. it can. Alternatively, in some cases, in step 254, a reactive gas such as nitric oxide (NO) or nitrous oxide (N ₂ O), or hydrogen (H ₂ ) / oxygen (O ₂ ) or nitrous oxide ( It may be desirable to use a reactive gas mixture such as N ₂ O) / hydrogen (H ₂ ).

  [0050] In step 257, the thermal oxide layer 402 is exposed to a metal ion-containing plasma that is used to dope the thermal oxide layer with a material desired to form the high-k dielectric layer 403. The high-k dielectric layer 403 formed in step 257 may be a silicon dioxide layer doped with hafnium (Hf), lanthanum (La), or other similar material. In one embodiment, the low energy deposition process is performed using a process chamber similar to the chamber described by FIGS. 4A-4C and 4F, referenced below. In one embodiment, the RF energy distributed to the processing region 522 is used to generate a plasma, after which a cathode bias is formed on and from the target (eg, reference numeral 505 in FIG. 4A or reference numeral 571 in FIG. 4B). It is desirable to distribute the dopant material to the thermal oxide layer 402 by sputtering this material. In one embodiment, the substrate support 562 is RF biased, DC biased, or grounded to inject sputtered or ionized material to a desired range of depth in the thermal oxide layer 402. It is desirable. In other embodiments, the substrate support is such that the voltage generated across the substrate support 562 relative to the plasma to generate a self-bias is low enough to reduce the energy of the ionized material that bombards the thermal oxide layer 402. It is desirable to “float” the body 562 electrically. Various methods of dispensing the low energy material to dope the thermal oxide layer 402 are described below in conjunction with FIGS. 4A-4F and 5A-5C. Through careful control of chamber pressure, RF power, pulsed DC power, bias applied to substrate support 562 and / or processing time, the amount of dopant and the concentration and depth of dopant material in thermal oxide layer 402 can be controlled. it can. In one embodiment, the plasma may contain not only argon ions and metal ions such as hafnium hafnium, lanthanum, aluminum, titanium, zirconium, strontium, lead, yttrium, barium, but also one or more. An optional inert gas may be contained. Typical inert gases include neon (Ne), helium (He), krypton (Kr), xenon (Xe), nitrogen (Ne), and the like. In one example, the thermal oxide layer 402 is doped with about 5 to about 30 atomic percent (atomic%) of hafnium (Hf). Generally, the dopant of the thermal oxide layer 402 is such that it is a few angstroms or at least near a few angstroms of zero before the junction between the thermal oxide layer 402 and the silicon channel surface (eg, surface 401B). It is desirable to reduce the concentration. In one example, using an inductively coupled variation of the processing chamber (reference number 500 in FIG. 4A), 10 atomic% (average) concentration of hafnium (Hf) applies −150 VDC to the hafnium target (reference number 505) and “ A 180 second and 10 millitorr chamber pressure process (e.g., distributes RF energy to a coil (reference 509) at a frequency of 13.56 MHz and a power of 50 watts using a floating "substrate pedestal with a 5% duty cycle) , Mainly using argon gas) in the thermal oxide layer 402. In another example, using a process configuration similar to that shown in FIG. 4G, 7 atom% concentration (average) hafnium (Hf) is about 100 watts of RF power (ie, ˜5%). Apply a duty cycle and ~ 2000W peak RF power) to the hafnium-containing target 505 and use a "floating" substrate pedestal at a frequency of 13.56 MHz at about 100 watts average RF power (ie ~ 5% duty cycle) And ~ 2000 W peak RF power) is applied in the thermal oxide layer using a 180 second and 10 millitorr chamber pressure process (primarily argon gas) applied to the coil 509. In one embodiment, the average RF power is maintained at a level less than about 1000 W to prevent damage to the thermal oxide layer 402 at step 257. In other embodiments, the average RF power used in step 257 is less than about 200W. In other embodiments, further, the average RF power used in step 257 is less than about 50W. In one embodiment, step 257 uses a low energy plasma processing chamber (eg, processing chamber 500 or process chamber 501) positioned in one of the substrate processing chambers 614A-614F in the integrated processing system 600 shown in FIG. Done.

[0051] In one embodiment, as shown in FIGS. 2A and 3D, instead of using step 254 and step 257 to form a high-k dielectric layer 403 from the thermal oxide layer 402, a metal organic chemical vapor phase is used. An alternative step 256 can be performed to deposit the high-k dielectric layer 404 on the surface 401B of the substrate 401 using a deposition (MOCVD) process, an atomic layer deposition (ALD) process, or other similar deposition process. The high-k dielectric layer 404 may be composed of zirconium oxide (ZrO ₂ ), hafnium oxide (Hf _x O _y ), hafnium silicate oxide (Hf _x Si _1-x O _y ), lanthanum oxide (La ₂ O ₃ ), and / or it is preferable to contain aluminum oxide _(Al 2 _{O 3),} but not limited thereto. Step 256 can be performed using an atomic layer deposition system, such as, for example, the Centura ALD High-K system available from Applied Materials. An ALD type reactor can be positioned in one of the substrate processing chambers 614A-614F in the integrated processing system 600 shown in FIG.

[0052] At step 259, a high-k dielectric layer 403 or a surface of the high-k dielectric layer 404 is terminated by performing a plasma deposition process to form a termination region 405. In general, the termination region 405 is formed by depositing a layer material and / or doping the high-k dielectric layer 403 or the high-k dielectric layer 404. The addition of a termination region 405 containing a passivating material such as lanthanum oxide (La ₂ O ₃ ) or aluminum oxide (Al ₂ O ₃ ) passivates the surface and is generally applied to conventional ALD or MoCVD high-k films. It is believed to solve the problems seen, Fermi level pinning or threshold voltage shift. In one embodiment, the high-k dielectric layer 403, or the high-k dielectric layer 404, is about 0.1 to about 10 atomic percent lanthanum (La), and / or about 0.1 to about 10 atomic percent aluminum. Doped with (Al). In other embodiments, the high-k dielectric layer 403, or the high-k dielectric layer 404, is about 0.25 to about 5 atomic% lanthanum (La) and / or about 1 to about 10 atomic% aluminum (Al ). Since it is desirable to reduce the dopant concentration of the high-k dielectric layer 403 or the high-k dielectric layer 404, it is believed that the high-k dielectric layer 403 or the high-k dielectric layer 404 will spread by several angstroms. In one embodiment, a lanthanum (La) dopant is introduced into the high-k dielectric layer 403 using the process chamber described in FIGS. 4A-4C below. In one example, −100 VDC is applied to a lantern target (eg, 505 in FIG. 4A) and RF is used at a frequency of 13.56 MHz and a power of 50 W using a “floating” substrate pedestal and a 5% duty cycle. 0.5 atomic percent (average) on a 10 atomic percent hafnium-doped high-k dielectric layer 403 using a chamber pressure process of 120 seconds and 10 millitorr (eg, primarily argon gas) that distributes energy to the coils. Concentrate lanthanum (La).

  [0053] In one embodiment, step 259 may be performed in a process chamber similar to process chamber 500 or process chamber 501 shown in FIGS. 4A-4C. In this configuration, the termination region 405 is formed by performing a low energy injection type process similar to the above process in step 257. In one embodiment, the RF material distributed to the processing region 522 is used to generate a plasma, and then form a cathode bias on the target 505 and sputter the material therefrom to make the dopant material a high-k dielectric layer. Distribute to most of the area above 403. In order to inject sputtered and ionized material into the high-k dielectric layer 403, the substrate support 562 may be RF biased, DC biased, grounded, or floating. Various methods of distributing the low energy material to dope the high-k dielectric layer 403 are described below in conjunction with FIGS. 4A-4F and 5A-5C below. Therefore, by carefully controlling the chamber pressure, RF power, pulsed DC bias, desired bias applied to the substrate support 562 and / or processing time, the amount of dopant and the concentration of dopant material in the high-k dielectric layer Depth can be controlled. In one embodiment, the dopant is an aluminum-containing material, a lanthanum-containing material, or other similar material.

  [0054] In one embodiment, step 259 may be performed using the processing chamber 500 positioned in one of the substrate processing chambers 614A-614F of the integrated processing system 600 shown in FIG. In one aspect, the processing chamber 500 used to perform step 259 is a different processing chamber than the process chamber used to perform step 257. In other embodiments, a single processing chamber 500 attached to the integrated processing system 600 is used to perform steps 257 and 259, each step being located in a processing region 522 of the processing chamber 500. This is done using different target materials.

  [0055] In other embodiments of step 259, termination region 405 may be an additional layer of material that is deposited on the surface of high-k dielectric layer 403 by performing a sputtering process. In one aspect, the sputtering process is performed using a process chamber similar to the process chamber 500 or process chamber 501 shown in FIGS. 4A-4C. In this structure, the termination region 405 generates a plasma using RF energy distributed to the processing region 522, and then forms a cathode bias on the target 505 and sputters material from it to produce high k. Formed by depositing a target material on top of the dielectric layer 403. The substrate support 562 is RF biased, grounded, or electrically floating to control the energy and depth of the sputtered and ionized material that is implanted into the high-k dielectric layer 403. May be. In one embodiment, the deposited layer contains aluminum (Al), lanthanum (La), or other suitable material.

[0056] In one embodiment, the optional step 260 uses an oxygen-containing RF plasma to oxidize exposed materials and convert them to dielectric materials. In one example, the high-k dielectric layer 403, the high-k dielectric layer 404, and / or the termination region 405 are exposed to an oxygen-containing plasma to form aluminum oxide or lanthanum oxide. In other embodiments, the plasma contains nitrogen (N ₂ ) and may contain one or more oxidizing gases such as O ₂ , NO, N ₂ O. The plasma may also contain one or more optional inert gases, such as argon (Ar) or helium (He). Step 260 can be performed, for example, using a decoupled plasma nitridation (DPN) plasma reactor of integrated processing system 600 (FIG. 7). In one embodiment, a thermal oxidation step is used instead of a plasma oxidation step to oxidize the exposed material and convert it to a dielectric material. In one example, the plasma oxidation process uses a nitrogen flow rate of about 100 seem and an oxygen flow rate of about 100 seem to produce a 5% duty cycle and 1000 W peak power (ie, an average power of 50 W) to oxidize the exposed material. This is done using an RF frequency of .56 MHz for 30 seconds.

[0057] In an alternative embodiment, optional step 262 is used instead of step 260. In step 262, the high-k dielectric layer 403, or high-k dielectric layer 404, and the substrate 401 are annealed at a temperature between about 600 ° C. and 1100 ° C. Lower temperature anneals, such as those performed at temperatures between about 600 ° C. and 800 ° C., can be performed on previously deposited materials such as hafnium and silicon (Si), oxygen (O ₂ ), or both. It can be advantageously used to prevent crystallization. Step 262 can be performed using a suitable thermal annealing chamber, such as the RADIANCE® or RTPXE ⁺ reactor of the integrated processing system 600, or a single substrate furnace or batch furnace. Step 262 forms a silicate sublayer in high-k dielectric layer 403 or termination region 405. In one embodiment, step 262 includes about 2 to about 5000 sccm of oxygen (O ₂ ) while maintaining a substrate surface temperature of about 600 ° C. to about 1100 ° C. and a process chamber pressure of about 0.1 to about 50 Torr. And at least one of about 100 to about 5000 sccm of mono-oxynitride (NO), and any gas may be mixed with nitrogen (N ₂ ) if desired. The process can be performed for about 5-180 seconds. In one example, step 262 is a 15 second, 900 ° C., 1 Torr process with oxygen (O ₂ ) gas at a flow rate of 60 sccm and nitrogen (N ₂ ) gas at a flow rate of 940 sccm. In another example, O ₂ is supplied at about 200 sccm (eg, an oxygen partial pressure of about 200 mT) while maintaining the process chamber at a temperature of about 1000 ° C. and a pressure of about 1 Torr for about 15 seconds, and nitrogen (N ₂ ) At about 800 sccm. In yet another example, NO is supplied at about 500 sccm while maintaining the chamber at a temperature of about 1000 ° C. and a pressure of about 0.5 Torr for about 15 seconds.

  [0058] In one embodiment, after performing any of steps 256, 257, or 259, neither step 260 or 262 is performed. In one embodiment of process sequence 251, an oxidation step similar to step 260 or 259 reoxidizes the dopant material deposited in step 257 before termination region 405 is deposited on high-k dielectric layer 403. To do so, it can be performed between steps 257 and 259.

[0059] In step 264, termination region 405 and high-k dielectric layer 403 or high-k dielectric layer 404 are treated in a nitrogen plasma to increase the amount of nitrogen in these regions. The process can be performed using a DNP reactor by applying about 10 to about 2000 sccm of nitrogen (N ₂ ), a substrate pedestal temperature of about 20 to about 500 ° C., and a reaction chamber pressure of about 5 to about 200 millitorr. it can. The radio frequency (RF) plasma is excited, for example, at about 13.56 MHz or 60 MHz using a continuous wave (CW) or pulsed plasma power source up to about 3-5 kW. During the pulse, the peak RF power, frequency and duty cycle are typically selected in the range of about 10 to 3000 W, about 10 kHz, 2% to 100%, respectively. This process can be performed for about 1 to 180 seconds. In one example, N ₂ is supplied at about 200 sccm, and a peak RF power of about 1000 W is pulsed at about 10 kHz with a duty cycle of about 5%, at a temperature of about 25 ° C. and a pressure of about 10 to about 80 millitorr. Applied to an inductive plasma source for seconds to 180 seconds. The plasma is generated using a quasi-remote plasma source, an inductive plasma source, or a radial line slot antenna (RLSA) source, among other plasma sources. In an alternative embodiment, a CW and / or microwave power source can be used to form a high nitrogen content region.

[0060] At step 266, the substrate 401 can be annealed to reduce leakage current between layers formed on the substrate 401, increasing the mobility of charge carriers in the channel region below the surface 401B. In addition, the reliability of the formed device is improved. Step 266 may assist in reducing the number of defects in the layer formed on the substrate 401. The action of annealing or deactivating the nitride layer formed in step 264 at step 266 also helps promote the formation of an effective barrier against boron diffusion from the boron-doped polycrystalline silicon gate electrode. To do. Step 266 can be performed using a suitable thermal annealing chamber, such as the RADIANCE® or RTPXE® reactor of the integrated processing system 600, or a single substrate or batch furnace. In one embodiment, the annealing process of step 266 includes a flow rate of about 2 to about 5000 sccm while maintaining a substrate surface temperature of about 800 ° C. to about 1100 ° C. and a reaction chamber pressure of about 0.1 to about 50 Torr. Of oxygen (O ₂ ) and at least one of nitric oxide (NO) at a flow rate of about 100 to about 5000 sccm, and the gas may be mixed with nitrogen (N ₂ ) if desired. . The process should take about 5-180 seconds. In one embodiment, oxygen (O ₂ ) gas is supplied at about 500 sccm while maintaining a temperature of about 1000 ° C. and a pressure of about 0.1 Torr for about 15 seconds. In one embodiment, step 266 uses a process method similar to that used in step 262 above.

  [0061] Upon completion of step 260, 262, 264 or 266, one or more layers are deposited over the formed layer to form the gate region, or gate electrode, of the MOS device formed using step 268. Form. In one embodiment of step 268, a polycrystalline silicon layer is deposited on the gate region above the layer to provide a gate electrode. In one example, the polycrystalline silicon layer is deposited using a conventional polycrystalline silicon deposition process. In one embodiment, a polycrystalline silicon deposition chamber (not shown) is part of integrated processing system 600. In one embodiment, the polycrystalline silicon is formed using a CVD or ALD reactor, such as a Centura CVD reactor available from Applied Materials, comprising one of the substrate processing chambers 614A-614F of the integrated processing system 600 shown in FIG. Deposited on the layer formed in process sequence 251.

  [0062] In another embodiment of step 268, the gate region 408 contains a plurality of conductive layers, such as a thin metal layer 407 and a polycrystalline silicon layer 406, as shown in FIG. 3F. In one embodiment, the gate region 408 includes a thin metal layer 407 deposited over the layer formed in the process sequence 251 to provide a gate material having a higher carrier concentration than a conventional polycrystalline silicon gate material. To do. The thin metal layer 407 may have a thickness of about 5 to about 200 angstroms. In one embodiment, the thin metal layer 407 includes tantalum (Ta), tantalum nitride (TaN), lanthanum carbide (LaC), tungsten (W), tungsten nitride (WN), silicon tantalum nitride (TaSiN), hafnium (Hf). , Aluminum (Al), ruthenium (Ru), cobalt (Co), titanium (Ti), nickel (Ni), aluminum nitride titanium (TiAlN), ruthenium nitride (RuN), hafnium nitride (HfN), nickel silicide (NiSi) ), Metal such as titanium nitride (TiN) or other suitable material. The thin metal layer 407 can be advantageously formed using the processing chamber 500 (FIG. 4A) or the process chamber 501 (FIGS. 4B-4C) attached to the integrated processing system 600 shown in FIG. In this configuration, the thin metal layer 407 generates a plasma using RF energy, biases the target and sputters metal therefrom, and then biases the substrate support 562 (FIGS. 4A-4B) as desired. And may be formed by depositing a target material on the layer formed in process sequence 251 by depositing a sputtered and ionized metal material on the preformed layer. The use of RF energy to drive the sputter deposition process allows a very small amount of material to be reliably deposited on the substrate surface. Conversely, the application of sputtering (DC) voltage required to reduce the deposition rate to a level low enough to form a thin metal layer usually does not sustain the sputtering plasma, so conventional physical vapor deposition. Or, sputtering techniques are severely limited in their ability to reliably deposit thin material layers. In other embodiments, the thin metal layer 407 can be formed using a conventional CVD, PECVD or ALD process.

  [0063] FIG. 2B illustrates another embodiment of a process sequence 251. As shown in FIG. The process sequence 251 shown in FIG. 2B is the same as the steps of the method shown in FIG. 2A, except that at least one of the two optional steps 258A and / or 258B is added between step 257 or steps 256 and 259. Is the same. In one embodiment, a plasma nitridation step is a process for nitriding one or more of the materials found in the high-k dielectric layer 403 formed in one of steps 254, 256, or 257, or the high-k dielectric layer 404. Added to order 251. In one example, a plasma nitridation process to prevent crystallization of hafnium material found in the high-k dielectric layer 403 or high-k dielectric layer 404 in subsequent annealing steps, such as steps 258B, 262, or 266. It is desirable to form a hafnium nitride-containing layer using In one embodiment, step 258A is performed using the process described herein in conjunction with step 264.

[0064] In one embodiment, the optional thermal annealing step, step 258B, reduces the defects and stresses in the formed high-k dielectric layer 403 or high-k dielectric layer 404 and increases the reliability of the formed device. Added to process sequence 251 to improve. In one embodiment, step 258B is performed using the process described herein in conjunction with step 262 and / or step 266. In one embodiment, step 258B ends after performing step 258A above. In one example, step 258B is a 15 second, 900 ° C., 1 Torr process with an oxygen (O ₂ ) gas flow rate of 60 sccm and a nitrogen (N ₂ ) gas flow rate of 940 sccm.

[0065] FIG. 2C is a diagram illustrating another embodiment of a process sequence 251. As shown in FIG. The process sequence 251 shown in FIG. 2C is the same as the step shown in FIG. 2A except that step 253 is added between steps 252 and 254 and step 256 is performed after step 254. In this embodiment, the plasma nitridation step, step 253, is added to the process sequence 251 after removing the native oxide layer in step 252, and the substrate surface is nitrided before performing step 254 or step 256. The nitrided silicon substrate surface assists in forming the desired silicon oxynitride (SiON) remaining on or near the surface of the silicon oxide layer formed in the subsequent thermal oxidation step (step 254). Conceivable. Formation of the SiON layer remaining on or near the formed silicon dioxide layer minimizes diffusion of the gate electrode material (step 268) into the gate dielectric layer in subsequent process steps. Can help. The order in which steps 256 and 254 are performed in this embodiment has been changed to allow the formation of a silicon oxynitride (SiON) junction layer prior to depositing the high-k dielectric layer using step 256; Helps improve the properties of the junction between the high-k dielectric layer and the channel region of the device. Step 253 can be performed in a DPN reactor available from Applied Materials of Santa Clara, California. In one example, step 253 uses a 10 second, 70 mTorr process using 25 W average RF power (5% duty cycle of 500 W peak RF power), 200 sccm of N ₂ gas flow, 25 ° C. substrate temperature. Also, in one embodiment of the process sequence 251, step 254 is altered to ensure that the desired characteristics of the nitrided silicon surface performed in step 253 are retained. In this case, it may be desirable to inject other reactive gases such as nitrogen (N ₂ ) along with oxygen into the process chamber at step 254 to ensure that a high quality dielectric film is formed. In one example, a silicon oxynitride (SiON) film has an oxygen (O ₂ ) gas flow rate of 15 sccm and a nitrogen (N ₂ ) gas flow rate of 5 slm for 30 seconds at 1050 ° C., 5 Torr (ie, 15 mTorr oxygen). Following the (partial pressure) process, an oxygen (O ₂ ) gas with a flow rate of 0.5 slm and a nitrogen (N ₂ ) gas with a flow rate of 4.5 slm are formed on the surface 401B using a modified gas setting of 15 seconds.

[0066] FIG. 2D is a diagram illustrating another embodiment of a process sequence 251. As shown in FIG. The process sequence 251 shown in FIG. 2D is the same as the step shown in FIG. 2A, except that two optional steps 255A or 255B can be added between steps 254 and 257. In one embodiment, an optional plasma nitridation step, step 255A, is added between steps 254 and 257 to nitride the top surface of the thermal oxide layer formed in step 254 to form a SiON layer. The SiON layer can act as a diffusion barrier that prevents the gate electrode material from diffusing into the gate dielectric layer. In one example, step 255A uses a 30 second, 10 millitorr process with 50 W average RF power (5% duty cycle of 1000 W peak RF power), N ₂ 200 sccm gas flow, substrate temperature of about 25 ° C. .

[0067] Referring to FIG. 2D, in one embodiment, an optional thermal annealing step, step 255B, is added to the process sequence 251 to reduce defects and stress in the formed high-k dielectric layer 403. Improve device reliability. In one example, the annealing process of step 255B may be performed at a flow rate of about 15 sccm of oxygen (O ₂ ) and a flow rate of about 500 sccm while maintaining a substrate temperature of about 1050 ° C. and a reaction chamber pressure of about 1 to about 5 Torr. This can be performed by supplying at least one of nitrogen (N ₂ ). In other embodiments, step 255B is performed using the process described herein in conjunction with step 262 and / or step 266. In one embodiment, step 255B is completed after performing step 255 above.

[0068] FIG. 2E is a diagram illustrating another embodiment of a process sequence 251. As shown in FIG. The process sequence 251 shown in FIG. 2E is similar to FIG. 2A except that step 254 is removed and step 252 is modified (new step 252A) to allow the wet cleaning process to form a silicon oxide-containing bonding layer. Same steps as shown. In this embodiment, the new step 252A cleans and intentionally forms an oxide layer on the surface 401B of the substrate using a wet cleaning process. The new step 252A can be performed in an Emerison ^™ chamber available from Applied Materials, Inc., Santa Clara, California. In one example, a 4-5 Angstrom oxide layer is immersed in a dilute hydrofluoric acid (HF) bath for 8 minutes in Step 252A, followed by a standard cleaning 1 (SC1) maintained at 50 ° C. for 6 minutes. Wash and dip in a bath (eg, <5% by volume ammonium hydroxide (NH ₄ OH) / <3% by volume hydrogen peroxide (H ₂ O ₂ ) / residual DI water), after which the substrate is Formed by rinsing for a desired time in a megasonic working tank containing DI water (ie 1500 W). In another example, the oxide layer can be formed by a wet cleaning process using an ozone (O ₃ ) containing cleaning solution.

[0069] FIG. 2F illustrates another embodiment of a process sequence 251. As shown in FIG. The process sequence 251 shown in FIG. 2F is the same as the step shown in FIG. 2A, except that step 256 is performed after step 254. In this embodiment, the order in which steps 256 and 254 are performed is that in step 256 a thin silicon dioxide (SiO ₂ ) layer (eg, <10 angstroms) is formed before depositing the high-k dielectric layer. Has been changed to allow. In one embodiment, a thin high-k dielectric layer 404 is deposited on the thermal oxide layer 402 grown in step 254 using an ALD type deposition process. This configuration shows the desired dielectric properties of the complete stack, while the thin silicon dioxide layer formed in step 254 provides a good dielectric / channel region junction at the junction between the device dielectric layer and the channel region. So it is considered useful.

Hardware aspects of design
[0070] As noted above, it is desirable to form a high-k dielectric layer using the plasma processing process described in conjunction with steps 257 and 259 above. Plasma processes used at large plasma potentials, for example on the order of tens of volts, can cause damage to the thin gate dielectric layer and even cause the impact metal atoms to enter the channel region underlying the formed MOS device. Damage to the dielectric layer, such as silicon dioxide, or incorporation into the region underlying the metal atoms is undesirable due to reduced device performance and increased leakage current. The various embodiments described below can be used to reliably form a gate dielectric layer using a plasma processing process. Examples of various devices that can be used to perform such a metal plasma process are described below in conjunction with FIGS. 4A-4C and 4F.

Inductively coupled plasma processing chamber
[0071] FIG. 4A shows a schematic cross-sectional view of one embodiment of a plasma processing chamber 500 that may be used to perform the process of steps 257 and / or 259 above. In this configuration, the processing chamber 500 is an inductively coupled plasma processing chamber that can process a substrate 502 such as the substrate 401 (FIG. 3A) in the processing region 522. In one embodiment, the processing chamber 500 is a modified plasma nitridation (DPN) chamber available from Applied Materials, Santa Clara, using an inductively coupled RF source.

  [0072] The processing chamber 500 typically contains an inductive RF source assembly 591, a DC source assembly 592, a target 505, a system controller 602, a process chamber assembly 593, and a substrate support assembly 594. The process chamber assembly 593 typically contains elements that can form a vacuum in the processing region 522 so that a plasma process can be performed therein. In general, the process chamber assembly 593 includes a chamber base 527, a chamber wall 528 and a chamber lid 529 that seal the processing region 522. The processing region 522 can be evacuated to a desired vacuum pressure by use of a vacuum pump 510 connected to the processing region 522 through the chamber base 527 and / or the chamber wall 528. In general, chamber wall 528 and chamber base 527 may be formed from a metal, such as aluminum or other suitable material. In one embodiment, the chamber wall 528 can have a removable chamber shield (not shown) that prevents material sputtered from the target 505 from resting on the chamber wall 528.

  [0073] Inductive RF source assembly 591 typically includes an RF generator 508 and an RF match 508A connected to a coil 509 positioned adjacent to chamber lid 529. In one embodiment, the RF generator 508 can operate at a frequency of about 400 kHz to about 20 MHz at about 0 to about 3000 W. In one example, the RF generator 508 operates at a frequency of 13.56 MHz. The chamber lid 529 is typically a dielectric element (eg, quartz, ceramic material) that is adapted so that the RF energy delivered from the inductive RF source assembly 591 forms a plasma in the processing region 522. In one embodiment, the coil 509 can be positioned near the target 505 such that the plasma generated in the processing region 522 is formed near the active surface of the target in a sputter process. Control of the plasma near the active surface can help control the plasma density near the region of the target that is sputtered during the low energy sputter deposition process. This configuration is useful for reducing the amount of unwanted plasma bombardment of extremely thin gate dielectric layers due to the plasma generated by coil 509.

  [0074] In one embodiment, the chamber lid 529 is modified to allow the vacuum sealed electrical feedthrough 504 to contact the target 505 positioned in the processing region. In this configuration, a coaxial cable 506 is connected to a vacuum sealed feedthrough 504 and energy is distributed from a DC power source 507 so that ions generated in the plasma sputter material from the target onto the substrate 502. In one aspect described below in conjunction with FIGS. 5A-5C, the system controller 602 is used to synchronize the output from the RF generator 508 and the DC power distributed from the DC source 592 assembly. In one embodiment, the target 505 may be pure material or hafnium (Hf), lanthanum (La), aluminum (Al), titanium (Ti), zirconium (Zr), strontium (Sr), lead (Pb), yttrium (Y Or an alloy containing an element selected from the group of barium (Ba).

  [0075] In one aspect, the process chamber assembly 593 is also adapted to distribute one or more process gases to the processing region 522 formed by the chamber base 527, the chamber wall 528, and the chamber lid 529. Contains system 550. The pressure in the processing region 522 may be controlled by use of a system controller 602 that is used to adjust the gas flow dispensed by the pumping rate of the vacuum pump 510 regulated by the gas distribution system 550 and the slot valve 511. In one aspect, the chamber pressure during processing is from about 5 millitorr to about 100 millitorr.

  [0076] The substrate support assembly 594 typically includes a substrate support 562 containing a substrate support member 562A. The substrate support member 562A can be a conventional electrostatic chuck or a simple substrate support pedestal that can be used to actively hold the substrate during processing. The temperature controller 561 is typically a substrate support member set to a desired temperature setting by the temperature controller 561 by use of conventional means such as embedded resistance heating elements or fluid cooling channels coupled to a heat exchanger (not shown). Adapted to heat and / or cool 562A. In one aspect, the temperature controller 561 is adapted to operate and heat to a temperature of about 20 ° C. to about 800 ° C. positioned on the substrate support member 562A. During processing, the substrate support 562 is connected to an RF generator such that an RF bias can be applied to the portion of the substrate support 562 for pulling ions that are in the plasma generated on the surface of the substrate 502 in the processing region 522. It is good to do. In one embodiment, the substrate support member 562A is grounded, DC biased, or electrically floating during the plasma process to minimize ion bombardment damage to the substrate 502.

  [0077] Distributing RF energy from the RF generator 508 to the process region 522 produces gas atoms in the process region that are ionized. The ionized atoms in the plasma are then applied to the target 505 due to the cathode bias applied to the target 505 by the DC source assembly 592 so that material can be sputtered from the target 505 and rest on the surface of the substrate 502. Be attracted. In an effort to reduce the interference and interaction between the RF energy delivered from the inductive RF source assembly 591 and the DC bias applied from the DC source assembly 592, interference is minimized, deposition rate, film uniformity, and film quality are maximized. It is often desirable to synchronize the energy pulses distributed from the DC source assembly 592 and the RF source assembly 591 so that they can be minimized when done. Pulsing the inductive RF source to excite the plasma ameliorates problems associated with low electron temperatures and high plasma potentials that cause damage to the surface of the substrate by generating and maintaining a low energy plasma. In general, ions generated by a pulsed RF induced plasma obtain ions with low ion energy (eg, <10 eV) that does not damage the substrate positioned in the plasma. This is more fully described by co-assigned US Pat. No. 6,831,021, filed June 12, 2003, the disclosure of which is incorporated herein. The low ion energy of most inert gases such as Argon (Ar), Neon (Ne), Krypton (Kr), or Xenon (Xe) is hafnium (Hf), lanthanum (La) or other heavy metals or dielectrics Not enough energy from the pulsed RF source to sputter atoms from a target manufactured from For example, for argon plasma, the sputtering threshold energies of Hf and La targets are 42.3 eV and 25.5 eV, respectively, and the safe ion energy for ion implantation into the gate oxide is typically less than 10 eV. That is, for RF-induced plasma, the sufficiently low ion energy that is safe to form the gate dielectric layer is not high enough to sputter desired metal ions from the target material. Therefore, there is a need to use a DC bias applied to the target from a DC source assembly 592 for performing the sputtering process. Various pulse deposition process aspects are described below in conjunction with FIGS. 5A-5C.

Capacitively coupled plasma processing chamber
[0078] FIGS. 4B-4C are schematic cross-sectional views of other embodiments of plasma processing chambers that may be used to perform the process described in steps 257 and / or 259 above. In this configuration, the process chamber 501 is a capacitively coupled plasma processing chamber that can process the substrate 502 in the processing region 522. Process chamber 501 typically contains a VHF source assembly 595, a target assembly 573, a system controller 602, a process chamber assembly 596, and a substrate support assembly 594. In this configuration, capacitively coupled plasma is formed in the processing region 522 between the target 571 contained in the process chamber assembly 596 and the grounded chamber wall 528 by use of a VHF source assembly 595 connected to the target 571. The process assembly 596 typically contains all of the elements described in conjunction with FIG. 4A above, except that the chamber lid 529 is replaced with a target assembly 573 and an electrical insulator 572 that are positioned hermetically on the chamber wall 528. To do. The elements in process chamber assembly 596 and substrate support assembly 594 are the same or similar to those described by process chamber 500, and as such, like reference numerals are used where appropriate and are not repeated below. .

  [0079] Referring to FIG. 4B, in one embodiment, the VHF source assembly 595 includes an RF source 524 adapted to distribute RF energy through one or more portions of the target assembly 573 to the processing region 522. Contains alignment 524A. The target assembly 573 typically contains a backing plate assembly 570 and a target 571. The backing plate 570 is from a magnetron assembly (not shown) adapted to facilitate full use of the heat exchanger (not shown) and target material in the process and to enhance deposition uniformity to the dispensed fluid. It may contain a fluid channel (not shown) for cooling the target.

  [0080] During operation of the process chamber 501, the VHF source assembly 595 is used to bias the target 571 so that atoms in the material from which the target 571 is formed can be deposited on the surface of the substrate 502. In one embodiment, the RF source 524 in the VHF source assembly 595 powers the processing region 522 through the target assembly 573 at a power of about 0.01 to about 5 kilowatts (kW) at an RF frequency of about 1 to about 200 MHz. Adapted to dispense. In one embodiment, the VHF source assembly 595 is used to provide sufficient energy on the capacitively coupled target 571 to reduce the voltage across the plasma sheath where ions generated by the plasma sputter material from the surface of the target 571. To generate a self-bias. Capacitive coupling electrodes, or targets, that are biased with a VHF source typically reach a self-bias voltage due to the difference in surface area between the anode and cathode (eg, target 571). The self-bias voltage that the target 571 reaches during processing can be adjusted to optimize the sputtering rate of the target 571. FIG. 4E is a diagram showing a graph of self-bias voltage and frequency. The graph typically shows the effect of frequency on the electrode's self-bias voltage when biased at increasingly higher frequencies. Since the magnitude of the self-bias voltage tends to decrease as the frequency increases, increasing the frequency of the VHF source assembly 595 can reduce the energy of ions impinging on the target. For example, a target that is biased with an RF signal at a frequency of 27 MHz has a voltage of only about 10 V using argon with a pressure of 50 mTorr and 300 W of RF power. In other examples, the DC bias on the target may be varied from about −50V to about −20V by varying the RF frequency from about 60 MHz to about 100 MHz with a constant RF power of about 400 W.

  [0081] Distributing energy to the target 571 at an RF frequency in the VHF range reduces the DC bias variation on the target as a function of the variation in frequency distributed to the target 571 and the variation in RF power, resulting in lower RF The process result of steps 257 and / or 259 may be improved for processes performed at frequency. Reducing DC bias fluctuations can be important when performing low power sputtering operations. Therefore, by controlling the frequency of the RF energy and power, for example, by distributing power to the target 571 at the desired duty cycle (below), the target DC bias can be accurately and repeatedly performed. Accurate and precise control of the DC bias ensures that the process of doping extremely thin gate dielectric layers can be performed accurately and repeatedly.

  [0082] Referring to FIG. 4D, in one example, when the sputtering gas is primarily argon (Ar) and the target is made from lanthanum (La), it is required to sputter lanthanum atoms from the target surface. The energy is at least 25.5 eV. This requires that the self-bias voltage generated on the target is high enough to produce ion energy of about 25.5 eV to ensure that some of the lanthanum atoms are sputtered from the target surface. It means that there is. Therefore, by controlling the frequency and power (eg, watts) distributed to the target 571, the sputter rate, gas atom ion energy, ion energy of sputtered atoms, and energy of atoms deposited on the substrate can be controlled. . Also, during the process, the bias to the substrate support 562 can be adjusted to control the energy that sputtered atoms have as they are deposited on or implanted into the gate dielectric layer. .

  [0083] Generally, the sputter process is performed in the process chamber 501 at a chamber pressure in the range of 1 millitorr to 100 millitorr and a heater temperature of about 20 ° C to about 800 ° C using an argon flow rate of about 1 sccm to about 500 sccm. it can. Preferably, the substrate temperature is about 200 ° C to 300 ° C. The excitation frequency of the RF source 254 can be adjusted from about 1 MHz to about 200 MHz to obtain the correct self-biased DC voltage that causes the target material to sputter into the plasma and the substrate surface. Preferably, the excitation frequency of the RF source 254 can be adjusted to a frequency of about 27 MHz to about 100 MHz, more preferably a frequency of about 30 MHz to about 60 MHz. In one example, for a lanthanum target, a frequency of 60 MHz can be selected to obtain the desired sputtering energy and low energy plasma. In one embodiment, it is desirable to adjust the space between the surface of the substrate 502 and the surface of the target 571 to adjust the uniformity and energy of the sputtered atoms deposited on the substrate surface. In one aspect, it is desirable to adjust the space of the substrate 502 relative to the surface of the target 571 during the deposition process to adjust the sputtered material depth and / or deposition uniformity of the gate oxide layer. is there.

  [0084] FIG. 4C is a diagram illustrating a second embodiment of the process chamber 501, wherein the VHF source assembly 595 illustrated in FIG. 4B is at different frequencies and / or powers that provide different sputtering characteristics at different times during the process. A dual VHF source assembly 597 containing two RF generators 524, 525, each adapted to distribute energy to the processing region 522 of the process chamber 501, has been replaced. The process chamber 501 shown in FIG. 4C typically contains an RF source 524 connected to a target assembly 573, a second RF source 525, an RF switch 526, and a match 524A. In this configuration, the energy delivered to the target assembly 573 from the dual VHF source assembly 597 can be switched between the RF source 524 and the second RF source 525 by use of the RF switch 526. The state of the switch 526 is controlled by the system controller 602. This embodiment is useful for target materials that require fast onset squeezing to remove oxide that can be formed on the target substrate during initial introduction or after a long idle time. The ability to switch to a lower frequency source (eg, about 27 MHz or less) allows a high self-biased DC voltage to be formed on the target 571, leading to a faster target sputtering rate. Thus, after the start process, the output of the dual VHF source assembly 597 can be varied by switching to a high frequency (about 60 MHz) source to reduce the sputtering rate and reduce the sputtered atomic ion energy. As such, potential damage to the gate dielectric layer on the substrate surface is reduced. In one example, the RF source 524 can distribute RF energy at a frequency of about 27 MHz with a power of 0 to about 2000 watts, and the second RF source 525 can have a frequency of about 40 to about 200 MHz at a frequency of about 0 to about 200 MHz. It can be distributed with RF energy with 500 watts of power.

  [0085] In one embodiment, the DC source assembly 592 may optionally be connected to the target assembly 573 to distribute one or more DC energy pulses in a plasma processing step. A DC bias may be superimposed on the VHF signal distributed from the VHF source assembly (eg, 595 and 597). The DC voltage applied to the target 571 can be used to more directly control the energy of ionized gas atoms impinging on the target 571 in the sputtering process.

  [0086] In one embodiment, as described above, during processing, RF, or VHF, bias is applied to a portion of the substrate support 562 to pull ions present in the plasma to the surface of the substrate 502. The substrate support 562 can be connected to the RF generator 523 to obtain. In one embodiment, substrate support member 562A is grounded, DC biased, or electrically floating during the plasma process to minimize ion bombardment damage of substrate 502.

Pulsed plasma treatment
[0087] FIGS. 5A-5C are for depositing sputtered material on the surface of the substrate 502 from the target 505 shown in FIG. 4A or the target 571 shown in FIG. 4B in steps 257 and / or 259 above. 2 is a diagrammatic representation of various pulsed plasma processes that may be used. The pulsed plasma process is typically a function of time, as shown in FIGS. 5A-5C, through the use of an inductive RF source assembly 591 or a VHF source assembly (ie, a VHF source assembly 595 of a dual VHF source assembly 597). As a series of continuous energy pulses distributed to the processing region 522 and a DC energy pulse distributed to the target from the DC source assembly 592. FIG. 5A illustrates a process in which RF energy 531 distributed from inductive RF source assembly 591 or VHF source assembly and DC voltage 535 distributed from DC source assembly 592 are plotted as a function of time. FIG. 5A shows a plot of RF energy 531 distributed by inductive RF source assembly 591 or VHF source assembly 595 and a plot of DC voltage 535 distributed to the target as a function of time, so that DC and RF, or FIG. 6 illustrates an embodiment in which VHF (hereinafter RF / VHF) pulses are synchronized. In this embodiment, the RF energy 531 and DC voltage 535 pulses are synchronized so that they are not applied simultaneously. In general, the DC pulse 532 provides an instantaneous attractive force to RF / VHF excited ions present in the plasma, and ions that accelerate toward the target 505 with sufficient energy cause the target to sputter a material from the plasma. The sputtered material that excites the target surface can enter the plasma formed in the processing region 522 with a pulsed RF / VHF pulse 533 and can then be ionized. Depending on whether the substrate support member 562A is RF / VHF biased, grounded, or floating, ionized sputtered atoms are distributed to the substrate surface with an energy setting by a plasma sheath generated near the substrate surface. obtain. In most cases, if a DC voltage pulse (or DC current pulse) is dispensed to ensure that the desired ion density and sputter rate can be achieved when using a low energy bias, within the processing chamber It is desirable to synchronize the end of the RF / VHF pulse 533 so that there is sufficient plasma.

  [0088] Continuing with reference to FIG. 5A, it is usually possible to generate ions with RF / VHF pulses 533 that do not have sufficient energy to sputter atoms from the target, especially in the design of inductively coupled plasma chambers. As desirable, the energy of the sputtered atoms can be more easily controlled by applying a DC bias to the target. In some cases, the use of RF / VHF pulses to ionize the sputtered target atoms to be promoted and injected into the substrate surface at low energy by using a low potential bias applied to the pedestal where the substrate is positioned. Is desirable. In one aspect, the application of a DC voltage pulse (or DC current pulse) to the target is made easier because the energy of ions generated in the plasma reduces the net increase in plasma energy due to DC energy application. Synchronized with a pulsed RF / VHF off cycle to allow it to be controlled. The DC pulse voltage can be applied at a value that provides sufficient energy to the argon ions to sputter the target material into the plasma of the doping process.

[0089] It should be noted that the system controller 602 can be used to synchronize the duty cycle with the RF / VHF pulse 533 and the DC pulse 532 to achieve the desired plasma density, sputter deposition rate, and plasma ion energy. It is. Referring to FIG. 5A, the duty cycle, which is the “on” time (t ₁ ) divided by the total period (t ₃ ) of the RF energy 531 pulse, ensures that the desired average density plasma is controlled. Note that can be optimized. Also, the duty cycle, which is the “on” time (t ₄ ) divided by the total period of the pulse of DC voltage 535 (t ₆ ), has been optimized to ensure that the desired average deposition rate is achieved. It is noted that you get.

  [0090] Referring to FIGS. 4B-4C and 5A-5C, in one embodiment, the VHF source assembly 595 is pulsed with a pulse frequency of 1-50 kHz and a duty cycle of 0.1-99%. Is set. In this configuration, a pulsed VHF source is used to generate and maintain the plasma formed in the processing region 522 while reducing the average plasma density and ion energy. The system controller 602 is used to control the energy of plasma ions and sputtered material by adjusting the duty cycle, pulse frequency, RF energy magnitude (ie, RF power), and RF energy frequency. Can do. In one embodiment, the system controller 602 is used to distribute RF energy to the coil 509 (FIG. 4A) with a duty cycle of about 1% to about 50% to distribute the low energy sputtered material to the substrate surface. Alternatively, in one embodiment, low energy sputtered material is distributed to the surface of the substrate by distributing RF energy to the target 571 (FIG. 4B) with a duty cycle of about 1% to about 50%. In some cases, the duty cycle distributed to coil 509 (FIG. 4A) or target (FIG. 4B) is kept between about 1% and about 10% to minimize the energy distributed to ions in the plasma. Is desirable.

[0091] FIG. 5B illustrates that a DC pulse 532 is distributed between at least a portion of pulsed RF energy 531 distributed from an RF source assembly 591 or a VHF source assembly (ie, a VHF source assembly 595 of a dual VHF source assembly 597). It is a figure which shows other embodiment of the pulsed plasma process. In yet another embodiment, as shown in FIG. 5C, RF energy 531 is maintained at a constant level for a period of time t ₁ and pulsed DC voltage 535 is applied to target 505 while RF energy is “on”. Distributed to. It should be noted that it is desirable to reduce the magnitude of the RF energy 531 in the DC pulse 532 to reduce any possible interference between the distributed signals. In one embodiment, an RF generator 523 (FIG. 4A) used to generate bias that attracts ions to a substrate positioned thereon at various portions of the RF / VHF plasma generation and / or pulsed DC sputtering stages of the process. It is desirable to bias the substrate support 562 using

  [0092] In other embodiments, it is desirable to pulse the RF / VHF energy so that the ions generated in the plasma do not have sufficient energy to sputter the target material. In this case, a DC bias applied to the target can be used to facilitate sputtering of the target material.

  [0093] In one embodiment, a pulsed RF / VHF signal is applied to the substrate support 562 to generate and maintain a plasma through the substrate surface. Thus, in one embodiment, the synchronized DC pulse is distributed to the target 571 and the synchronized VHF pulse is distributed to the substrate support 562 to sputter the target material into the plasma doping the gate dielectric.

Grounded collimator design
[0094] FIG. 4F shows a schematic cross-sectional view of another embodiment of a processing chamber 500 that can be used for metal plasma processing of a gate dielectric layer, ie, a low energy sputtering process for forming a doped gate dielectric layer. FIG. In this embodiment, a grounded collimator 540 is mounted between the substrate 502 and the target 505 to capture charged metal ions. The addition of a grounded collimator 540 facilitates primarily neutral sputtered atoms to reach the substrate 502, forming a thin metal layer, potentially a single monolayer, on the substrate surface. The collimator typically includes a plurality of holes 540A that are distributed across a grounded plate that allows neutral atoms and possibly some ions to pass from the processing region near the target to the substrate surface. Plate or wire mesh. Neutral atom energy is usually part of the energy required to sputter atoms from the target surface, and neutral atoms are not affected by the plasm potential, so this method can be used on the surface of the gate dielectric. Depositing such a layer usually results in very small ion bombardment damage. This metal layer can then be incorporated into the subsequently formed oxide film, so that problems associated with the implantation of metal or nitrogen ions, for example, silicon damage or metal penetration into the silicon layer underlying the substrate A high dielectric constant or “high k” dielectric layer is produced. Those skilled in the art will achieve the same function that the process chamber 501 shown in FIGS. 4B and 4C captures a large percentage of charged particles in the plasma before impacting the substrate surface to reduce damage to the gate dielectric layer. Thus, it is understood that a collimator 540 that is grounded between the target 571 and the surface of the substrate 502 may be included.

Another process chamber design
[0095] FIG. 4G is a schematic cross-section of another embodiment of a processing chamber 500 that can be used in a metal plasma treatment of a gate dielectric layer, ie, a low energy sputtering process to form a doped gate dielectric layer. FIG. In one embodiment of the processing chamber 500, the output of the inductive source assembly 591 is connected to the target 505 so that plasma can be generated in the processing region 522 through the use of the coil 509 and capacitively coupled target 505. In one embodiment, target 505 couples to the output of RF match 508A through a coil 508B that is sized to achieve resonance when power is distributed by generator 508 through RF match 508A. Referring to FIG. 4A, when the RF bias of the target 505 is applied, the coil 509 generates a plasma while the RF frequency and RF power distributed to the target 505 controls the DC bias and thus the ion energy impinging on the target 505. It becomes possible to form. In addition, the use of an inductively coupled plasma generating element that can be pulsed at a desired duty cycle and a capacitively coupled plasma generating element allows easier control of the DC bias, sputter rate, and sputter ion energy applied to the target (ie, self-bias). It becomes possible to make it. By more careful control of chamber pressure, RF frequency, RF power, duty cycle, bias applied to substrate support 562 and / or processing time, the amount of sputtered material in the dielectric layer and the concentration of sputtered material Depth can be controlled. The use of a single RF generator 508 and RF match 508A reduces chamber cost and system complexity. In one embodiment, DC source assembly 593 couples to target 505 so that DC pulses can be distributed to target 505 during or between RF pulses distributed by RF generator 508.

  [0096] In another embodiment, shown in FIG. 4H, it may be desirable to have a separate RF generator 565 and RF matching 565A that provides RF energy to the target 505, while the coil 509 has an RF generator 508 and an RF matching 508A. RF bias is applied separately depending on use. In this configuration, the new RF match 565A and RF generator 565 can be controlled separately from the inductively coupled source assembly 591 element through the use of the system controller 602. In one aspect, the DC source assembly 592 is coupled to the target 505 such that DC pulses can be distributed by the inductively coupled RF source assembly 591 and / or RF generator, or distributed to the target 505 between RF pulses.

Plasma processing system
[0097] One or more plasma processing chambers, such as FIGS. 4A-4C and 4F above, are beneficially integrated into a multi-chamber, multi-process substrate processing platform, such as the integrated processing system 600 shown in FIG. obtain. Examples of integrated processing systems that can be adapted to benefit from the present invention are described in co-assigned US Pat. No. 5,882,165 filed Mar. 16, 1999; filed Feb. 16, 1993. U.S. Pat. No. 6,440,261; U.S. Pat. No. 6,440,261 filed Aug. 27, 2002, the disclosures of which are incorporated herein in their entirety. The integrated processing system 600 may include a factory interface 604, load ports 605A-D, a system controller 602, vacuum load locks 606A, 608B, a transfer chamber 610, and a plurality of substrate processing chambers 614A-614F. One or more of the substrate processing chambers 614A-F may include a plasma such as the processing chamber 500 and / or one or more process chambers 501 used to perform the plasma processing described herein in conjunction with FIGS. 2-5 above. It may be configured as a processing chamber. In other embodiments, the integrated processing system 600 may include more than six process chambers.

  [0098] In accordance with aspects of the present invention, the integrated processing system 600 typically comprises a plurality of chambers and robots, preferably controlling and performing various processing methods and sequences performed in the integrated processing system 600. A programmed system controller 602 is provided. The system controller 602 is typically designed to facilitate control and automation of the entire system, and typically includes a central processing unit (CPU) (not shown), memory (not shown), support circuitry ( Or I / O) (not shown). The CPU is used in industrial settings to control various system functions, chamber processes and support hardware (eg, detectors, robots, motors, gas source hardware) and system and chamber processes (eg, chamber temperature, It may be one of any type of computer processor that monitors process sequence capability, chamber processing time, I / O signals, etc.). The robot 613 is centrally located in a transfer chamber 610 that transfers the substrate to one of various process chambers mounted at the position of the load lock chamber 606A or 606B to 614A-F. The robot 613 typically includes a blade assembly 613A and an arm assembly 613B that are attached to a robot drive assembly 613C. The robot 613 is adapted to transfer the substrate “W” to the various processing chambers through the use of commands sent from the system controller 602. A robot assembly that may be adapted to benefit from the present invention is a co-assigned U.S. Pat. No. 5,469,035 filed Aug. 30, 1994, entitled “Two-axis magnetically coupled robot”; U.S. Pat. No. 5,447,409 entitled “RobotAssembly” filed on Apr. 11, 2000; and 6,379,095 named “Robot For Handling Semiconductor Substrates” filed Apr. 14, 2000, The disclosure is incorporated herein in its entirety. A plurality of slit valves (not shown) are provided from the transfer chamber 610 to the process chamber 614A- so that each chamber may be evacuated separately to perform a vacuum process during the process sequence described herein. Each of 614F can be used to selectively separate.

  [0099] An important advantage of incorporating a plasma chamber into the integrated processing system 600 is that continuous process steps can be performed on the substrate without exposure to air. This allows a process such as the deposition of sputtered atoms on the surface of the substrate described above with FIGS. 2-5 to be performed without oxidizing the newly deposited extremely thin metal layer. Uncontrolled oxidation of newly deposited material prior to performing a stabilization anneal is also avoided by incorporating multiple process chambers into an integrated processing system 600 that includes a process chamber capable of performing an anneal step. The integrated system oxidizes the high-k dielectric layer 403 or the material (eg, dopant material) found in the high-k dielectric layer 404 by not exposing the substrate to ambient oxygen sources that are not present in the non-integrated process. To prevent. Thus, contamination seen in non-integrated processes can directly affect the reproducibility of device manufacturing processes and average device performance.

  [0100] In one embodiment of the integrated processing system 600, the chamber connected to the substrate processing chamber 614A or the factory interface 604 may be configured to perform the RCA cleaning described above in process step 252. Thereafter, after removal of the native oxide layer 401A (see FIG. 3A), the substrate is processed using a conventional rapid thermal oxidation (RPO) process, plasma enhanced chemical vapor deposition (PECVD) performed in the processing chamber chamber 614B. Or have a dielectric layer (eg, thermal oxide layer 402, high-k dielectric layer 404) formed thereon using ALD. The substrate processing chambers 614 and 614D are configured as plasma processing chambers similar to the processing chamber 500 and / or the process chamber 501 for performing the process steps 257 and 259, respectively. Therefore, the plasma process can be performed on the substrate in the processing chambers 614C and 714D while maintaining the substrate in a vacuum, so that the native oxide is regenerated on the various layers disposed on the substrate. It is prevented from growing. This is particularly important when the exposed layer contains a substance with a high affinity for oxygen, such as lanthanum. In one aspect, step 260 is performed sequentially on a substrate in the substrate processing chamber 614E to oxidize the metal surface formed in the substrate processing chamber 614D. In an alternative embodiment, step 262 can be performed in an RTP chamber located in the substrate processing chamber 614E. Thereafter, a plasma nitridation process (step 264), such as the DPN process available from Applied Materials, may be performed in the processing chamber 614F. In other aspects, step 266 can be performed in a substrate processing chamber 614E, or an RTP chamber located in substrate processing chamber 614F, if available.

  [0101] In other embodiments, step 252 (ie, native oxide removal step) and step 254 (ie, thermal oxide layer deposition step) can be performed in different systems. In this embodiment, substrate processing chambers 614A and 614B may be configured as a plasma processing chamber similar to processing chamber 500 and / or process chamber 501 for performing process steps 257 and 259, respectively. In one aspect, step 260 is performed sequentially on the substrate in substrate processing chamber 614C to oxidize the metal surface performed in substrate processing chamber 614B. Alternatively, in other aspects, step 262 can be performed in RTP chamber 614. A plasma nitridation process (step 264), such as the DPN process available from Applied Materials, can be performed in a processing chamber positioned within the substrate processing chamber 614D. In one aspect, step 266 can be performed in RTP chamber 614E or substrate processing chamber 614C, if available. In one aspect, after step 260 is completed in the substrate processing chamber 614C, the surface nitridation step can be performed in the substrate processing chamber 614D without being removed from the substrate vacuum and exposed to air.

Alternative method of forming a gate oxide layer
[0102] FIG. 6A is a process flow diagram illustrating a method 100 of manufacturing a gate dielectric of a field effect transistor according to one embodiment of the present invention. The method 100 includes process steps performed on a substrate in the fabrication of an exemplary CMOS field effect transistor gate structure. FIG. 6A is a diagram summarizing the complete process of method 100. At least a portion of the method 100 can be performed using a processing reactor of an integrated semiconductor substrate processing system (ie, a cluster tool). One such processing system is the CENTURA® integrated processing system available from Applied Materials, Inc., Santa Clara, California.

  [0103] FIGS. 6B-6G are schematic cross-sectional views of a series of substrates in which a gate structure is fabricated using the method of FIG. 6A. The cross-sectional views of FIGS. 6B-6G relate to individual processing steps performed to fabricate the gate dielectric in the larger gate structure (not shown) of the transistor. The images of FIGS. 6B-6G are not reduced at a constant ratio and are simplified for the sake of illustration.

[0104] Method 100 begins at step 102 and proceeds to step 118. Referring first to FIGS. 6A and 6B, in step 104, a silicon (Si) substrate 200 is prepared (eg, a 200 mm wafer, a 300 mm wafer) to remove the native oxide (SiO ₂ ) layer 204 from the substrate surface. Exposed to solution. In one embodiment, layer 204 is removed using a cleaning solution comprising hydrogen fluoride (HF) and deionized (DI) water (ie, hydrofluoric acid solution). In one embodiment, the cleaning liquid is an aqueous solution containing about 0.1 to about 10% by weight HF maintained at a temperature of about 20 ° C. to about 30 ° C. In other embodiments, the cleaning solution has about 0.5 wt% HF maintained at a temperature of about 25 ° C. At step 104, the substrate 200 can be immersed in a cleaning solution and rinsed with deionized water. Step 104 can be performed in a single substrate processing chamber or a multiple substrate batch type process chamber that can include the distribution of ultrasonic energy during the process. Alternatively, step 104 can be performed using the single substrate wet cleaning reactor of integrated processing system 600 (FIG. 7). In other embodiments, layer 204 can be removed using an RCA cleaning method. Upon completion of step 104, the substrate 200 is placed in a vacuum loadlock or nitrogen (N ₂ ) purge environment.

[0105] At step 106, a thermal oxide (SiO ₂ ) layer 206 is grown on the substrate 200 (FIG. 6C). In general, the thermal oxide layer 206 has a thickness of about 3 angstroms to about 35 angstroms. In one embodiment, the thickness of the thermal oxide layer 206 is between about 6 angstroms and about 15 angstroms. The process of depositing the thermal oxide layer at step 106 may be performed using an RTP reactor such as a RADIANCE® RTP reactor positioned on the integrated processing system 600 shown in FIG. The RADIANCE® RTP reactor is available from Applied Materials, Santa Clara, California.

[0106] In step 108, the thermal oxide layer 206 is exposed to a metal ion-containing plasma. Illustratively, step 108 forms a metal sublayer 209 of silicon metal oxide, silicate, oxynitride film on the substrate 200 (FIG. 6D). In one embodiment, a metal layer 208 having a thickness of about 1 angstrom to about 5 angstroms may be advantageously formed on the surface of the thermal oxide layer 206 at step 108. In one embodiment, the metal ion-containing plasma contains an inert gas and at least one metal ion such as hafnium or lanthanum. The inert gas contains not only argon but also one or more desired inert gases such as neon (Ne), helium (He), krypton (Kr), or xenon (Xe). In one embodiment, the metal ion-containing plasma may contain nitrogen (N ₂ ) gas.

[0107] In step 110, the thermal oxide layer 206 is exposed to an oxygen-containing plasma to oxidize the metal sublayer 209 and the metal layer 208, if applicable, and convert them to the dielectric region 210 (FIG. 6E). In other embodiments, the plasma may contain not only nitrogen (N ₂ ) but also one or more oxidizing gases such as O ₂ , NO, N ₂ O. The plasma may contain one or more inert gases such as argon (Ar), neon (Ne), helium (He), krypton (Kr), or xenon (Xe). Step 110 can be performed, for example, using a plasma nitridation (DPN) plasma reactor of integrated processing system 600 (FIG. 7).

[0108] In an alternative embodiment where step 112 is used instead of step 110, the substrate 200 is annealed at a temperature of about 800 to about 1100 ° C. Step 112 may be performed using a suitable thermal annealing chamber, such as the RADIANCE® or RTPXE ⁺ reactor of the integrated processing system 600, or a single substrate furnace or batch furnace. The thermal oxidation step 112 will form a dielectric region 210 that contains no dielectric material. In one aspect, the derivative region 210 may contain a silicate material. In one embodiment, the annealing process of step 112 may include oxygen (O ₂ ) gas at a pressure of about 800 to about 1100 ° C. and a reaction chamber pressure of about 0.1 to about 50 Torr. Performing by supplying nitric oxide (NO) at a flow rate between 2 and about 5000 sccm at a flow rate between about 100 and about 5000 sccm, and optionally supplying a gas that may be mixed with nitrogen (N ₂ ). it can. The annealing process can be performed for about 5 to about 180 seconds. In one example, oxygen (O ₂ ) is supplied at a flow rate of about 500 sccm while maintaining the chamber at a temperature of about 1000 ° C. and a pressure of about 0.1 Torr for about 15 seconds. In another example, nitrogen oxide (NO) is supplied at a flow rate of about 500 sccm while maintaining the chamber at a substrate temperature of about 1000 ° C. and a pressure of about 0.5 Torr for about 15 seconds.

[0109] In step 114, a nitride layer 214 is formed to increase the amount of nitrogen on the top surface of the structure formed by exposing the surface of the substrate 200 to nitrogen plasma (FIG. 6F). A process can be formed using a DPN reactor by supplying nitrogen (N ₂ ) at a substrate pedestal temperature of about 10-2000 sccm, a substrate pedestal temperature of about 20-5000 ° C., and a reaction chamber pressure of about 5-1000 mTorr. Radio frequency (RF) plasma is excited at, for example, 13.56 MHz using a continuous wave (CW) or pulsed plasma power source up to about 3-5 kW. During the pulse, peak RF power, frequency, and duty cycle are typically selected in the range of about 10-3000 W, about 2-100 kHz, and 2-100%, respectively. This process should take about 1-180 seconds. In one embodiment, N ₂ is supplied at about 200 sccm and a peak RF power of about 1000 W is pulsed at about 10 kHz with a duty cycle of about 5%, at a temperature of about 25 ° C. and a pressure of about 100-80 mTorr. Apply to inductive plasma source for 15-180 seconds. The plasma can be produced using a quasi-remote plasma source, an inductive plasma source, or a radial line slot antenna (RLSA) source, among other plasma sources. In an alternative embodiment, a CW source and / or pulsed microwave power can be used to form the nitride layer 214. The nitride layer 214 may be formed on the top surface of the dielectric region 210 (FIG. 6E).

[0110] In step 116, the gate dielectric layers 206, 214, 209 and the substrate 200 are annealed. Step 116 not only improves the reduction of leakage current in layers 206, 214, 209 and increases the mobility of charge carriers in the channel region under the silicon dioxide (SiO ₂ ) sublayer 216, but also the gate dielectric. Improve overall reliability. Step 116 may be performed using a suitable thermal annealing chamber such as the RADIANCE® or RTPXE ⁺ reactor of the integrated processing system 300 or a single substrate furnace or batch furnace. By the thermal oxidation step 116, a silicon dioxide (SiO ₂ ) sublayer 216 is formed and formed on the silicon dielectric film junction (FIG. 6G). Step 116 not only increases the charge carrier mobility in the channel region under the silicon dioxide (SiO ₂ ) sublayer 216 but also improves the reliability of the dielectric / silicon junction.

[0111] In one embodiment, while maintaining a substrate surface temperature of about 800-1100 ° C. and a reaction chamber pressure of about 0.1-50 Torr, the annealing process of step 116 comprises about 2-5000 sccm of oxygen ( O ₂ ) and at least one of about 100-5000 sccm of nitric oxide (NO), and optionally by supplying a gas that may be mixed with nitrogen (N ₂ ). The process can be performed for about 5-180 seconds. In one example, oxygen (O ₂ ) is supplied at about 500 sccm while maintaining the chamber at a temperature of about 1000 ° C. and a pressure of about 0.1 Torr for about 15 seconds.

  [0112] After completion of step 116, the method 100 ends at step 118. In the manufacture of integrated circuits, the method 100 advantageously forms an extremely thin gate dielectric with improved leakage current reduction and increases charge carrier mobility in the channel region.

  [0113] While the above is directed to embodiments of the invention, many other embodiments of the invention may be made without departing from the basic scope of the invention, which is covered by the following patents: Determined by the claims.

FIG. 1A (prior art) is a schematic cross-sectional view of a FET, which can be fabricated in accordance with the present invention. FIG. 1B (prior art) is a graph showing nitrogen concentration profiles for a conventional thermal nitridation process and a conventional plasma nitridation process based on a secondary ion mass spectrometer. FIG. 2A is a process flow diagram illustrating a method for fabricating a gate dielectric of a field effect transistor according to one embodiment of the present invention. FIG. 2B is a process flow diagram illustrating a method for fabricating a gate dielectric of a field effect transistor according to one embodiment of the present invention. FIG. 2C is a process flow diagram illustrating a method for fabricating a gate dielectric of a field effect transistor according to one embodiment of the present invention. FIG. 2D is a process flow diagram illustrating a method for fabricating a gate dielectric of a field effect transistor according to one embodiment of the present invention. FIG. 2E is a process flow diagram illustrating a method for fabricating a gate dielectric of a field effect transistor according to one embodiment of the present invention. FIG. 2F is a process flow diagram illustrating a method for fabricating a gate dielectric of a field effect transistor according to one embodiment of the present invention. FIG. 3A shows a series of schematic cross-sectional views of a substrate in which a gate structure is manufactured using the method of FIG. 2A. FIG. 3B shows a series of schematic cross-sectional views of a substrate in which a gate structure is manufactured using the method of FIG. 2A. FIG. 3C shows a series of schematic cross-sectional views of a substrate in which a gate structure is manufactured using the method of FIG. 2A. FIG. 3D shows a series of schematic cross-sectional views of a substrate where the gate structure is manufactured using the method of FIG. 2A. FIG. 3E shows a series of schematic cross-sectional views of a substrate in which a gate structure is manufactured using the method of FIG. 2A. FIG. 3F shows a series of schematic cross-sectional views of a substrate in which the gate structure is manufactured using the method of FIG. 2A. FIG. 4A is a schematic cross-sectional view illustrating a plasma processing chamber according to another embodiment of the present invention. FIG. 4B is a schematic cross-sectional view illustrating a plasma processing chamber according to another embodiment of the present invention. FIG. 4C is a schematic cross-sectional view illustrating a plasma processing chamber according to another embodiment of the present invention. FIG. 4D is a theoretical calculation table showing various characteristics of the hafnium and lanthanum targets of one embodiment of the present invention. FIG. 4E is a graph of self-bias voltage and frequency for a capacitively coupled plasma processing chamber according to one embodiment of the present invention. FIG. 4F is a schematic cross-sectional view of a plasma processing chamber according to an embodiment of the present invention. FIG. 4G is a schematic cross-sectional view of a plasma processing chamber according to one embodiment of the present invention. FIG. 4H is a schematic cross-sectional view of a plasma processing chamber according to an embodiment of the present invention. FIG. 5A is a diagram illustrating off-cycle timing of pulsed RF / VHF excitation energy and pulsed DC voltage applied to a target according to another embodiment of the present invention. FIG. 5B is a diagram illustrating off-cycle timing of pulsed RF / VHF excitation energy and pulsed DC voltage applied to a target according to another embodiment of the present invention. FIG. 5C is a diagram illustrating off-cycle timing of a pulsed DC voltage pulse and RF / VHF excitation energy applied to a target according to another embodiment of the present invention. FIG. 6A is a process flow diagram illustrating a method 100 for fabricating a gate dielectric of a field effect transistor according to one embodiment of the present invention. FIG. 6B shows a series of schematic cross-sectional views of a substrate where the gate structure is manufactured using the method of FIG. 6A. FIG. 6C shows a series of schematic cross-sectional views of a substrate where the gate structure is manufactured using the method of FIG. 6A. 6D shows a series of schematic cross-sectional views of a substrate where the gate structure is manufactured using the method of FIG. 6A. FIG. 6E shows a series of schematic cross-sectional views of a substrate where the gate structure is manufactured using the method of FIG. 6A. 6F shows a series of schematic cross-sectional views of a substrate where the gate structure is manufactured using the method of FIG. 6A. FIG. 6G shows a series of schematic cross-sectional views of a substrate in which a gate structure is manufactured using the method of FIG. 6A. FIG. 7 is a diagram showing an integrated processing system according to an embodiment of the present invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Field effect transistor, 12 ... Substrate, 13 ... Source / drain junction 14 ... Gate dielectric layer, 16 ... Gate electrode, 18 ... Side wall spacer, 200 ... Substrate, 204 ... layer, 206 ... Thermal oxide layer, 208 ... Metal layer, 209 ... Metal sublayer, 210 ... Dielectric region, 214 ... Nitride layer, 401 ... Substrate, 401A ... Natural oxide layer, 401B ... Cleaned surface, 402 ... Thermal oxide layer, 403 ... High-k dielectric Layer, 404 ... high-k dielectric layer, 405 ... termination region, 407 ... thin metal layer, 500 ... processing chamber, 501 ... process chamber, 502 ... substrate, 504 ... electrical feedthrough, 505 ... target, 506 ... coaxial cable 507 ... DC power supply, 508 ... RF generator, 509 ... coil, 510 ... vacuum pump, 511 ... throttle valve, 522 ... processing area 523 ... RF generator, 524 ... RF source, 525 ... RF generator, 526 ... RF stitch, 527 ... chamber base, 528 ... chamber wall, 529 ... chamber lid, 531 ... RF energy, 532 ... DC pulse, 533 ... RF / VHF pulse, 535 ... DC voltage, 540 ... collimator, 540A ... hole, 550 ... gas distribution system, 561 ... temperature controller, 562 ... substrate support, 562A ... substrate support member, 571 ... target, 572 ... electric insulator, 573 ... target assembly, 591 ... inductive RF source, 592 ... DC source assembly, 593 ... process chamber assembly, 594 ... substrate support assembly, 595 ... VHF source assembly, 596 ... process chamber assembly, 597 ... VHF source assembly Buri, 600 ... Integrated processing system, 602 ... System controller, 604 ... Factory interface, 605A-D ... Load port, 606A ... Load lock chamber, 606B ... Load lock chamber, 610 ... Transfer chamber, 613 ... Robot, 614A-614F ... Substrate processing chamber, 571... Target.

Claims (6)

A method of forming a semiconductor device comprising:
Forming a dielectric layer having a desired thickness on the surface of the substrate;
Forming a first material concentration gradient within at least a portion of the thickness of the dielectric layer using a low energy sputtering process;
The low energy sputtering process comprises:
Pulsing RF energy with a first RF frequency and a first RF power into a processing region of a low energy sputtering chamber using an RF generator;
Pulsing a DC voltage distributed from a DC source assembly to a target disposed within the processing region;
Synchronizing the pulsed RF energy and the pulsed DC voltage so that the amount of the first material removed from the target can be disposed in the dielectric layer;
Exposing the dielectric layer and the first material to an RF plasma comprising nitrogen;
Depositing a second material on the dielectric layer;
Including a method.   The method of claim 1, wherein the first material is selected from the group consisting of zirconium, hafnium, lanthanum, strontium, lead, yttrium, and barium.   The method of claim 1, wherein the dielectric layer contains a material selected from the group consisting of silicon dioxide, hafnium oxide, zirconium oxide, hafnium silicate oxide, lanthanum oxide, and aluminum oxide. Placing an amount of a third material in the dielectric layer prior to exposing the dielectric layer to an RF plasma comprising nitrogen, the third material comprising hafnium, lanthanum, aluminum, titanium, zirconium, strontium contains lead, yttrium, and an element selected from the group consisting of barium, further comprising a step, the method according to claim 1. The dielectric material layer and said first material and said third material comprising the steps of exposing the oxidizing environment, the oxidative environment uses a thermal oxidation process or a plasma oxidation process, further comprising the steps of claim 4 Method.   The second material is a material selected from the group consisting of polycrystalline silicon, tantalum, tantalum nitride, tantalum carbide, tungsten, tungsten nitride, silicon tantalum nitride, hafnium, aluminum, ruthenium, cobalt, titanium, nickel, and titanium nitride. The method of Claim 1 containing.

Images