TW202412219A - 半導體封裝 - Google Patents
半導體封裝 Download PDFInfo
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- TW202412219A TW202412219A TW112130400A TW112130400A TW202412219A TW 202412219 A TW202412219 A TW 202412219A TW 112130400 A TW112130400 A TW 112130400A TW 112130400 A TW112130400 A TW 112130400A TW 202412219 A TW202412219 A TW 202412219A
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- semiconductor
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- pad
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 329
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Abstract
一種半導體封裝包括:第一半導體晶片,包括第一半導體層、第一貫穿電極及第一接合接墊,第一貫穿電極在垂直方向上穿過第一半導體層,第一接合接墊連接至第一貫穿電極;以及第二半導體晶片,包括第二半導體層、配線結構、配線接墊及第二接合接墊,第二半導體層位於第一半導體晶片上,配線結構位於第二半導體層與第一半導體晶片之間,配線接墊在配線結構下方連接至配線結構,第二接合接墊在配線接墊下方連接至配線接墊且與第一接合接墊接觸,其中第二接合接墊包括朝向配線接墊突出的突出部。
Description
本發明概念的態樣是有關於一種半導體封裝及其製造方法。
[相關申請案的交叉參考]
本申請案主張優先於2022年8月31日在韓國智慧財產局提出申請的韓國專利申請案第10-2022-0109983號,所述韓國專利申請案的揭露內容全文併入本案供參考。
根據半導體封裝的小型化及高效能的趨勢,正在開發在一個封裝中嵌入實行不同功能的多個半導體晶片的系統級封裝(system-in-package,SiP)技術。為在封裝內形成連接半導體晶片的精細配線,已利用形成矽穿孔(through silicon via,TSV)以及經由接合接墊將半導體晶片彼此接合的技術。
本發明概念的態樣是提供一種可靠性改善的半導體封裝及其製造方法。
根據本發明概念的態樣,一種半導體封裝包括:第一半導體晶片,包括第一半導體層、第一貫穿電極及第一接合接墊,第一貫穿電極在垂直方向上穿過第一半導體層,第一接合接墊連接至第一貫穿電極;以及第二半導體晶片,包括第二半導體層、配線結構、配線接墊及第二接合接墊,第二半導體晶片設置於第一半導體晶片上,配線結構位於第二半導體層與第一半導體晶片之間,配線接墊在配線結構下方連接至配線結構,第二接合接墊連接至配線接墊且設置於配線接墊下方,第二接合接墊與第一接合接墊接觸。第二接合接墊包括頂部部分及突出部,突出部自頂部部分突出至配線接墊中。
根據本發明概念的另一態樣,一種半導體封裝包括:第一半導體晶片;以及多個第二半導體晶片,垂直地堆疊於第一半導體晶片上。所述多個第二半導體晶片中的每一者包括:半導體層,具有後表面及與後表面相對的前表面;後接合接墊,位於半導體層的後表面上;貫穿電極,穿過半導體層且連接至後接合接墊;電晶體,位於半導體層的前表面上;前接合接墊,位於半導體層的前表面上;配線結構,將貫穿電極連接至電晶體且形成於前表面與前接合接墊之間;以及配線接墊,位於配線結構與前接合接墊之間。前接合接墊具有頂表面且包括自頂表面延伸至配線接墊中的突出部。
根據本發明概念的另一態樣,一種半導體封裝包括第一結構以及位於第一結構上的第二結構,其中第一結構包括:第一半導體層,具有彼此相對的第一前表面與第一後表面;第一裝置層,位於第一半導體層的第一前表面上且包括第一配線結構;第一貫穿電極,穿過第一半導體層且連接至第一裝置層的第一配線結構;以及第一接合結構,包括第一接合接墊及第一接合絕緣層,第一接合接墊位於第一半導體層的第一後表面上且連接至第一貫穿電極,第一接合絕緣層位於第一接合接墊的側表面上,且第二結構包括:第二半導體層,具有彼此相對的第二前表面與第二後表面;第二裝置層,位於第二半導體層的第二前表面上且包括第二配線結構;以及第二接合結構,包括第二接合接墊及第二接合絕緣層,第二接合接墊位於第二裝置層下方且被接合成與第一接合接墊接觸,第二接合絕緣層被接合成與第一接合絕緣層接觸,其中第二接合接墊包括中心區及環繞中心區的外部區,且中心區的上端部的高度低於外部區的上端部的高度。
根據本發明概念的另一態樣,一種製造半導體封裝的方法包括:形成第一結構,所述第一結構包括第一半導體層、在垂直方向上穿過第一半導體層的第一貫穿電極、連接至第一貫穿電極的第一接合接墊以及環繞第一接合接墊的第一接合絕緣層;形成第二半導體層、位於第二半導體層上的配線結構、位於配線結構上的配線接墊以及位於配線接墊上的第二接合絕緣層;形成穿過第二接合絕緣層的開口以暴露出配線接墊;移除配線接墊的一部分並形成配線接墊的凹陷部分;藉由在開口及凹陷部分中形成第二接合接墊來形成第二結構;以及對第一結構與第二結構進行接合,使得第一接合接墊與第二接合接墊彼此接觸且使第一接合絕緣層與第二接合絕緣層彼此接觸。
在下文中,將參照附圖對本發明概念實例性實施例進行闡述。
圖1是示出根據本發明概念實例性實施例的半導體封裝的剖視圖。
圖2A是示出根據本發明概念實例性實施例的半導體封裝的部分放大圖。圖2A是圖1中的區「A」的放大圖。圖2B是示出根據本發明概念實例性實施例的半導體封裝的平面圖。圖2B是僅示意性地示出作為根據實例性實施例的半導體封裝的主要組件的配線接墊243及前接合接墊245的圖。
參照圖1、圖2A及圖2B,根據實例性實施例的半導體封裝1000可包括第一半導體晶片100以及多個第二半導體晶片200A、200B、200C及200D。所述多個第二半導體晶片200A、200B、200C及200D可在垂直方向(Z軸方向)上堆疊。根據實施例,可以較圖式中所示的數目更大或更小的數目提供所述多個第二半導體晶片200A、200B、200C及200D。舉例而言,根據本發明概念的半導體封裝可包括三個或少於三個或者五個或多於五個第二半導體晶片。
在垂直方向(Z軸方向)上堆疊的第一半導體晶片100與所述多個第二半導體晶片200A、200B、200C及200D可經由第一貫穿電極132及第二貫穿電極232進行電性連接。第一半導體晶片100以及所述多個第二半導體晶片200A、200B、200C及200D可具有其中自相應的半導體晶片的上表面及下表面暴露出的元件在不存在單獨的連接構件(例如,金屬柱、焊料凸塊等)的條件下直接接合(例如,此可被稱為混合接合或直接接合)的結構。舉例而言,可在第一半導體晶片100與所述多個第二半導體晶片200A、200B、200C及200D之中的最下部的第二半導體晶片200A之間的介面處形成介電質對介電質接合及/或銅對銅接合,且亦可在所述多個第二半導體晶片200A、200B、200C及200D中的相鄰半導體晶片之間形成介電質對介電質接合及/或銅對銅接合。
如圖2A中所示,下部的第二半導體晶片(例如,200A)的後接合絕緣層221及後接合接墊225可接合且耦合至上部的第二半導體晶片(例如,200B)的前接合絕緣層241及前接合接墊245。為易於說明,本文中可能使用例如「在…之下(beneath)」、「在…下方(below)」、「下部的(lower)」、「上方(above)」、「上部的(upper)」、「頂部的(top)」、「底部的(bottom)」、「前部的(front)」、「後部的(rear)」及類似用語等空間相對性用語來闡述圖中所示出的一個元件或特徵與另一(其些)元件或特徵的關係。應理解,除非上下文另有清楚的指示,否則除圖中所繪示的定向以外,空間相對性用語亦旨在囊括裝置在使用或操作中的不同定向。舉例而言,若圖中裝置被翻轉,則被闡述為在其他元件或特徵「下方」或「之下」的元件此時將被定向為在其他元件或特徵「上方」。因此,用語「位於…下方」可囊括上方及下方兩種定向。裝置可具有其他定向(旋轉90度或處於其他定向),且本文中所使用的空間相對性描述語可相應地進行解釋。序數(例如,「第一」、「第二」、「第三」等)可簡單地用作某些元件、步驟等的標籤,以將此些元件、步驟等彼此區分開。在說明書中,未使用「第一」、「第二」等闡述的用語在申請專利範圍中仍可被稱為「第一」或「第二」。另外,使用特定序數(例如,特定申請專利範圍中的「第一」)引用的用語可在別處使用不同的序數(例如,說明書或另一申請專利範圍中的「第二」)進行闡述。
在下文中,將詳細地對根據實例性實施例的半導體封裝1000的組件進行闡述。
第一半導體晶片100包括:第一半導體層101,具有彼此相對(例如,對立)的第一前表面101S1與第一後表面101S2;第一裝置層110,位於第一前表面101S1上;第一後表面結構120,位於第一後表面101S2上;以及第一貫穿結構130。第一半導體晶片100可為在第一裝置層110中包括多個邏輯裝置及/或記憶體裝置的緩衝晶片或控制晶片。第一半導體晶片100可自堆疊於第一半導體晶片100上的所述多個第二半導體晶片200A、200B、200C及200D向外部(例如,半導體封裝1000的外部)傳輸訊號且亦可自外部向所述多個第二半導體晶片200A、200B、200C及200D傳輸訊號及功率。
第一半導體層101可包含例如半導體元素(例如,矽(Si)或鍺(Ge))或化合物半導體(例如,碳化矽(SiC)、砷化鎵(GaAs)、砷化銦(InAs)或磷化銦(InP))或者例如由所述半導體元素或所述化合物半導體形成。第一半導體層101可具有絕緣體上矽(silicon-on-insulator,SOI)結構。第一半導體層101可包括主動區,例如摻雜有雜質的阱或摻雜有雜質的結構。第一半導體層101可包括各種裝置隔離結構,例如淺溝槽隔離(shallow trench isolation,STI)結構。第一半導體層101可具有有效表面及與有效表面相對定位的非有效表面,所述有效表面具有主動區。第一前表面101S1可為有效表面,而第一後表面101S2可為非有效表面。
第一裝置層110可包括第一半導體層101的第一積體電路(integrated circuit,IC)。第一IC可包括用於傳輸位址命令或控制命令的電路(例如,輸入/輸出(input/output,I/O)電路),使得所述多個第二半導體晶片200A、200B、200C及200D可儲存或輸出資料。舉例而言,根據實施例,IC可藉由邏輯裝置及記憶體裝置來實行邏輯功能及記憶體功能,但亦可僅包括邏輯裝置且僅實行邏輯功能。
第一裝置層110可包括各種類型的各別裝置。所述各別裝置可設置於第一半導體層101的第一前表面101S1的主動區上且可包括各種主動裝置及/或被動裝置。第一裝置層110可包括第一配線結構112,第一配線結構112將覆蓋所述各別裝置的第一層間絕緣層111與所述各別裝置彼此連接、將所述各別裝置連接至第一半導體層101的主動區或者將所述各別裝置連接至連接凸塊140。第一層間絕緣層111可包含氧化矽、氮化矽、氮氧化矽或正矽酸四乙酯(tetraethylorthosilicate,TEOS)或者由氧化矽、氮化矽、氮氧化矽或TEOS形成。第一層間絕緣層111可包括多個層。第一配線結構112可包含包括例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金等的金屬材料或者由所述金屬材料形成。第一配線結構112可具有包括配線圖案及通孔的多層式結構。在第一裝置層110與第一半導體層101之間可設置有絕緣保護膜(未示出),以將第一配線結構112與第一半導體層101電性分隔開。
連接凸塊140可設置於第一裝置層110下方。除用於與所述多個第二半導體晶片200A、200B、200C及200D進行連通的凸塊以外,連接凸塊140亦可包括用於與外部裝置(例如,圖11中的「800」)進行連通的凸塊。連接凸塊140可包含低熔點金屬或包括錫(Sn)的合金(例如,Sn-Ag-Cu)或者由低熔點金屬或包括錫(Sn)的合金形成。連接凸塊140可為例如焊料球。連接凸塊140中的每一者可具有平台形狀、球形狀或引腳形狀。連接凸塊140中的每一者可被形成為多層或單層。
第一後表面結構120可設置於第一半導體層101的第一後表面101S2上(例如,非有效表面上)。第一後表面結構120可包括連接至第一貫穿電極132的第一接合接墊125以及位於第一接合接墊125的側表面上的第一接合絕緣層121。第一接合接墊125及第一接合絕緣層121可被直接接合至所述多個第二半導體晶片200A、200B、200C及200D之中的最下部的第二半導體晶片200A。第一接合絕緣層121可由氧化矽、氮化矽、碳氮化矽(silicon carbonitride)及碳氮氧化矽中的任一者形成。第一接合絕緣層121可具有多層式結構。在本說明書中,第一後表面結構120可被稱為「第一接合結構」。
第一貫穿結構130可在垂直方向(Z軸方向)上穿過第一半導體層101且提供將第一配線結構112與第一接合接墊125彼此連接的電性路徑。第一貫穿結構130可包括第一間隔件131及第一貫穿電極132。第一貫穿電極132可包括導電插塞及環繞導電插塞的障壁層,且此結構可與以下更詳細地闡述的圖2所示第二貫穿電極232的結構相同或相似。
所述多個第二半導體晶片200A、200B、200C及200D可設置於第一半導體晶片100上。所述多個第二半導體晶片200A、200B、200C及200D中的每一者包括:第二半導體層201,具有彼此相對的第二前表面201S1與第二後表面201S2;第二裝置層210,位於第二前表面201S1上;第二前結構240(例如,第二前表面結構),設置於第二裝置層210下方;第二後結構220(例如,第二後表面結構),位於第二半導體層201的第二後表面201S2上;以及第二貫穿結構230。由於所述多個第二半導體晶片200A、200B、200C及200D可具有實質上相同或相似的結構,因此將主要對底部處的第二半導體晶片200A進行闡述,且將不再對用於相同組件的參考編號及冗餘說明予以贅述。然而,不同於其他的第二半導體晶片200A、200B及200C,最上部的第二半導體晶片200D可不包括第二貫穿結構230。另外,第二半導體層201、第二裝置層210及第二貫穿結構230具有與第一半導體晶片100的第一半導體層101、第一裝置層110及第一貫穿結構130的特性相同或相似的特性,將不再對其冗餘說明予以贅述。
第二半導體層201的第二前表面201S1可為具有主動區的有效表面,而第二半導體層201的第二後表面201S2可為與有效表面相對地定位的非有效表面。第二半導體層201可包含與第一半導體層101的材料相同或相似的材料。第二半導體層201可具有較第一半導體層101小的大小(例如,面積及/或厚度),但並非僅限於此。
第二裝置層210可包括電晶體202、裝置隔離層204、第二層間絕緣層205及第二配線結構206。
第二裝置層210可包括第二IC,第二IC包括設置於第二半導體層201的第二前表面201S1(例如,有效表面)上的電晶體202。第二IC可包括基於自第一半導體晶片100接收的位址命令及控制命令來儲存或輸出資料的記憶體裝置。舉例而言,記憶體裝置可包括例如動態隨機存取記憶體(dynamic random access memory,DRAM)及靜態隨機存取記憶體(static random access memory,SRAM)等揮發性記憶體裝置或者例如相變隨機存取記憶體(phase-change random access memory,PRAM)、磁性隨機存取記憶體(magnetic random access memory,MRAM)、鐵電隨機存取記憶體(ferroelectric random access memory,FeRAM)及電阻式隨機存取記憶體(resistive random access memory,RRAM)等非揮發性記憶體裝置。在此種情形中,可在高頻寬記憶體(high bandwidth memory,HBM)產品或電子資料處理(electro data processing,EDP)產品中使用根據實例性實施例的半導體封裝。
如圖2A中所示,電晶體202中的每一者可包括閘極電極202g、閘極介電層202d及雜質區202a。雜質區202a可為例如摻雜有雜質的阱或摻雜有雜質的結構。雜質區202a可用作例如電晶體202的源極區或汲極區。閘極介電層202d可設置於閘極電極202g與第二半導體層201的主動區之間。主動區可由第二半導體層201中的裝置隔離層204界定。裝置隔離層204可藉由淺溝槽隔離(STI)製程形成。閘極間隔件203設置於閘極電極202g的兩側上,且閘極間隔件203可將閘極電極202g與雜質區202a電性絕緣。電晶體202可經由第二配線結構206電性連接至第二貫穿電極232及前接合接墊245。舉例而言,雜質區202a可連接至第二配線結構206且電性連接至第二貫穿電極232。
第二層間絕緣層205可覆蓋電晶體202及第二配線結構206。第二層間絕緣層205可包含例如氧化矽、氮化矽、氮氧化矽或正矽酸四乙酯(TEOS)或者由氧化矽、氮化矽、氮氧化矽或TEOS形成。
第二前結構240可設置於第二裝置層210下方。第二前結構240可包括配線接墊243以及前接合絕緣層241,配線接墊243在第二配線結構206下方連接至第二配線結構206,前接合絕緣層241覆蓋配線接墊243及前接合接墊245。在本說明書中,第二前結構240可被稱為「第二接合結構」或「前接合結構」。
配線接墊243可設置於前接合接墊245與第二配線結構206的配線圖案206L的最下部的配線圖案之間。配線接墊243可連接至第二配線結構206的插塞或通孔206P,且可具有較第二配線結構206的每一配線圖案206L的厚度大的厚度。配線接墊243可由銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金形成。配線接墊243可包含與第二配線結構206的材料及前接合接墊245的材料不同的材料。舉例而言,配線接墊243可包含第二配線結構206或前接合接墊245中所不包含的鋁(Al)或鋁(A1)合金。
在根據實例性實施例的半導體封裝1000中,第二前結構240可更包括鈍化層244,鈍化層244覆蓋位於第二裝置層210下方的配線接墊243的側表面及底表面。鈍化層244可包含絕緣材料(例如,氮化矽(SiN)、碳化矽(SiC)、氮氧化矽(SiON)、碳氮化矽(SiCN)、氮化鋁(AlN)、氮氧化鋁(AlON)、氧化鋁(AlO)或碳氧化鋁(AlOC)中的一者)或者由所述絕緣材料形成。
前接合接墊245可設置於第二半導體層201的第二前表面201S1上。前接合接墊245可接合至前接合接墊245下方的後接合接墊225或第一接合接墊12以形成接合介面IF的一部分。在本說明書中,前接合接墊245可被稱為「第二接合接墊」。應理解,當一元件被稱為「連接」或「耦合」至另一元件或「位於另一元件上」時,所述元件可直接連接或耦合至所述另一元件或位於所述另一元件上或者可存在中間元件。相反地,當一元件被稱為「直接連接」或「直接耦合」至另一元件、或者被稱為與另一元件「接觸(contacting或in contact with)」(或使用詞語「接觸(contact)」的任何形式)、或者被稱為「接合至(bonded to)」另一元件時,在接觸點處不存在中間元件。用於闡述元件之間關係的其他詞語應以類似的方式進行解釋(例如,「位於...之間(between)」相對於「直接位於...之間(directly between)」、「相鄰(adjacent)」相對於「直接相鄰(directly adjacent)」等)。
前接合接墊245可穿過前接合絕緣層241及鈍化層244以與配線接墊243接觸。在實例性實施例中,前接合接墊245可具有隨著前接合接墊245的寬度在朝向配線接墊243的方向上減小而傾斜的側表面,但根據實施例,前接合接墊245可具有實質上相同的寬度且可具有與第二半導體層201的第二後表面201S2垂直的垂直側表面。
前接合接墊245的上表面可與配線接墊243的下表面接觸。前接合接墊245的上表面的寬度(或例如來自平面圖的平面面積)可小於配線接墊243的下表面的寬度(或平面面積)。前接合接墊245的整個上表面可與配線接墊243的下表面交疊。參照圖2B,在平面圖中,前接合接墊245可具有設置於配線接墊243內的圓形形狀或橢圓形形狀。
在實例性實施例中,前接合接墊245可包括朝向配線接墊243突出的突出部245P。突出部245P亦可被闡述為隆起(ridge)或唇(lip)。突出部245P可自前接合接墊245的頂部部分或頂表面突出或延伸。突出部245P可延伸至配線接墊243中。舉例而言,配線接墊243可包括藉由突出部245P而凹陷的凹陷部分,且配線接墊243可覆蓋突出部245P。在實例性實施例中,突出部245P可在Z方向上相對於前接合接墊245的中心軸具有對稱形狀。前接合接墊245可具有上表面,所述上表面包括作為突出部245P的表面的第一表面及自第一表面延伸的第二表面。因此,當自平面圖觀察時,前接合接墊245的與配線接墊243接觸的上表面的表面積可大於由前接合接墊245的同一上表面佔據的平面面積。
前接合接墊245在前接合接墊245的頂表面處的在水平方向上的平均寬度可介於例如約1微米至約20微米的範圍內。突出部245P的寬度(在水平方向上)及厚度(在垂直方向上)中的每一者可介於例如約0.1微米至約5微米的範圍內。前接合接墊245在其頂表面處的在水平方向上的寬度可為例如突出部245P的在水平方向上的寬度的4倍至20倍之間,且可為例如突出部245P的在垂直方向上的厚度的4倍至20倍之間。在一些實施例中,突出部245P的在垂直方向上的厚度可為突出部245P的在水平方向上的寬度的0倍至2倍之間。
參照圖2B,前接合接墊245可包括中心區245C及環繞中心區245C的外部區245O。突出部245P可位於外部區245O中。突出部245P可為外部區245O的位於較中心區245C的上表面的垂直水平高的垂直水平處的至少部分。中心區245C的上端部的高度可低於外部區245O的上端部的高度。在實例性實施例中,突出部245P可位於整個外部區245O上。在此種情形中,突出部245P可具有沿著外部區245O一體地延伸的環形形狀或環形狀。在實例性實施例中,突出部245P可沿著前接合接墊245的側表面延伸。
根據本發明概念實例性實施例,前接合接墊245與配線接墊243之間的接觸面積可由於前接合接墊245的結構具有突出部245P而相對增大。由於接觸面積的增大,前接合接墊245與配線接墊243之間的黏附性可得到改善及/或熱傳遞特性可得到改善,使得可提供可靠性改善的半導體封裝。具體而言,當前接合接墊245與配線接墊243包含不同的材料時,可顯著地改善由於介面剝離而引起的缺陷。另外,藉由將突出部245P形成為相對於中心軸具有對稱形狀,可防止由於在特定方向上發生介面剝離而引起的缺陷。
前接合接墊245可包括障壁層245a及導電層245b。在實例性實施例中,障壁層245a可覆蓋導電層245b的側表面及上表面。在實例性實施例中,障壁層245a可被設置成在突出部245P內具有共形厚度。障壁層245a可包含金屬化合物(例如,氮化鈦(TiN)、氮化鉭(TaN)或氮化鎢(WN))或者可由所述金屬化合物形成。導電層245b可包含金屬材料(例如,鎢(W)、鈦(Ti)、鋁(Al)或銅(Cu))或者由所述金屬材料形成。導電層245b可為例如銅(Cu)。
前接合絕緣層241可覆蓋配線接墊243及位於第二裝置層210下方的鈍化層244,且可環繞前接合接墊245的側表面。前接合絕緣層241的下表面與前接合接墊245的下表面一起形成接合介面IF,且可與前接合接墊245的下表面實質上共面。前接合絕緣層241可由氧化矽、氮化矽、碳氮化矽及碳氮氧化矽之中的不同的材料形成。在本說明書中,儘管可使用其他用語,但前接合絕緣層241亦可被稱為「第二接合絕緣層」。當指代定向、佈局、位置、形狀、大小、成分、數量或其他量度時,本文中使用的例如「相同」、「相等」、「平的」或「共面」等用語未必意指完全等同的定向、佈局、位置、形狀、大小、成分、數量或其他量度,而是旨在囊括在例如由於製造製程而可能出現的可接受的變化範圍內的幾乎等同的定向、佈局、位置、形狀、大小、成分、數量或其他量度。除非上下文或其他陳述另外指明,否則用語「實質上」在本文中可用來強調此種含義。舉例而言,被闡述為「實質上相同」、「實質上相等」或「實質上共面」的用語可為完全相同、完全相等或完全共面的,或者可在例如由於製造製程而可能出現的可接受的變化範圍內為相同、相等或共面的。
第二後結構220可包括後接合接墊225及後接合絕緣層221,後接合接墊225位於第二半導體層201的第二後表面201S2上,後接合絕緣層221覆蓋第二半導體層201的第二後表面201S2且覆蓋後接合接墊225。在本說明書中,儘管可使用其他用語,但第二後結構220亦可被稱為「第一接合結構」或「後接合結構」。
後接合接墊225可與第二半導體層201的第二貫穿電極232接觸。後接合接墊225可接合至後接合接墊225上的前接合接墊245以形成接合介面IF的一部分。在本說明書中,儘管可使用其他用語,但後接合接墊225亦可被稱為「第一接合接墊」。
根據實施例,後接合接墊225可具有寬度朝向接合介面IF增大的傾斜的側表面,但亦可具有實質上相同的寬度且具有與接合介面IF垂直的垂直側表面。
後接合接墊225可包括障壁層225a及導電層225b。在實例性實施例中,障壁層225a可覆蓋導電層225b的側表面及下表面。障壁層225a可包含金屬化合物(例如,氮化鈦(TiN)、氮化鉭(TaN)或氮化鎢(WN))或者由所述金屬化合物形成。導電層225b可包含金屬材料,例如鎢(W)、鈦(Ti)、鋁(Al)或銅(Cu)。導電層245b可為例如銅(Cu)。
後接合絕緣層221的上表面可與後接合接墊225的上表面形成接合介面IF,且可與後接合接墊225的上表面實質上共面。後接合絕緣層221可由氧化矽、氮化矽、碳氮化矽及碳氮氧化矽之中的不同材料形成。
下部的第二半導體晶片200A的第二後結構220可接合至上部的第二半導體晶片200B的第二前結構240。相似地,下部的第二半導體晶片200B的第二後結構220可與上部的第二半導體晶片200C的第二前結構240接合並進行組合。舉例而言,所述多個第二半導體晶片200A、200B、200C及200D可藉由將下部的半導體晶片的每一第二後結構220與上部的半導體晶片的第二前結構240直接接合來進行堆疊。
在實例性實施例中,前接合接墊245與後接合接墊225可具有其中寬度及厚度中的至少一方面彼此不同的不對稱結構。舉例而言,後接合接墊225可具有第一厚度T1,而前接合接墊245可具有較第一厚度T1大的第二厚度T2。由於第二厚度T2大於第一厚度T1,因此可藉由金屬材料(例如,銅)的膨脹來穩定地對前接合接墊245與後接合接墊225進行接合而在前接合接墊245與後接合接墊225之間不存在空隙或空的空間。
第二貫穿結構230可在垂直方向(Z軸方向)上穿過第二半導體層201,且提供連接至前接合接墊245及後接合接墊225的電性路徑。第二貫穿結構230可包括第二間隔件231及第二貫穿電極232。第二間隔件231可包含氧化矽、氮氧化矽、氮化矽、聚合物或其組合或者由氧化矽、氮氧化矽、氮化矽、聚合物或其組合形成,且可為單個層或多層式層。如圖2A中所示,第二貫穿電極232可包括導電插塞232b及環繞導電插塞232b的障壁層232a。在實例性實施例中,根據實施例,障壁層232a可環繞導電插塞232b的外表面,但亦可覆蓋導電插塞232b的上表面。在此種情形中,障壁層232a可設置於後接合接墊225與導電插塞232b之間。障壁層232a可包含金屬化合物(例如,氮化鈦(TiN)、氮化鉭(TaN)或氮化鎢(WN))或者為所述金屬化合物。導電插塞232b可包含例如金屬材料(例如,鎢(W)、鈦(Ti)、鋁(Al)或銅(Cu))或者為例如所述金屬材料。
根據實例性實施例的半導體封裝1000可更包括在第一半導體晶片100上環繞第二半導體晶片200A、200B、200C及200D的包封體500。包封體500可設置於第一半導體晶片100上且可對第二半導體晶片200A、200B、200C及200D中的每一者的至少一部分進行密封。如圖1中所示,包封體500可被形成為暴露出最上部的第二半導體晶片200D的上表面。然而,根據實施例,包封體500可被形成為覆蓋最上部的第二半導體晶片200D的上表面。包封體500可包含例如環氧樹脂模製化合物(epoxy mold compound,EMC)或者由例如EMC形成,但包封體500的材料不受特別限制。
接下來,將參照圖3A至圖10B對根據本發明概念實例性實施例的經修改實例進行闡述。
圖3A、圖3B、圖4、圖5、圖6A、圖9A、圖10A及圖10B是示出根據本發明概念實例性實施例的半導體封裝的部分放大圖。圖3A、圖3B、圖4、圖5、圖6A、圖9A、圖10A及圖10B示出與圖1中的區「A」對應的區的放大圖。圖6B、圖7、圖8及圖9B是示出根據本發明概念實例性實施例的半導體封裝的平面圖。圖6B、圖7、圖8及圖9B是僅示意性地示出作為根據實例性實施例的半導體封裝的主要組件的配線接墊243及前接合接墊245的圖。
參照圖3A,在半導體封裝1000A中,前接合接墊245的突出部245Pa可被延伸成具有相對深的深度。突出部245Pa的厚度(例如,高度)可大於突出部245Pa的寬度。隨著前接合接墊245的寬度(或平面面積)由於半導體封裝的高度整合而減小,突出部245Pa的厚度可相對增大以增大前接合接墊245與配線接墊243之間的介面面積。然而,即使在此種情形中,突出部245Pa的上端部亦可在不穿過配線接墊243的條件下與配線接墊243接觸。根據一些實施例,突出部245Pa的厚度可為例如突出部245Pa的寬度的2倍至5倍。
參照圖3B,在半導體封裝1000B中,前接合接墊245的突出部245Pb可包括在鈍化層244與配線接墊243之間延伸的部分。形成突出部245Pb的障壁層245a與導電層245b可具有不同的形狀。障壁層245a可朝向鈍化層244與配線接墊243之間的空間在側向上延伸,而導電層245b可不朝向所述空間在側向上延伸。然而,突出部245Pb及相鄰的鈍化層244的形狀並非僅限於此,且可根據用於形成與突出部245Pb對應的凹陷部分的蝕刻製程的製程條件而不同地進行改變。
參照圖4,在半導體封裝1000C中,不同於圖2A所示突出部245P,可僅使用障壁層245a來填充前接合接墊245的突出部245Pc。障壁層245a可不具有實質上均勻的厚度,乃因障壁層245a完全地填充突出部245P。
參照圖5,在半導體封裝1000D中,前接合接墊245的上表面可朝向配線接墊243具有凹的形狀。前接合接墊245可包括中心區245C及環繞中心區245C的外部區245O(例如,參見圖2B),且中心區245C的上端部的高度可低於外部區245O的上端部的高度。然而,不同於具有圖2A所示突出部245P的上表面結構,前接合接墊245的上表面可具有擁有連續斜面或連續彎曲弧面的上表面結構。
參照圖6A及圖6B,在半導體封裝1000E中,前接合接墊245的突出部245Pe可具有不對稱形狀。突出部245Pe可具有在Z方向上相對於前接合接墊245的中心軸不對稱的形狀。舉例而言,突出部245Pe可具有厚度不規則的環形形狀。此可為由於在用於形成突出部245Pe的圖案化製程中罩幕未對準而形成的結構。
參照圖7,在半導體封裝1000F或半導體封裝1000G中,前接合接墊245可具有多邊形結構,例如在平面圖中為四邊形或六邊形。然而,即使在此種情形中,前接合接墊245在平面圖中亦可被定位於配線接墊243內。另外,突出部245Pf及突出部245Pg可沿著前接合接墊245的外表面具有多邊形結構的環形形狀。
參照圖8,在半導體封裝1000H中,突出部245Ph可包括沿著外部區245O彼此間隔開的多個突起部。即,不同於具有環形形狀的圖2A所示突出部245P,可佈置有具有孔洞型結構的多個突起部。所述孔洞被示出為具有圓形形狀,但並非僅限於此且可被改變成各種形狀,例如卵形形狀及正方形形狀。在實例性實施例中,所述多個突起部可以規則的間隔彼此間隔開,但亦可以各種方式進行排列。
由於突出部245Ph被形成為具有所述多個突起部,因此前接合接墊245與配線接墊243之間的接觸面積相對增大,藉此提供可靠性改善的半導體封裝。
參照圖9A及圖9B,在半導體封裝1000I中,突出部245Pi可與以上參照圖8闡述的突起部相似地包括彼此間隔開的多個突起部,但所述多個突起部亦可排列於外部區245O及中心區245C兩者中。其中排列有所述多個突起部的排列關係可根據實施例不同地發生改變。
參照圖10A,在半導體封裝1000J中,前接合接墊245與後接合接墊225可具有不同的寬度,特別是在前接合接墊245與後接合接墊225彼此面對的表面上具有不同的寬度,但在一些情形中所述兩個接合接墊亦可整個地具有不同的寬度。
後接合接墊225可具有第一寬度W1,而前接合接墊245可具有較第一寬度W1大的第二寬度W2。根據本實施例,由於第一寬度W1大於第二寬度W2,因此可確保前接合接墊245與後接合接墊225的對準裕度。
參照圖10B,在半導體封裝1000K中,前接合接墊245可使配線接墊243的下部部分凹陷。前接合接墊245可具有上表面,所述上表面包括作為突出部的表面的第一表面及自第一表面延伸的第二表面,且第二表面可位於較配線接墊243的下表面的水平高的水平處。此可為由於在藉由對前接合絕緣層241進行蝕刻而形成開口的製程中藉由蝕刻製程而部分地移除配線接墊243的下部部分而形成的結構。
圖11是示出根據本發明概念實例性實施例的半導體封裝的剖視圖。
參照圖11,根據實例性實施例的半導體封裝2000可包括封裝基板600、中介層基板700及至少一個晶片結構1000。另外,半導體封裝2000可更包括被設置成在中介層基板700上與晶片結構1000相鄰的邏輯晶片或處理器晶片800。
封裝基板600可包括設置於本體的下表面上的下部接墊612、設置於本體的上表面上的上部接墊611以及將下部接墊612電性連接至上部接墊611的重佈線電路613。封裝基板600可為上面安裝有中介層基板700、邏輯晶片800及晶片結構1000的支撐基板,且可為用於半導體封裝的包括印刷電路板(printed circuit board,PCB)、陶瓷基板、玻璃基板、帶狀配線板(tape wiring board)及類似基板的基板。封裝基板600的本體可端視基板的類型而定包含不同的材料。舉例而言,當封裝基板600是PCB時,封裝基板600可為在本體覆銅疊層(body copper-clad laminate)或覆銅疊層的一個表面或兩個表面上附加地堆疊配線層的形式。可分別在封裝基板600的下表面及上表面上形成阻焊層。下部接墊612及上部接墊611以及重佈線電路613可形成連接封裝基板600的下表面與上表面的電性路徑。下部接墊612及上部接墊611以及重佈線電路613可包含例如以下中的至少一者的金屬材料或者由例如以下中的至少一者的金屬材料形成:銅(Cu)、鋁(Al)、鎳(Ni)、銀(Ag)、金(Au)、鉑(Pt)、錫(Sn)、鉛(Pb)、鈦(Ti)、鉻(Cr)、鈀(Pd)、銦(In)、鋅(Zn)及碳(C)或者包括二或更多種金屬的合金。重佈線電路613可包括多個重佈線層及連接所述多個重佈線層的通孔。在封裝基板600的下表面上可設置有連接至下部接墊612的外部連接端子620。外部連接端子620可包含錫(Sn)、銦(In)、鉍(Bi)、銻(Sb)、銅(Cu)、銀(Ag)、鋅(Zn)、鉛(Pb)及/或其合金中的一或多者或者由所述一或多者形成。
中介層基板700可包括基板本體701、下部保護層703、下部接墊705、內連線結構710、金屬凸塊720及穿孔730。晶片結構1000及處理器晶片800可經由中介層基板700而堆疊於封裝基板600上。中介層基板700可將晶片結構1000及處理器晶片800彼此電性連接。
基板本體701可由例如矽基板、有機基板、塑膠基板及玻璃基板中的任一者形成。當基板本體701是矽基板時,中介層基板700可被稱為矽中介層。此外,當基板本體701是有機基板時,中介層基板700可被稱為面板中介層(panel interposer)。
下部保護層703可設置於基板本體701的下表面上,且下部接墊705可設置於下部保護層703上。下部接墊705可連接至穿孔730。晶片結構1000及處理器晶片800可經由設置於下部接墊705上的金屬凸塊720電性連接至封裝基板600。
內連線結構710可設置於基板本體701的上表面上且可包括層間絕緣層711及單層式配線結構或多層式配線結構712。當內連線結構710具有多層式配線結構時,不同層的配線圖案可經由接觸通孔彼此連接。
穿孔730可自基板本體701的上表面延伸至下表面且穿過基板本體701。此外,穿孔730可延伸至內連線結構710中且電性連接至內連線結構710的配線。當基板本體701是矽時,穿孔730可被稱為TSV。穿孔730的其他結構及材料可與針對圖1所示半導體封裝1000闡述的結構及材料相同。端視實施例而定,中介層基板700可在中介層基板700中僅包括內連線結構且可不包括穿孔。
中介層基板700可用於對封裝基板600與晶片結構1000或處理器晶片800之間的輸入電性訊號進行轉換或傳輸的目的。因此,中介層基板700可不包括例如主動裝置或被動裝置等裝置。此外,根據實施例,內連線結構710可設置於穿孔730下方。舉例而言,內連線結構710與穿孔730之間的位置關係可為相對的。
金屬凸塊720可設置於中介層基板700的下表面上且電性連接至內連線結構710的配線。中介層基板700可經由金屬凸塊720而堆疊於封裝基板600上。金屬凸塊720可經由內連線結構710及穿孔730的配線連接至下部接墊705。在實例中,下部接墊705中的用於電源或接地的一些下部接墊705可被整合並連接至金屬凸塊720,使得下部接墊705的數目可大於金屬凸塊720的數目。
邏輯晶片或處理器晶片800可包括例如中央處理單元(central processing unit,CPU)、圖形處理單元(graphics processing unit,GPU)、現場可程式化閘陣列(field programmable gate array,FPGA)、數位訊號處理器(digital signal processor,DSP)、密碼處理器(cryptographic processor)、微處理器、微控制器、類比-數位轉換器(analog-to-digital converter,ADC)、應用專用IC(application-specific IC,ASIC)及類似裝置。端視邏輯晶片或處理器晶片800中所包括的裝置的類型而定,半導體封裝2000可被稱為伺服器定向的半導體封裝或行動定向的半導體封裝。
晶片結構1000可具有與以上參照圖1至圖10B闡述的半導體封裝1000的特性相似或相同的特性。舉例而言,晶片結構1000可具有其中第一半導體晶片100與第二半導體晶片200A、200B、200C及200D直接接合、第二半導體晶片200A、200B、200C及200D的後接合接墊225與前接合接墊245可直接接合且前接合接墊245可包括朝向配線接墊243突出的突出部245P的結構。
半導體封裝2000可更包括內部包封體,所述內部包封體覆蓋位於中介層基板700上的晶片結構1000及處理器晶片800的側表面及上表面。另外,半導體封裝2000可更包括覆蓋中介層基板700的外部包封體及位於封裝基板600上的內部包封體。外部包封體與內部包封體可一起形成且在一個實施例中彼此不區分。根據實例性實施例,半導體封裝2000可更包括覆蓋位於封裝基板600上的晶片結構1000及處理器晶片800的散熱板。
圖12是示出根據實例性實施例的半導體封裝的剖視圖。
參照圖12,半導體封裝3000A可包括在垂直方向上堆疊的第一半導體晶片100與第二半導體晶片200。第一半導體晶片100與第二半導體晶片200可在不存在單獨的連接構件的條件下藉由直接接合進行耦合。由於第一半導體晶片100的結構與圖1及圖2A所示第一半導體晶片100的結構相同,因此將不再對其說明予以贅述。然而,第一半導體晶片100的第一裝置層110可包括各別裝置,且所述各別裝置可包括:場效電晶體(field effect transistor,FET),例如平面FET或鰭式場效電晶體(fin field effect transistor,FinFET);快閃記憶體;記憶體裝置,例如DRAM、SRAM、電性可抹除可程式化唯讀記憶體(electrically erasable programmable read only memory,EEPROM)、PRAM、MRAM、FeRAM、RRAM等;邏輯裝置,例如及(AND)、或(OR)及非(NOT);以及各種主動裝置及/或被動裝置,例如系統大型積體電路(large scale integrated circuit,LSI)、互補金屬氧化物半導體(complementary metal oxide semiconductor,CMOS)影像感測器(CMOS image sensor,CIS)、微機電系統(micro-electro mechanical system,MEMS)。第二半導體晶片200可包括單個晶片且可不包括第二貫穿結構230。然而,第二半導體晶片200可具有與以上參照圖1及圖2A闡述者相似的第二半導體層201及第二前結構240,且第二前結構240可接合至第一半導體晶片100的第一後結構120。在實例性實施例中,第二半導體晶片200可為構成多晶片模組(multi-chip module,MCM)的小晶片(chiplet),但並非僅限於此。
圖13是示出根據實例性實施例的半導體封裝的剖視圖。
參照圖13,除半導體封裝3000B更包括上面安裝有第一半導體晶片100的封裝基板300及在封裝基板300上對第一半導體晶片100及第二半導體晶片200進行包封的包封體260以外,半導體封裝3000B亦可具有與以上參照圖12闡述的特性相同或相似的特性。
作為實例,第一半導體晶片100可為包括例如CPU、GPU、FPGA、AP、DSP、密碼處理器、微處理器、微控制器、ADC、ASIC及類似裝置的邏輯晶片。此外,第二半導體晶片200可包括記憶體晶片,例如DRAM、SRAM、PRAM、MRAM、FeRAM或RRAM。在本實施例中,第二半導體晶片200被示出為與圖12所示形狀相同,但亦可具有與以上參照圖1至圖10B闡述的形狀相似的形狀。舉例而言,第二半導體晶片200可包括電源管理IC(power management IC,PMIC)晶片。
封裝基板300可包括設置於本體的下表面上的下部接墊312、設置於本體的上表面上的上部接墊311以及將下部接墊312電性連接至上部接墊311的重佈線電路313。封裝基板300可為用於半導體封裝的包括印刷電路板(printed circuit board,PCB)、陶瓷基板、玻璃基板、帶狀配線板(tape wiring board)及類似基板的基板。可分別在封裝基板300的下表面及上表面上形成阻焊層。下部接墊312及上部接墊311以及重佈線電路313可形成連接封裝基板300的下表面與上表面的電性路徑。在封裝基板300的下表面上可設置有連接至下部接墊312的外部連接端子320。
圖14A至圖14G是依序示出根據本發明概念實例性實施例的半導體晶片的製造製程的剖視圖。圖14A至圖14G示出對晶圓進行切塊以形成包括第二半導體晶片的多個半導體晶片的製程,且圖14B及圖14C是圖14A所示區「B」的放大圖。
參照圖14A,可形成暴露出配線接墊243的開口OP。
首先,可使用接合材料層將用於所述多個第二半導體晶片200的第二半導體晶圓200W臨時接合成藉由第一載體5進行支撐。第二半導體晶圓200W可包括第二前表面201S1及第二後表面201S2且可被接合成使得第二後表面201S2面向第一載體5。
在第二半導體晶圓200W的第二前表面201S1上,可形成包括電晶體202(參照圖2A)的第二IC、連接至電晶體202的第二配線結構206以及覆蓋第二配線結構206的第二層間絕緣層205,以形成第二裝置層210,且可在自第二半導體層201的前表面201S1延伸的通孔中沈積導電材料以形成第二貫穿結構230。第二貫穿結構230可被形成為具有不完全穿過第二半導體晶圓200W的深度。第二貫穿結構230可被形成為具有例如通孔中間結構。然而,第二貫穿結構230的結構並非僅限於此,且可被形成為具有通孔優先結構或通孔最末結構。通孔優先結構可指其中在形成第二裝置層210的各別裝置之前首先形成第二貫穿結構230的結構,通孔中間結構可指其中在形成各別裝置之後形成第二裝置層210之前形成第二貫穿結構230的結構,且通孔最末結構可指其中在完全形成第二裝置層210之後形成第二貫穿結構230的結構。
接下來,可沈積並形成前接合絕緣層241的覆蓋第二裝置層210的部分,且可藉由圖案化製程來形成配線接墊243。可藉由對在此製程中沈積的前接合絕緣層241的厚度進行調節而將配線接墊243的厚度調節成較配線結構206的配線圖案206L(圖2A)的厚度厚。在進一步形成前接合絕緣層241的一部分以覆蓋配線接墊243的上表面之後,可實行圖案化製程以形成開口OP,開口OP經由前接合絕緣層241而暴露出配線接墊243的上表面的至少一部分。開口OP的寬度(或平面面積)可小於配線接墊243的寬度(或平面面積)。根據實施例,在此製程中,可使用與其餘區的材料不同的材料藉由單獨的沈積製程來形成前接合絕緣層241的上部區。
參照圖14B,可藉由移除配線接墊243的一部分來形成凹陷部分243R。
可實行使用罩幕M的蝕刻製程以自配線接墊243的藉由開口OP而被暴露出的上表面移除配線接墊243的一部分,進而形成凹陷部分243R。在實例性實施例中,罩幕M可被形成為在開口OP內具有較開口OP的直徑小的大小,且開口OP的中心軸被設置成與罩幕M的中心軸匹配,藉此形成具有環形形狀或環形狀的凹陷部分243R。然而,根據實施例,凹陷部分243R的形狀、大小及排列關係可根據罩幕M的類型或蝕刻製程的製程條件而不同地進行改變。舉例而言,可藉由改變罩幕M的設置於開口OP中的一部分的形狀來提供圖8至圖9B所示半導體封裝1000H及半導體封裝1000I。
參照圖14C,可形成初步前接合接墊245'。
可藉由使用導電材料來填充開口OP及凹陷部分243R同時在前接合絕緣層241上沈積導電材料來形成初步前接合接墊245'。導電材料可包括金屬化合物(例如,氮化鈦(TiN)、氮化鉭(TaN)或氮化鎢(WN))及/或金屬材料(例如,鎢(W)、鈦(Ti)、鋁(Al)或銅(Cu))或者可為所述金屬化合物及/或所述金屬材料。
在此製程中,可藉由依序地沈積金屬化合物材料與金屬材料來形成初步前接合接墊245',且可藉由後續製程由障壁層245a及導電層245b來形成初步前接合接墊245'。
參照圖14D,可形成前接合接墊245且可將第二半導體晶圓200W臨時地接合至第二載體10。
可藉由透過實行平坦化製程移除初步前接合接墊245'的一部分使得前接合絕緣層241的上表面被暴露出而形成前接合接墊245。
接下來,可將設置於第二半導體層201的第二前表面201S1上的前接合接墊245及前接合絕緣層241臨時地接合至第二載體10。可藉由接合材料層(例如,膠水)將前接合接墊245的上表面與前接合絕緣層241的上表面臨時地接合成藉由第二載體10進行支撐。可移除第二半導體層201的第二後表面201S2上的第一載體5。
參照圖14E,可對第二半導體晶圓200W的上表面實行研磨製程以減小第二半導體晶圓200W的厚度。因此,第二半導體晶圓200W的上表面US可被形成為低於第二貫穿結構230的上端部T。當移除第二半導體晶圓200W的一部分時,第二貫穿結構230的上端部T可自第二半導體晶圓200W的上表面US突出。藉由研磨製程,第二半導體晶圓200W的厚度可減小至第二半導體晶片200的期望厚度。作為研磨製程,可利用磨製製程(例如,化學機械研磨(chemical mechanical polishing,CMP)製程)、回蝕製程或其組合。舉例而言,可藉由實行磨製製程而將第二半導體晶圓200W減小至具有特定厚度,且可藉由在恰當的條件下應用回蝕來充分地暴露出第二貫穿孔洞(through-hole)結構230。
參照圖14F,可形成後接合絕緣層221及後接合接墊225。
後接合絕緣層221可被形成為覆蓋第二貫穿結構230的上表面及側表面的暴露於第二半導體晶片200上的部分,且覆蓋第二半導體層201的上表面。根據實施例,在此製程中,可藉由單獨的沈積製程使用與當前區的其餘部分的材料不同的材料對後接合絕緣層221的上部區進行沈積。
接下來,可對後接合絕緣層221進行圖案化以形成暴露出第二貫穿結構230的開口,且可在開口中沈積導電材料,且可對導電材料實行平坦化製程以形成後接合接墊225。導電材料可包括金屬化合物(例如,氮化鈦(TiN)、氮化鉭(TaN)或氮化鎢(WN))及/或金屬材料(例如,鎢(W)、鈦(Ti)、鋁(Al)或銅(Cu))或者為所述金屬化合物及/或所述金屬材料。
參照圖14G,可沿著切割道SL對第二半導體晶圓200W進行剖切以將第二半導體晶圓200W分成多個第二半導體晶片200。然後,可移除第二載體10。
圖15至圖17是示出將參照圖14A至圖14G製造的半導體晶片接合於晶圓上的製程的剖視圖。圖15至圖17示出將參照圖14A至圖14G製造的第二半導體晶片接合於上面形成有第一半導體晶片的晶圓上的製程。
參照圖15,首先,可使用黏合材料層將具有第一貫穿結構130的第一半導體晶片100的第一半導體晶圓100W附接至第三載體20。第一半導體晶圓100W可處於其中實施第一半導體晶片100的組件的狀態。
接下來,可將藉由圖14A至圖14G的製造製程製造的第二半導體晶片200附接於第一半導體晶圓100W上。第二半導體晶片200可附接於第一半導體晶圓100W上,使得第二前結構240面對第一半導體晶圓100W。
參照圖16,在將第一半導體晶片100的第一後結構120與第二半導體晶片200的第二前結構240彼此接合之後,可實行熱處理製程(例如,熱壓縮製程)以達成直接接合或混合接合。在直接接合中,第一後結構120的第一接合接墊125與第二前結構240的前接合接墊245可彼此接觸以形成銅(Cu)對銅(Cu)接合,但並非僅限於此。另外,第一接合絕緣層121與前接合絕緣層241可彼此接觸以藉由介電質對介電質接合來進行接合。第一接合接墊125可包括障壁層125a及導電層125b。障壁層125a可包含金屬化合物(例如,氮化鈦(TiN)、氮化鉭(TaN)或氮化鎢(WN))或者由所述金屬化合物形成。導電層125b可包含金屬材料,例如鎢(W)、鈦(Ti)、鋁(Al)或銅(Cu)。第一貫穿結構130可包括第一間隔件131及第一貫穿電極132。第一貫穿電極132可包括導電插塞132b及環繞導電插塞132b的障壁層132a。障壁層132a可包含金屬化合物(例如,氮化鈦(TiN)、氮化鉭(TaN)或氮化鎢(WN))或者由所述金屬化合物形成。導電插塞132b可包含例如金屬材料(例如,鎢(W)、鈦(Ti)、鋁(Al)或銅(Cu))。
參照圖17,可依序地對第二半導體晶片200A、200B、200C及200D進行堆疊。對於第二半導體晶片200A、200B、200C及200D,可以與以上參照圖15及圖16闡述的方式相似的方式藉由直接接合或混合接合而將其他的第二半導體晶片200B、200C及200D接合於半導體晶片上以堆疊於例如最下部的第二半導體晶片200A上。
此後,可在第一半導體晶圓100W上形成包封體500,可實行研磨製程且可沿著切割道SL對包封體500及第一半導體晶圓100W進行剖切以分隔出多個半導體封裝1000。
為對第一半導體晶片100與第二半導體晶片200的接合製程進行闡述,已將晶粒對晶圓接合作為實例進行闡述,但根據實施例,對第一半導體晶片100與第二半導體晶片200進行接合的製程可被不同地改變成晶粒對晶粒接合或晶圓對晶圓接合。
由於用於在半導體晶片之間進行直接接合的接合接墊具有突出部,因此配線接墊與接合接墊之間的接觸面積增大,藉此提供可靠性改善的半導體封裝及其製造方法。
儘管以上已示出並闡述了實例性實施例,然而對於熟習此項技術者而言將顯而易見的是,在不背離本發明的由隨附申請專利範圍界定的範圍的條件下,可做出潤飾及變化。
5:第一載體
10:第二載體
20:第三載體
100:第一半導體晶片
100W:第一半導體晶圓
101:第一半導體層
101S1:第一前表面
101S2:第一後表面
110:第一裝置層
111:第一層間絕緣層
112:第一配線結構
120:第一後表面結構/第一後結構
121:第一接合絕緣層
125:第一接合接墊
130:第一貫穿結構
131:第一間隔件
132:第一貫穿電極
140:連接凸塊
200、200A、200B、200C、200D:第二半導體晶片
200W:第二半導體晶圓
201:第二半導體層
201S1:第二前表面/前表面
201S2:第二後表面
202:電晶體
202a:雜質區
202d:閘極介電層
202g:閘極電極
203:閘極間隔件
204:裝置隔離層
205:第二層間絕緣層
206:第二配線結構/配線結構
206L:配線圖案
206P:通孔
210:第二裝置層
220:第二後結構
221:後接合絕緣層
225:後接合接墊
125a、132a、225a、232a、245a:障壁層
125b、225b、245b:導電層
230:第二貫穿結構/第二貫穿孔洞結構
231:第二間隔件
232:第二貫穿電極
132b、232b:導電插塞
240:第二前結構
241:前接合絕緣層
243:配線接墊
243R:凹陷部分
244:鈍化層
245:前接合接墊
245':初步前接合接墊
245C:中心區
245O:外部區
245P、245Pa、245Pb、245Pc、245Pe、245Pf、245Pg、245Ph、245Pi:突出部
300、600:封裝基板
500:包封體
311、611:上部接墊
312、612、705:下部接墊
313、613:重佈線電路
320、620:外部連接端子
700:中介層基板
701:基板本體
703:下部保護層
710:內連線結構
711:層間絕緣層
712:多層式配線結構
720:金屬凸塊
730:穿孔
800:處理器晶片/邏輯晶片
1000:晶片結構/半導體封裝
1000A、1000B、1000C、1000D、1000E、1000F、1000G、1000H、1000I、1000J、1000K、2000、3000A、3000B:半導體封裝
A、B:區
IF:接合介面
M:罩幕
OP:開口
SL:切割道
T:上端部
T1:第一厚度
T2:第二厚度
US:上表面
W1:第一寬度
W2:第二寬度
結合附圖閱讀以下詳細說明,將更清楚地理解本發明概念的以上及其他態樣、特徵及優點,在附圖中:
圖1是示出根據本發明概念實例性實施例的半導體封裝的剖視圖。
圖2A是示出根據本發明概念實例性實施例的半導體封裝的部分放大圖,且圖2B是示出根據本發明概念實例性實施例的半導體封裝的平面圖。
圖3A、圖3B、圖4、圖5、圖6A、圖6B、圖7、圖8、圖9A、圖9B、圖10A及圖10B是示出根據本發明概念實例性實施例的半導體封裝的部分放大圖及平面圖。
圖11是示出根據本發明概念實例性實施例的半導體封裝的剖視圖。
圖12是示出根據本發明概念實例性實施例的半導體封裝的剖視圖。
圖13是示出根據本發明概念實例性實施例的半導體封裝的剖視圖。
圖14A至圖14G是依序示出根據本發明概念實例性實施例的半導體晶片的製造製程的剖視圖。
圖15至圖17是示出將參照圖14A至圖14G製造的半導體晶片接合於晶圓上的製程的剖視圖。
200A、200B:第二半導體晶片
201:第二半導體層
201S1:第二前表面
201S2:第二後表面
202:電晶體
202a:雜質區
202d:閘極介電層
202g:閘極電極
203:閘極間隔件
204:裝置隔離層
205:第二層間絕緣層
206:第二配線結構
206L:配線圖案
206P:通孔
210:第二裝置層
220:第二後結構
221:後接合絕緣層
225:後接合接墊
225a、232a、245a:障壁層
225b、245b:導電層
230:第二貫穿結構
231:第二間隔件
232:第二貫穿電極
232b:導電插塞
240:第二前結構
241:前接合絕緣層
243:配線接墊
244:鈍化層
245:前接合接墊
245P:突出部
1000:晶片結構/半導體封裝
A:區
IF:接合介面
T1:第一厚度
T2:第二厚度
Claims (20)
- 一種半導體封裝,包括: 第一半導體晶片,包括第一半導體層、第一貫穿電極及第一接合接墊,所述第一貫穿電極在垂直方向上穿過所述第一半導體層,所述第一接合接墊連接至所述第一貫穿電極;以及 第二半導體晶片,包括第二半導體層、配線結構、配線接墊及第二接合接墊,所述第二半導體晶片設置於所述第一半導體晶片上,所述配線結構在所述第二半導體層與所述第一半導體晶片之間,所述配線接墊在所述配線結構下方連接至所述配線結構,所述第二接合接墊連接至所述配線接墊且設置於所述配線接墊下方,所述第二接合接墊與所述第一接合接墊接觸, 其中所述第二接合接墊包括頂部部分及自所述頂部部分突出至所述配線接墊中的突出部。
- 如請求項1所述的半導體封裝,其中所述配線接墊包含與形成所述配線結構的材料不同且與形成所述第二接合接墊的材料不同的金屬材料。
- 如請求項2所述的半導體封裝,其中所述配線接墊包含鋁(Al),且所述第二接合接墊包含銅(Cu)。
- 如請求項1所述的半導體封裝,其中所述配線接墊包括凹陷部分,所述凹陷部分通過所述突出部而凹陷且覆蓋所述突出部。
- 如請求項1所述的半導體封裝,其中: 所述第二接合接墊包括中心區及環繞所述中心區的外部區,且 所述突出部位於所述外部區中。
- 如請求項5所述的半導體封裝,其中所述突出部具有沿著所述外部區一體地延伸的環形形狀(annular shape)或環形狀(ring shape)。
- 如請求項5所述的半導體封裝,其中所述突出部包括沿著所述外部區彼此間隔開的多個突起部。
- 如請求項1所述的半導體封裝,其中: 所述配線接墊的下表面的寬度大於所述第二接合接墊的上表面的寬度,且 所述第二接合接墊的整個所述上表面與所述配線接墊的所述下表面垂直地交疊。
- 如請求項1所述的半導體封裝,更包括: 鈍化層,覆蓋所述配線接墊的側表面及下表面, 其中所述第二接合接墊通過所述鈍化層接觸所述配線接墊。
- 如請求項9所述的半導體封裝,其中所述突出部具有延伸至所述鈍化層與所述配線接墊之間的空間的部分。
- 如請求項1所述的半導體封裝,其中 所述第二接合接墊具有上表面,所述上表面包括第一表面及自所述第一表面延伸的第二表面,所述第一表面為所述突出部的表面,且 所述第二表面在較所述配線接墊的下表面的垂直水平高的垂直水平處。
- 如請求項1所述的半導體封裝,其中所述突出部在所述垂直方向上相對於所述第二接合接墊的中心軸具有對稱形狀。
- 如請求項1所述的半導體封裝,其中在平面圖中,所述第二接合接墊具有圓形形狀、橢圓形形狀或多邊形形狀。
- 一種半導體封裝,包括: 第一半導體晶片;以及 多個第二半導體晶片,垂直地堆疊於所述第一半導體晶片上, 其中: 所述多個第二半導體晶片中的每一者包括: 半導體層,具有後表面及與所述後表面相對的前表面; 後接合接墊,在所述半導體層的所述後表面上; 貫穿電極,穿過所述半導體層且連接至所述後接合接墊; 電晶體,在所述半導體層的所述前表面上; 前接合接墊,在所述半導體層的所述前表面上; 配線結構,將所述貫穿電極連接至所述電晶體且形成於所述前表面與所述前接合接墊之間;以及 配線接墊,在所述配線結構與所述前接合接墊之間, 其中所述前接合接墊具有頂表面且包括自所述頂表面延伸至所述配線接墊中的突出部。
- 如請求項14所述的半導體封裝,其中所述配線接墊包含鋁(Al)且具有較所述前接合接墊的寬度大的寬度。
- 如請求項14所述的半導體封裝,其中: 所述多個第二半導體晶片中的每一者更包括: 後接合絕緣層,環繞所述後接合接墊的側表面;以及 前接合絕緣層,環繞所述前接合接墊的側表面, 其中: 所述後接合絕緣層與所述後接合接墊形成後接合結構; 所述前接合絕緣層與所述前接合接墊形成前接合結構,且 藉由將所述多個第二半導體晶片之中的下部半導體晶片的各所述後接合結構直接接合至所述多個第二半導體晶片之中的與所述下部半導體晶片相鄰的上部半導體晶片的所述前接合結構而對所述多個第二半導體晶片進行堆疊。
- 如請求項14所述的半導體封裝,其中: 各所述後接合接墊具有第一厚度,且 各所述前接合接墊具有較所述第一厚度厚的第二厚度。
- 一種半導體封裝,包括: 第一結構;以及 第二結構,在所述第一結構上, 其中 所述第一結構包括: 第一半導體層,具有彼此相對的第一前表面與第一後表面; 第一裝置層,在所述第一半導體層的所述第一前表面上且包括第一配線結構; 第一貫穿電極,穿過所述第一半導體層且連接至所述第一裝置層的所述第一配線結構;以及 第一接合結構,包括第一接合接墊及第一接合絕緣層,所述第一接合接墊在所述第一半導體層的所述第一後表面上且連接至所述第一貫穿電極,所述第一接合絕緣層在所述第一接合接墊的側表面上,且 所述第二結構包括: 第二半導體層,具有彼此相對的第二前表面與第二後表面; 第二裝置層,在所述第二半導體層的所述第二前表面上且包括第二配線結構;以及 第二接合結構,包括第二接合接墊及第二接合絕緣層,所述第二接合接墊在所述第二裝置層下方且被接合成與所述第一接合接墊接觸,所述第二接合絕緣層被接合成與所述第一接合絕緣層接觸, 其中: 所述第二接合接墊包括中心區及環繞所述中心區的外部區,且 所述中心區的上端部的高度低於所述外部區的上端部的高度。
- 如請求項18所述的半導體封裝,其中所述第二接合接墊包括在所述外部區中朝向所述第二半導體層突出的突出部。
- 如請求項18所述的半導體封裝,其中所述第二接合接墊具有在寬度及厚度中的至少一者方面與所述第一接合接墊的結構不同的結構。
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US20230092410A1 (en) * | 2021-09-17 | 2023-03-23 | Samsung Electronics Co., Ltd. | Semiconductor package and method of manufacturing the same |
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US20230092410A1 (en) * | 2021-09-17 | 2023-03-23 | Samsung Electronics Co., Ltd. | Semiconductor package and method of manufacturing the same |
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