TW202412188A - Non-volatile memory structure and method for forming the same - Google Patents

Abstract

A non-volatile memory structure includes a substrate and a gate stack layer over the substrate. The gate stack layer includes an active pattern and a rail block. The active pattern includes a plurality of first active stacks and a plurality of second active stacks. The first active stacks and the second active stacks are arranged separately in the first direction and extended in the second direction. The second direction is different from the first direction. The rail block is extended in the first direction. The rail block has the first side and the second side opposite to the first side. The first active stacks connect the first side of the rail block, and the second active stacks connect the second side of the rail block. Also, the first side of the rail block includes a plurality of first protruding portions arranged separately in the first direction.

Description

Non-volatile memory structure and forming method thereof

The present invention relates to a non-volatile memory structure and a method for forming the same, and more particularly to a flash memory structure and a method for forming the same.

As the flash memory process continues to shrink, many challenges arise. For example, after multiple pattern transfer processes, the connection between the long columnar active stacks and the stacking block in the memory structure may be too narrow or even completely disconnected, making it impossible for the subsequent contacts set on the stacking block to stably or even electrically connect to the gates of these active stacks. Therefore, the industry still needs to improve the manufacturing method of non-volatile memory structure to overcome the problems caused by the shrinking of component size.

The present invention provides a non-volatile memory structure, including a substrate and a gate stacking layer formed on the substrate. The gate stacking layer includes an active pattern and a rail block. The active pattern includes a plurality of first active stacks and a plurality of second active stacks, which are respectively arranged at intervals in a first direction and extend respectively along a second direction, which is different from the first direction. The rail block extends along the first direction, and the rail block has a first side and a second side opposite to each other, the first active stack is connected to the first side, the second active stack is connected to the second side, and the first side includes a plurality of first protrusions arranged at intervals in the first direction.

The present invention provides a method for forming a non-volatile memory structure, comprising providing a substrate; sequentially forming an active layer, a hard mask layer, and a core pattern on the substrate; forming spacers on the sidewalls of the core pattern; removing the core pattern, and forming the remaining spacers on the hard mask layer; providing a patterned photoresist layer above the spacers, the patterned photoresist layer comprising a main body and a plurality of wing portions, wherein the main body extends along a first direction. The wing portions are connected to a first side of the main body and are spaced apart in the first direction. The wing portions protrude in a second direction, which is different from the first direction. Then, the hard mask layer is etched according to the patterned photoresist layer and the spacers to form a hard mask pattern; and the hard mask pattern is transferred to the active layer to form a gate stack layer.

Figures 1A to 1I are schematic diagrams showing the formation of a non-volatile memory structure at different manufacturing stages according to an embodiment of the present invention. Figure 1F is a schematic cross-sectional diagram taken along line B-B in the three-dimensional diagram of Figure 1F-1. Figure 1F-2 is a schematic cross-sectional diagram taken along line C-C in the three-dimensional diagram of Figure 1F-1. Figure 1F-3 is a schematic partial top view of Figure 1F-1. Figure 1G-1 is a three-dimensional diagram of a memory structure at an intermediate stage of the manufacturing process according to an embodiment of the present invention. Figure 1G is a schematic cross-sectional diagram taken along line B-B in Figure 1G-1. Figure 1G-2 is a schematic partial top view of the memory structure in Figure 1G-1. Fig. 1I is a schematic cross-sectional view taken along line B-B in Fig. 1I-1. Fig. 1I-2 is a schematic top view of a portion of the memory structure in Fig. 1I-1.

Referring to FIG. 1A , first, a substrate 100 is provided, such as a semiconductor substrate. In one embodiment, the substrate 100 may be an elemental semiconductor substrate, such as a silicon substrate or a germanium substrate; or a compound semiconductor substrate, such as a silicon carbide substrate or a gallium arsenide substrate. In one embodiment, the substrate 100 may be an insulator-covered silicon substrate.

Afterwards, an active layer 110 is formed on the substrate 100. The active layer 110 is a stack of multiple material layers, including a tunnel oxide layer 102, a conductive layer 104, and a silicon nitride layer 106 formed sequentially on the substrate 100. The tunnel oxide layer 102 may include, for example, silicon oxide or a high dielectric constant (k>4) material. The high dielectric constant material may include, for example, bismuth oxide, bismuth silicon oxide, bismuth aluminum oxide, or bismuth tantalum oxide. The conductive layer 104 may include, for example, polysilicon or doped polysilicon.

Referring again to FIG. 1A , a hard mask layer 112, a hard mask layer 113, a sacrificial core layer 114, and an anti-reflective layer 115 are sequentially formed on the active layer 110. The hard mask layer 112 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In one embodiment, the material of the hard mask layer 112 includes tetraethoxysilane (TEOS). The material of the hard mask layer 113 includes polycrystalline silicon. The sacrificial core layer 114 may include a carbon-rich material, such as a carbon layer or spin-on carbon. The anti-reflective layer 115 may include a silicon-rich material, such as silicon oxynitride.

Next, referring to FIG. 1A , a patterned photoresist layer 116 is formed on the anti-reflection layer 115 . The patterned photoresist layer 116 includes a plurality of photoresists 1161 disposed in the array region of the memory structure and openings 1163 between the photoresists 1161 .

Afterwards, the anti-reflection layer 115 and the sacrificial core layer 114 below are etched using the patterned photoresist layer 116 as a mask to remove the portions of the anti-reflection layer 115 and the sacrificial core layer 114 not covered by the patterned photoresist layer 116 (i.e., the portions corresponding to the openings 1163) until the upper surface of the hard mask layer 113 is exposed, as shown in FIG. 1B. In this example, after the etching process, the anti-reflection layer 115' and the core pattern 1145 are formed. The patterned photoresist layer 116 can be completely consumed in the etching process or removed by an additional ash process. In one embodiment, the etching process is a dry etching process. Furthermore, according to one embodiment, after the etching process, a trimming process may be performed on the core pattern 1145 to reduce defects formed on the surface of the memory structure.

Referring to FIG. 1C , a spacer material layer 118 is formed on the hard mask layer 113, and the spacer material layer 118 conformably covers the hard mask layer 113, the core pattern 1145, and the anti-reflection layer 115′. As shown in FIG. 1C , the spacer material layer 118 fills the opening 1163 but does not completely fill the opening 1163. The spacer material layer 118 may include a dielectric material, such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof, and the formation method thereof may include a chemical vapor deposition method or other suitable methods.

Referring to FIG. 1D , a portion of the spacer material layer 118 is removed to form a spacer 1185 and a gap 1187. The spacer 1185 is formed on the sidewalls of the core pattern 1145 and the anti-reflection layer 115′, for example, and the gap 1187 is formed in the opening 1163 (FIG. 1C ) and exposes a portion of the upper surface of the hard mask layer 113. The method of removing a portion of the spacer material layer 118 may include, for example, a dry etching process.

1E, the anti-reflection layer 115' and the core pattern 1145 are removed to form a gap 1186. The gap 1186 exposes a portion of the upper surface of the underlying hard mask layer 113. The method of removing the core pattern 1145 may include, for example, a dry etching process.

Referring again to FIG. 1E , the bottom of the gap 1186 has a width W _C in the direction D1, and the bottom of the gap 1187 has a width W _B in the direction D1. In this example, the width W _C of the bottom of the gap 1186 and the width W _B of the bottom of the gap 1187 are substantially equal. In other embodiments, the width W _C may be greater than or less than the width W _B , and the present disclosure is not limited thereto.

It is worth mentioning that in the step of FIG. 1C , the thickness of the spacer material layer 118 can be controlled to control the width of the spacer 1185 and the active stack 162 formed subsequently. In addition, the position where the spacer 1185 is formed can be determined according to the position of the core pattern 1145.

Next, referring to FIGS. 1F, 1F-1, 1F-2, and 1F-3, a sacrificial material layer 131, an anti-reflective layer 132, and a patterned photoresist layer 30 are sequentially formed on the hard mask layer 113 (e.g., along direction D3). The sacrificial material layer 131 may include a carbon-rich material, such as a carbon layer or spin-on carbon. In one embodiment, the sacrificial material layer 131 may completely cover the spacer 1185 and fill the gaps 1186 and 1187. The anti-reflective layer 132 may include silicon oxynitride.

1F-1, 1F-2 and 1F-3, the patterned photoresist layer 30 has a special pattern, for example, including a main body 30M and a plurality of wing portions 31 and a plurality of flat portions 32 located at two opposite sides of the main body 30M. In detail, in one embodiment, as shown in FIG. 1F-3, the main body 30M has a first side 301 and a second side 302 opposite to each other, wherein the plurality of wing portions 31 include a first wing portion 311 located at the first side 301 and a second wing portion 312 located at the second side 302, and the plurality of flat portions 32 include a first flat portion 321 located at the first side 301 and a second flat portion 322 located at the second side 302. The first wing 311 and the first flat portion 321 are alternately arranged in the direction D1, and the first wing 311 protrudes along the direction D2; the second wing 312 and the second flat portion 322 are alternately arranged in the direction D1, and the second wing 312 protrudes along the direction D4. The direction D4 is, for example (but not limited to), the opposite direction to the direction D2. In this example, as shown in Figures 1F-1 and 1F-3, in the direction D2, the first flat portion 321 of the first side 301 of the main body 30M corresponds to the second wing 312 of the second side 302, and the first wing 311 of the first side 301 corresponds to the second flat portion 322 of the second side 302. In other examples, the wings on the opposite sides of the patterned photoresist layer 30 may be completely staggered as shown in Figure 1F-3, or may be only partially staggered or completely corresponding.

As shown in FIG. 1F-3 , the first wing 311 and the second wing 312 of the patterned photoresist layer 30 are offset in the direction D2. For example, the center line L _C1 of the first wing 311 in the direction D2 is offset from the center line L _C2 of the second wing 312 in the direction D2.

Furthermore, in this example, as shown in FIG. 1F-1, although the spacer 1185 is covered by the patterned photoresist layer 30, in order to clearly show the relative pattern position between the patterned photoresist layer 30 and the underlying spacer 1185, the spacer 1185 is drawn with a dotted line in FIG. 1F-3 (and subsequent FIG. 2A and FIG. 3A). As shown in FIG. 1F-3, each wing portion 31 of the patterned photoresist layer 30 covers a portion of two adjacent spacers 1185, and covers a gap 1186 or 1187 between the two spacers 1185. Therefore, the width W _P1 of the single first wing portion 311 in the direction D1 is greater than the gap distance W _t1 between two adjacent spacers 1185, but less than the sum of twice the width W _S of each spacer 1185 and the gap distance W _t1 , that is, W _t1 < W _P1 <2×W _S +W _t1 . Similarly, the single second wing portion 312 has a width W _P2 in the direction D1, wherein W _t1 < W _P2 <2×W _S +W _t1 .

In one embodiment, a single first wing 311 or a single second wing 312 covers a gap 1186 or 1187 between two adjacent partition walls 1185, and covers about half of the width of two adjacent partition walls 1185, referring to FIG. 1F-3, that is, W _P1 =W _P2 =W _S +W _t1 .

After FIG. 1F , a pattern transfer process as shown in FIGS. 1G , 1H , and 1I is performed to form a gate stack layer on the substrate 100 .

Please refer to FIG. 1F, FIG. 1F-1, FIG. 1F-2, FIG. 1G and FIG. 1G-1. An etching process is performed using the patterned photoresist layer 30 and the spacer 1185 as masks to sequentially etch away the anti-reflection layer 132, the sacrificial material layer 131, and the portion of the hard mask layer 113 not covered by the patterned photoresist layer 30 and the spacer 1185 until the upper surface 112a of the hard mask layer 112 is exposed. In one embodiment, the etching process is dry etching.

It is particularly noted that the hard mask layer 113 after the etching process forms a hard mask pattern 1135. For details, please refer to FIG. 1G-1. For the area not covered by the patterned photoresist layer 30, the pattern of the spacer 1185 is transferred to the hard mask layer 113, and for the area covered by the patterned photoresist layer 30, the pattern of the patterned photoresist layer 30 is transferred to the hard mask layer 113 to form the hard mask pattern 1135. In addition, the spacer 1185 not covered by the patterned photoresist layer 30 may be consumed in whole or in part during the etching process, so a portion of the spacer 1185' may be left on the hard mask pattern 1135. In one embodiment, after the etching process, the patterned photoresist layer 30 and the anti-reflection layer 132′ and the sacrificial material layer 131′ thereunder are further removed.

Referring to FIG. 1G and FIG. 1H , the hard mask pattern 1135 and the spacer 1185′ (if any remain) are used as masks to perform an etching process on the underlying material layer until the upper surface of the active layer 110 is exposed, such as the upper surface 106a of the silicon nitride layer 106. In one embodiment, the etching process is dry etching. As shown in FIG. 1H , the hard mask layer 112 after the etching process forms a hard mask pattern 1125.

Referring to FIG. 1H and FIG. 1I , the hard mask pattern 1125 is used as a mask to perform an etching process on the material layer below to form the active layer 110 'and the substrate 100 '. As shown in FIG. 1I , the active layer 110 ' includes a tunneling oxide layer 102 ', a conductive layer 104 ', and a silicon nitride layer 106 '. In addition, the hard mask pattern 1125 may be partially consumed during the etching process, leaving the hard mask pattern 1126.

Referring to FIGS. 1I, 1I-1, and 1I-2, after etching the underlying material layer using the hard mask pattern 1125 as a mask, a gate stack layer 16 is formed, which includes an active pattern 160 and a rail block 163. In one embodiment, additional components (e.g., source/drain regions) may be formed on this structure to produce a non-volatile memory device. Non-volatile memory is, for example, a NAND flash memory.

Referring to FIGS. 1I-1 and 1I-2, the rail block 163 has a first side 1631 and a second side 1632 opposite to each other. The first side 1631 includes a plurality of first protrusions _1635P and a plurality of first bases _1635F arranged alternately in the direction D1, and the first protrusions _1635P protrude along the direction D2. Similarly, the second side 1632 includes a plurality of second protrusions _1636P and a plurality of second bases _1636F arranged alternately in the direction D1, and the second protrusions _1636P protrude along the direction D4. In this example, the first protrusions _1635P and the second protrusions _1636P are offset in the direction D2. For example, in FIG. 1I-2, the center line _LG1 of the first protrusion _1635P in the direction D2 and the center line _LG2 of the second protrusion _1636P in the direction D2 are staggered. In addition, in the direction D2, the first protrusion _1635P may correspond to the second base _1636F , and the first base _1635F may correspond to the second protrusion _1636P . In other embodiments, the first protrusion _1635P and the second protrusion _1636P may be arranged correspondingly in the direction D2, for example, the first base _1635F may correspond to the second base _1636F , and the first protrusion _1635P may correspond to the second protrusion _1636P (as shown in the subsequent FIG. 3B).

In one embodiment, the active pattern 160 includes a plurality of active stacks 161 and 162 (which subsequently form memory cells) connected to the rail block 163, wherein the active stacks 161 and 162 are respectively connected to the first side 1631 and the second side 1632 of the rail block 163. Furthermore, there are grooves 170 between adjacent active patterns 160, and the grooves 170 include grooves 171 and 172. Specifically, there are grooves 171 between the active stacks 161, and there are grooves 172 between the active stacks 162. The active stacks 161, the active stacks 162, the grooves 171, and the grooves 172 all extend, for example, along the direction D2 or D4. In one embodiment, two adjacent grooves 171 correspond to the first base _1635F and the first protrusion _1635P of the rail block 163, respectively; and two adjacent grooves 172 correspond to the second base _1636F and the second protrusion _1636P of the rail block 163, respectively. In subsequent manufacturing processes, insulating materials may be filled into the grooves 171 and the grooves 172 to form corresponding shallow groove isolation members (not shown).

Furthermore, in one embodiment, if the gate stacking layer 16 is viewed from above, the end of the trench 171/172 connected to the protruding portion of the rail block 163 has a larger width than the extension portion. For example, as shown in FIG. 1I-2, the trench 171 includes an extension portion 1715 and an end portion 1716, wherein the end portion 1716 is respectively connected to the extension portion 1715 and the protruding portion _1635P of the first side 1631 of the rail block 163. The extension portion 1715 has a width _Wt1 in the direction D1, and the maximum width of the end portion 1716 in the direction D1 is defined as a width _Wt2 , and the width _Wt2 is greater than the width _Wt1 . The groove 172 includes an extension portion 1725 and an end portion 1726, wherein the end portion 1726 is respectively connected to the extension portion 1725 and the protrusion _1636P of the second side 1632 of the rail block 163. The extension portion 1725 has a width W _t3 in the direction D1, and the maximum width of the end portion 1726 in the direction D1 is defined as a width W _t4 , and the width W _t4 is greater than the width W _t3 .

It is particularly noted that, as can be seen from the above figures (FIG. 1G-2 and FIG. 1I-2), a single spacer 1185 has ends located on both sides of each wing 31 (including the first wing 311 and the second wing 312) of the patterned photoresist layer 30 and an extension away from the patterned photoresist layer 30. Here, the active pattern 160 formed corresponds to the pattern of the extension of the spacer 1185, and the rail block 163 formed corresponds to the pattern formed by the patterned photoresist layer 30 and the ends of the spacer 1185. The connection between the active pattern 160 and the rail block 163 can have a sufficient connection area without the risk of disconnection. According to a formation method of an embodiment of the present disclosure, for example, the first wing 311 and the second wing 312 of the patterned photoresist layer 30 shown in FIG. 1F-1 correspond to the first protrusion _1635P and the second protrusion _1636P of the rail block 163 shown in FIG. 1I-1, respectively.

FIG. 2A is a partial top view schematic diagram of a conventional patterned photoresist layer 40 disposed in a process step corresponding to FIG. 1F-3. Referring to the process step of FIG. 1F-1, the spacer 1185 of FIG. 2A is located below the anti-reflection layer 132 and covered by the sacrificial material layer 131, and the spacer 1185 is drawn with a dotted line to clearly show the relative pattern position between the patterned photoresist layer 40 and the underlying spacer 1185. FIG. 2B is a top view schematic diagram after an etching process is performed on the underlying material layer using the patterned photoresist layer 40 and the spacer 1185 combined as shown in FIG. 2A. The difference between FIG. 2A and FIG. 1F-3 is only that the pattern of the patterned photoresist layer is different. FIG. 2B corresponds to the process steps of FIG. 1G-2, and the difference is only in the pattern after etching the material layer below. The same components in FIG. 2A and FIG. 2B as those in FIG. 1F-3 and FIG. 1G-2 are labeled with the same reference numerals for the sake of clarity.

When the anti-reflection layer 132/sacrificial material layer 131 below the patterned photoresist layer 40 of FIG. 2A is etched (for example, the process steps described in FIG. 1G are performed), when the etching is performed to expose the spacer 1185 and the sacrificial material layer 131 at the gap 1187 is to be etched, the edge of the patterned photoresist layer 40, the spacer 1185 and the sacrificial material layer 131 at the gap 1187 are exposed. 185 and the gap 1187 will generate multiple height differences, thereby making the edge of the patterned photoresist layer 40, the spacer 1185, and the intersection of the gap 1187 (as indicated by the arrow in FIG. 2A) more susceptible to the attack of the etching plasma (i.e., a faster etching rate), resulting in more spacer 1185 material being etched. Therefore, as shown in FIG. 2B, the etching process causes the spacer 1185 to form a concave defect _1185D adjacent to the side of the patterned photoresist layer 40. It is particularly noted that when using a conventional patterned photoresist layer 40, if concave defects _1185D are simultaneously generated on two opposite sides of a single spacer 1185 at the same position in the direction D2, the concave defects _1185D may expand with subsequent processing, thereby cutting off the pattern there, making it impossible for the finally formed active stack to be connected to the rail block.

Please refer to Figures 1F-3 and 1G-2 again. Figure 1G-2 is a partial top view schematic diagram of the etching process of the material layer below using the patterned photoresist layer 30 shown in Figure 1F-3. The steps of Figures 1F-3 and 1G-2 and the subsequent transfer of the pattern of the patterned photoresist layer 30 to the active layer below have been described in the formation steps of Figures 1G, 1H, and 1I above, and will not be repeated here.

In this embodiment, the patterned photoresist layer has a protruding first wing 311 and a second wing 312. When the etching process is performed, only the gap 1187/1186 corresponding to the first wing 311/the second wing 312 is adjacent to the edge of the patterned photoresist layer 30 (as indicated by the arrows shown in FIG. 1F-3) is susceptible to more attack by the etching plasma, resulting in more spacer 1185 material being etched. However, the gap 1186/1187 corresponding to the first flat portion 321/the second flat portion 322 is adjacent to the edge of the patterned photoresist layer 30 and will not be over-etched due to the shielding effect. Therefore, compared to the top view pattern (FIG. 2B) produced by etching using the patterned photoresist layer 40 as shown in FIG. 2A, after etching using the patterned photoresist layer 30 provided in FIG. 1F-3, as shown in FIG. 1G-2, the concave defects _1185D will not be formed simultaneously on both sides of the same position of a single spacer 1185 in the direction D2, thereby avoiding the risk of the pattern being interrupted in the subsequent process.

FIG. 3A is a partial top view schematic diagram of a patterned photoresist layer 50 according to other embodiments of the present disclosure being provided in a process step corresponding to FIG. 1F-3. The difference between FIG. 3A and FIG. 1F-3 is that the patterns of the patterned photoresist layers 50 and 30 are different. Furthermore, referring to the process step of FIG. 1F-1, the spacer 1185 of FIG. 3A is located below the anti-reflection layer 132 and is covered by the sacrificial material layer 131, so the spacer 1185 is drawn with a dotted line. FIG. 3B is a top view schematic diagram after an etching process is performed on the underlying material layer using the pattern composed of the patterned photoresist layer 50 and the spacer 1185 as shown in FIG. 3A. Furthermore, the same components in Figures 3A and 3B as those in Figures 1F-3 and 1I-2 are labeled with the same numbers for the sake of clarity.

As shown in FIG. 3A , the patterned photoresist layer 50 includes a main body 50M and a plurality of wing portions 51 and a plurality of flat portions 52 located at opposite sides of the main body 50M. Specifically, in one embodiment, the main body 50M has a first side 501 and a second side 502 opposite to each other, wherein the plurality of wing portions 51 include a first wing portion 511 located at the first side 501 and a second wing portion 512 located at the second side 502, and the plurality of flat portions 52 include a first flat portion 521 located at the first side 501 and a second flat portion 522 located at the second side 502. The first wing portion 511 and the first flat portion 521 are alternately arranged in a direction D1, and the first wing portion 511 protrudes along a direction D2; and the second wing portion 512 and the second flat portion 522 are alternately arranged in a direction D1, and the second flat portion 522 protrudes along a direction D4. Direction D4 is, for example (but not limited to), the opposite direction to direction D2. In this example, in direction D2, the first wing portion 511 of the first side 501 of the main body 50M corresponds to the second wing portion 512 of the second side 502, and the first flat portion 521 of the first side 301 corresponds to the second flat portion 522 of the second side 502.

As shown in FIG. 3A , in one embodiment, the first wing 511 and the second wing 512 of the patterned photoresist layer 50 are disposed correspondingly in the direction D2. For example, the center line L _C1 of the first wing 511 in the direction D2 coincides with the center line L _C2 of the second wing 512 in the direction D2.

After multiple subsequent processes, the pattern formed by the spacer 1185 and the patterned photoresist layer 50 shown in FIG3A can be used to form a gate stacking layer including an active pattern 160 and a rail block 163, a partial top view of which is shown in FIG3B. The active pattern 160 formed in FIG3B corresponds to the pattern of the spacer 1185, and the rail block 163 formed corresponds to the pattern of the main body 50M of the patterned photoresist layer 50. The content of the components in FIG3B can refer to the description of the above-mentioned FIG1I-2.

In summary, the non-volatile memory structure and the method for forming the same according to an embodiment of the present disclosure can use a patterned photoresist layer with a special pattern, so that the pattern of the patterned photoresist layer can be smoothly transferred to the active layer after multiple subsequent processes without adding additional costs. In addition, the manufactured gate stack layer not only includes a rail block with a sufficient area for setting contacts, but also can manufacture multiple active stacks that are smoothly connected to the rail block without the risk of disconnection, so that the contacts subsequently set on the rail block can be electrically connected to the conductive layers (such as gates) of these active stacks. Therefore, even if the edge of the active stack connected to the rail block has a portion of inwardly concave material loss during the etching process (as shown in FIG. 1G-2), there is no risk of line breakage. Therefore, the yield and reliability of the formed non-volatile memory can be improved.

Although the present invention has been disclosed as above by the embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the scope of the attached patent application.

100, 100': substrate 102, 102': tunnel oxide layer 104, 104': conductive layer 106, 106': silicon nitride layer 110, 110': active layer 112, 113: hard mask layer 1125, 1126, 1135: hard mask pattern 114: sacrificial core layer 1145: core pattern 115, 115', 132, 132': anti-reflective layer 116, 30, 40, 50: patterned photoresist layer 1161: photoresist 1163: opening 118: spacer material layer 1185: spacer 1185': patterned spacer 1185 _D : Concave defect 1186, 1187: Gap 131, 131': Sacrificial material layer 16: Gate stack layer 160: Active pattern 161, 162: Active stack 170, 171, 172: Groove 163: Rail block 30M, 50M: Main body 301, 1631, 501: First side 302, 1632, 502: Second side 1635 _P : First protrusion 1635 _F : First base 1636 _P : Second protrusion 1636 _F : second base 1715: first extension 1725: second extension 1716: first end 1726: second end 31, 51: wing 311, 511: first wing 312, 512: second wing 321, 521: first flat portion 322, 522: second flat portion 106a, 112a: upper surface W _S , W _C , W _B , W _P1 , W _P2 , W _S : width W _t1 , W _t3 : extension width W _t2 , W _t4 : end width D1, D2, D3, D4: direction BB, CC: section line L _C1 , L _C2 , L _G1 , L _G2 : center line

Figures 1A to 1F, 1F-1, 1F-2, 1F-3, 1G, 1G-1, 1G-2, 1H, 1I, 1I-1 and 1I-2 are schematic diagrams showing the formation of a non-volatile memory structure at different stages according to an embodiment of the present invention. Figure 2A is a partial top view schematic diagram showing a conventional patterned photoresist layer being provided in the process step corresponding to Figure 1F-3; Figure 2B is a top view schematic diagram showing the etching process of the underlying material layer using the patterned photoresist layer shown in Figure 2A. FIG. 3A is a partial top view schematic diagram of a patterned photoresist layer according to other embodiments of the present disclosure being set in the process step corresponding to FIG. 1F-3; FIG. 3B is a top view schematic diagram of an etching process of a material layer below using the patterned photoresist layer of other embodiments of the present disclosure.

100’: Base

102’: Tunneling oxide layer

104’: Conductive layer

106’: Silicon nitride layer

110’: Active layer

1126: Hard mask pattern

16: Gate stack layer

160: Active Graphics

161,162: Active stacking

163: Rail block

1631: First side

1632: Second side

1635 _P : First protrusion

1635 _F : First base

1636 _P : Second protrusion

1636 _F : Second base

170,171,172: Grooves

D1,D2,D3,D4: Direction

B-B: section line

Claims (15)

A non-volatile memory structure includes: a substrate; and a gate stacking layer formed on the substrate, the gate stacking layer including: an active pattern including a plurality of first active stacks and a plurality of second active stacks, the first active stacks and the second active stacks are respectively arranged at intervals in a first direction and extend respectively along a second direction, the second direction being different from the first direction; and a rail block extending along the first direction, the rail block having a first side and a second side opposite to each other, the first active stacks connected to the first side, the second active stacks connected to the second side, the first side including a plurality of first protrusions arranged at intervals in the first direction. A non-volatile memory structure as claimed in claim 1, wherein the second side of the rail block includes a plurality of second protrusions, and the second protrusions are arranged at intervals in the first direction. As in the non-volatile memory structure of claim 2, the first protrusions and the second protrusions are arranged correspondingly in the second direction. The non-volatile memory structure of claim 2, wherein the first center lines of the first protrusions in the second direction overlap with the second center lines of the second protrusions in the second direction. A non-volatile memory structure as claimed in claim 2, wherein the first protrusions and the second protrusions are shifted in the second direction, wherein the first center lines of the first protrusions in the second direction are staggered with the second center lines of the second protrusions in the second direction. As in the non-volatile memory structure of claim 2, the first side of the rail block further includes a plurality of first bases, and the first bases are arranged alternately with the first protrusions, and the second side of the rail block further includes a plurality of second bases, and the second bases are arranged alternately with the second protrusions. A non-volatile memory structure as claimed in claim 6, wherein the first bases correspond to the second bases, and the first protrusions correspond to the second protrusions. A non-volatile memory structure as claimed in claim 6, wherein the first protrusions correspond to the second bases, and the first bases correspond to the second protrusions. The non-volatile memory structure of claim 6 further includes a plurality of first shallow trench isolation members arranged alternately with the first active stacks, wherein the first shallow trench isolation members extend along the second direction, and two adjacent first shallow trench isolation members correspond to the first base and the first protrusion, respectively, wherein the first shallow trench isolation members respectively include: a first extension portion having a first extension width in the first direction; and a first end portion respectively connecting the first extension portion and the first side of the support rail block, having a first end width in the first direction, and the first end width is greater than the first extension width. A method for forming a non-volatile memory structure, comprising: providing a substrate; forming an active layer, a hard mask layer, and a core pattern on the substrate in sequence; forming spacers on the sidewalls of the core pattern; removing the core pattern, and the remaining spacers are formed on the hard mask layer; providing a patterned photoresist layer above the spacers, the patterned photoresist layer comprising: a main body extending along a first direction; and a plurality of wings connected to a first side of the main body and spaced apart in the first direction, the wings protruding in a second direction, the second direction being different from the first direction; etching the hard mask layer according to the patterned photoresist layer and the spacers to form a hard mask pattern; and Transfer the hard mask pattern to the active layer to form a gate stacking layer. A method for forming a non-volatile memory structure as claimed in claim 10, wherein the wings connected to the first side of the main body are first wings, and the patterned photoresist layer further includes a plurality of second wings connected to the second side of the main body and protruding along the second direction, and the second wings are arranged at a distance from each other in the first direction, and the first side is opposite to the second side. A method for forming a non-volatile memory structure as claimed in claim 11, wherein the first wings and the second wings are arranged correspondingly in the second direction. A method for forming a non-volatile memory structure as claimed in claim 11, wherein the first wings and the second wings are shifted in the second direction. A method for forming a non-volatile memory structure as claimed in claim 11, wherein the patterned photoresist layer further comprises: A plurality of first flat portions and the first wing portions are arranged alternately; and A plurality of second flat portions and the second wing portions are arranged alternately. A method for forming a non-volatile memory structure as claimed in claim 10, wherein each width of the wing portions in the first direction is greater than the gap distance between two adjacent spacers and less than the sum of twice the width of each spacer and the gap distance.