TW202410738A - Pixel circuit - Google Patents

Abstract

A pixel circuit is provided. The pixel circuit includes a light-emitting diode, a current control block, a pulse width control block, and a light-emitting driving block. The light emitting diode has an anode and a cathode receiving a system low voltage. The current control block receives a current data voltage and a system high voltage to provide a driving current based on the current data voltage. The pulse width control block receives a grayscale data voltage and a sweeping signal to provide a pulse width signal based on the grayscale data voltage. The light emitting driving block is coupled to the current control block, the pulse width control block and the anode of the light emitting diode, and receives the driving current and the pulse width signal to provide the driving current to the anode of the light emitting diode based on the pulse width signal.

Description

Pixel circuit

The present invention relates to a pixel circuit, and in particular to a light emitting diode pixel circuit.

As environmental awareness rises, energy saving, lifespan, color saturation, and power quality are gradually becoming factors that consumers consider when purchasing. At the same time, the rapid development of semiconductor technology and the reduction of costs have driven light-emitting components to become the mainstream of future lighting and display markets. Among them, organic light-emitting diodes (OLEDs) and micro-light-emitting diodes (uLEDs) are the main components currently used in self-luminous display panels.

However, the luminance curves of micro-LEDs (uLEDs) and organic LEDs (OLEDs) are different, that is, when operating at the same brightness, the luminous efficiency of the LEDs is very low. In addition, since the current range operated by the driving circuit of the organic LED falls within the low luminous efficiency range of the micro-LED, the driving circuit of the organic LED developed earlier cannot be directly applied to the micro-LED. Therefore, in order to drive the micro-LED, the existing driving circuit needs to be modified or redesigned accordingly.

The present invention provides a pixel circuit that can be driven by pulse width modulation and pulse amplitude modulation, so that the light-emitting diode operates in an efficiency range and avoids color cast caused by the deviation of the light-emitting wavelength of the light-emitting diode. .

The pixel circuit of the present invention includes a light-emitting diode, a current control block, a pulse width control block, and a light-emitting driving block. The light-emitting diode has an anode and a cathode that receives the system's low voltage. The current control block receives the current data voltage and the system high voltage to provide driving current based on the current data voltage. The pulse width control block receives the gray-scale data voltage and the swing signal to provide a pulse width signal based on the gray-scale data voltage. The light-emitting driving block is coupled to the current control block, the pulse width control block and the anode of the light-emitting diode, and receives the driving current and the pulse width signal to provide the driving current to the anode of the light-emitting diode based on the pulse width signal.

Based on the above, in the pixel circuit of the embodiment of the present invention, the current control block provides a driving current based on the current data voltage, and the pulse width control block provides a pulse width signal based on the grayscale data voltage. In this way, the pixel circuit fixes the current density of the driving current through pulse amplitude modulation, allowing the light-emitting diodes to operate in the efficiency range. At the same time, the size of the driving current is fixed to avoid color changes caused by the deviation of the light-emitting wavelength of the light-emitting diodes. bias, and control the length of the light-emitting diode's light-emitting time through pulse width modulation to produce different gray levels.

In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be construed to have meanings consistent with their meanings in the context of the relevant technology and the present invention, and are not to be construed as idealistic or excessive Formal meaning, unless expressly defined as such herein.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or sections or parts thereof shall not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element", "component", "region", "layer" or "section" discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms including "at least one" unless the content clearly dictates otherwise. "or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will also be understood that when used in this specification, the terms "comprises" and/or "includes" designate the presence of stated features, regions, integers, steps, operations, elements and/or components but do not exclude one or more The presence or addition of other features, regions, steps, operations, elements, parts and/or combinations thereof.

FIG1 is a circuit diagram of a pixel circuit according to the first embodiment of the present invention. Referring to FIG1 , in the present embodiment, the pixel circuit 100 includes a light-emitting diode DEL1, a current control block 110, a pulse width control block 120, and a light-emitting driving block 130, wherein the light-emitting diode DEL1 includes, for example, a micro light-emitting diode, but the present embodiment is not limited thereto.

The light-emitting diode DEL1 has an anode and a cathode receiving the system low voltage VSS. The current control block 110 receives the current data voltage DataI and the system high voltage VDD to provide a driving current Idrv based on the current data voltage DataI. The pulse width control block 120 receives the grayscale data voltage DataG and the swing signal Sweep to provide a pulse width signal PW based on the grayscale data voltage DataG. The light-emitting driving block 130 is coupled to the current control block 110, the pulse width control block 120 and the anode of the light-emitting diode DEL1, and receives the driving current Idrv and the pulse width signal PW to provide the driving current Idrv to the anode of the light-emitting diode DEL1 based on the pulse width signal PW.

Thereby, the pixel circuit 100 fixes the current density of the driving current Idrv through pulse amplitude modulation, allowing the light-emitting diode DEL1 to operate in the efficiency range, and at the same time fixes the size of the driving current Idrv to avoid the deviation of the emission wavelength of the light-emitting diode DEL1. The color shift caused by the shift is controlled, and the length of the light-emitting diode DEL1 is controlled through pulse width modulation to produce different gray levels.

In the present embodiment, the current control block 110 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a first capacitor C1, wherein the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are P-type transistors, but the present embodiment is not limited thereto. The first transistor T1 has a first end for receiving a system high voltage VDD, a control end, and a second end for providing a driving current Idrv. The second transistor T2 has a first end, a control end for receiving a first control signal S1, and a second end for receiving a first reference voltage Vref1, wherein the first reference voltage Vref1 can be any DC level.

The third transistor T3 has a first terminal receiving the current data voltage DataI, a control terminal receiving the second control signal S2, and a second terminal. The first capacitor C1 is coupled between the control terminal of the first transistor T1 and the second terminal of the third transistor T3. The fourth transistor T4 has a first terminal coupled to the second terminal of the third transistor T3, a control terminal receiving the emission control signal EM, and a second terminal receiving the second reference voltage Vref2, where the second reference voltage Vref2 may be A DC level that is different from the first reference voltage Vref1. The fifth transistor T5 has a first terminal coupled to the second terminal of the first transistor T1, a control terminal receiving the third control signal S3, and a second terminal coupled to the first terminal of the second transistor T2. The sixth transistor T6 has a first terminal coupled to the control terminal of the first transistor T1, a control terminal receiving the second control signal S2, and a second terminal coupled to the first terminal of the second transistor T2.

In the present embodiment, the pulse width control block 120 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a second capacitor C2, wherein the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11 are P-type transistors, but the present embodiment is not limited thereto.

The seventh transistor T7 has a first terminal receiving the first reference voltage Vref1, a control terminal receiving the first control signal S1, and a second terminal. The eighth transistor T8 has a first terminal for receiving the grayscale data voltage DataG, a control terminal for receiving the second control signal S2, and a second terminal. The ninth transistor T9 has a first terminal coupled to the second terminal of the eighth transistor T8, a control terminal receiving the emission control signal EM, and a second terminal receiving the swing signal Sweep. The second capacitor C2 is coupled between the second terminal of the seventh transistor T7 and the second terminal of the sixth transistor T6.

The tenth transistor T10 has a first terminal coupled to the second terminal of the seventh transistor T7, a control terminal receiving a third control signal S3, and a second terminal providing the pulse width signal PW. The eleventh transistor T11 has a first terminal coupled to the second terminal of the tenth transistor T10 , a control terminal coupled to the second terminal of the seventh transistor T7 , and a second terminal receiving the fourth control signal S4 .

In this embodiment, the light-emitting driving block 130 includes a twelfth transistor T12 and a thirteenth transistor T13, where the twelfth transistor T12 and the thirteenth transistor T13 are P-type transistors as an example, but The embodiments of the present invention are not limited to this. The twelfth transistor T12 has a first terminal receiving the driving current Idrv, a control terminal receiving the pulse width signal PW, and a second terminal coupled to the anode of the light-emitting diode DEL1. The thirteenth transistor T13 has a first terminal receiving the first reference voltage Vref1, a control terminal receiving the fourth control signal S4, and a second terminal coupled to the control terminal of the twelfth transistor T12.

In this embodiment, since the light-emitting diodes DEL1 with different light-emitting colors have different luminous efficiencies, for the same gray scale value, when the current data voltage DataI is applied to the light-emitting diodes DEL1 with different light-emitting colors, Can have different voltage levels.

FIG. 2 is a schematic diagram of the driving waveform of the pixel circuit during a single picture period according to the first embodiment of the present invention. Please refer to Figures 1 and 2. In a single picture period, it includes at least a first reset period Rst1, a compensation period Cmp, a second reset period Rst2, and a light emitting period Emi, and the first reference voltage Vref1 can be a P-type transistor. Enable level (such as low power level).

In the first reset period Rst1, the first control signal S1 and the second control signal S2 are at an enable level (e.g., a low voltage level), and the third control signal S3, the fourth control signal S4, the emission control signal EM, and the swing signal Sweep are maintained at a disable level (e.g., a high voltage level). At this time, the second transistor T2, the third transistor T3, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned on, and the fourth transistor T4, the fifth transistor T5, the ninth transistor T9, the tenth transistor T10, and the thirteenth transistor T13 are turned off. The first transistor T1 and the eleventh transistor T11 are turned on by the first reference voltage Vref1, and the twelfth transistor T12 is turned off because of the fourth control signal S4 at the disable level.

In the compensation period Cmp, the second control signal S2 and the third control signal S3 are at the enable level, and the first control signal S1, the fourth control signal S4, the emission control signal EM, and the swing signal Sweep are at the disable level. At this time, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the tenth transistor T10 are turned on, and the second transistor T2, the fourth transistor T4, the seventh transistor T7, the ninth transistor T9, and the thirteenth transistor T13 are turned off. The voltage of the control end of the first transistor T1 rises to the system high voltage VDD-critical voltage of the first transistor T1 through the leakage current, and the voltage of the control end of the eleventh transistor T11 and the twelfth transistor T12 rises to the high voltage level-critical voltage of the eleventh transistor T11 through the leakage current.

During the second reset period Rst2, the fourth control signal S4 and the emission control signal EM are at the enable level, and the first control signal S1, the second control signal S2, the third control signal S3 and the swing signal Sweep are at the disabled level. accurate position. At this time, the fourth transistor T4, the ninth transistor T9, and the thirteenth transistor T13 are turned on, and the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the third transistor T6 are turned on. The seventh transistor T7, the eighth transistor T8 and the tenth transistor T10 are turned off. Moreover, the voltage at the control terminal of the first transistor T1 is the system high voltage VDD - the critical voltage of the first transistor T1 + (current data voltage DataI - the second reference voltage Vref2), and the voltage at the control terminal of the eleventh transistor T11 is The high voltage level - the critical voltage of the eleventh transistor T11 - (grayscale data voltage DataG - high voltage level), and the voltage of the control terminal of the twelfth transistor T12 is the first reference voltage Vref1.

During the light-emitting period Emi, the first control signal S1, the second control signal S2, the third control signal S3, and the fourth control signal S4 are at the disabled level, the emission control signal EM is at the enabled level, and the swing signal Sweep is at the disabled level. The energy level changes linearly to the enabling level. At this time, the fourth transistor T4 and the ninth transistor T9 are turned on, and the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T7 are turned on. The transistor T8, the tenth transistor T10, and the thirteenth transistor T13 are turned off. Moreover, the voltage at the control terminal of the first transistor T1 is the system high voltage VDD - the critical voltage of the first transistor T1 + (current data voltage DataI - the second reference voltage Vref2), and the voltage at the control terminal of the eleventh transistor T11 is High voltage level - critical voltage of the eleventh transistor T11 - (grayscale data voltage DataG - high voltage level) + swing signal Sweep, and the voltage of the control terminal of the twelfth transistor T12 is at the level of the eleventh transistor T11 When turned on, it switches from a low voltage level to a high voltage level.

In this embodiment, the second reset period Rst2 and the luminous period Emi can be repeatedly executed multiple times in a single frame period, that is, the twelfth transistor T12 and the thirteenth transistor T13 are switched multiple times in a single frame period, wherein the number of switching affects the flicker degree of the frame. Alternatively, the second reset period Rst2 and the luminous period Emi can be repeatedly executed multiple times in multiple frame periods, that is, the twelfth transistor T12 and the thirteenth transistor T13 can be switched multiple times in multiple frame periods.

FIG3 is a circuit diagram of a pixel circuit according to a second embodiment of the present invention. Referring to FIG1 and FIG3 , the pixel circuit 200 is substantially the same as the pixel circuit 100, and the difference lies in the current control block 210, in which the same or similar components are used. Compared with the current control block 110, the current control block 210 omits the sixth transistor T6, that is, the second end of the transistor T5 is more directly coupled to the control end of the first transistor T1.

FIG. 4 is a schematic circuit diagram of a pixel circuit according to a third embodiment of the present invention. Referring to FIGS. 1 and 4 , the pixel circuit 300 is substantially the same as the pixel circuit 100 , except that the current control block 310 uses the same or similar components. Compared with the current control block 110, the current control block 310 omits the sixth transistor T6 and changes the voltages received by the third transistor T3 and the fourth transistor T4. Furthermore, in this embodiment, the second terminal of the transistor T5 is directly coupled to the control terminal of the first transistor T1, the first terminal of the third transistor T3 receives the swing signal Sweep, and the fourth transistor T4 The second terminal receives the current data voltage DataI.

FIG5 is a circuit diagram of a pixel circuit according to a fourth embodiment of the present invention. Referring to FIG1 and FIG5 , the pixel circuit 400 is substantially the same as the pixel circuit 100, and the difference lies in the current control block 410, the pulse width control block 420, and the light-emitting drive block 430, wherein the same or similar components are used. In this embodiment, the third control signal S3 is the same as the second control signal S2.

In the current control block 410, the sixth transistor T6 is omitted, that is, the second end of the transistor T5 is more directly coupled to the control end of the first transistor T1, the first end of the third transistor T3 receives the second reference voltage Vref2, and the second end of the fourth transistor T4 receives the current data voltage DataI, wherein the second reference voltage Vref2 can be a DC level greater than the system low voltage VSS.

The pulse width control block 420 further includes a third capacitor C3. The third capacitor C3 is coupled between the first terminal of the seventh transistor T7 and the second terminal of the seventh transistor T7, and the eleventh capacitor C3 is coupled between the first terminal of the seventh transistor T7 and the second terminal of the seventh transistor T7. The second terminal of the crystal T11 receives the second reference voltage Vref2. The light-emitting driving block 430 further includes a fourteenth transistor T14. The fourteenth transistor T14 has a first end coupled to the second end of the twelfth transistor T12, a control end that receives the pulse width emission signal EPWN, and a second terminal coupled to the anode of the light-emitting diode DEL1.

FIG. 6 is a schematic diagram of the driving waveform of the pixel circuit during a single picture period according to the fourth embodiment of the present invention. Please refer to Figures 5 and 6. In a single picture period, it includes at least a first reset period Rst1, a compensation period Cmp, a second reset period Rst2, and a light-emitting period Emi, and the first reference voltage Vref1 can be a P-type transistor. Enable level (such as low power level).

During the first reset period Rst1, the first control signal S1 and the emission control signal EM are at the enable level (such as a low voltage level), and the second control signal S2, the third control signal S3, the fourth control signal S4, and the pulse The wide emission signal EPWN and the swing signal Sweep are maintained at a disabled level (such as a high voltage level). At this time, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are turned on, and the third transistor T3, the fifth transistor T5, the eighth transistor 8T, the ninth transistor T9, and the tenth transistor T7 are turned on. The transistor T10, the thirteenth transistor T13, and the fourteenth transistor T14 are turned off. Furthermore, the first transistor T1 and the eleventh transistor T11 are turned on under the influence of the first reference voltage Vref1, and the twelfth transistor T12 is turned off under the influence of the second reference voltage Vref2.

In the compensation period Cmp, the second control signal S2 and the third control signal S3 are at the enable level, and the first control signal S1, the fourth control signal S4, the emission control signal EM, the pulse width emission signal EPWN and the swing signal Sweep are at the disable level. At this time, the third transistor T3, the fifth transistor T5, the eighth transistor T8 and the tenth transistor T10 are turned on, and the second transistor T2, the fourth transistor T4, the seventh transistor T7, the ninth transistor T9, the thirteenth transistor T13 and the fourteenth transistor T14 are turned off. The voltage of the control end of the first transistor T1 rises to the system high voltage VDD-critical voltage of the first transistor T1 through the leakage current, and the voltage of the control end of the eleventh transistor T11 and the twelfth transistor T12 rises to the second reference voltage Vref2-critical voltage of the eleventh transistor T11 through the leakage current.

In the second reset period Rst2, the fourth control signal S4 and the emission control signal EM are at the enable level, and the first control signal S1, the second control signal S2, the third control signal S3, the pulse width emission signal EPWN and The swing signal Sweep is a disabled level. At this time, the fourth transistor T4, the ninth transistor T9, and the thirteenth transistor T13 are turned on, and the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the third transistor T6 are turned on. The seventh transistor T7, the eighth transistor T8, the tenth transistor T10 and the fourteenth transistor T14 are turned off. Moreover, the voltage at the control terminal of the first transistor T1 is the system high voltage VDD - the critical voltage of the first transistor T1 + (current data voltage DataI - the second reference voltage Vref2), and the voltage at the control terminal of the eleventh transistor T11 is The second reference voltage Vref2 - the threshold voltage of the eleventh transistor T11 - (grayscale data voltage DataG - high voltage level), and the voltage of the control terminal of the twelfth transistor T12 is the first reference voltage Vref1.

In the light emission period Emi, the first control signal S1, the second control signal S2, the third control signal S3, and the fourth control signal S4 are at the disable level, the emission control signal EM and the pulse width emission signal EPWN are at the enable level, and the swing signal Sweep changes linearly from the disable level to the enable level. At this time, the fourth transistor T4 and the ninth transistor T9 are turned on, and the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the tenth transistor T10, the thirteenth transistor T13, and the fourteenth transistor T14 are turned off. Furthermore, the voltage of the control end of the first transistor T1 is the system high voltage VDD-the critical voltage of the first transistor T1+(the current data voltage DataI-the second reference voltage Vref2), the voltage of the control end of the eleventh transistor T11 is the high voltage level-the critical voltage of the eleventh transistor T11-(the grayscale data voltage DataG-the high voltage level)+the swing signal Sweep, and the voltage of the control end of the twelfth transistor T12 is switched from the low voltage level to the high voltage level when the eleventh transistor T11 is turned on.

In summary, in the pixel circuit of the embodiment of the present invention, the current control block provides the driving current based on the current data voltage, and the pulse width control block provides the pulse width signal based on the grayscale data voltage. Thus, the pixel circuit fixes the current density of the driving current through pulse amplitude modulation, so that the LED operates in the efficiency range, and at the same time fixes the size of the driving current to avoid the color shift caused by the wavelength deviation of the LED, and controls the light emission time of the LED through pulse width modulation to generate different grayscales.

Although the present invention has been disclosed as above by the embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the scope of the attached patent application.

100, 200, 300, 400: pixel circuit 110, 210, 310, 410: current control block 120, 420: pulse width control block 130, 430: light-emitting drive block C1: first capacitor C2: second capacitor C3: third capacitor Cmp: compensation period DataG: grayscale data voltage DataI: current data voltage DEL1: light-emitting diode EM: emission control signal Emi: emission period EPWN: pulse width emission signal Idrv: drive current PW: pulse width signal Rst1: first reset period Rst2: second reset period S1: first control signal S2: second control signal S3: third control signal S4: fourth control signal Sweep: swing signal Sweep: swing signal T1: first transistor T10: tenth transistor T11: eleventh transistor T12: twelfth transistor T13: thirteenth transistor T14: fourteenth transistor T2: second transistor T3: third transistor T4: fourth transistor T5: fifth transistor T6: sixth transistor T7: seventh transistor T8: eighth transistor T9: ninth transistor VDD: system high voltage Vref1: first reference voltage Vref2: second reference voltage VSS: system low voltage

FIG. 1 is a schematic circuit diagram of a pixel circuit according to the first embodiment of the present invention. FIG. 2 is a schematic diagram of the driving waveform of the pixel circuit during a single picture period according to the first embodiment of the present invention. FIG. 3 is a schematic circuit diagram of a pixel circuit according to a second embodiment of the present invention. FIG. 4 is a schematic circuit diagram of a pixel circuit according to a third embodiment of the present invention. FIG. 5 is a schematic circuit diagram of a pixel circuit according to a fourth embodiment of the present invention. FIG. 6 is a schematic diagram of the driving waveform of the pixel circuit during a single picture period according to the fourth embodiment of the present invention.

100: Pixel circuit

110:Current control block

120: Pulse width control block

130: Luminous drive block

C1: first capacitor

C2: Second capacitor

DataG: Grayscale data voltage

DataI: current data voltage

DEL1: LED

EM: transmit control signal

Idrv: driving current

PW: pulse width signal

S1: First control signal

S2: Second control signal

S3: The third control signal

S4: Fourth control signal

Sweep: Swing signal

Sweep: swing signal

T1: First transistor

T10: The tenth transistor

T11: Eleventh transistor

T12: Twelfth transistor

T13: Thirteenth transistor

T2: Second transistor

T3: The third transistor

T4: The fourth transistor

T5: The fifth transistor

T6: The sixth transistor

T7: The seventh transistor

T8: The eighth transistor

T9: Ninth transistor

VDD: system high voltage

Vref1: first reference voltage

Vref2: Second reference voltage

VSS: System low voltage

Claims (18)

A pixel circuit includes: a light-emitting diode having an anode and a cathode receiving a system low voltage; a current control block receiving a current data voltage and a system high voltage to provide a driving current based on the current data voltage; a pulse width control block receiving a grayscale data voltage and a swing signal to provide a pulse width signal based on the grayscale data voltage; A light-emitting driving block is coupled to the current control block, the pulse width control block and the anode of the light-emitting diode, and receives the driving current and the pulse width signal to provide the driving current to the anode of the light-emitting diode based on the pulse width signal. The pixel circuit of claim 1, wherein the current control block includes: A first transistor having a first terminal for receiving the high voltage of the system, a control terminal, and a second terminal for providing the driving current; a second transistor having a first terminal, a control terminal receiving a first control signal, and a second terminal receiving a first reference voltage; a third transistor having a first terminal, a control terminal receiving the second control signal, and a second terminal; a first capacitor coupled between the control terminal of the first transistor and the second terminal of the third transistor; a fourth transistor having a first terminal coupled to the second terminal of the third transistor, a control terminal receiving a transmission control signal, and a second terminal; and A fifth transistor has a first terminal coupled to the second terminal of the first transistor, a control terminal receiving a third control signal, and a first terminal coupled to the second transistor. Second end. The pixel circuit as described in claim 2, wherein the current control block further includes: A sixth transistor having a first end coupled to the control end of the first transistor, a control end receiving a second control signal, and a second end coupled to the first end of the second transistor. The pixel circuit of claim 2, wherein the first terminal of the third transistor receives the current data voltage, and the second terminal of the fourth transistor receives a second reference voltage. The pixel circuit of claim 2, wherein the first terminal of the third transistor receives the swing signal, and the second terminal of the fourth transistor receives the current data voltage. A pixel circuit as described in claim 2, wherein the first end of the third transistor receives a second reference voltage, and the second end of the fourth transistor receives the current data voltage. The pixel circuit of claim 2, wherein the third control signal is the same as the second control signal. The pixel circuit of claim 1, wherein the pulse width control block includes: a seventh transistor having a first terminal that receives a first reference voltage, a control terminal that receives a first control signal, and a second terminal; An eighth transistor has a first terminal that receives the gray-scale data voltage, a control terminal that receives a second control signal, and a second terminal; a ninth transistor having a first terminal coupled to the second terminal of the eighth transistor, a control terminal receiving a transmission control signal, and a second terminal receiving the swing signal; a second capacitor coupled between the second terminal of the seventh transistor and the second terminal of the sixth transistor; a tenth transistor having a first terminal coupled to the second terminal of the seventh transistor, a control terminal receiving a third control signal, and a second terminal providing the pulse width signal; and An eleventh transistor has a first terminal coupled to the second terminal of the tenth transistor, a control terminal coupled to the second terminal of the seventh transistor, and a second terminal. The pixel circuit of claim 8, wherein the pulse width control block further includes: A third capacitor is coupled between the first terminal of the seventh transistor and the second terminal of the seventh transistor. The pixel circuit of claim 8, wherein the third control signal is the same as the second control signal. The pixel circuit of claim 8, wherein the second terminal of the eleventh transistor receives a fourth control signal. The pixel circuit of claim 8, wherein the second terminal of the eleventh transistor receives a second reference voltage. The pixel circuit of claim 1, wherein the light-emitting driving block includes: a twelfth transistor having a first terminal for receiving the drive current, a control terminal for receiving the pulse width signal, and a second terminal coupled to the anode of the light-emitting diode; and A thirteenth transistor has a first terminal receiving a first reference voltage, a control terminal receiving a fourth control signal, and a second terminal coupled to the control terminal of the twelfth transistor. The pixel circuit of claim 13, wherein the light-emitting driving block further includes: A fourteenth transistor having a first terminal coupled to the second terminal of the twelfth transistor, a control terminal receiving a pulse width emission signal, and a first terminal coupled to the anode of the light emitting diode. Second end. The pixel circuit of claim 13, wherein the twelfth transistor and the thirteenth transistor are switched multiple times during a single picture period. A pixel circuit as described in claim 13, wherein the twelfth transistor and the thirteenth transistor are switched multiple times during multiple frame periods. A pixel circuit as described in claim 1, wherein for the same grayscale value, the current data voltage has different voltage levels when applied to the states of the light-emitting diodes with different luminous colors. The pixel circuit of claim 1, wherein the light-emitting diode includes a micro light-emitting diode.

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