TW202416256A - Pixel circuit - Google Patents

Abstract

A pixel circuit is provided. The pixel circuit includes a light emitting diode, a pulse amplitude control block, a pulse width control block, and a reset block. The light emitting diode has an anode receiving a system high voltage, and a cathode. The pulse amplitude control block is coupled between the cathode of the light-emitting diode and a system low voltage, and receives a first reference voltage to control a driving current of the light-emitting diode based on the first reference voltage. The pulse width control block is coupled to the pulse amplitude control block, receives a data voltage, and controls the pulse amplitude control block based on the data voltage to determine a single providing time of the driving current. The reset block is coupled to the pulse amplitude control block to set a state of the pulse amplitude control block.

Description

Pixel circuit

The present invention relates to a pixel circuit, and in particular to a light emitting diode pixel circuit.

As environmental awareness rises, energy saving, lifespan, color saturation, and power quality are gradually becoming factors that consumers consider when purchasing. At the same time, the rapid development of semiconductor technology and cost reduction have driven light-emitting components to become the mainstream of future lighting and display markets. Among them, organic light-emitting diodes (OLEDs) and micro-light-emitting diodes (uLEDs) are the main components currently used in self-luminous display panels.

However, the luminance curves of micro LEDs (uLEDs) and organic LEDs (OLEDs) are different, that is, when operating at the same brightness, the luminous efficiency of the LEDs is very low. In addition, since the current range operated by the driving circuit of the organic LED falls within the low luminous efficiency range of the micro LED, the driving circuit of the organic LED developed earlier cannot be directly applied to the micro LED. Therefore, in order to drive the micro LED, the existing driving circuit needs to be modified or redesigned accordingly.

The present invention provides a pixel circuit that can be driven by pulse width modulation (PWM) but does not require an external sweep signal.

The pixel circuit of the present invention includes a light-emitting diode, a pulse amplitude control block, a pulse width control block, and a reset block. The light-emitting diode has an anode and a cathode for receiving a system high voltage. The pulse amplitude control block is coupled between the cathode of the light-emitting diode and the system low voltage, and receives a first reference voltage to control the driving current of the light-emitting diode based on the first reference voltage. The pulse width control block is coupled to the pulse amplitude control block, receives a data voltage, and controls the pulse amplitude control block based on the data voltage to determine a single supply time of the driving current. The reset block is coupled to the pulse amplitude control block to set the state of the pulse amplitude control block.

Based on the above, in the pixel circuit of the embodiment of the present invention, the pulse width control block uses the data voltage and the current source to determine the single supply time of the driving current, that is, the current source is used to replace the external input ramp signal, which can simplify the relevant layout method of the pixel circuit and simplify the overall wiring cost of the panel.

In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by ordinary technicians in the field to which the present invention belongs. It will be further understood that those terms as defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present invention, and will not be interpreted as an idealized or overly formal meaning unless expressly defined as such herein.

It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and/or parts, these elements, components, regions, and/or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the "first element", "component", "region", "layer" or "part" discussed below can be referred to as a second element, component, region, layer or part without departing from the teachings of this article.

The terms used herein are for the purpose of describing specific embodiments only and are not restrictive. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms, including "at least one". " or "means" and/or". As used herein, the terms "and/or" include any and all combinations of one or more of the relevant listed items. It should also be understood that when used in this specification, the terms "include" and/or "include" specify the presence and/or parts of the features, regions, entireties, steps, operations, elements, components and/or parts, but do not exclude the presence or addition of one or more other features, regions, entireties, steps, operations, elements, components and/or combinations thereof.

FIG1 is a circuit diagram of a pixel circuit according to an embodiment of the present invention. Referring to FIG1 , in the present embodiment, the pixel circuit 100 includes a light emitting diode LD1, a pulse amplitude control block 110, a reset block 120, and a pulse width control block 130, wherein the light emitting diode LD1 includes, for example, a micro light emitting diode, but the present embodiment is not limited thereto.

The light emitting diode LD1 has an anode and a cathode for receiving a system high voltage VDD. The pulse amplitude control block 110 is coupled between the cathode of the light emitting diode LD1 and the system low voltage VSS, and receives a first reference voltage V _REF to control a driving current Idr of the light emitting diode LD1 based on the first reference voltage V _REF . The reset block 120 is coupled to the pulse amplitude control block 110 to set the state of the pulse amplitude control block 110. The pulse width control block 130 is coupled to the pulse amplitude control block 110, receives the data voltage V _DATA , and includes a current source CS, wherein the pulse width control block 130 controls the pulse amplitude control block 110 based on the data voltage V _DATA and the current source CS to determine a single providing time of the driving current Idr.

According to the above, the pulse width control block 130 uses the data voltage V _DATA and the current source CS to determine the single providing time of the driving current Idr, that is, the current source CS is used to replace the external input ramp signal, that is, there is no need for a ramp signal with a linear rise or fall in voltage level, which can simplify the relevant layout method of the pixel circuit 100 and simplify the overall wiring cost of the panel.

In the present embodiment, the pulse amplitude control block 110 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a first capacitor C1, wherein the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are respectively P-type transistors, but the embodiments of the present invention are not limited thereto.

The first transistor T1 has a first end coupled to the cathode of the light emitting diode LD1, a control end, and a second end. The second transistor T2 has a first end receiving a low voltage _VL , a control end receiving a first control signal S1[n], and a second end coupled to the control end of the first transistor T1, where n is a derivative number. The third transistor T3 has a first end coupled to the second end of the first transistor T1, a control end receiving an emission control signal EM[n], and a second end receiving a system low voltage VSS.

The fourth transistor T4 has a first end, a control end for receiving the light control signal EM[n], and a second end coupled to the cathode of the light emitting diode LD1. The first capacitor C1 is coupled between the control end of the first transistor T1 and the first end of the fourth transistor T4. The fifth transistor T5 has a first end for receiving the first reference voltage V _REF , a control end for receiving the second control signal S2[n], and a second end coupled to the first end of the fourth transistor T4. The sixth transistor T6 has a first end coupled to the control end of the first transistor T1, a control end for receiving the next-stage first control signal S1[n+1] (i.e., the third control signal), and a second end coupled to the second end of the first transistor T1, wherein the first control signal S1[n] and the next-stage first control signal S1[n+1] may differ by one clock unit.

In this embodiment, the reset block 120 includes a seventh transistor T7, wherein the seventh transistor T7 is a P-type transistor, but the embodiment of the present invention is not limited thereto. The seventh transistor T7 has a first terminal coupled to the cathode of the light-emitting diode LD1, a control terminal receiving the next-stage control signal S1[n+1], and a second terminal receiving the second reference voltage V _REF2 .

In the present embodiment, the pulse width control block 130 includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a second capacitor C2, and a third capacitor C3, wherein the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 are respectively P-type transistors, but the present embodiment is not limited thereto.

The eighth transistor T8 has a first end coupled to the control end of the first transistor T1, a control end, and a second end receiving the second reference voltage V _REF2 . The second capacitor C2 is coupled between the control end of the eighth transistor T8 and the second reference voltage V _REF2 . The ninth transistor T9 serves as a current source CS and has a first end, a control end, and a second end receiving the low voltage V _L. The third capacitor C3 is coupled between the control end of the eighth transistor T8 and the control end of the ninth transistor T9. The tenth transistor T10 has a first end coupled to the control end of the eighth transistor T8, a control end receiving the light emission control signal EM[n], and a second end coupled to the first end of the ninth transistor T9.

The eleventh transistor T11 has a first end receiving a first reference voltage V _REF , a control end receiving a second control signal S2[n], and a second end coupled to the control end of the eighth transistor T8. The twelfth transistor T12 has a first end receiving a low voltage V _L , a control end receiving a first control signal S1[n], and a second end coupled to the control end of the ninth transistor T9. The thirteenth transistor T13 has a first end, a control end receiving a third control signal S1[n+1], and a second end coupled to the control end of the ninth transistor T9. The fourteenth transistor T14 has a first end receiving a data voltage V _DATA , a control end coupled to the first end of the thirteenth transistor T13, and a second end coupled to the first end of the thirteenth transistor T13. The fourteenth transistor T14 is connected in a diode type.

In the embodiment of the present invention, the ninth transistor T9 may match the fourteenth transistor T14, that is, the channel length ratio of the ninth transistor T9 may be substantially the same as the channel length ratio of the fourteenth transistor T14.

FIG2 is a schematic diagram of a driving waveform of a pixel circuit according to an embodiment of the present invention. Referring to FIG1 and FIG2, in this embodiment, the pixel circuit 100 at least sequentially operates in a reset period Prst, a compensation period Pcmp, a light-emitting period Pem, and a shutdown period Poff.

During the reset period Prst, the first control signal S1[n] and the second control signal S2[n] are at an enable level (e.g., a gate low voltage V _GL ), and the next-stage first control signal S1[n] and the luminous control signal EM[n] are at a disable level (e.g., a gate high voltage V _GH ). At this time, the second transistor T2, the fifth transistor T5, the eleventh transistor T11, and the twelfth transistor T12 are turned on, and the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the tenth transistor T10, and the thirteenth transistor T13 are turned off. Furthermore, the node voltage A of the control end of the first transistor T1 is the low voltage V _L , the node voltage B of the second end of the fifth transistor T5 is the first reference voltage V _REF , the node voltage C of the control end of the eighth transistor is the first reference voltage V _REF , and the node voltage D of the control end of the ninth transistor is the low voltage V _L . The first transistor T1 is turned on by the node voltage A, the eighth transistor T8 is turned off by the node voltage C, and the ninth transistor T9 is turned on by the node voltage D.

In the compensation period Pcmp, the second control signal S2[n] and the next-stage first control signal S1[n] are at the enable level, and the first control signal S1[n] and the luminous control signal EM[n] are at the disable level. At this time, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eleventh transistor T11, and the thirteenth transistor T13 are turned on, and the second transistor T2, the third transistor T3, the fourth transistor T4, the tenth transistor T10, and the twelfth transistor T12 are turned off. Furthermore, the node voltage A of the control end of the first transistor T1 is the second reference voltage V _REF2 - the critical voltage V _TH1 of the first transistor T1, the node voltage B of the second end of the fifth transistor T5 is the first reference voltage V _REF , the node voltage C of the control end of the eighth transistor is the first reference voltage V _REF , and the node voltage D of the control end of the ninth transistor is the data voltage V _DATA - the critical voltage V _TH14 of the fourteenth transistor T14. The first transistor T1 is turned on by the node voltage A, the eighth transistor T8 is turned off by the node voltage C, and the ninth transistor T9 is turned off by the node voltage D.

In the luminous period Pem, the luminous control signal EM[n] is at the enable level, and the first control signal S1[n], the second control signal S2[n] and the next first control signal S1[n] are at the disable level. At this time, the third transistor T3, the fourth transistor T4, and the tenth transistor T10 are turned on, and the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eleventh transistor T11, the twelfth transistor T12 and the thirteenth transistor T1 are turned off. Furthermore, a node voltage A of the control end of the first transistor T1 is a second reference voltage V _REF2 - a critical voltage V _TH1 of the first transistor T1 ┼(system high voltage VDD - a voltage across the light emitting diode LD1 VLED - a first reference voltage V _REF ), a node voltage B of the second end of the fifth transistor T5 is a system high voltage VDD - a voltage across the light emitting diode LD1 VLED, a node voltage C of the control end of the eighth transistor is a first reference voltage V _REF -ΔV, and a node voltage D of the control end of the ninth transistor is a data voltage V _DATA - a critical voltage V _TH14 of the fourteenth transistor T14 -ΔV, wherein ΔV is a voltage difference generated over time. The first transistor T1 is turned on by the node voltage A, the eighth transistor T8 is turned off by the node voltage C, and the ninth transistor T9 is turned on by the node voltage D. Furthermore, the driving current Idr is related to the first reference voltage V _REF and the second reference voltage V _REF2 .

Further, when the second reference voltage V _REF2 - (first reference voltage V _REF - ΔV) ≦ the critical voltage V _TH8 of the eighth transistor T8, the eighth transistor T8 is cut off, and thus the first transistor T1 remains turned on; when the second reference voltage V _REF2 - (first reference voltage V _REF - ΔV) > the critical voltage V _TH8 of the eighth transistor T8, the eighth transistor T8 is turned on, causing the node voltage A to change to the second reference voltage V _REF2 , and thus the first transistor T1 is changed to be cut off.

During the off period Poff, the first control signal S1[n], the second control signal S2[n], the next-stage first control signal S1[n] and the luminous control signal EM[n] are at the disable level. At this time, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12 and the thirteenth transistor T1 are turned off. Furthermore, the node voltage A of the control end of the first transistor T1 is the second reference voltage V _REF2 , the node voltage B of the second end of the fifth transistor T5 is the system high voltage VDD-the voltage across the light-emitting diode LD1 VLED, the node voltage C of the control end of the eighth transistor is the low voltage V _L , and the node voltage D of the control end of the ninth transistor is the data voltage V _DATA -the critical voltage V _TH14 of the fourteenth transistor T14 ┼(low voltage V _L -first reference voltage V _REF ). Among them, the first transistor T1 is turned off due to the node voltage A, the eighth transistor T8 is turned on due to the node voltage C, and the ninth transistor T9 is turned on due to the node voltage D.

According to the above, the embodiment of the present invention can propose a 14T3C circuit architecture for a micro-LED pixel circuit, which is applied to a micro-LED spliced display. The pixel circuit 100 can operate the LED at the optimal luminous efficiency point through pulse-width modulation (PWM) control to reduce power consumption at low gray levels, and compensate for the critical voltage variation of the first transistor T1 and the ninth transistor T9 and the variation of the power supply voltage drop (IR Drop) of the system high voltage VDD, thereby increasing the consistency of the driving current. Furthermore, the ninth transistor T9 can be used to generate a constant current source CS to discharge the node voltage C, so that the voltage of the node voltage C gradually decreases to replace the ramp signal; by determining the value of the data voltage V _DATA , the conduction time of the eighth transistor T8 is controlled to achieve pulse width modulation driving to reduce the overall power consumption; and, the critical voltage variation of the first transistor T1 and the ninth transistor T9 and the power supply voltage drop (IR Drop) of the system high voltage VDD are compensated, effectively improving the stability of the luminous current.

In summary, in the pixel circuit of the embodiment of the present invention, the pulse width control block uses the data voltage and the current source to determine the single supply time of the driving current, that is, the current source is used to replace the external input ramp signal, which can simplify the relevant layout method of the pixel circuit and simplify the overall wiring cost of the panel.

Although the present invention has been disclosed as above by the embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the scope of the attached patent application.

100: Pixel circuit 110: Pulse amplitude control block 120: Reset block 130: Pulse width control block A, B, C, D: Node voltage C1: First capacitor C2: Second capacitor C3: Third capacitor CS: Current source EM[n]: Light emitting control signal Idr: Driving current LD1: Light emitting diode Pcmp: Compensation period Pem: Light emitting period Poff: Off period Prst: Reset period S1[n]: First control Signal S1[n+1]: Next level first control signal S2[n]: Second control signal T1: First transistor T10: Tenth transistor T11: Eleventh transistor T12: Twelfth transistor T13: Thirteenth transistor T14: Fourteenth transistor T2: Second transistor T3: Third transistor T4: Fourth transistor T5: Fifth transistor T6: Sixth transistor T7: Seventh transistor T8: Eighth transistor T9: Ninth transistor V _DATA : Data voltage VDD: System high voltage V _L : Low voltage V _REF : First reference voltage V _REF2 : Second reference voltage VSS: System low voltage

FIG1 is a circuit diagram of a pixel circuit according to an embodiment of the present invention. FIG2 is a driving waveform diagram of a pixel circuit according to an embodiment of the present invention.

100: Pixel circuit

110: Pulse amplitude control block

120: Reset block

130: Pulse width control block

A, B, C, D: node voltage

C1: first capacitor

C2: Second capacitor

C3: The third capacitor

CS: Current source

EM[n]: luminous control signal

Idr: driving current

LD1: Light Emitting Diode

S1[n]: first control signal

S1[n+1]: the first control signal of the next level

S2[n]: Second control signal

T1: First transistor

T10: The tenth transistor

T11: Eleventh transistor

T12: twelfth transistor

T13: Thirteenth transistor

T14: Fourteenth transistor

T2: Second transistor

T3: The third transistor

T4: The fourth transistor

T5: The fifth transistor

T6: Sixth transistor

T7: Seventh transistor

T8: The eighth transistor

T9: Ninth transistor

V _DATA : Data voltage

VDD: system high voltage

V _L : Low voltage

V _REF : First reference voltage

V _REF2 : Second reference voltage

VSS: System low voltage

Claims (8)

A pixel circuit includes: a light-emitting diode having an anode and a cathode receiving a system high voltage; a pulse amplitude control block coupled between the cathode of the light-emitting diode and a system low voltage and receiving a first reference voltage to control a driving current of the light-emitting diode based on the first reference voltage; a pulse width control block coupled to the pulse amplitude control block, receiving a data voltage and including a current source, wherein the pulse width control block controls the pulse amplitude control block based on the data voltage and the current source to determine a single supply time of the driving current; and A reset block is coupled to the pulse amplitude control block to set the state of the pulse amplitude control block. A pixel circuit as described in claim 1, wherein the pulse amplitude control block includes: a first transistor having a first end coupled to the cathode of the light-emitting diode, a control end, and a second end; a second transistor having a first end receiving a low voltage, a control end receiving a first control signal, and a second end coupled to the control end of the first transistor; a third transistor having a first end coupled to the second end of the first transistor, a control end receiving a light-emitting control signal, and a second end receiving the system low voltage; a fourth transistor having a first end, a control end receiving the light-emitting control signal, and a second end coupled to the cathode of the light-emitting diode; a first capacitor coupled between the control end of the first transistor and the first end of the fourth transistor; a fifth transistor having a first end receiving the first reference voltage, a control end receiving a second control signal, and a second end coupled to the first end of the fourth transistor; and a sixth transistor having a first end coupled to the control end of the first transistor, a control end receiving a third control signal, and a second end coupled to the second end of the first transistor. The pixel circuit as described in claim 2, wherein the reset block includes: A seventh transistor having a first end coupled to the cathode of the light-emitting diode, a control end receiving the third control signal, and a second end receiving a second reference voltage. The pixel circuit as described in claim 3, wherein the pulse width control block includes: an eighth transistor having a first end coupled to the control end of the first transistor, a control end, and a second end receiving the second reference voltage; a second capacitor coupled between the control end of the eighth transistor and the second reference voltage; a ninth transistor, serving as the current source, having a first end, a control end, and a second end receiving the low voltage; a third capacitor coupled between the control end of the eighth transistor and the control end of the ninth transistor; a tenth transistor having a first end coupled to the control end of the eighth transistor, a control end receiving the light control signal, and a second end coupled to the first end of the ninth transistor; An eleventh transistor having a first end receiving the first reference voltage, a control end receiving the second control signal, and a second end coupled to the control end of the eighth transistor; A twelfth transistor having a first end receiving the low voltage, a control end receiving the first control signal, and a second end coupled to the control end of the ninth transistor; A thirteenth transistor having a first end, a control end receiving the third control signal, and a second end coupled to the control end of the ninth transistor; and A fourteenth transistor having a first end receiving the data voltage, a control end coupled to the first end of the thirteenth transistor, and a second end coupled to the first end of the thirteenth transistor. A pixel circuit as described in claim 4, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor and the fourteenth transistor are each a P-type transistor. A pixel circuit as described in claim 4, wherein the channel length ratio of the ninth transistor is the same as the channel length ratio of the fourteenth transistor. A pixel circuit as described in claim 2, wherein the third control signal is the first control signal of the next level. A pixel circuit as described in claim 1, wherein the light-emitting diode comprises a micro light-emitting diode.

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