TW202408105A - Process method and produced structure of low series resistance high-speed surface-emitting laser to optimize and reduce the series resistance value to avoid the problem of over-corrosion and ensure the accuracy of the resistance value - Google Patents
Process method and produced structure of low series resistance high-speed surface-emitting laser to optimize and reduce the series resistance value to avoid the problem of over-corrosion and ensure the accuracy of the resistance value Download PDFInfo
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本發明涉及一種VCSEL（Vertical Cavity Surface Emitting Laser,面射型雷射）元件之製程技術領域，特別涉及一種低串聯電阻高速面射型雷射之製程方法及其製成結構。The present invention relates to the technical field of manufacturing VCSEL (Vertical Cavity Surface Emitting Laser, surface-emitting laser) components, and in particular to a manufacturing method of a low series resistance high-speed surface-emitting laser and its manufacturing structure.
VCSEL元件泛屬LD（Laser Diode, 半導體雷射）元件的一種，其結構由下而上一般係依序包含有一基板、一下DBR（Distributed Bragg Reflector, 分佈式布拉格反射鏡）層、一共振腔體、一上DBR層及一組正負極金屬接觸層，以利用高反射率之DBR產生共振腔而使雷射光由晶粒表面垂直發射出來。只是，高反射率之DBR是用兩種不同折射率的材料交互堆疊而成，除有反射率分布曲線尖銳的問題外，亦有因晶體介面上明顯能隙差異而造成串聯電阻過大的情況存在。而，為因應高速數據傳輸的市場需求，習知製程技術係相應調整該組正負極金屬接觸層的設置結構，例如，可將該負極金屬接觸層設置於該基板上方鄰接處或該下DBR層上方鄰接處等兩種位置，據此以實現調整整體元件電流路徑所對應之元件串聯電阻阻值的效果。VCSEL elements are generally a type of LD (Laser Diode, semiconductor laser) element. Its structure generally includes a substrate, a DBR (Distributed Bragg Reflector, distributed Bragg reflector) layer, and a resonant cavity in sequence from bottom to top. , an upper DBR layer and a set of positive and negative metal contact layers to use the high reflectivity DBR to generate a resonant cavity to emit laser light vertically from the surface of the crystal grain. However, high-reflectivity DBR is made of two materials with different refractive indexes stacked alternately. In addition to the problem of sharp reflectivity distribution curves, there are also situations where the series resistance is too large due to the obvious energy gap difference on the crystal interface. . However, in order to meet the market demand for high-speed data transmission, the conventional process technology adjusts the arrangement structure of the set of positive and negative metal contact layers accordingly. For example, the negative metal contact layer can be arranged adjacent to the upper part of the substrate or the lower DBR layer. There are two positions, such as the upper adjacent position, to achieve the effect of adjusting the resistance value of the series resistor of the component corresponding to the current path of the overall component.
由此可知，習知製程技術中，為設置該負極金屬接觸層係需先蝕刻掉該上DBR層、該共振腔體及甚至該下DBR層，但於蝕刻製程中卻常有蝕刻深度無法精準控制及批次蝕刻時深度差異無法再現的問題存在，即使使用監控系統來控制蝕刻停止時點，也會因反應腔內存留有蝕刻氣體或蝕刻溶液而造成過蝕的情況，進而致使元件串聯阻值存在有高誤差值的詬病。如此，對於現今不斷追求高速及高流量傳輸的互聯網運作模式而言，不穩定的元件品質將可能造成整體互聯網系統的訊息調制效率及傳輸速度受限制，實不利於產業發展的進程。It can be seen from this that in the conventional process technology, in order to set up the negative electrode metal contact layer, the upper DBR layer, the resonant cavity and even the lower DBR layer need to be etched away first. However, in the etching process, the etching depth is often not accurate. There is a problem that the depth difference cannot be reproduced during control and batch etching. Even if a monitoring system is used to control the etching stop time, over-etching will occur due to the etching gas or etching solution remaining in the reaction chamber, which will lead to the series resistance of the components. There are criticisms of high error values. In this way, for today's Internet operation model that constantly pursues high-speed and high-traffic transmission, unstable component quality may cause the information modulation efficiency and transmission speed of the overall Internet system to be limited, which is really detrimental to the process of industrial development.
有感於此，如何透過製程改善而縮小VCSEL元件的串聯電阻阻值誤差範圍，藉以改善上述習知技術之缺失，且進一步地，得依據元件規格需求，同時調整元件中正極及負極金屬接觸層的設置位置而達最佳化低串聯電阻阻值的效果，即為本發明所欲探究之課題。In view of this, how to narrow the error range of the series resistance of VCSEL components through process improvement, thereby improving the deficiencies of the above-mentioned conventional technology, and further, according to the requirements of component specifications, the positive and negative metal contact layers in the component can be adjusted at the same time The setting position to optimize the effect of low series resistance is the subject of the present invention.
本發明之主要目的在於提供一種低串聯電阻高速面射型雷射之製程方法及其製成結構，以透過蝕刻停止層的應用而改善蝕刻製程中過蝕問題，據此而精確掌控元件中正負極金屬接觸層之設置位置並達高穩定元件品質的效益。The main purpose of the present invention is to provide a low series resistance high-speed surface-emitting laser manufacturing method and its manufacturing structure, so as to improve the over-etching problem in the etching process through the application of an etching stop layer, and thereby accurately control the positive and negative electrodes of the component. The location of the metal contact layer achieves the benefit of high and stable component quality.
為實現上述目的，本發明係揭露一種低串聯電阻高速面射型雷射之製程方法，係包含下列步驟：磊晶形成一半導體結構，其由下而上堆疊有一基板、一下DBR層、一共振腔體及一上DBR層，且該上DBR層設有22～30個上雙層堆疊對，該下DBR層設有32～40個下雙層堆疊對；設置重摻雜之一第一停止層及一第二停止層，係依據一預設阻值於鄰近該共振腔體之上下方處分別選定該第一停止層之設置位置及該第二停止層之設置位置，其中該第一停止層之設置位置位於該上DBR層區域中擇一位置穿插或取代該上DBR層之部分或該上DBR層下方鄰接處，該第二停止層之設置位置位於該下DBR層上方鄰接處或該下DBR層區域中擇一位置穿插或取代該下DBR層之部分，據此以透過該第一停止層之設置位置及該第二停止層之設置位置最佳化地降低該串聯電阻之阻值大小；於該半導體結構之環側設置一負極金屬接觸區，並對應該負極金屬接觸區位置由上而下蝕刻至該第二停止層而使該半導體結構中央部位形成一第一高台；於該第一高台之一側設置一正極金屬接觸區，並對應該正極金屬接觸區位置由上而下蝕刻至該第一停止層而使該第一高台上部位形成一第二高台，且該第二高台面積小於該第一高台；及分別設置一正極金屬接觸層於該第一停止層上，及設置一負極金屬接觸層於該第二停止層上。In order to achieve the above object, the present invention discloses a low series resistance high-speed surface-emitting laser manufacturing method, which includes the following steps: epitaxially forming a semiconductor structure, which is stacked from bottom to top with a substrate, a DBR layer, and a resonance Cavity and an upper DBR layer, and the upper DBR layer is provided with 22 to 30 upper double-layer stacking pairs, and the lower DBR layer is provided with 32 to 40 lower double-layer stacking pairs; a first stop for heavy doping is provided layer and a second stop layer, and the first stop layer and the second stop layer are respectively selected based on a preset resistance value above and below the resonant cavity, where the first stop layer The layer is located at a location in the area of the upper DBR layer that intersects or replaces part of the upper DBR layer or is adjacent to the lower DBR layer. The second stop layer is located at an adjacent location above or adjacent to the lower DBR layer. Select a position in the lower DBR layer area to intersperse or replace a portion of the lower DBR layer, thereby optimally reducing the resistance of the series resistor through the position of the first stop layer and the position of the second stop layer. Size; a negative metal contact area is provided on the ring side of the semiconductor structure, and the negative metal contact area is etched from top to bottom to the second stop layer to form a first platform in the center of the semiconductor structure; A positive metal contact area is provided on one side of the first platform, and the positive metal contact area is etched from top to bottom to the first stop layer to form a second platform on the first platform, and the second platform is etched from top to bottom to the first stop layer. The area of the high platform is smaller than the first high platform; and a positive metal contact layer is provided on the first stop layer, and a negative metal contact layer is provided on the second stop layer.
其中，該第一停止層及該第二停止層係採用InP、InGaP、GaAsP或AlGaAsP之含磷材料且採n/p重摻雜，以降低蝕刻速率而提升該正極金屬接觸層及該負極金屬接觸層的設置位置精準性，進而確保該串聯電阻之阻值精確性。各該上雙層堆疊對分別為Al (0.9)Ga (0.1)As/Al (0.1)Ga (0.9)As堆疊結構，而設置該第一停止層時，該等上雙層堆疊對之其中一對係由In (x)Ga (1-x)P/Al (0.1)Ga (0.9)As結構所取代；各該下雙層堆疊對分別為Al (0.9)Ga (0.1)As/Al (0.1)Ga (0.9)As堆疊結構，而設置該第二停止層時，該等下雙層堆疊對之其中一對係由In (x)Ga (1-x)P/Al (0.1)Ga (0.9)As結構所取代，且X為0.56～0.71。於該半導體結構之環側設置該負極金屬接觸區，並對應該負極金屬接觸區位置利用乾蝕刻法由上而下蝕刻該上DBR層、該第一停止層及該共振腔體至鄰近該第二停止層上方處後，利用濕蝕刻法蝕刻該第二停止層上方剩餘部位至該第二停止層，使該半導體結構中央部位形成該第一高台；接著，對該第一高台進行一氧化作業，以使該共振腔體中一氧化層側邊氧化而形成有一氧化孔洞，且於該第一高台之一側設置該正極金屬接觸區，並對應該正極金屬接觸區位置利用乾蝕刻法由上而下蝕刻該上DBR層至鄰近該第一停止層上方處，再利用濕蝕刻法蝕刻剩餘部位至該第一停止層，而使該第一高台上部位形成該第二高台。 Among them, the first stop layer and the second stop layer are made of phosphorus-containing materials such as InP, InGaP, GaAsP or AlGaAsP and are heavily n/p doped to reduce the etching rate and increase the positive electrode metal contact layer and the negative electrode metal. The contact layer is positioned accurately to ensure the accuracy of the resistance value of the series resistor. Each upper double-layer stacked pair is an Al (0.9) Ga (0.1) As/Al (0.1) Ga (0.9) As stacked structure, and when the first stop layer is provided, one of the upper double-layer stacked pairs The pairs are replaced by In (x) Ga (1-x) P/Al (0.1) Ga (0.9) As structures; the lower double-layer stack pairs are Al (0.9) Ga ( 0.1) As/Al (0.1 ) Ga (0.9) As stack structure, and when the second stop layer is provided, one of the lower double-layer stack pairs is composed of In (x) Ga (1-x) P/Al (0.1) Ga (0.9 ) replaced by As structure, and X is 0.56~0.71. The negative metal contact area is provided on the ring side of the semiconductor structure, and the upper DBR layer, the first stop layer and the resonant cavity are etched from top to bottom using a dry etching method to adjacent to the third After placing above the second stop layer, wet etching is used to etch the remaining portion above the second stop layer to the second stop layer, so that the first platform is formed in the center of the semiconductor structure; then, an oxidation operation is performed on the first platform , so as to oxidize the side of an oxide layer in the resonant cavity to form an oxidation hole, and set the positive metal contact area on one side of the first platform, and use dry etching method to position the positive metal contact area from above Then, the upper DBR layer is etched to a position adjacent to the first stop layer, and then the remaining portion is etched to the first stop layer using a wet etching method, so that the first elevated platform portion forms the second elevated platform.
並且，利用濕蝕刻法蝕刻至該停止層時係使用NH 4OH：H 2O 2蝕刻液。利用濕蝕刻法蝕刻至該停止層時係使用配方比例1：10的NH 4OH：H 2O 2蝕刻液。利用濕蝕刻法蝕刻採用InGaAsP材料之該第一停止層及該第二停止層時，係使用HCL：H 3PO 4蝕刻液。利用濕蝕刻法蝕刻採用InP或InGaP材料之該第一停止層及該第二停止層時，係使用H 3PO 4：H 2O 2：H 2O蝕刻液。利用濕蝕刻法蝕刻採用InP材料之該第一停止層及該第二停止層時，係使用H 2SO 4：H 2O 2：H 2O蝕刻液或C 6H 8O 7：H 2O 2蝕刻液。 Furthermore, when etching to the stop layer by wet etching, an NH 4 OH:H 2 O 2 etching liquid is used. When etching to the stop layer by wet etching, a NH 4 OH: H 2 O 2 etching solution with a formula ratio of 1:10 is used. When using the wet etching method to etch the first stop layer and the second stop layer made of InGaAsP material, HCL:H 3 PO 4 etching liquid is used. When using wet etching to etch the first stop layer and the second stop layer made of InP or InGaP material, H 3 PO 4 :H 2 O 2 :H 2 O etching liquid is used. When using the wet etching method to etch the first stop layer and the second stop layer using InP material, use H 2 SO 4 : H 2 O 2 : H 2 O etching solution or C 6 H 8 O 7 : H 2 O 2 etching liquid.
另外，為實現次一目的，本發明更揭露一種利用如上述之製程方法製作而成的高速面射型雷射結構。In addition, to achieve the second object, the present invention further discloses a high-speed surface-emitting laser structure manufactured using the above-mentioned manufacturing method.
綜上所述，本發明係利用含磷材料之該等停止層搭配相應的蝕刻溶液來實現減緩磊晶層蝕刻速率的目的，以解決該上DBR層及該下DBR層於蝕刻製程中過蝕的問題，據此而精確掌控該等正負極金屬接觸層之該設置位置而達提升整體VCSEL結構品質穩定性的功效。並且，本發明依據該預設阻值於該共振腔體上下方鄰近處來選定該第一停止層及該第二停止層之設置位置的作業手段，係可使該VCSEL結構具客製化的最佳化低串聯阻值而便利後續應用系統的配置，進而提升產品實用效益並滿足市場應用需求。順帶一提的是，該第一停止層置入該上DBR層及該第二停止層置入該下DBR層時，若使用In (x)Ga (1-x)P/Al (0.1)Ga (0.9)As結構取代原先Al (0.9)Ga (0.1)As/Al (0.1)Ga (0.9)As結構之雙層堆疊對時，可能有載子濃度差 變小而影響此層堆疊對反射率的疑慮，然，因本發明係使該上DBR層設有22～30個上雙層堆疊對，該下DBR層設有32～40個下雙層堆疊對，故對上下DBR層而言仍可維持整體＞99%的反射率，亦即不影響整體元件的發光效率。 To sum up, the present invention uses the stop layers of phosphorus-containing materials and the corresponding etching solution to achieve the purpose of slowing down the etching rate of the epitaxial layer, so as to solve the problem of over-etching of the upper DBR layer and the lower DBR layer during the etching process. problem, based on which the placement positions of the positive and negative metal contact layers can be precisely controlled to improve the quality and stability of the overall VCSEL structure. Moreover, the present invention selects the arrangement positions of the first stop layer and the second stop layer based on the preset resistance value near the upper and lower parts of the resonant cavity, which enables the VCSEL structure to be customized. Optimizing low series resistance facilitates the configuration of subsequent application systems, thereby improving product practical benefits and meeting market application needs. By the way, when the first stop layer is placed in the upper DBR layer and the second stop layer is placed in the lower DBR layer, if In (x) Ga (1-x) P/Al (0.1) Ga is used (0.9) As structure replaces the original Al (0.9) Ga (0.1) As/Al (0.1) Ga (0.9) As structure double-layer stacking pair, there may be a carrier concentration difference However, the present invention makes the upper DBR layer provided with 22 to 30 upper double-layer stack pairs, and the lower DBR layer is provided with 32 to 40 lower double-layer stack pairs. Yes, so the overall reflectivity of >99% can still be maintained for the upper and lower DBR layers, which means it does not affect the luminous efficiency of the overall device.
為使本領域具有通常知識者能清楚了解本新型之內容，謹以下列說明搭配圖式，敬請參閱。In order to enable those with ordinary knowledge in the field to clearly understand the contents of the present invention, the following description is accompanied by the drawings, please refer to them.
請參閱第1、2圖，其係分別為本發明一較佳實施例之流程圖及結構示意圖。如圖所示，該低串聯電阻高速面射型雷射之製程方法係包含下列步驟：步驟S10，磊晶形成一半導體結構10，其由下而上至少堆疊有一基板100、一下DBR層101、一共振腔體102及一上DBR層103，且該上DBR層103設有22～30個上雙層堆疊對1030，該下DBR層101設有32～40個下雙層堆疊對1010；步驟S11，設置重摻雜之一第一停止層104及一第二停止層105，係依據一預設阻值於鄰近該共振腔體102之上下方處分別選定該第一停止層104之設置位置及該第二停止層105之設置位置，其中該第一停止層104之設置位置位於該上DBR層103區域中擇一位置穿插或取代該上DBR層103之部分，或者，該第一停止層104之設置位置位於該上DBR層103下方鄰接處，而該第二停止層105之設置位置位於該下DBR層101上方鄰接處，或者，該第二停止層105之設置位置位於該下DBR層101區域中擇一位置穿插或取代該下DBR層101之部分，據此以透過該第一停止層104之設置位置及該第二停止層105之設置位置最佳化地降低該串聯電阻之阻值大小；步驟S12，於該半導體結構之環側設置一負極金屬接觸區，並對應該負極金屬接觸區位置由上而下蝕刻至該第二停止層105而使該半導體結構中央部位形成一第一高台11；步驟S13，於該第一高台11之一側設置一正極金屬接觸區，並對應該正極金屬接觸區位置由上而下蝕刻至該第一停止層104而使該第一高台11上部位形成一第二高台12，且該第二高台12面積小於該第一高台11；及步驟S14，分別設置一正極金屬接觸層106於該第一停止層104上，及設置一負極金屬接觸層107於該第二停止層105上。Please refer to Figures 1 and 2, which are respectively a flow chart and a schematic structural diagram of a preferred embodiment of the present invention. As shown in the figure, the low series resistance high-speed surface-emitting laser manufacturing method includes the following steps: Step S10, epitaxially forming a semiconductor structure 10, which is stacked from bottom to top with at least one substrate 100, a DBR layer 101, A resonant cavity 102 and an upper DBR layer 103, and the upper DBR layer 103 is provided with 22 to 30 upper double-layer stacking pairs 1030, and the lower DBR layer 101 is provided with 32 to 40 lower double-layer stacking pairs 1010; steps S11, a heavily doped first stop layer 104 and a second stop layer 105 are provided, and the placement positions of the first stop layer 104 are selected respectively above and below adjacent to the resonant cavity 102 based on a preset resistance value. And the setting position of the second stop layer 105, wherein the setting position of the first stop layer 104 is located in the area of the upper DBR layer 103, interspersing or replacing the part of the upper DBR layer 103, or, the first stop layer 104 is located adjacent to the lower part of the upper DBR layer 103, and the second stop layer 105 is located adjacent to the upper part of the lower DBR layer 101, or the second stop layer 105 is located at the lower DBR layer. Select a position in the area 101 to intersperse or replace a portion of the lower DBR layer 101, thereby optimally reducing the resistance of the series resistor through the position of the first stop layer 104 and the position of the second stop layer 105. value; step S12, set a negative metal contact area on the ring side of the semiconductor structure, and etch the negative metal contact area from top to bottom to the second stop layer 105 to form a first stop layer in the center of the semiconductor structure. A high platform 11; step S13, a positive metal contact area is provided on one side of the first high platform 11, and the position of the positive metal contact area is etched from top to bottom to the first stop layer 104 to make the first high platform 11 A second high platform 12 is formed on the upper part, and the area of the second high platform 12 is smaller than that of the first high platform 11; and step S14, a positive metal contact layer 106 is respectively set on the first stop layer 104, and a negative metal contact is set Layer 107 is on the second stop layer 105 .
由此可知，利用該製程方法製作而成之一高速面射型雷射結構1由下而上至少設有該基板100、該下DBR層101、該第二停止層105、該共振腔體102、該第一停止層104及該上DBR層103，於該第二停止層105之上之該高速面射型雷射結構1中央部位形成有該第一高台11，且該第一高台11上部位形成有面積相對較小之該第二高台12，而該第一高台11一側旁之該第二停止層105上係設有該負極金屬接觸層107，該第二高台12旁之該第一停止層104上設有該正極金屬接觸層106。其中，該第一停止層104之設置位置位於該上DBR層103區域中擇一位置穿插或取代該上DBR層103之部分、或該上DBR層103下方鄰接處，該第二停止層105之設置位置位於該下DBR層101上方鄰接處、或該下DBR層101區域中擇一位置穿插或取代該下DBR層101之部分，據此以透過設置於該共振腔體102鄰近處之該第一停止層104之設置位置及該第二停止層105之設置位置而達最佳化地降低該串聯電阻阻值大小的效果。It can be seen from this that a high-speed surface-emitting laser structure 1 produced by this process method is provided with at least the substrate 100, the lower DBR layer 101, the second stop layer 105, and the resonant cavity 102 from bottom to top. , the first stop layer 104 and the upper DBR layer 103, the first platform 11 is formed in the center of the high-speed surface-emitting laser structure 1 above the second stop layer 105, and the first platform 11 is The second platform 12 with a relatively small area is formed at the position, and the negative metal contact layer 107 is provided on the second stop layer 105 on one side of the first platform 11. The positive metal contact layer 106 is disposed on a stop layer 104 . Wherein, the first stop layer 104 is located at a location in the area of the upper DBR layer 103 that intersects or replaces the upper DBR layer 103, or is adjacent below the upper DBR layer 103, and the second stop layer 105 is The location is located adjacent to the upper part of the lower DBR layer 101, or a location in the area of the lower DBR layer 101 intersperses or replaces a part of the lower DBR layer 101, thereby passing through the third part of the lower DBR layer 101 located adjacent to the resonant cavity 102. The arrangement position of a stop layer 104 and the arrangement position of the second stop layer 105 achieve the effect of optimally reducing the resistance value of the series resistor.
請參閱第3、4A～4D圖，其係分別為本發明二較佳實施例之流程圖及流程示意圖。如圖所示，該高速面射型雷射結構1之一半導體結構10一般係主要包含有一基板100、一下DBR層101、一共振腔體102及一上DBR層103，據此，為改善歐姆接觸以達最佳化之低串聯電阻高速面射型雷射之該製程方法可包含下列步驟：步驟S20，依據一預設阻值，分別選定n/p型重摻雜之一第一停止層104及一第二停止層105於該半導體結構10中鄰近該共振腔體102上下方處之一設置位置而形成一設計結構，且該第一停止層104之設置位置可位於該上DBR層103區域中擇一位置穿插或取代該上DBR層103之部分、或該上DBR層103下方鄰接處；該第二停止層105之設置位置位於該下DBR層101上方鄰接處、或該下DBR層101區域中擇一位置穿插或取代該下DBR層101之部分，以供透過該第一停止層104及該第二停止層105之設置位置進一步決定後續製程中一正極金屬接觸層106及一負極金屬接觸層107之設置位置。Please refer to Figures 3 and 4A to 4D, which are respectively flow charts and flow schematic diagrams of two preferred embodiments of the present invention. As shown in the figure, the semiconductor structure 10 of the high-speed surface-emitting laser structure 1 generally mainly includes a substrate 100, a lower DBR layer 101, a resonant cavity 102 and an upper DBR layer 103. Accordingly, in order to improve the ohmic The process method of contacting to achieve optimized low series resistance high-speed surface-emitting laser may include the following steps: Step S20: Select one of the n/p-type heavily doped first stop layers according to a preset resistance value. 104 and a second stop layer 105 in the semiconductor structure 10 adjacent to a position above and below the resonant cavity 102 to form a design structure, and the position of the first stop layer 104 can be located on the upper DBR layer 103 Select a position in the area to intersperse or replace the part of the upper DBR layer 103, or the adjacent part below the upper DBR layer 103; the second stop layer 105 is located at the upper adjacent part of the lower DBR layer 101, or the lower DBR layer Select a position in the 101 area to intersperse or replace a portion of the lower DBR layer 101 to further determine a positive metal contact layer 106 and a negative electrode in the subsequent process through the placement of the first stop layer 104 and the second stop layer 105 The location of the metal contact layer 107.
步驟S21，依據上述設計結構，磊晶形成該半導體結構10，其由下而上至少堆疊有該基板100、該下DBR層101、該第二停止層105、該共振腔體102、該第一停止層104及該上DBR層103，且該共振腔體102由下而上至少可設有一下批覆層1020、一主動層1021、一上批覆層1022、一氧化層1023及一上隔離層1024。該上DBR層103設有22～30個上雙層堆疊對1030，該下DBR層101設有32～40個下雙層堆疊對1010。各該上雙層堆疊對1030分別為Al (0.9)Ga (0.1)As/Al (0.1)Ga (0.9)As堆疊結構，而該第一停止層104採用InP、InGaP、GaAsP或AlGaAsP之含磷材料製成，故設置該第一停止層104時，該等上雙層堆疊對1030之其中一對可能由In (x)Ga (1-x)P/Al (0.1)Ga (0.9)As結構所取代，X為0.56～0.71；各該下雙層堆疊對1010分別為Al (0.9)Ga (0.1)As/Al (0.1)Ga (0.9)As堆疊結構，且該第二停止層105亦採用InP、InGaP、GaAsP或AlGaAsP之含磷材料製成，故設置該第二停止層105時，該等下雙層堆疊對1010之其中一對由In (x)Ga (1-x)P/Al (0.1)Ga (0.9)As結構所取代，X為0.56～0.71。 Step S21, based on the above design structure, the semiconductor structure 10 is epitaxially formed, which is stacked from bottom to top with at least the substrate 100, the lower DBR layer 101, the second stop layer 105, the resonant cavity 102, and the first The stop layer 104 and the upper DBR layer 103, and the resonant cavity 102 can be provided with at least a lower cladding layer 1020, an active layer 1021, an upper cladding layer 1022, an oxide layer 1023 and an upper isolation layer 1024 from bottom to top. . The upper DBR layer 103 is provided with 22-30 upper double-layer stacking pairs 1030, and the lower DBR layer 101 is provided with 32-40 lower double-layer stacking pairs 1010. Each of the upper double-layer stack pairs 1030 is an Al (0.9) Ga (0.1) As/Al (0.1) Ga (0.9) As stack structure, and the first stop layer 104 is made of InP, InGaP, GaAsP or AlGaAsP containing phosphorus. material, so when the first stop layer 104 is provided, one of the upper double-layer stack pairs 1030 may be made of In (x) Ga (1-x) P/Al (0.1) Ga (0.9) As structure Replaced , It is made of phosphorus-containing materials such as InP, InGaP, GaAsP or AlGaAsP. Therefore, when the second stop layer 105 is provided, one of the lower double-layer stack pairs 1010 is made of In (x) Ga (1-x) P/Al (0.1) Ga (0.9) As structure substituted, X is 0.56~0.71.
步驟S22，於該半導體結構10環側設置一負極金屬接觸區13，並對應該負極金屬接觸區13位置利用乾蝕刻法由上而下蝕刻該上DBR層103、該第一停止層104及該共振腔體102至鄰近該第二停止層105上方處後，步驟S220，利用如配方比例1：10的NH 4OH：H 2O 2之蝕刻液濕蝕刻該第二停止層105上方剩餘的垂直結構部位至該第二停止層105，使該半導體結構10中央部位形成一第一高台11。步驟S23，對該第一高台11進行一氧化作業，以使該共振腔體102中該氧化層1023因其含鋁量高而側邊氧化形成有一氧化孔洞10230。步驟S24，於該第一高台11之一側設置一正極金屬接觸區14，並對應該正極金屬接觸區14位置利用乾蝕刻法由上而下蝕刻該上DBR層103至鄰近該第一停止層104上方處，再於步驟S240中，利用如配方比例1：10的NH 4OH：H 2O 2之蝕刻液濕蝕刻該第一停止層104上方剩餘的垂直結構部位至該第一停止層104，使該第一高台11上部位形成面積較該第一高台11小之一第二高台12。於本實施例中，當該第一停止層104及該第二停止層105採用InGaAsP材料時，更可使用HCL：H 3PO 4蝕刻液進行濕蝕刻；該第一停止層104及該第二停止層105採用InP或InGaP材料時，更可使用H 3PO 4：H 2O 2：H 2O蝕刻液進行濕蝕刻；該第一停止層104及該第二停止層105採用InP材料時，更可使用H 2SO 4：H 2O 2：H 2O蝕刻液或C 6H 8O 7：H 2O 2蝕刻液進行濕蝕刻。 Step S22, a negative metal contact area 13 is provided on the ring side of the semiconductor structure 10, and the upper DBR layer 103, the first stop layer 104 and the upper DBR layer 103, the first stop layer 104 and the negative metal contact area 13 are etched from top to bottom using a dry etching method. After the resonant cavity 102 reaches the position adjacent to the second stop layer 105, in step S220, the remaining vertical areas above the second stop layer 105 are wet-etched using an etching solution of NH 4 OH: H 2 O 2 with a formula ratio of 1:10. The structure portion reaches the second stop layer 105, so that a first platform 11 is formed in the central portion of the semiconductor structure 10. In step S23, an oxidation operation is performed on the first high platform 11, so that the side of the oxide layer 1023 in the resonance cavity 102 due to its high aluminum content is oxidized to form an oxidation hole 10230. Step S24, a positive metal contact area 14 is provided on one side of the first platform 11, and the upper DBR layer 103 is etched from top to bottom using a dry etching method at the position of the positive metal contact area 14 to be adjacent to the first stop layer. Above the first stop layer 104, in step S240, the remaining vertical structural parts above the first stop layer 104 are wet-etched to the first stop layer 104 using an etching solution of NH 4 OH: H 2 O 2 with a formula ratio of 1:10. , so that the upper part of the first high platform 11 forms a second high platform 12 with an area smaller than that of the first high platform 11 . In this embodiment, when the first stop layer 104 and the second stop layer 105 are made of InGaAsP material, HCL: H 3 PO 4 etchant can be used for wet etching; When the stop layer 105 is made of InP or InGaP material, H 3 PO 4 : H 2 O 2 : H 2 O etching solution can be used for wet etching; when the first stop layer 104 and the second stop layer 105 are made of InP material, Wet etching can also be carried out using H 2 SO 4 : H 2 O 2 : H 2 O etching solution or C 6 H 8 O 7 : H 2 O 2 etching solution.
步驟S25，設置該正極金屬接觸層106於該第一停止層104上的同時，步驟S26，設置該負極金屬接觸層107於該第二停止層104上。據此，透過採用含磷材料之該第一停止層104及該第二停止層105與蝕刻液間的化學作用，即減緩了蝕刻速率而可避免蝕刻製程中該上DBR層103及該下DBR層101的過蝕問題，進而提升該正極金屬接觸層106及該負極金屬接觸層107的設置位置精準性，進而達確保由該正極金屬接觸層106至該負極金屬接觸層107之元件電流路徑所對應之該串聯電阻阻值恆定的功效。承上所述，利用該製程方法製作而成之該高速面射型雷射結構1之元件串聯電阻阻值（R）在不計電容值的前提下，可如圖5所示為R=R1+R2+R3，且R1及R3因該第一停止層104及該第二停止層105採n/p重摻雜設置而呈低電阻阻值，故有益於降低該串聯電阻整體阻值。據此，以該共振腔體102鄰近處為該第一停止層104及該第二停止層105之設置範圍時，透過此兩者間的設置距離調整，即可隨之微調串聯阻值大小，進而使該高速面射型雷射結構1具有最佳化之低串聯阻值的特色而適應市場需求。In step S25, the positive metal contact layer 106 is disposed on the first stop layer 104, and in step S26, the negative metal contact layer 107 is disposed on the second stop layer 104. Accordingly, through the chemical interaction between the first stop layer 104 and the second stop layer 105 using phosphorus-containing materials and the etching liquid, the etching rate is slowed down and the upper DBR layer 103 and the lower DBR layer can be avoided during the etching process. The over-etching problem of the layer 101 is thereby improved to improve the placement accuracy of the positive metal contact layer 106 and the negative metal contact layer 107, thereby ensuring the component current path from the positive metal contact layer 106 to the negative metal contact layer 107. Correspondingly, the resistance of the series resistor is constant. Following the above, the series resistance (R) of the component of the high-speed surface-emitting laser structure 1 produced by this process method, excluding the capacitance value, can be as shown in Figure 5: R=R1+ R2+R3, and R1 and R3 have a low resistance value because the first stop layer 104 and the second stop layer 105 are n/p heavily doped, so it is beneficial to reduce the overall resistance value of the series resistor. Accordingly, when the first stop layer 104 and the second stop layer 105 are located near the resonant cavity 102, the series resistance can be fine-tuned by adjusting the distance between them. Furthermore, the high-speed surface-emitting laser structure 1 has the characteristics of optimized low series resistance and adapts to market demand.
惟，以上所述者，僅為本發明之較佳實施例而已，並非用以限定本發明實施之範圍；故在不脫離本發明之精神與範圍下所作之均等變化與修飾，皆應涵蓋於本發明之專利範圍內。However, the above are only preferred embodiments of the present invention and are not intended to limit the scope of the present invention; therefore, equal changes and modifications made without departing from the spirit and scope of the present invention should be included in within the patent scope of this invention.
S10～S14:步驟 S20～S26:步驟 1:高速面射型雷射結構 10:半導體結構 100:基板 101:下DBR層 1010:下雙層堆疊對 102:共振腔體 1020:下批覆層 1021:主動層 1022:上批覆層 1023:氧化層 10230:氧化孔洞 1024:隔離層 103:上DBR層 1030:上雙層堆疊對 104:第一停止層 105:第二停止層 106:正極金屬接觸層 107:負極金屬接觸層 11:第一高台 12:第二高台 13:負極金屬接觸區 14:正極金屬接觸區 S10～S14: steps S20～S26: steps 1: High-speed surface-emitting laser structure 10: Semiconductor structure 100:Substrate 101: Lower DBR layer 1010: Lower double layer stacking pair 102: Resonance cavity 1020: Next batch of cladding layer 1021:Active layer 1022: Previous batch of cladding 1023:Oxide layer 10230: Oxidized holes 1024:Isolation layer 103: Go to DBR layer 1030: Upper double layer stacking pair 104: First stop layer 105: Second stop layer 106: Positive metal contact layer 107: Negative metal contact layer 11:The first high platform 12:The second high platform 13: Negative metal contact area 14: Positive metal contact area
第1圖，為本發明一較佳實施例之流程圖。 第2圖，為本發明一較佳實施例之結構示意圖。 第3圖，為本發明二較佳實施例之流程圖。 第4A～4D圖，為本發明二較佳實施例之流程示意圖。 第5圖，為本發明二較佳實施例之串聯電阻阻態示意圖。 Figure 1 is a flow chart of a preferred embodiment of the present invention. Figure 2 is a schematic structural diagram of a preferred embodiment of the present invention. Figure 3 is a flow chart of the second preferred embodiment of the present invention. Figures 4A to 4D are flow diagrams of two preferred embodiments of the present invention. Figure 5 is a schematic diagram of the resistance state of the series resistor in the second preferred embodiment of the present invention.
S10~S14:步驟 S10~S14: Steps
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