TW202406039A - 用於晶片對晶圓裝置之形成有底部填充阻擋件的半導體裝置及方法 - Google Patents

用於晶片對晶圓裝置之形成有底部填充阻擋件的半導體裝置及方法 Download PDF

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TW202406039A
TW202406039A TW112119555A TW112119555A TW202406039A TW 202406039 A TW202406039 A TW 202406039A TW 112119555 A TW112119555 A TW 112119555A TW 112119555 A TW112119555 A TW 112119555A TW 202406039 A TW202406039 A TW 202406039A
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semiconductor
semiconductor die
barrier wall
underfill material
semiconductor device
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TW112119555A
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English (en)
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金禹淳
崔峻榮
金永澈
金勁吾
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新加坡商星科金朋私人有限公司
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Publication of TW202406039A publication Critical patent/TW202406039A/zh

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Abstract

一種半導體裝置，其具有半導體晶粒，半導體晶粒具有敏感區域。阻擋壁在半導體晶粒上方靠近敏感區域形成。在實施例中，阻擋壁具有垂直區段及側翼。阻擋壁能具有與複數個垂直區段整合為一單體本體之複數個圓形區段。替代地，阻擋壁具有以兩個或多於兩個重疊列布置之複數個分開的垂直區段。複數個導體柱形成於半導體晶粒上方。電組件設置於半導體晶粒上方。半導體晶粒該組件設置於基板上方。絕緣層在基板上方而於阻擋壁外形成。底部填充材料沉積於半導體晶粒與基板之間。阻擋壁及絕緣層抑制底部填充材料接觸敏感區域之任何部分。

Description

用於晶片對晶圓裝置之形成有底部填充阻擋件的半導體裝置及方法
本發明大體上係關於半導體裝置，且更特定言之，係關於一種用於晶片對晶圓（chip-to-wafer；C2W）裝置之形成有底部填充阻擋件的半導體裝置及方法。
半導體裝置常見於現代的電子產品中。半導體裝置是進行廣範圍的功能，例如是訊號處理、高速計算、發送及接收電磁訊號、控制電子裝置、光電、以及產生用於電視顯示器的視覺影像。半導體裝置是見於通訊、電力轉換、網路、電腦、娛樂、以及消費者產品的領域中。半導體裝置亦見於軍事的應用、航空、汽車、工業用控制器、以及辦公室設備中。
半導體裝置常常含有一或多個半導體晶粒及整合式被動裝置（integrated passive device；IPD）以進行必需電功能。在一實例中，C2W裝置典型地開始於含有許多第一類型之半導體晶粒的主動半導體晶圓。第一類型之半導體晶粒包含通常在晶粒周邊處的敏感區域，諸如波導、感測器、光學或光子區。複數個導體柱形成於第一半導體晶粒之主動表面上。第二類型之半導體晶粒自其晶圓單體化且安裝至導體柱之間的第一半導體晶圓之主動表面。具有導體柱之第一半導體晶粒以及第二半導體晶粒經單體化且安裝至互連基板。底部填充材料沉積於第一半導體晶粒與互連基板之間，圍繞導體柱及第二半導體晶粒，以用於隔離及環境保護。應保護第一半導體晶粒之敏感區域不受底部填充材料影響以避免污染或覆蓋敏感區域，從而引起可靠性問題、缺陷及故障。
在一態樣中，本發明揭示一種半導體裝置，其包括半導體晶粒、阻擋壁、電組件、基板及底部填充材料。半導體晶粒包含敏感區域。阻擋壁在該半導體晶粒上方靠近該敏感區域形成。電組件設置於該半導體晶粒上方。該半導體晶粒及該電組件設置於該基板上方。底部填充材料沉積於該半導體晶粒與該基板之間，其中該阻擋壁抑制該底部填充材料接觸該敏感區域。
在另一態樣中，本發明揭示一種半導體裝置，其包括半導體晶粒、阻擋壁及底部填充材料。半導體晶粒包含敏感區域。阻擋壁在該半導體晶粒上方靠近該敏感區域形成。底部填充材料沉積於該半導體晶粒上方，其中該阻擋壁抑制該底部填充材料接觸該敏感區域。
在又一態樣中，本發明揭示一種製作半導體裝置之方法，其包括提供包含敏感區域之半導體晶粒；在該半導體晶粒上方靠近該敏感區域形成阻擋壁；及將底部填充材料沉積於該半導體晶粒上方，其中該阻擋壁抑制該底部填充材料接觸該敏感區域。
本發明是在以下參考所述圖式的說明中，以一或多個實施例來加以描述，其中相同的元件符號代表相同或類似的元件。儘管本發明是以用於達成本發明之目的之最佳模式來加以描述，但所屬技術領域中具有通常知識者將會體認到的是，其欲涵蓋可內含在藉由以下的揭露內容及圖式所支持之所附請求項及其等同者所界定的本發明的精神與範疇內的替代、修改以及等同者。如同在此所用的術語「半導體晶粒」是指所述字詞的單數及複數形兩者，且於是能指稱單一半導體裝置及多個半導體裝置兩者。
半導體裝置一般使用兩個複雜的過程：前段製造（front-end manufacturing）及後段製造（back-end manufacturing）來加以製作。前段製造牽涉到複數個晶粒在半導體晶圓表面上的形成。在該晶圓上的每一個晶粒含有電連接以形成功能電路的主動及被動電性構件。例如電晶體及二極體的主動電性構件具有控制電流流動的能力。例如電容器、電感器及電阻器的被動電性構件創建進行電路功能所必要的電壓及電流之間的關係。
後段製造指將完成的晶圓切割或單粒化成為個別的半導體晶粒，且為了結構的支撐、電互連及環境的隔離來封裝所述半導體晶粒。為了單粒化所述半導體晶粒，所述晶圓是沿著晶圓的非功能區域（稱為切割道或切割線）來加以劃線且截斷。所述晶圓是使用雷射切割工具或鋸片而單粒化。在單粒化之後，所述個別的半導體晶粒設置在封裝基板上，所述封裝基板包含用於與其它系統構件互連的接腳或接觸墊。形成在所述半導體晶粒上方的接觸墊接著連接至所述封裝內的接觸墊。所述電連接能使用導體層、凸塊、短柱凸塊、導電膏或引線接合來做成。密封劑或其它模製材料沉積在該封裝上方，以提供實體支撐及電性隔離。所述完成的封裝接著插入電性系統中，且使得所述半導體裝置的功能為可供其它系統構件使用。
圖1a展示具有基底基板材料52之半導體晶圓50，基底基板材料諸如矽、鍺、磷化鋁、砷化鋁、砷化鎵、氮化鎵、磷化銦、碳化矽或用於結構支撐之其他塊體材料。複數個半導體晶粒或組件54形成於由非主動晶粒間晶圓區域或切割道56分離的晶圓50上。切割道56提供切割區域以將半導體晶圓50單體化成個別半導體晶粒54。在一個實施例中，半導體晶圓50具有100至450毫米（mm）之寬度或直徑。
圖1b展示半導體晶圓50之一部分的截面圖。各半導體晶粒54具有背面或非主動表面58、及含有類比或數位電路的主動表面60，該等類比或數位電路實施為形成於晶粒內且根據晶粒之電設計及功能而電互連的主動裝置、被動裝置、導體層及介電層。舉例而言，電路能包含形成於主動表面60內之一或多個電晶體、二極體及其他電路元件，以實施類比電路或數位電路，諸如數位訊號處理器（digital signal processor；DSP）、特殊應用積體電路（application specific integrated circuit；ASIC）、記憶體或其他訊號處理電路。半導體晶粒54亦能含有諸如電感器、電容器及電阻器等IPD以用於RF訊號處理。
使用PVD、CVD、電解電鍍、無電鍍製程或其他合適之金屬沉積製程在主動表面60上方形成導體層62。導體層62能為鋁（Al）、銅（Cu）、錫（Sn）、鎳（Ni）、金（Au）、銀（Ag）或其他合適的導體材料之一或多層。導體層62作為電連接至主動表面60上之電路的接觸襯墊而操作。
使用蒸鍍、電解電鍍、無電鍍、丸滴或網印製程將導體凸塊材料沉積於導體層62上方。凸塊材料能為Al、Sn、Ni、Au、Ag、鉛（Pb）、鉍（Bi）、Cu、焊料及以上各者之組合，以及選用焊劑溶液。舉例而言，凸塊材料能為共晶Sn/Pb、高鉛焊料或不含鉛焊料。使用合適的附接或接合製程將凸塊材料接合至導體層62。在一實施例中，凸塊材料藉由將材料加熱超過其熔點而迴焊以形成球或凸塊64。在一實施例中，凸塊64形成於具有潤濕層、障壁層及黏著劑層之凸塊下金屬（under bump metallization；UBM）上方。凸塊64亦能經壓縮接合或熱壓縮接合至導體層62。凸塊64表示能形成於導體層62上方之一種類型互連結構。互連結構亦能使用接合線、導電膏、短柱凸塊、微凸塊或其他電互連件。
在圖1c中，使用鋸片或雷射切割工具68透過切割道56將半導體晶圓50單體化成個別半導體晶粒54。能檢測及電測試個別半導體晶粒54以用於在單體化後識別良裸晶粒或單元（known good die or unit；KGD/KGU）。
圖2a是展示半導體晶圓100，其具有例如矽、鍺、磷化鋁、砷化鋁、砷化鎵、氮化鎵、磷化銦、碳化矽、或是其它用於結構支承的塊料的基底基板材料102。複數個半導體晶粒或構件104形成在晶圓100上，半導體晶粒104藉由非作用的晶粒間晶圓區域或切割道106來加以分開。切割道106提供切割區域以將半導體晶圓100單粒化成為個別的半導體晶粒104。在一實施例中，半導體晶圓100具有100毫米至450毫米（mm）的寬度或直徑。
圖2b展示半導體晶圓100的一部分的橫截面圖。每一個半導體晶粒104具有背表面或非主動表面108、以及包含類比或數位電路的主動表面110，所述類比或數位電路是實施為形成在所述晶粒之內且根據所述晶粒的電性設計及功能來電互連的主動元件、被動元件、導體及介電層。例如，所述電路可包含一或多個電晶體、二極體及其它的電路元件，其形成在主動表面110內以實施類比電路或數位電路，其例如數位訊號處理器（digital signal processor；DSP）、特殊應用積體電路（application specific integrated circuit；ASIC）、記憶體或其它的訊號處理電路。半導體晶粒104亦可包含例如電感器、電容器及電阻器之整合式被動裝置（Integrated Passive Device；IPD）以用於射頻（Radio frequency；RF）訊號處理。
導體層112是用PVD、CVD、電解電鍍、無電鍍製程或其它適當的金屬沉積製程而形成在主動表面110上方。導體層112能為一或多層的鋁（Al）、銅（Cu）、錫（Sn）、鎳（Ni）、金（Au）、銀（Ag）或其它適當的導體材料。導體層112操作為電連接至主動表面110上的電路的接觸墊。背面108能經受以研磨機114進行之研磨操作以平坦化表面。
在圖3a中，複數個導體柱或柱130形成於半導體晶圓100之導體層112上。各導體柱130具有立軸132及形成於該立軸之遠端上的凸塊134。阻焊劑能形成於表面110上方。阻焊劑經蝕刻以形成用於導體柱130之位置的通孔。以導體材料填充該等通孔，且移除阻焊劑，從而留下立軸132。凸塊134接著形成於立軸132之遠端上。立軸132能為Al、Cu、Sn、Ni、Au、Ag或其他合適導體材料。凸塊材料能為Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及以上各者之組合、以及選用焊劑溶液。在一實施例中，導體柱130具有60至140 µm之高度H。
各半導體晶粒104具有形成於主動表面110中之敏感區域138。在一實施例中，敏感區域138為波導。敏感區域138能為通常在晶粒之周邊處的感測器、光學、光子區或半導體晶粒104之其他特徵，其應受到保護免受外來材料或其他污染。在一些狀況下，諸如波導，敏感區域138延伸至半導體晶粒104之邊緣以繼續至鄰接晶粒或其他裝置。
阻擋壁或圍欄144在半導體晶圓100之主動表面110上方靠近敏感區域138形成。在一實施例中，阻擋壁144形成於導體柱130與敏感區域138之間。阻擋壁144包含具有足夠結構強度以耐受底部填充材料之流動的各種剛性材料區段，較佳與導體柱130同時形成且以與導體柱130相同的材料形成。阻擋壁144將用以阻斷或抑制稍後施加之底部填充材料到達敏感區域138。
在圖3b中，複數個電組件140設置於半導體晶圓100之主動表面110上，且電連接及機械連接至導體層112。電組件140各自使用取放操作定位於晶圓100上方。舉例而言，電組件140能類似於來自圖1c之半導體晶粒54，其中主動表面60及凸塊64朝向半導體晶圓100之表面110而定向。電組件140能為離散電裝置或IPD，諸如二極體、電晶體、電阻器、電容器及電感器。替代地，電組件140能包含其他半導體晶粒、半導體封裝、表面黏著裝置、離散電裝置或IPD。
使電組件140與晶圓100之表面110接觸。圖3c繪示電連接至且機械連接至晶圓100之導體層112之電組件140。設置於半導體晶圓100上之電組件140為C2W裝置。
使用鋸片或雷射切割工具146透過切割道106將半導體晶圓100單體化成個別半導體晶粒104，各個半導體晶粒具有設置於主動表面110上之額外半導體晶粒54及導體柱130。能檢測並電測試具有導體柱130及電組件140之個別半導體晶粒104以用於在單體化後識別KGD/KGU。
半導體晶粒104、半導體晶粒54、導體柱130、阻擋壁144及敏感區域138之組合構成C2W半導體封裝件148。
圖4a展示互連基板150之截面圖，該互連基板包含導體層152及絕緣層154。導體層152能為一或多層Al、Cu、Sn、Ni、Au、Ag或其他合適導體材料。能使用PVD、CVD、電解電鍍、無電鍍製程或其他合適的金屬沉積製程形成導體層。導體層152提供跨越基板150之水平電互連件以及在基板150之頂表面156與底表面158之間的垂直電互連件。導體層152之部分能取決於半導體晶粒104及其他電組件之設計及功能而為電共用的或電隔離的。絕緣層154含有一或多層二氧化矽（silicon dioxide；SiO 2）、氮化矽（silicon nitride；Si 3N 4）、氮氧化矽（silicon oxynitride；SiON）、五氧化二鉭（tantalum pentoxide；Ta 2O 5）、氧化鋁（aluminum oxide；Al 2O 3）、阻焊劑、聚醯亞胺、苯環丁烯（benzocyclobutene；BCB）、聚苯並噁唑（polybenzoxazoles；PBO）及具有類似絕緣及結構特性之其他材料。能使用PVD、CVD、印刷、層疊、旋塗、噴塗、燒結或熱氧化形成絕緣層。絕緣層154在所述導體層152之間提供隔離。
來自圖3c之半導體封裝件148定位於互連基板150之表面156上方，其中導體柱130朝向該基板定向。使半導體封裝件148與互連基板150之表面156接觸。圖4b展示設置於互連基板150上之半導體封裝件148，其中導體柱130電連接至且機械連接至表面156上之導體層152。
圖4c為半導體封裝件148之仰視圖。額外電組件160能設置於半導體晶粒104之主動表面110上，與在圖3b至圖3c中一樣。電組件160能類似於來自圖1c之半導體晶粒54，但具有不同形式及功能，其中主動表面60及凸塊64朝向半導體晶粒104之表面110定向。半導體封裝件148展示在電組件140及電組件160之各側上的兩列導體柱130。阻擋壁144設置於導體柱130與敏感區域138之間，接近敏感區域。阻擋壁144展示為具有主壁144a及側翼144b。
圖4d為半導體封裝件148之另一實施例的仰視圖。電組件160設置於半導體晶粒104之主動表面110上。電組件160能類似於來自圖1c之半導體晶粒54，但具有不同形式及功能，其中主動表面60及凸塊64朝向半導體晶粒104之主動表面110定向。在此狀況下，阻擋壁144置放於一列導體柱130內，靠近敏感區域138。阻擋壁144展示為具有主壁144a及側翼144b。
圖4e為半導體封裝件148之另一實施例的仰視圖。電組件160設置於半導體晶粒104之主動表面110上。電組件160能類似於來自圖1c之半導體晶粒54，但具有不同形式及功能，其中主動表面60及凸塊64朝向半導體晶粒104之表面110定向。在此狀況下，半導體晶粒104具有兩個的敏感區域138a及敏感區域138b，其中各別阻擋壁144a及阻擋壁144b各自置放於一列導體柱130內，靠近敏感區域138。
在圖4f中，底部填充材料166，諸如環氧樹脂，沉積於半導體晶粒104下方且圍繞導體柱130、以及電組件140及電組件160。底部填充材料166隔離並保護電組件140及電組件160之主動表面、半導體晶粒104之主動表面110及導體柱130。然而，阻擋壁144阻斷或抑制底部填充材料166到達敏感區域138。阻擋壁144保護敏感區域138免於底部填充材料166污染或覆蓋。
在圖4g中，使用蒸鍍、電解電鍍、無電鍍、丸滴或網印製程將導體凸塊材料沉積於表面158上之導體層152上方。凸塊材料能為Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及以上各者之組合、以及選用焊劑溶液。舉例而言，凸塊材料能為共晶Sn/Pb、高鉛焊料或不含鉛焊料。使用合適的附接或接合製程將凸塊材料接合至導體層152。在一實施例中，凸塊材料藉由將材料加熱超過其熔點而迴焊以形成球或凸塊168。在一實施例中，凸塊168形成於具有潤濕層、障壁層及黏著劑層之UBM上方。凸塊168亦能經壓縮接合或熱壓縮接合至導體層152。在一實施例中，凸塊168為用於耐久性且維持其高度的銅芯凸塊。凸塊168表示能形成於導體層152上方之一種類型互連結構。互連結構亦能使用接合線、導電膏、短柱凸塊、微凸塊或其他電互連件。
半導體晶粒104、半導體晶粒54、導體柱130、阻擋壁144、敏感區域138、互連基板150及底部填充材料166之組合構成C2W半導體封裝件169。
圖5a至圖5b進一步繪示阻擋壁144之細節。圖5a為展示阻擋壁144之細節的截面圖。圖5b為展示阻擋壁144之細節的仰視圖。在一實施例中，阻擋壁144包含複數個剛性材料區段，其具有變化或不同的寬度，具有足夠結構強度以耐受底部填充材料之流動。垂直區段170具有第一寬度，且圓形區段172具有大於垂直區段之第一寬度的第二寬度。交替的垂直區段170與圓形區段整合為單體本體。區段170至區段172能由一或多層Al、Cu、Sn、Ni、Au、Ag或具有足夠剛性及結構強度以耐受底部填充材料之流動的其他合適材料製成。替代地，區段170至區段172能由以下各者製成：多層可撓性層疊物、陶瓷、覆銅箔層疊板（copper clad laminate；CCL）、玻璃、聚合物、環氧樹脂模製化合物、預浸漬（預浸料）之聚四氟乙烯（PTFE）、FR-4、FR-1、CEM-1或CEM-3與酚棉漿紙、環氧樹脂、樹脂、編織玻璃、毛玻璃、聚酯以及其他增強纖維或織物之組合的一或多個層疊層、SiO 2、Si 3N 4、SiON、Ta 2O 5、Al 2O 3、阻焊劑、聚醯亞胺、BCB、PBO及具有適於耐受底部填充材料之流動的類似絕緣及結構屬性之其他材料。在一實施例中，區段170至區段172為Cu，其與導體柱130同時形成。
區段170至區段172之尖端171在到達基板150之表面156之前終止，從而在阻擋壁144與基板150之表面156之間留下間隙，以允許底部填充材料在阻擋壁下方及周圍流動。圖5a展示半導體晶粒104之另外細節，包含形成於半導體晶粒104之主動表面110上方之絕緣層173及導體層175。導體層175係電連接至導體柱130以及導體層112之重佈層（redistribution layer；RDL）之部分。絕緣層173為導體層175提供隔離。敏感區域138延伸至半導體晶粒104之側表面177。在波導之情況下，敏感區域138將與鄰近晶粒或其他裝置連接。阻擋壁144可具有與導體柱130類似的高度。
諸如阻焊劑之絕緣層174形成於表面156上方、阻擋壁144外部及半導體晶粒104之佔據面積外部。在一實施例中，自半導體晶粒104之邊緣至最外部導體柱之距離為D1 = 534微米（µm）。自半導體晶粒104至互連基板150之距離為D2 = 120 µm。自半導體晶粒104至絕緣層174之距離為D3 =至少100 µm。絕緣層174之厚度為D4 = 10至15 µm。自導體柱130至阻擋壁144之距離為D5 = 50 µm。阻擋壁144之長度為至少D6 = 6.0 mm。
底部填充材料166自左至右流動。在到達阻擋壁144之後，底部填充材料在區段170至區段172下方及周圍流動，其中流動藉由絕緣層174阻止。阻擋壁144提供足夠剛性及結構強度以使得底部填充材料166在阻擋件結構下方及周圍流動。根據阻擋壁144之區段170至區段172之性質以及絕緣層174抑制底部填充材料之流動，底部填充材料166未達到側表面177上之敏感區域138。敏感區域138及實質所有側表面177保持不含有底部填充材料166。
圖6a至圖6b繪示阻擋壁144之替代實施例。圖6a為展示阻擋壁144之細節的截面圖。圖6b為展示阻擋壁144之細節的仰視圖。在一實施例中，阻擋壁144包含具有足夠結構強度以耐受底部填充材料之流動的剛性材料之複數個實體分開的垂直區段。分開的垂直區段180形成第一列阻擋壁144及側翼。分開的垂直區段182形成第二列阻擋壁144。應注意的是，垂直區段182與第一列垂直區段180之間的間隙重疊。舉例而言，一垂直區段182置放於鄰近且分開的所述垂直區段180之間的間隙中。阻擋壁144能具有分開的垂直區段的任何數目個重疊列。分開的垂直區段180至垂直區段182能由一或多層Al、Cu、Sn、Ni、Au、Ag或具有足夠剛性及結構強度以耐受底部填充材料之流動的其他合適材料製成。替代地，垂直區段180至垂直區段182能由以下各者製成：多層能撓性層疊物、陶瓷、CCL、玻璃、聚合物、環氧樹脂模製化合物、PTFE預浸料、FR-4、FR-1、CEM-1或CEM-3與酚棉漿紙、環氧樹脂、樹脂、編織玻璃、毛面玻璃、聚酯以及其他增強纖維或織物之組合的一或多個層疊層、SiO 2、Si 3N 4、SiON、Ta 2O 5、Al 2O 3、阻焊劑、聚醯亞胺、BCB、PBO及具有適於耐受底部填充材料之流動的類似絕緣及結構屬性之其他材料。在一實施例中，分開的垂直區段180至垂直區段182為Cu，其與導體柱130同時形成。
分開的垂直區段180至垂直區段182之尖端183在到達基板150之表面156之前終止，從而在阻擋壁144與基板150之表面156之間留下間隙，以允許底部填充材料在阻擋壁144下方及周圍流動。圖6a展示半導體晶粒104之另外細節，包含形成於半導體晶粒104之主動表面110上方之絕緣層185及導體層187。導體層187係電連接至導體柱130及導體層112之RDL之部分。絕緣層185為導體層187提供隔離。敏感區域138延伸至半導體晶粒104之側表面189。在波導之情況下，敏感區域138將與鄰近晶粒或其他裝置連接。
諸如阻焊劑之絕緣層184形成於表面156上方、阻擋壁144外部及半導體晶粒104之佔據面積外部。在一實施例中，自半導體晶粒104之邊緣至最外部導體柱之距離為D7 = 534 µm。自半導體晶粒104至互連基板150之距離為D8 = 120 µm。自半導體晶粒104至絕緣層184之距離為D9 =至少100 µm。絕緣層184之厚度為D10 = 10至15 µm。自導體柱130至阻擋壁144之距離為D11 = 50 µm。阻擋壁144之長度為至少D12 = 6.0 mm。
底部填充材料166自左至右流動。在到達阻擋壁144之後，底部填充材料在分開的垂直區段180至垂直區段182下方及周圍流動，其中流動藉由絕緣層184阻止。阻擋壁144提供足夠剛性及結構強度以使得底部填充材料166在阻擋件結構下方及周圍流動。根據阻擋壁144之單獨垂直區段180至182之性質以及絕緣層184抑制底部填充材料之流動，底部填充材料166並未達到側表面189上之敏感區域138。敏感區域138及實質所有側表面189保持不含底部填充材料166。
圖7a至圖7b繪示阻擋壁144之另一替代實施例。圖7a為展示阻擋壁144之細節的截面圖。圖7b為展示阻擋壁144之細節的仰視圖。在一實施例中，阻擋壁144包含具有足夠剛性及結構強度以耐受底部填充材料之流動的複數個垂直區段。垂直區段190能由一或多層Al、Cu、Sn、Ni、Au、Ag或具有足夠剛性及結構強度以耐受底部填充材料之流動的其他合適材料製成。替代地，垂直區段190能由以下各者製成：多層能撓性層疊物、陶瓷、CCL、玻璃、聚合物、環氧樹脂模製化合物、PTFE預浸料、FR-4、FR-1、CEM-1或CEM-3與酚棉漿紙、環氧樹脂、樹脂、編織玻璃、毛面玻璃、聚酯以及其他增強纖維或織物之組合的一或多個層疊層、SiO 2、Si 3N 4、SiON、Ta 2O 5、Al 2O 3、阻焊劑、聚醯亞胺、BCB、PBO及具有適於耐受底部填充材料之流動的類似絕緣及結構屬性之其他材料。在一實施例中，垂直區段190為Cu，其與導體柱130同時形成。
垂直區段190之尖端193在到達基板150之表面156之前終止，從而在阻擋壁144與基板150之表面156之間留下間隙，以允許底部填充材料在阻擋壁144下方及周圍流動。圖7a展示半導體晶粒104之另外細節，包含形成於半導體晶粒104之主動表面110上方之絕緣層195及導體層197。導體層197係電連接至導體柱130以及導體層112之RDL之部分。絕緣層195為導體層197提供隔離。敏感區域138延伸至半導體晶粒104之側表面199。在波導之情況下，敏感區域138將與鄰近晶粒或其他裝置連接
諸如阻焊劑之第一絕緣層194a在表面156上方而在阻擋壁144外部形成。諸如阻焊劑之第二絕緣層194b形成於第一絕緣層194a上方。在一實施例中，自半導體晶粒104之邊緣至最外部導體柱之距離為D13 = 534 µm。自半導體晶粒104至互連基板150之距離為D14 = 120 µm。絕緣層194a及絕緣層194b之厚度為D15 = 25至30 µm。自導體柱130至阻擋壁144之距離為D16 = 50 µm。阻擋壁144之長度為至少D17 = 6.0 mm。
底部填充材料166自左至右流動。在到達阻擋壁144之後，底部填充材料在垂直區段190下方及周圍流動，其中流動藉由絕緣層194a至絕緣層194b阻止。阻擋壁144提供足夠剛性及結構強度以使得底部填充材料166在阻擋件結構下方及周圍流動。根據阻擋壁144之垂直區段190之性質以及絕緣層194a至絕緣層194b抑制底部填充材料之流動，底部填充材料166並未達到側表面199上之敏感區域138。敏感區域138及實質所有側表面199保持不含底部填充材料166。
圖8繪示具有晶片載體基板或PCB 402的電子裝置400，其中複數個半導體封裝件設置在PCB 402的表面上方，其包含半導體封裝件169。電子裝置400能取決於應用而具有一類型的半導體封裝件、或是多種類型的半導體封裝件。
電子裝置400能是獨立的系統，其使用所述半導體封裝以進行一或多個電性功能。或者是，電子裝置400能是較大系統的子構件。例如，電子裝置400能是平板電腦、行動電話、數位攝像機、通訊系統或是其它電子裝置的部分。或者是，電子裝置400能是可插入到電腦中的顯示卡、網路介面卡或其它的訊號處理卡。所述半導體封裝能包含微處理器、記憶體、ASIC、邏輯電路、類比電路、RF電路、離散裝置、或是其它半導體晶粒或電性構件。小型化及重量縮減是產品被市場所接受所必需的。在半導體裝置之間的距離可被縮減以達成較高的密度。
在圖8中，PCB 402提供通用基板，以用於設置在所述PCB上的半導體封裝的結構支撐及電互連。導體訊號跡線404是使用蒸鍍、電解電鍍、無電鍍、網印或其它適當金屬沉積製程而形成在PCB 402的表面上方或PCB 402的層之內。訊號跡線404提供用於在所述半導體封裝、所安裝構件、以及其它外部的系統構件的每一個之間的電性通信。跡線404亦提供電源及接地連接至每一個所述半導體封裝。
在一些實施例中，半導體裝置具有兩個封裝層級。第一層級封裝是用於將所述半導體晶粒機械式及電性附接至中間基板的技術。第二層級封裝牽涉到將所述中間基板機械式及電性附接至所述PCB。在其它實施例中，半導體裝置可只有該第一層級封裝，其中該晶粒是直接機械式及電性設置在所述PCB上。出於說明之目的，包含接合線封裝406及覆晶408的數種類型的第一層級封裝展示在PCB 402上。另外，數種類型的第二層級封裝，其包含球柵陣列410、凸塊晶片載體（bump chip carrier；BCC）412、平台格柵陣列（land grid array；LGA）416、多晶片模組或系統級封裝（system in package；SIP）模組418、方形扁平無導線封裝（quad flat non-leaded package；QFN）420、方形扁平封裝422、嵌入式晶圓級球柵陣列（embedded wafer level ball grid array；eWLB）424以及晶圓級晶片尺度封裝（wafer level chip scale package；WLCSP）426展示為設置在PCB 402上。在一實施例中，eWLB 424是扇出晶圓級封裝（fan-out wafer level package；Fo-WLP），且WLCSP 426是扇入晶圓級封裝（fan-in wafer level package；Fi-WLP）。根據系統需求，使用第一及第二層級的封裝類型的任意組合來加以配置的半導體封裝及其它的電子構件的任意組合能連接至PCB 402。在一些實施例中，電子裝置400包含單一附接的半導體封裝，而其它實施例需要多個互連的封裝。藉由在單一基板上方組合一或多個半導體封裝，製造商能將預製的構件併入到電子裝置及系統中。因為所述半導體封裝包含複雜功能性，因此能使用較不昂貴組件及流暢的製造製程來製造電子裝置。所產生的裝置不大能發生故障且製作起來較不昂貴的，此導致較低的成本給消費者。
雖然已詳細繪示本發明之一或多個實施例，但所屬領域中具有通常知識者將瞭解，能在不脫離如以下申請專利範圍中所闡述之本發明之範疇的情況下對彼等實施例作出修改及調適。
50:晶圓 52:基底基板材料 54:半導體晶粒/組件 56:切割道 58:非主動表面 60:主動表面 62:導體層 64:凸塊 68:雷射切割工具 100:晶圓 102:基底基板材料 104:半導體晶粒/構件 106:切割道 108:背面/非主動表面 110:主動表面/表面 112:導體層 114:研磨機 130:導體柱/柱 132:立軸 134:凸塊 138:敏感區域 138a:敏感區域 138b:敏感區域 140:電組件 144:阻擋壁/圍欄 144a:主壁 144b:側翼 146:雷射切割工具 148:半導體封裝件 150:互連基板/基板 152:導體層 154:絕緣層 156:表面 158:表面 160:電組件 166:底部填充材料 168:凸塊 169:半導體封裝件 170:垂直區段/區段 171:尖端 172:圓形區段/區段 173:絕緣層 174:絕緣層 175:導體層 177:側表面 180:垂直區段 182:垂直區段 183:尖端 184:絕緣層 185:絕緣層 187:導體層 189:側表面 190:垂直區段 193:尖端 194a:第一絕緣層/絕緣層 194b:第二絕緣層/絕緣層 195:絕緣層 197:導體層 199:側表面 400:電子裝置 402:PCB 404:跡線 406:接合線封裝 408:覆晶 410:球柵陣列 412:凸塊晶片載體 416:平台格柵陣列 418:多晶片模組或系統級封裝模組 420:方形扁平無導線封裝 422:方形扁平封裝 424:嵌入式晶圓級球柵陣列 426:晶圓級晶片尺度封裝 D1:距離 D2:距離 D3:距離 D4:厚度 D5:距離 D6:長度 D7:距離 D8:距離 D9:距離 D10:厚度 D11:距離 D12:長度 D13:距離 D14:距離 D15:厚度 D16:距離 D17:長度 H:高度
[圖1a]至[圖1c]繪示具有由切割道分離之複數個第一半導體晶粒的第一半導體晶圓； [圖2a]至[圖2b]繪示具有由切割道分離之複數個第二半導體晶粒的第二半導體晶圓； [圖3a]至[圖3c]繪示將第一半導體晶粒及複數個導體柱設置於第二半導體晶圓上； [圖4a]至[圖4g]繪示將單體化第二半導體晶粒設置於具有阻擋壁之互連基板上以保護敏感區域； [圖5a]至[圖5b]繪示阻擋壁之第一實施例； [圖6a]至[圖6b]繪示阻擋壁之第二實施例； [圖7a]至[圖7b]繪示阻擋壁之第三實施例；及 [圖8]繪示印刷電路板（printed circuit board；PCB），其具有設置於該PCB之表面上的不同類型之封裝件。
54:半導體晶粒
58:非主動表面
62:導體層
64:凸塊
104:半導體晶粒/構件
108:背面/非主動表面
110:主動表面/表面
130:導體柱/柱
132:立軸
134:凸塊
138:敏感區域
140:電組件
144:阻擋壁/圍欄
148:半導體封裝件
150:互連基板/基板
152:導體層
154:絕緣層
156:表面
158:表面
166:底部填充材料

Claims (15)

  1. 一種半導體裝置，其包括： 半導體晶粒，其包含敏感區域； 阻擋壁，其在該半導體晶粒上方靠近該敏感區域形成； 電組件，其設置於該半導體晶粒上方； 基板，其中該半導體晶粒及該電組件設置於該基板上方；及 底部填充材料，其沉積於該半導體晶粒與該基板之間，其中該阻擋壁抑制該底部填充材料接觸該敏感區域。
  2. 如請求項1之半導體裝置，其進一步包含形成於該半導體晶粒上方之複數個導體柱。
  3. 如請求項1之半導體裝置，其中該阻擋壁包含垂直區段及側翼。
  4. 如請求項1之半導體裝置，其中該阻擋壁包含與複數個垂直區段整合為單體本體之複數個圓形區段。
  5. 如請求項1之半導體裝置，其中該阻擋壁包含複數個分開的垂直區段。
  6. 一種半導體裝置，其包括： 半導體晶粒，其包含敏感區域； 阻擋壁，其在該半導體晶粒上方靠近該敏感區域形成；及 底部填充材料，其沉積於該半導體晶粒上方，其中該阻擋壁抑制該底部填充材料接觸該敏感區域。
  7. 如請求項6之半導體裝置，其進一步包含形成於該半導體晶粒上方之複數個導體柱。
  8. 如請求項6之半導體裝置，其中該阻擋壁包含垂直區段及側翼。
  9. 如請求項6之半導體裝置，其中該阻擋壁包含與複數個垂直區段整合為單體本體之複數個圓形區段。
  10. 如請求項6之半導體裝置，其中該阻擋壁包含複數個分開的垂直區段。
  11. 一種製作半導體裝置之方法，其包括： 提供包含敏感區域之半導體晶粒； 在該半導體晶粒上方靠近該敏感區域形成阻擋壁；及 將底部填充材料沉積於該半導體晶粒上方，其中該阻擋壁抑制該底部填充材料接觸該敏感區域。
  12. 如請求項11之方法，其進一步包含在該半導體晶粒上方形成複數個導體柱。
  13. 如請求項11之方法，其中形成該阻擋壁包含形成垂直區段及側翼。
  14. 如請求項11之方法，其中形成該阻擋壁包含形成與複數個垂直區段整合為單體本體之複數個圓形區段。
  15. 如請求項11之方法，其中形成該阻擋壁包含形成複數個分開的垂直區段。
TW112119555A 2022-07-15 2023-05-25 用於晶片對晶圓裝置之形成有底部填充阻擋件的半導體裝置及方法 TW202406039A (zh)

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