TW202401573A - 半導體元件及其製作方法 - Google Patents

半導體元件及其製作方法 Download PDF

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TW202401573A
TW202401573A TW111122678A TW111122678A TW202401573A TW 202401573 A TW202401573 A TW 202401573A TW 111122678 A TW111122678 A TW 111122678A TW 111122678 A TW111122678 A TW 111122678A TW 202401573 A TW202401573 A TW 202401573A
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layer
gate structure
dielectric layer
contact plug
interlayer dielectric
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TW111122678A
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張溫文
何坤展
陳俊隆
邱崇益
呂銘洲
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聯華電子股份有限公司
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Priority to TW111122678A priority Critical patent/TW202401573A/zh
Priority to US17/868,753 priority patent/US20230411489A1/en
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Abstract

本發明揭露一種製作半導體元件的方法，其主要先形成一閘極結構於基底上，然後形成一層間介電層於閘極結構上，形成一接觸洞於閘極結構旁的層間介電層內，進行一電漿摻雜製程以形成一摻雜層於層間介電層內以及一源極/汲極區域於閘極結構旁，形成一導電層於接觸洞內，平坦化該導電層以形成一接觸插塞，去除該摻雜層以形成一氣孔於接觸插塞旁，再形成一停止層於層間介電層以及接觸插塞上。

Description

半導體元件及其製作方法
本發明是關於一種製作半導體元件的方法，尤指一種於接觸插塞周圍形成氣孔的方法。
隨著半導體元件尺寸的逐漸縮小，內連線結構的線寬的逐漸變窄也使得傳輸訊號的線阻值(line resistance, R)變大。此外，導線間的間距縮小也使得寄生電容(parasitic capacitance, C)變大。因此，使得訊號因RC延遲的狀況增加，導致晶片運算速度減慢，降低了晶片的效能。
寄生電容(C)係與介電層之介電常數或k值(k-value)呈線性相關。低介電常數介電材料可降低晶片上整個內連線結構的電容值、降低訊號的RC延遲以及增進晶片效能。降低整體的電容同時降低了耗電量。對於超大型積體電路(ULSI)的設計而言，採用低介電常數材料以及低阻值的金屬材料，可以使得整個內連線結構達到最佳效能。因此，習知技術通常試圖藉由將金屬間的間隙以低介電常數材料填滿以降低RC延遲。
一般常用氧化矽材料(SiO 2) 作為介電材料，雖然其具有相對高的介電常數值(4.1-4.5)，但由於其具有良好的熱穩定性與化學穩定性，再加上容易藉由一般的氧化物蝕刻製程形成高深寬比(high aspect ratio)的接觸窗與介層洞，因此仍被廣泛的採用。然而，隨著元件尺寸縮小以及封裝密度增高，勢必需要縮減金屬導線間的間距，以有效的連結整個積體電路。因此，目前也研發出多種低介電常數之材料以進一步降低晶片的RC值。諸如氟化二氧化矽(fluorinated SiO 2)、氣溶膠(aerogel)、聚合物等等。另一種降低內連線間的介電常數值之方法則是在結構中形成氣隙(air gap)。一般氧化矽材料的介電常數約介於4或更高，而空氣的介電常數則約為1左右。
雖然對於降低RC值而言空氣為最佳的介電材料，然而要實際在積體電路製程中引入氣隙結構仍面臨許多問題。例如：不具支撐力的氣隙結構會造成半導體裝置整體的結構應力強度隨之減弱，可能使得結構變形，且弱化的結構更可能在後續的積體電路製程中遭遇各種不同的問題。因此如何改良現有製程來克服上述問題即為現今一重要課題。
本發明一實施例揭露一種製作半導體元件的方法，其主要先形成一閘極結構於基底上，然後形成一層間介電層於閘極結構上，形成一接觸洞於閘極結構旁的層間介電層內，進行一電漿摻雜製程以形成一摻雜層於層間介電層內以及一源極/汲極區域於閘極結構旁，形成一導電層於接觸洞內，平坦化該導電層以形成一接觸插塞，去除該摻雜層以形成一氣孔於接觸插塞旁，再形成一停止層於層間介電層以及接觸插塞上。
本發明另一實施例揭露一種半導體元件，其主要包含一閘極結構設於基底上，一源極/汲極區域設於閘極結構旁，一層間介電層環繞閘極結構，一接觸插塞設於閘極結構旁之層間介電層內，一氣孔環繞接觸插塞以及一停止層設於層間介電層以及接觸插塞上。
請參照第1圖至第6圖，第1圖至第6圖為本發明一實施例製作半導體元件之方法示意圖。如第1圖所示，首先提供一基底12，例如一矽基底或矽覆絕緣(SOI)基板，其上可定義有一電晶體區，例如一PMOS電晶體區或一NMOS電晶體區，且基底12內可設有複數個由氧化矽所構成作為電性隔離之用的淺溝渠隔離(shallow trench isolation, STI)。需注意的是，本實施例雖以製作一般平面型(planar)場效電晶體為例，但在其他變化實施例中，本發明之半導體製程亦可應用於非平面型場效電晶體(non-planar)例如鰭狀結構場效電晶體。此時，第1圖所標示之基底12即相對應代表為形成於基底12上的鰭狀結構。
依據本發明一實施例，鰭狀結構較佳透過側壁圖案轉移(sidewall image transfer, SIT)技術製得，其程序大致包括：提供一佈局圖案至電腦系統，並經過適當地運算以將相對應之圖案定義於光罩中。後續可透過光微影及蝕刻製程，以形成多個等距且等寬之圖案化犧牲層於基底上，使其個別外觀呈現條狀。之後依序施行沉積及蝕刻製程，以於圖案化犧牲層之各側壁形成側壁子。繼以去除圖案化犧牲層，並在側壁子的覆蓋下施行蝕刻製程，使得側壁子所構成之圖案被轉移至基底內，再伴隨鰭狀結構切割製程(fin cut)而獲得所需的圖案化結構，例如條狀圖案化鰭狀結構。
除此之外，鰭狀結構之形成方式又可包含先形成一圖案化遮罩(圖未示)於基底12上，再經過一蝕刻製程，將圖案化遮罩之圖案轉移至基底12中以形成鰭狀結構。另外，鰭狀結構之形成方式也可以先形成一圖案化硬遮罩層(圖未示)於基底12上，並利用磊晶製程於暴露出於圖案化硬遮罩層之基底12上成長出例如包含矽鍺的半導體層，而此半導體層即可作為相對應的鰭狀結構。這些形成鰭狀結構的實施例均屬本發明所涵蓋的範圍。
接著可於基底12上形成至少一閘極結構14或虛置閘極。在本實施例中，閘極結構14之製作方式可依據製程需求以先閘極(gate first)製程、後閘極(gate last)製程之先高介電常數介電層(high-k first)製程以及後閘極製程之後高介電常數介電層(high-k last)製程等方式製作完成。以本實施例之先閘極製程為例，可先依序形成一閘極介電層16或介質層、一由多晶矽所構成之閘極材料層18以及一選擇性硬遮罩20於基底12上，並利用一圖案化光阻(圖未示)當作遮罩進行一圖案轉移製程，以單次蝕刻或逐次蝕刻步驟，去除部分硬遮罩20、部分閘極材料層18以及部分閘極介電層16，然後剝除圖案化光阻，以於基底12上形成由圖案化之閘極介電層16、圖案化之閘極材料層18以及圖案化之硬遮罩20所構成的閘極結構14。
然後在閘極結構14側壁形成至少一側壁子22，並於側壁子22兩側的基底12中形成一輕摻雜汲極24。在本實施例中，側壁子22可為單一側壁子或複合式側壁子，例如可細部包含一偏位側壁子以及一主側壁子。其中偏位側壁子與主側壁子可包含相同或不同材料，且兩者均可選自由氧化矽、氮化矽、氮氧化矽以及氮碳化矽所構成的群組。輕摻雜汲極24可依據所置備電晶體的導電型式而包含不同摻質，例如可包含P型摻質或N型摻質。
接著可先選擇性形成一接觸洞蝕刻停止層(圖未示)於基底12表面與閘極結構14上，再形成一層間介電層26於閘極結構14上。然後可進行一圖案轉移製程，例如可利用一圖案化遮罩去除部分層間介電層26以形成接觸洞28暴露出閘極結構14兩側的輕摻雜汲極24。
隨後如第2圖所示，進行一電漿摻雜(plasma doping)製程30以形成一摻雜層32於層間介電層26內以及一源極/汲極區域34於閘極結構14旁。更具體而言，本階段所進行的電漿摻雜製程30除了等向性地將摻質植入接觸洞28兩側的層間介電層26頂部與側壁內形成摻雜層32之外，又同時將摻質植入接觸洞28正下方的基底12內形成源極/汲極區域34。由於摻質是等向性的被植入層間介電層26內，因此在此階段設於層間介電層26頂部的摻雜層32厚度較佳等於層間介電層26側壁的摻雜層32厚度以及基底12內源極/汲極區域34的深度，而基底12內位於閘極結構14一側的源極/汲極區域34整體寬度則略等於各接觸洞28寬度。
需注意的是，本實施例雖僅以一道電漿摻雜製程30便於層間介電層26內形成具有均一厚度的摻雜層32，但不侷限於此，依據本發明其他實施例又可進行一道以上一般離子佈植製程來取代上述電漿摻雜製程30，其中一般離子佈植製程可包含一道垂直離子佈植製程與另一道斜角離子佈植製程，以於層間介電層26頂部與側壁內形成相同厚度的摻雜層32，以及於接觸洞28正下方的基底12內形成源極/汲極區域34，此變化型也屬本發明所涵蓋的範圍。
如第3圖所示，然後進行一熱處理製程36使摻質略為擴散至周圍的層間介電層26與基底12內，包括植入於層間介電層26內的摻雜層32經熱處理製程36擴散後整體厚度較第2圖略為增加且源極/汲極區域34的整體寬度也朝兩側略為延伸使源極/汲極區域34兩側邊緣約略切齊摻雜層32的外側側壁。
接著如第4圖所示，依序於各接觸洞28中填入導電材料例如由鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)或其組合所構成的阻障層38以及由鎢(W)、銅(Cu)、鋁(Al)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide, CoWP)等低電阻材料或其組合所構成的金屬層40。之後進行一平坦化製程，例如以化學機械研磨製程去除部分導電材料以及層間介電層26頂部的摻雜層32以形成接觸插塞42於各接觸洞28內電連接源極/汲極區域34。
值得注意的是，本實施例雖以接觸插塞42直接接觸源極/汲極區域34為例，但不侷限於此，依據本發明其他實施例形成接觸插塞42時接觸插塞42中的部分阻障層38又可與基底12表面反應形成矽化金屬層(圖未示)，此變化型也屬本發明所涵蓋的範圍。
然後如第5圖所示，可選擇於形成或不形成圖案化遮罩的情況下進行一蝕刻製程，利用例如稀釋氫氟酸(diluted hydrofluoric acid, dHF)來去除接觸插塞34與層間介電層26之間的所有摻雜層32以形成氣孔44於接觸插塞34周圍並暴露出源極/汲極區域34表面。需注意的是，在不形成圖案化遮罩的情況下本發明較佳利用含有摻質的摻雜層32與周圍不含摻質的接觸插塞42及層間介電層26之間的選擇比來完全去除摻雜層32。
隨後如第6圖所示，先形成停止層46於層間介電層26上將前述氣孔44進行封口，形成金屬間介電層48於停止層46上，利用微影暨蝕刻製程去除部分金屬間介電層48與部分停止層46形成開口(圖未示)並再次暴露出氣孔44及接觸插塞42頂表面，再依序形成由鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)或其組合所構成的阻障層38以及由鎢(W)、銅(Cu)、鋁(Al)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide, CoWP)等低電阻材料或其組合所構成的金屬層40於開口內。之後進行一平坦化製程，例如以化學機械研磨製程去除部分阻障層38與部分金屬層40形成金屬內連線50電連接下方的接觸插塞42。至此即完成本發明一實施例之半導體元件的製作。
如第6圖所示，本發明又揭露一種半導體元件結構，其主要包含至少一閘極結構14設於基底12上，源極/汲極區域34設於閘極結構14旁，層間介電層26環繞閘極結構14，一接觸插塞42設於閘極結構14旁的層間介電層26內，一氣孔44環繞接觸插塞42，一停止層46與金屬間介電層48設於層間介電層26上，以及金屬內連線50設於停止層46與金屬間介電層48內並設於接觸插塞及氣孔44上。
從細部來看，氣孔44較佳暴露源極/汲極區域34、層間介電層26側壁以及接觸插塞42側壁或各氣孔44較佳由源極/汲極區域34、層間介電層26、金屬內連線50以及接觸插塞42所環繞。另外氣孔44頂表面較佳切齊接觸插塞42頂表面且氣孔44底表面切齊接觸插塞42底表面。需注意的是，本實施例的金屬內連線50雖不填入下方的氣孔44內，但不侷限於此，依據本發明其他實施例於形成金屬內連線50時部分金屬內連線50的導電材料包括阻障層38與金屬層40可填入氣孔44內使金屬內連線50底表面略低於層間介電層26與接觸插塞42頂表面，此變化型也屬本發明所涵蓋的範圍。
另外需注意的是，本實施例雖以由多晶矽所構成的閘極結構為例，但不侷限於此，依據本發明其他實施例又可於前述層間介電層26形成後以及接觸插塞42形成前選擇性進行一金屬閘極置換(replacement metal gate, RMG)製程將閘極結構14轉換為金屬閘極。舉例來說，可先進行一選擇性之乾蝕刻或濕蝕刻製程，例如利用氨水(ammonium hydroxide, NH 4OH)或氫氧化四甲銨(Tetramethylammonium Hydroxide, TMAH)等蝕刻溶液來去除閘極結構14中的硬遮罩20、閘極材料層18甚至閘極介電層16，以於層間介電層26中形成凹槽(圖未示)。之後依序形成一選擇性介質層或閘極介電層、一高介電常數介電層、一功函數金屬層以及一低阻抗金屬層於凹槽內，然後進行一平坦化製程，例如利用化學機械研磨(chemical mechanical polishing, CMP)製程去除部分低阻抗金屬層、部分功函數金屬層以及部分高介電常數介電層以形成金屬閘極。若以利用後高介電常數介電層製程所製作的金屬閘極為例，閘極結構14或金屬閘極較佳包含一介質層或閘極介電層、一U型高介電常數介電層、一U型功函數金屬層以及一低阻抗金屬層。
依據本發明一實施例，高介電常數介電層包含介電常數大於4的介電材料，例如選自氧化鉿(hafnium oxide，HfO 2)、矽酸鉿氧化合物(hafnium silicon oxide, HfSiO 4)、矽酸鉿氮氧化合物(hafnium silicon oxynitride, HfSiON)、氧化鋁(aluminum oxide, Al 2O 3)、氧化鑭(lanthanum oxide, La 2O 3)、氧化鉭(tantalum oxide, Ta 2O 5)、氧化釔(yttrium oxide, Y 2O 3)、氧化鋯(zirconium oxide, ZrO 2)、鈦酸鍶(strontium titanate oxide, SrTiO 3)、矽酸鋯氧化合物(zirconium silicon oxide, ZrSiO 4)、鋯酸鉿(hafnium zirconium oxide, HfZrO 4)、鍶鉍鉭氧化物(strontium bismuth tantalate, SrBi 2Ta 2O 9, SBT)、鋯鈦酸鉛(lead zirconate titanate, PbZr xTi 1-xO 3, PZT)、鈦酸鋇鍶(barium strontium titanate, Ba xSr 1-xTiO 3, BST)、或其組合所組成之群組。
功函數金屬層較佳用以調整形成金屬閘極之功函數，使其適用於N型電晶體(NMOS)或P型電晶體(PMOS)。若電晶體為N型電晶體，功函數金屬層可選用功函數為3.9電子伏特(eV)～4.3 eV的金屬材料，如鋁化鈦(TiAl)、鋁化鋯(ZrAl)、鋁化鎢(WAl)、鋁化鉭(TaAl)、鋁化鉿(HfAl)或TiAlC (碳化鈦鋁)等，但不以此為限；若電晶體為P型電晶體，功函數金屬層可選用功函數為4.8 eV～5.2 eV的金屬材料，如氮化鈦(TiN)、氮化鉭(TaN)或碳化鉭(TaC)等，但不以此為限。功函數金屬層與低阻抗金屬層之間可包含另一阻障層(圖未示)，其中阻障層的材料可包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等材料。低阻抗金屬層則可選自銅(Cu)、鋁(Al)、鎢(W)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide，CoWP)等低電阻材料或其組合。由於依據金屬閘極置換製程將虛置閘極轉換為金屬閘極乃此領域者所熟知技藝，在此不另加贅述。
綜上所述，本發明主要於閘極結構上形成層間介電層之後先於閘極結構旁的層間介電層內形成接觸洞，然後進行一電漿摻雜製程以形成一摻雜層於層間介電層內以及一源極/汲極區域於閘極結構旁，之後形成由阻障層與金屬層所構成的導電層於接觸洞內，平坦化導電層以形成一接觸插塞，去除摻雜層以形成一氣孔於接觸插塞旁，最後再形成一停止層於層間介電層以及接觸插塞上。依據本發明之較佳實施例利用此方式於接觸插塞周圍形成氣孔可大幅改善元件的電阻電容延遲(RC delay)。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
12:基底 14:閘極結構 16:閘極介電層 18:閘極材料層 20:硬遮罩 22:側壁子 24:輕摻雜汲極 26:層間介電層 28:接觸洞 30:電漿摻雜製程 32:摻雜層 34:源極/汲極區域 36:熱處理製程 38:阻障層 40:金屬層 42:接觸插塞 44:氣孔 46:停止層 48:金屬間介電層 50:金屬內連線
第1圖至第6圖為本發明一實施例製作半導體元件之方法示意圖。
12:基底
14:閘極結構
16:閘極介電層
18:閘極材料層
20:硬遮罩
22:側壁子
24:輕摻雜汲極
26:層間介電層
34:源極/汲極區域
38:阻障層
40:金屬層
42:接觸插塞
44:氣孔
46:停止層
48:金屬間介電層
50:金屬內連線

Claims (12)

  1. 一種製作半導體元件的方法，其特徵在於，包含： 形成一閘極結構於一基底上； 形成一層間介電層於該閘極結構上； 形成一接觸洞於該閘極結構旁之該層間介電層內； 進行一電漿摻雜製程以形成一摻雜層於該層間介電層內以及一源極/汲極區域於該閘極結構旁； 形成一導電層於該接觸洞內； 平坦化該導電層以形成一接觸插塞； 去除該摻雜層以形成一氣孔於該接觸插塞旁；以及 形成一停止層於該層間介電層以及該接觸插塞上。
  2. 如申請專利範圍第1項所述之方法，另包含： 形成一輕摻雜汲極於該閘極結構旁； 形成一側壁子於該閘極結構旁；以及 形成該層間介電層於該閘極結構上。
  3. 如申請專利範圍第1項所述之方法，另包含進行一濕蝕刻製程去除該摻雜層。
  4. 如申請專利範圍第3項所述之方法，另包含利用稀釋氫氟酸去除該摻雜層。
  5. 如申請專利範圍第1項所述之方法，其中該氣孔暴露該源極/汲極區域、該層間介電層以及該接觸插塞。
  6. 如申請專利範圍第1項所述之方法，其中該氣孔頂表面切齊該接觸插塞頂表面。
  7. 如申請專利範圍第1項所述之方法，其中該氣孔底表面切齊該接觸插塞底表面。
  8. 一種半導體元件，其特徵在於，包含： 一閘極結構設於一基底上； 一源極/汲極區域設於該閘極結構旁； 一層間介電層環繞該閘極結構； 一接觸插塞設於該閘極結構旁之該層間介電層內； 一氣孔環繞該接觸插塞；以及 一停止層設於該層間介電層以及該接觸插塞上。
  9. 如申請專利範圍第8項所述之半導體元件，另包含： 一輕摻雜汲極設於該閘極結構旁；以及 一側壁子設於該閘極結構旁。
  10. 如申請專利範圍第8項所述之半導體元件，其中該氣孔暴露該源極/汲極區域、該層間介電層以及該接觸插塞。
  11. 如申請專利範圍第8項所述之半導體元件，其中該氣孔頂表面切齊該接觸插塞頂表面。
  12. 如申請專利範圍第8項所述之半導體元件，其中該氣孔底表面切齊該接觸插塞底表面。
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