TW202401023A - Pins detection system for multi-pins chip and method thereof - Google Patents

Abstract

A Pins detection system for multi-pins chip and a method thereof are provided. A chip detection circuit board with test circuit, to-be-tested chip fixture, test chip and JTAG port is provided. Each pin of test chip are electrical connection to each pin of to-be-tested chip fixture respectively. JTAG port, test chip and to-be-tested chip fixture are connected in series through test circuit to form JTAG link. Detection device, JTAG controller and chip detection circuit board are connected in series. Detection signal is generated by detection device through JTAG controller to detect each pin of to-be-tested chip on chip detection circuit board and feedback detection result to detection device to complete detection of pin of to-be-detected chip. Therefore, the efficiency of providing convenient and fast functional detection of the pins of multi-pins chip may be achieved.

Description

Pin detection system and method applicable to multi-pin chips

A detection system and method thereof, in particular, a chip detection circuit board that provides a JTAG connection port, a detection chip and a chip fixture to be tested are connected in series through a detection circuit to form a JTAG link. The detection device detects the chip detection circuit through a JTAG controller. A pin detection system and method suitable for multi-pin chips that perform pin detection on the chip to be detected on the board.

The current inspection of complex multi-pin chips requires, in addition to quality assurance on the appearance of the chip, solder ball oxidation, etc., it is also necessary to conduct functional testing on complex multi-pin chips. Functional testing generally uses small-batch sampling to measure yield. Existing testing methods have problems such as high testing costs, long testing cycles, and complex testing methods that are inconvenient for batch testing.

To sum up, it can be seen that there have long been problems in the previous technology that for complex multi-pin chip inspection, the inspection cost is high, the inspection period is long, and the inspection method is complex and inconvenient for batch inspection. Therefore, it is necessary to propose improved technology. means to solve this problem.

In view of the existing problems in the prior art that the detection cost of complex multi-pin wafers is high, the detection cycle is long, and the detection method is complex and inconvenient for batch testing, the present invention discloses a pin detection method suitable for multi-pin wafers. System and method thereof, wherein:

The pin detection system disclosed by the present invention and suitable for multi-pin chips includes: a chip detection circuit board, a Joint Test Action Group (JTAG) controller and a detection device. The chip detection circuit board further includes : The chip fixture to be tested, the chip for detection and the JTAG connection port.

The wafer detection circuit board has a detection circuit. The wafer to be tested clamp of the wafer detection circuit board is electrically connected to the detection circuit. The wafer to be tested clamp provides clamping and fixation of the wafer to be detected. The detection wafer is electrically connected to the detection circuit. Each pin of the chip and each pin corresponding to the chip fixture to be tested are electrically connected to each other through the detection circuit; wherein, the JTAG connection port, the detection chip and the chip fixture to be tested are connected in series through the detection circuit to form a JTAG link.

The JTAG controller forms an electrical connection with the JTAG connection port; the detection device forms an electrical connection with the JTAG controller, and the detection device generates a detection signal; wherein, the detection device sends a detection signal to the JTAG controller, and the JTAG controller sends a detection signal to the chip detection Circuit board, chip detection The circuit board detects each pin of the chip to be detected based on the detection signal and feeds back the detection results to the detection device to complete the detection of the pins of the chip to be detected.

The pin detection method disclosed in the present invention and suitable for multi-pin chips includes the following steps:

First, a wafer detection circuit board with a detection circuit, a wafer clamp to be tested, a wafer for detection, and a JTAG connection port is provided; then, the wafer to be tested clamp is electrically connected to the detection circuit, and the wafer to be tested clamp provides clamping and fixation of the wafer to be detected. ; Then, the detection chip is electrically connected to the detection circuit, and each pin of the detection chip and each pin corresponding to the chip fixture to be tested are electrically connected to each other through the detection circuit; then, the JTAG connection port, detection The chip and the chip fixture to be tested are connected in series through the detection circuit to form a JTAG link; then, the JTAG controller forms an electrical connection with the JTAG connection port; then, the detection device forms an electrical connection with the JTAG controller, and the detection device generates a detection signal ; Finally, the detection device sends the detection signal to the JTAG controller, and the JTAG controller sends the detection signal to the chip detection circuit board. The chip detection circuit board detects each pin of the chip to be detected based on the detection signal and feeds back the detection results to the detection device. To complete the detection of the chip pins to be detected.

The system and method disclosed by the present invention are as described above. The difference between the system and the prior art is that it provides a chip detection circuit board with a detection circuit, a chip fixture to be tested, a detection chip and a JTAG connection port. Each pin of the detection chip is separately Each pin corresponding to the chip fixture under test is electrically connected to each other through the detection circuit. The JTAG connection port, the chip for detection and the chip fixture under test are connected in series through the detection circuit to form a JTAG link. The detection device, JTAG controller and The chip detection circuit board forms a series connection, and the detection device generates detection signals through the JTAG controller to detect each pin of the chip to be detected on the chip detection circuit board and feeds back the detection results to the detection device to complete the detection of the pins of the chip to be detected. .

Through the above technical means, the present invention can achieve the technical effect of providing convenient and rapid functional testing of the pins of a multi-pin chip.

The embodiments of the present invention will be described in detail below with reference to the drawings and examples, so that the implementation process of how to apply technical means to solve technical problems and achieve technical effects of the present invention can be fully understood and implemented accordingly.

The following will first describe the pin detection system disclosed in the present invention suitable for multi-pin chips, and please refer to "Figure 1". "Figure 1" illustrates the pin detection system of the present invention suitable for multi-pin chips. System block diagram of bit detection system.

The pin detection system disclosed by the present invention and suitable for multi-pin chips includes: a chip detection circuit board 10, a JTAG controller 20 and a detection device 30. The chip detection circuit board 10 further includes: a wafer to be tested fixture 11, a detection device Use chip 12 and JTAG port 13.

The wafer detection circuit board 10 has a detection circuit. The wafer to be tested clamp 11 of the wafer detection circuit board 10 is electrically connected to the detection circuit. The wafer to be tested clamp 11 provides clamping and fixation of the wafer to be detected. Please refer to "Chapter 11" for the wafer to be tested clamp 11. As shown in Figure 2, Figure 2 is a three-dimensional view of the chip clamp under test suitable for pin position detection of multi-pin chips according to the present invention.

The detection chip 12 is electrically connected to the detection circuit. Each pin of the detection chip 12 and each pin corresponding to the wafer clamp 11 to be tested are electrically connected to each other through the detection circuit. When the wafer to be detected is clamped and fixed, When the chip to be tested is in the fixture 11, each pin of the chip for testing 12 can be electrically connected to each other through the detection circuit with each pin of the chip to be tested. It is worth noting that the chip fixture 11 for the chip to be tested is The clamped and fixed wafer to be tested and the detection wafer 12 are the same wafer.

Please refer to "Figure 3", which is a JTAG link diagram suitable for pin detection of multi-pin chips according to the present invention.

The wafer to be tested fixture 11 defines a test data input (TDI) pin, a test data output (TDO) pin, and a test clock (Test Clock, TCK) according to the clamped and fixed wafer to be tested. pins and Test Mode Select (TMS) pins; the detection chip 12 also defines TDI pins, TDO pins, TCK pins and TMS pins; the JTAG connection port 13 also defines TDI pins, TDO pin, TCK pin and TMS pin.

The TCK pins of the chip fixture 11 to be tested, the TCK pins of the detection chip 12 and the TCK pins of the JTAG connection port 13 are connected to each other; the TMS pins of the chip fixture 11 to be tested, the TMS pins of the detection chip 12 and JTAG The TMS pins of port 13 are connected to each other.

The TDI pin of the JTAG connection port 13 is connected to the TDI pin of the detection chip 12. The TDO pin of the detection chip 12 is connected to the TDI pin of the chip fixture 11 to be tested. The TDO pin of the chip fixture 11 to be tested is connected to the JTAG Connect to the TDO pin of port 13

, whereby the JTAG connection port 13, the detection chip 12 and the chip fixture 11 to be tested can be connected in series through the detection circuit to form a JTAG link.

The JTAG controller 20 further includes a JTAG connection port 21 and a Universal Serial Bus (USB) connection port 22. The detection device 30 further includes a USB connection port 31, the JTAG connection port 21 of the JTAG controller 20 and the chip detection circuit board. The JTAG connection port 13 of 10 is electrically connected through a JTAG connection cable, and the USB connection port 31 of the detection device 30 and the USB connection port 22 of the JTAG controller 20 are electrically connected through a USB connection cable. The aforementioned detection device 30 is, for example, a general Computers, notebook computers, etc. are only used as examples and do not limit the application scope of the present invention.

Please refer to "Figure 4", which is a schematic diagram of the pin detection of the chip to be detected when the present invention is suitable for the pin detection of multi-pin chips.

The detection device 30 generates a detection signal and sends it to the JTAG controller 20. The JTAG controller 20 can convert the detection signal into a JTAG format detection signal suitable for boundary scan (Boundary Scan, BS) detection. The JTAG controller 20 then converts the converted signal into a detection signal. The detection signal is sent to the chip detection circuit board 10. The chip detection circuit board 10 can detect each pin of the chip to be detected based on the detection signal and feed back the detection results to the detection device to complete the detection of the pins of the chip to be detected.

As shown in "Figure 4", the detection signal of the first pin 121 of the detection chip 12 is "0101", and the detection result of the first pin 141 of the chip 14 to be detected is "0101". The detection device 30 The detection result received as feedback from the first pin 141 of the chip 14 to be tested is “0101” and the detection signal is “0101” and it is found to be the same, that is, the first pin 141 of the chip 14 to be tested is normal.

As shown in "Figure 4", the detection signal of the second pin 122 of the detection chip 12 is "1010", and the detection result of the second pin 142 of the chip 14 to be detected is "1111". The detection device 30 The detection result feedback received from the second pin 142 of the chip 14 to be detected is "1111" and is not affected by the detection signal "1010", that is, the detection result of the second pin 142 of the chip 14 to be detected is an open circuit abnormality.

As shown in "Figure 4", the detection signal of the third pin 123 of the detection chip 12 is "1010" and the detection signal of the fourth pin 124 of the detection chip 12 is "1011". The detection signal of the chip 14 to be detected is The detection result of the third pin 143 is “1011” and the detection result of the fourth pin 144 of the wafer 14 to be detected is “1011”. The detection device 30 receives the third pin 143 of the wafer 14 to be detected. And the detection results fed back by the fourth pin 144 are “1011” and “1011” respectively.

Since the detection signals detected by the third pin 143 and the fourth pin 144 of the chip 14 to be detected are “1010” and “1011” respectively, and the third pin 143 and the fourth pin 144 of the chip 14 to be detected are The feedback detection results are "1011" and "1011" respectively, and the detection device 30 can detect that the detection results of the third pin 143 and the fourth pin 144 of the chip 14 to be detected are short circuit abnormalities.

Next, the operation method of the present invention will be described below, and please refer to "Fig. 5". "Fig. 5" is a flow chart of a pin detection method suitable for multi-pin chips according to the present invention.

The pin detection method disclosed in the present invention and suitable for multi-pin chips includes the following steps:

First, provide a chip detection circuit board with a detection circuit, a chip fixture to be tested, a chip for detection, and a JTAG connection port (step 101); then, the chip fixture to be tested forms an electrical connection with the detection circuit, and the chip fixture to be tested provides the chip to be tested. The chip is clamped and fixed (step 102); then, the detection chip is electrically connected to the detection circuit, and each pin of the detection chip and each pin corresponding to the wafer clamp to be tested are electrically connected to each other through the detection circuit. (Step 103); Then, the JTAG connection port, the detection chip and the chip fixture to be tested are connected in series through the detection circuit to form a JTAG link (Step 104); then, the JTAG controller and the JTAG connection port form an electrical connection (Step 105 ); then, the detection device forms an electrical connection with the JTAG controller, and the detection device generates a detection signal (step 106); finally, the detection device sends the detection signal to the JTAG controller, and the JTAG controller sends the detection signal to the chip detection circuit board, and the chip The detection circuit board detects each pin of the chip to be detected based on the detection signal and feeds back the detection results to the detection device to complete the detection of the pins of the chip to be detected (step 107).

To sum up, it can be seen that the difference between the present invention and the prior art is to provide a chip detection circuit board with a detection circuit, a fixture for the chip to be tested, a detection chip and a JTAG connection port. Each pin of the detection chip is connected to the chip to be tested. Each pin corresponding to the test chip fixture is electrically connected to each other through the detection circuit. The JTAG connection port, the detection chip and the chip fixture to be tested are connected in series through the detection circuit to form a JTAG link. The detection device, JTAG controller and chip detection The circuit boards are connected in series, and the detection device generates detection signals through the JTAG controller to detect each pin of the chip to be detected on the chip detection circuit board and feeds back the detection results to the detection device to complete the detection of the pins of the chip to be detected.

This technical means can solve the problems existing in the previous technology for complex multi-pin chip inspection, such as high inspection cost, long inspection period and complicated inspection methods that are inconvenient for batch inspection, thereby achieving the goal of providing convenient and fast inspection. The technical efficacy of functional testing of the pins of multi-pin chips.

Although the embodiments disclosed in the present invention are as above, the described contents are not used to directly limit the patent protection scope of the present invention. Anyone with ordinary knowledge in the technical field to which the present invention belongs may make slight changes in the form and details of the implementation without departing from the spirit and scope of the present invention. The patent protection scope of the present invention must still be defined by the attached patent application scope.

10: Chip detection circuit board 11: Wafer fixture to be tested 12: Chip for detection 121:First foot position 122:Second foot position 123:Third foot position 124:Fourth pin 13:JTAG port 14: Wafer to be inspected 141:First foot position 142:Second foot position 143:Third foot position 144:Fourth pin 20:JTAG controller 21:JTAG port 22:USB port 30:Detection device 31:USB port TDI: test data input pin TDO: test data output pin TCK: test clock pin TMS: test mode selection pin Step 101: Provide a chip test circuit board with a test circuit, a fixture for the chip under test, a chip for test, and a JTAG connection port Step 102: The wafer clamp to be tested forms an electrical connection with the detection circuit, and the wafer clamp to be tested provides clamping and fixation of the wafer to be tested. Step 103: The detection chip is electrically connected to the detection circuit. Each pin of the detection chip and each pin corresponding to the chip fixture to be tested are electrically connected to each other through the detection circuit. Step 104: The JTAG connection port, the detection chip and the chip fixture to be tested are connected in series through the detection circuit to form a JTAG link Step 105: The JTAG controller forms an electrical connection with the JTAG port Step 106: The detection device forms an electrical connection with the JTAG controller, and the detection device generates a detection signal Step 107: The detection device sends a detection signal to the JTAG controller, and the JTAG controller sends the detection signal to the chip detection circuit board. The chip detection circuit board detects each pin of the chip to be detected based on the detection signal and feeds back the detection results to the detection device. To complete the detection of the chip pins to be detected

Figure 1 is a system block diagram of a pin detection system suitable for multi-pin chips according to the present invention. Figure 2 is a perspective view of a chip fixture under test suitable for pin detection of multi-pin chips according to the present invention. Figure 3 shows a JTAG link diagram applicable to pin detection of multi-pin chips according to the present invention. Figure 4 is a schematic diagram of the pin detection of the chip to be detected when the present invention is applicable to the pin detection of multi-pin chips. FIG. 5 is a flowchart of a pin detection method suitable for multi-pin chips according to the present invention.

10: Chip detection circuit board

11: Wafer fixture to be tested

12: Chip for detection

13:JTAG port

20:JTAG controller

21:JTAG port

22:USB port

30:Detection device

31:USB port

Claims (10)

A pin detection system suitable for multi-pin chips, which includes: A wafer detection circuit board, the wafer detection circuit board has a detection circuit, and the wafer detection circuit board further includes: A wafer clamp to be tested, the wafer clamp to be tested is electrically connected to the detection circuit, and the wafer to be tested clamp provides a clamping and fixing of the wafer to be tested; A detection chip, the detection chip is electrically connected to the detection circuit, and each pin of the detection chip corresponds to each pin of the wafer clamp to be tested through the detection circuit. form an electrical connection; and A joint test action group (Joint Test Action Group, JTAG) port, the JTAG port; Wherein, the JTAG connection port, the detection chip and the chip fixture to be tested are connected in series through the detection circuit to form a JTAG link; A JTAG controller, the JTAG controller is electrically connected to the JTAG connection port; and A detection device, the detection device is electrically connected to the JTAG controller, and the detection device generates a detection signal; Wherein, the detection device sends the detection signal to the JTAG controller, the JTAG controller sends the detection signal to the chip detection circuit board, and the chip detection circuit board detects the detection signal based on the detection signal. Each pin of the wafer to be detected is detected separately and the detection results are fed back to the detection device to complete the detection of the pins of the wafer to be detected. The pin detection system suitable for multi-pin chips as described in claim 1, wherein the detection device compares the detection signal provided by the pin of the chip to be detected and the detection result fed back by the pin of the chip to be detected is the same, The pin position of the chip to be tested is normal. The pin detection system suitable for multi-pin chips as described in claim 1, wherein the detection device compares the detection signal provided by the pin of the chip to be detected and the detection result fed back by the pin of the chip to be detected is not the same. , the pin of the chip to be detected is an open circuit abnormality. The pin detection system suitable for multi-pin chips as described in claim 1, wherein the detection device provides different detection signals for the two pins of the chip to be detected, and the two pins of the chip to be detected feedback the detection The result is the same test result, and the two pins of the chip to be tested are short-circuited. The pin detection system suitable for multi-pin chips as described in claim 1, wherein the chip fixture to be tested, the chip for detection and the JTAG connection port respectively define test data input (TDI). ) pin, test data output (Test Data Output, TDO) pin, test clock (Test Clock, TCK) pin and test mode select (Test Mode Select, TMS) pin, the chip fixture to be tested, the The detection chip and the TCK pin of the JTAG connection port are connected to each other, the chip fixture to be tested, the detection chip and the TMS pin of the JTAG connection port are connected to each other, and the TDI pin of the JTAG connection port is connected to each other. It is connected to the TDI pin of the detection chip, the TDO pin of the detection chip is connected to the TDI pin of the wafer clamp to be tested, and the TDO pin of the wafer clamp to be tested is connected to the JTAG connection port. The TDO pins are connected, so that the JTAG connection port, the detection chip and the chip fixture to be tested are connected in series through the detection circuit to form a JTAG link. A pin detection method suitable for multi-pin chips, which includes the following steps: Provide a chip detection circuit board having a detection circuit, a chip fixture to be tested, a detection chip and a JTAG connection port; The wafer to be tested clamp is electrically connected to the detection circuit, and the wafer to be tested clamp provides a clamping and fixing of the wafer to be tested; The detection chip is electrically connected to the detection circuit, and each pin of the detection chip and each pin corresponding to the wafer clamp to be tested are electrically connected to each other through the detection circuit; The JTAG connection port, the detection chip and the chip fixture to be tested are connected in series through the detection circuit to form a JTAG link; A JTAG controller forms an electrical connection with the JTAG connection port; A detection device is electrically connected to the JTAG controller, and the detection device generates a detection signal; and The detection device sends the detection signal to the JTAG controller, the JTAG controller sends the detection signal to the chip detection circuit board, and the chip detection circuit board detects the detection signal based on the detection signal. Each pin of the chip is detected separately and the detection result is fed back to the detection device to complete the detection of the pin of the chip to be detected. The pin detection method suitable for multi-pin chips as described in claim 6, wherein the detection device compares the detection signal provided by the pin of the chip to be detected and the detection result fed back by the pin of the chip to be detected is the same, The pin position of the chip to be tested is normal. The pin detection method suitable for multi-pin chips as described in claim 6, wherein the detection device compares the detection signal provided by the pin of the chip to be detected with the detection result fed back by the pin of the chip to be detected. , the pin of the chip to be detected is an open circuit abnormality. The pin detection method suitable for multi-pin chips as described in claim 6, wherein the detection device provides different detection signals for the two pins of the chip to be detected, and the two pins of the chip to be detected feedback the detection The result is the same test result, and the two pins of the chip to be tested are short-circuited. The pin detection method suitable for multi-pin chips as described in claim 6, wherein the chip fixture to be tested, the detection chip and the JTAG connection port respectively define TDI pins, TDO pins, and TCK pins and TMS pins, the chip fixture to be tested, the chip for detection and the TCK pins of the JTAG connection port are connected to each other, the chip fixture for the chip to be tested, the chip for detection and the JTAG connection port The TMS pins of the JTAG connection port are connected to each other, the TDI pin of the JTAG connection port is connected to the TDI pin of the detection chip, the TDO pin of the detection chip is connected to the TDI pin of the wafer fixture to be tested, The TDO pin of the chip to be tested fixture is connected to the TDO pin of the JTAG connection port, so that the JTAG connection port, the detection chip and the chip to be tested fixture are connected in series through the detection circuit to form a JTAG chain. road.

Images