TW202343758A - Memory device - Google Patents

Abstract

A memory device is provided. The memory device includes a stacked structure, a lower isolation structure in the stacked structure, and two memory strings in the stacked structure. The stacked structure includes conductive layers. The lower isolation structure has an upper surface in a lower portion of the stacked structure. The lower isolation structure separates at least one conductive layer of the conductive layers into a first conductive strip and a second conductive strip. The first conductive strip and the second conductive strip are electrically isolated from each other. Two memory strings are electrically connected to the first conductive strip and the second conductive strip respectively.

Description

memory device

The present invention relates to memory devices, and in particular to memory devices including lower isolation structures.

In recent years, three-dimensional memory devices have been widely used in various fields because they can achieve higher storage capacity and have better electronic properties. However, as the storage density and integration of three-dimensional memory devices increase, the problem of interference between components in the memory device becomes more serious.

Therefore, there is a need to provide an improved memory device that can reduce interference problems during the operation of the memory device.

The present invention relates to a memory device including a lower isolation structure to reduce interference problems during operation of the memory device.

According to an embodiment of the present invention, a memory device is provided. The memory device includes a stacked structure, a lower isolation structure arranged in the stacked structure, and a two-memory cell series arranged in the stacked structure. The stacked structure contains multiple conductive layers. The lower isolation structure has a surface above the lower portion of the stacked structure. The lower isolation structure separates at least one conductive layer among the plurality of conductive layers into a first conductive strip and a second conductive strip, and the first conductive strip and the second conductive strip are electrically isolated from each other. The two memory cell series are electrically connected to the first conductive strip and the second conductive strip respectively.

In order to have a better understanding of the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings.

Relevant embodiments are presented below, and the memory device and the manufacturing method thereof proposed in the present disclosure are described in detail along with the drawings. However, this disclosure is not limited thereto. The descriptions in the embodiments, such as detailed structures, steps of manufacturing methods and material applications, are only for illustration, and the scope of protection of the present disclosure is not limited to the described aspects. Those in the relevant technical field can change and modify the structure and manufacturing method of the embodiment to meet the needs of practical applications without departing from the spirit and scope of the present disclosure. Therefore, other implementation aspects not proposed in this disclosure may also be applicable. Furthermore, the drawings are simplified to clearly illustrate the contents of the embodiments, and the dimensional proportions in the drawings are not drawn to the same proportions as the actual product. Therefore, the description and drawings are only used to describe the embodiments and are not used to limit the scope of the present disclosure. The same or similar component symbols are used to represent the same or similar components.

The ordinal numbers used in the specification and the scope of the patent application, such as "first", "second", "third", etc., are used to modify the elements. They do not imply or represent that the element has any previous ordinal numbers, nor does it mean that the element has any previous ordinal numbers. Represents the order of a certain component with another component, or the order of the manufacturing method. The use of these serial numbers is only used to clearly distinguish one component with a certain name from another component with the same name.

Various embodiments of the present invention can be applied to a variety of different three-dimensional (3D) stacked memory structures. For example, embodiments may be applied to, but are not limited to, three-dimensional NAND flash memory devices.

Please refer to Figures 1A and 1B at the same time. Figure 1A is a schematic top view of the memory device 10 according to an embodiment of the present invention. Figure 1B is along the section line P1 in Figure 1A. A schematic cross-sectional view of the memory device 10 . The memory device 10 may include a substrate 100, a stacked structure S, a plurality of pillar elements 103, at least one upper isolation structure 104, at least a lower isolation structure 105, and a plurality of isolation elements 106.

The stacked structure S is arranged on the substrate 100 . The stacked structure S may include a plurality of insulating layers 101 and a plurality of conductive layers 102 staggeredly stacked along the first direction D1. The first direction D1, the second direction D2 and the third direction D3 may be perpendicular to each other. The first direction D1 may be a normal direction of the upper surface of the substrate 100 . The first direction D1 may be, for example, the Z direction, the second direction D2 may be, for example, the X direction, and the third direction D3 may be, for example, the Y direction. The plurality of insulating layers 101 isolate the plurality of conductive layers 102 from each other. For the sake of simplicity, FIG. 1B does not show all the layers of the stacked structure S. The number of layers in the stacked structure S can be adjusted according to needs. In an embodiment, the conductive layer 102 in the stacked structure S has a thickness T1 in the first direction D1, and the thickness T1 is about 200-350 angstrom; ).

A plurality of column elements 103 are dispersedly arranged in the stacked structure S. The pillar element 103 may extend through the stacked structure S along the first direction D1. The pillar component 103 may include a memory layer 121, a channel layer 122, an insulating pillar 123 and a pad 124. Memory layer 121 may surround channel layer 122. The memory layer 121 may have a tubular shape, such as a tubular shape with one end open and the other end closed. The channel layer 122 may be disposed between the memory layer 121 and the insulating pillar 123 and surround the insulating pillar 123 . The channel layer 122 may have a tubular shape, such as a tubular shape with one end open and the other end closed. The lower portion of the memory layer 121 is removed to expose a portion of the channel layer 122 . The exposed portion of the channel layer is electrically connected to the substrate 100 . In another example, the memory layer 121 may have a tube shape with both ends open. The bottom of the memory layer 121 is removed to expose a portion of the channel layer 122 . The exposed portion of the channel layer is electrically connected to the substrate 100 . The pads 124 can be disposed on the channel layer 122 and the insulating pillars 123 and are surrounded by the memory layer 121 . The pads 124 can be electrically connected to the channel layer 122 .

At least one upper isolation structure 104 is configured in the stacked structure S. The upper isolation structure 104 may extend along the first direction D1 and penetrate one or more insulating layers 101 and/or one or more conductive layers 102 in the stacked structure S. For example, in the embodiment shown in FIG. 1B , the upper isolation structure 104 can be disposed on the upper part of the stacked structure S, and can penetrate the four insulating layers 101 and the three conductive layers 102 located on the upper part of the stacked structure S. Specifically, the upper isolation structure 104 penetrates the three conductive layers 102 farthest from the substrate 100 among the plurality of conductive layers 102, and causes each of the three conductive layers 102 to be separated into conductive strips 133, 134, 135, 136. The conductive strips 133, 134, 135 and 136 are electrically isolated from each other. In one embodiment, the upper isolation structure 104 can separate at least three conductive layers 102 located on the upper portion of the stacked structure S. For example, the upper isolation structure 104 can separate 3-7 conductive layers 102 located on the upper part of the stacked structure S.

At least one isolation structure 105 is configured in the stack structure S. The lower isolation structure 105 may extend along the first direction D1 and penetrate one or more insulation layers 101 and/or one or more conductive layers 102 in the stack structure S. For example, in the embodiment shown in FIG. 1B , the lower isolation structure 105 can be disposed at the lower part of the stacked structure S and penetrate the four insulating layers 101 and the three conductive layers 102 located at the lower part of the stacked structure S. The upper surface 105u of the lower isolation structure 105 may be located at the lower part of the stacked structure S. In one example, the lower isolation structure 105 may extend from the upper surface 105u to the substrate 100 . The lower isolation structure 105 penetrates at least three conductive layers 102 closest to the substrate 100 among the plurality of conductive layers 102, and causes each of the at least three conductive layers 102 to be separated into conductive strips 131, 132. The conductive strips 131 (eg, the first conductive strips) and the conductive strips 132 (eg, the second conductive strips) may be located on opposite sides of the lower isolation structure 105 respectively. The conductive strips 131 and 132 are electrically isolated from each other. In one embodiment, the lower isolation structure 105 can separate at least three conductive layers 102 located at the lower part of the stacked structure S. For example, the lower isolation structure 105 can separate 3-10 conductive layers 102 located at the lower part of the stacked structure S.

In this embodiment, the number of the upper isolation structures 104 is greater than the number of the lower isolation structures 105 , and an upper isolation structure 104 among the plurality of upper isolation structures 104 may at least partially overlap with the lower isolation structure 105 in the first direction D1 . In one embodiment, on a plane including the second direction D2 and the third direction D3, the lower isolation structure 105 may be substantially aligned with an upper isolation structure 104 among the plurality of upper isolation structures 104 (eg, FIG. 1A The lower isolation structure 105 generally aligned with an upper isolation structure 104 is represented by a dotted line).

A plurality of isolation elements 106 are dispersedly arranged in the stacked structure S. As shown in FIG. 1A , the isolation element 106 may be a strip extending along the second direction D2. As shown in FIG. 1B , the isolation element 106 may extend through the stacked structure S along the first direction D1 . The isolation element 106 may include an isolation film 141 and a conductive film 142. The isolation film 141 may be disposed between the conductive film 142 and the stacked structure S. The isolation film 141 can be used to electrically isolate the conductive film 142 from the plurality of conductive layers 102 . The bottom of the isolation film 141 is removed to expose a portion of the conductive film 142 . The exposed portion of the conductive film 142 is electrically connected to the substrate 100 . The isolation element 106 may serve as a source line, such as a common source line.

The memory device 10 may also include a plurality of memory cell series arranged in the stacked structure S. Each memory cell series may include a plurality of memory cells arranged along the first direction D1, and the memory cells may be defined in the memory layer 121 at the intersection of the conductive layer 102 and the channel layer 122 of the pillar element 103. For the sake of simplicity, only four memory cell series M1, M2, M3, and M4 are marked in Figures 1A-1B. However, in practice, the memory device may include more memory cell series. The memory cell string M1 can share the channel layer 122 of the pillar element 103 where it is located. The memory cell series M1 can electrically connect the channel layer 122, the conductive strip 131 and the conductive strip 133. The memory cell series M2 can share the channel layer 122 of the column element 103 where it is located, and the memory cell series M2 can be electrically connected to the channel layer 122, the conductive strip 131 and the conductive strip 134. The memory cell series M3 can share the channel layer 122 of the column element 103 where it is located, and the memory cell series M3 can be electrically connected to the channel layer 122, the conductive strip 132 and the conductive strip 135. The memory cell series M4 can share the channel layer 122 of the pillar element 103 where it is located, and the memory cell series M4 can be electrically connected to the channel layer 122, the conductive strip 132 and the conductive strip 136.

In one embodiment, the memory device 10 may include at least one string selection line and at least one ground selection line electrically connected to opposite ends of the memory cell string. For example, the three conductive layers 102 (conductive strips 133 , 134 , 135 , 136 ) in the memory device 10 that are farthest from the substrate 100 can serve as string selection lines for the memory cell string. The memory cells defined in the memory layer 121 at the intersection of the conductive strips 133, 134, 135, 136 and the channel layer 122 of the pillar element 103 can serve as series selection transistors. The three conductive layers 102 (conductive strips 131, 132) of the memory device 10 closest to the substrate 100 can serve as ground selection lines for the memory cell string. The memory cells defined in the memory layer 121 at the intersection of the conductive strips 131 and 132 and the channel layer 122 of the pillar element 103 can serve as ground selection transistors. Other conductive layers 102 in the memory device 10 (eg, the conductive layer 102 that is not separated by the upper isolation structure 104 and the lower isolation structure 105 ) may serve as word lines. In the memory device 10 , the conductive layer 102 serving as the series selection line is divided into conductive strips 133 , 134 , 135 , and 136 by the upper isolation structure 104 . The conductive strips 133, 134, 135, 136 are electrically isolated from each other. Therefore, the series selection transistors electrically connected to the memory cell series M1, M2, M3, and M4 respectively can be independently controlled through different series selection lines. In the memory device 10 , the conductive layer 102 serving as the ground selection line is divided into conductive strips 131 and 132 by the lower isolation structure 105 . The conductive strips 131, 132 are electrically isolated from each other. Therefore, the ground selection transistors electrically connected to the memory cell series M1 and M2 respectively can be controlled through a common ground selection line. The ground selection transistors electrically connected to the memory cell series M3 and M4 respectively can be controlled through another common ground selection line.

The memory device 10 may also include at least a first upper conductive structure 107 and at least a second upper conductive structure 108 . At least one first upper conductive structure 107 and at least one second upper conductive structure 108 may be disposed above the stacked structure S. The first upper conductive structure 107 and the second upper conductive structure 108 can be electrically connected to the channel layer 122 and the pad 124 of different pillar elements 103 respectively. In this embodiment, the first upper conductive structure 107 and the second upper conductive structure 108 are disposed above the eight pillar elements 103 arranged along the third direction D3 (as shown in FIG. 1A ). The first upper conductive structure 107 The channel layer 122 (as shown in Figure 1B) of four pillar elements 103 among the eight pillar elements 103 is electrically connected to the memory cell series M1, M2, M3, M4. The second upper conductive structure 108 is electrically connected to The channel layer 122 (shown as a dotted line in FIG. 1B ) connected to the other four pillar elements 103 among the eight pillar elements 103 is in series with other memory cells. The first upper conductive structure 107 and the second upper conductive structure 108 can serve as bit lines.

In one embodiment, the memory device 10 may include multiple blocks, and multiple isolation elements 106 isolate the multiple blocks from each other. Each block may include multiple sub-blocks, and multiple upper isolation structures 104 isolate the multiple sub-blocks from each other. The memory device 10 can be operated on a sub-block basis, such as a read operation or an erase operation.

FIG. 1C is a schematic cross-sectional view of the memory device 10 along the sectional line P1-1 in FIG. 1A. In one embodiment, the memory device 10 may further include a plurality of tubular elements 109 dispersedly arranged in the stack structure S. The tubular element 109 may extend through the stack structure S along the first direction D1 and be disposed under the upper isolation structure 104 . The tubular component 109 may include a memory layer 151 , a dummy channel layer 152 and an insulating pillar 153 . Memory layer 151 may surround dummy channel layer 152. The memory layer 151 may have a tubular shape, such as a tubular shape with one end open and the other end closed. The dummy channel layer 152 may be disposed between the memory layer 151 and the insulating pillar 153 and surround the insulating pillar 153 . The dummy channel layer 152 may have a tubular shape, such as a tubular shape with one end open and the other end closed. The memory layer 151 of the tubular element 109 may be similar to the memory layer 121 of the pillar element 103 . The insulating posts 153 of the tubular element 109 may be similar to the insulating posts 123 of the post element 103 . In one embodiment, the dummy channel layer 152 may refer to a channel layer without a driving circuit. In one embodiment, the dummy channel layer 152 can be understood as an electrically floating component.

In one embodiment, a control circuit, such as a CMOS logic circuit, can be disposed in a peripheral region of the memory device 10 to form a structure in which the control circuit is placed next to the array (CMOS next to array; CnA). In one embodiment, a control circuit, such as a CMOS logic circuit, can be disposed in an area below the memory device 10 to form a structure in which the control circuit is placed under the array (CMOS under array; CuA). In one embodiment, a control circuit, such as a CMOS logic circuit, may be bonded to the memory device 10 to form a control circuit bonded array (CMOS bonded array; CbA).

Please refer to Figure 1D. Figure 1D is an equivalent circuit diagram of the memory cell series M1, M2, M3 and M4 in the memory device 10 shown in Figure 1B. In Figure 1B, each memory cell series M1, M2, M3, and M4 is electrically connected to three series selection lines and three ground selection lines. However, for the sake of simplicity, Figure 1D only shows that each memory cell series M1, M2, M3, and M4 is connected to three series selection lines and three ground selection lines. A series selection line and a ground selection line are provided at opposite ends of the memory cell string.

A plurality of word lines WL (for example, the conductive layer 102) are electrically connected to the memory cell series M1, M2, M3, and M4. The memory cell series M1, M2, M3, and M4 are electrically connected between the bit line BL (for example, the first upper conductive structure 107) and the source line SL.

The series selection line SSL1 (for example, the conductive strip 133) and the ground selection line GSL1 (for example, the conductive strip 131) are electrically connected to opposite ends of the memory cell series M1. The series selection line SSL1 is electrically connected between the bit line BL and the memory cell series M1. The intersection of the series selection line SSL1 and the memory cell series M1 can be defined as the series selection transistor 161. The ground selection line GSL1 is electrically connected between the source line SL and the memory cell series M1 . The intersection of the ground selection line GSL1 and the memory cell series M1 can be defined as the ground selection transistor 165 . The series selection line SSL2 (for example, the conductive strip 134) and the ground selection line GSL1 (for example, the conductive strip 131) are electrically connected to opposite ends of the memory cell series M2. The series selection line SSL2 is electrically connected between the bit line BL and the memory cell series M2. The intersection of the series selection line SSL2 and the memory cell series M2 can be defined as the series selection transistor 162. The ground selection line GSL1 is electrically connected between the source line SL and the memory cell series M2. The intersection of the ground selection line GSL1 and the memory cell series M2 can be defined as the ground selection transistor 166. The series selection line SSL3 (for example, the conductive strip 135) and the ground selection line GSL2 (for example, the conductive strip 132) are electrically connected to opposite ends of the memory cell series M3. The series selection line SSL3 is electrically connected between the bit line BL and the memory cell series M3. The intersection of the series selection line SSL3 and the memory cell series M3 can be defined as the series selection transistor 163. The ground selection line GSL2 is electrically connected between the source line SL and the memory cell series M3. The intersection of the ground selection line GSL2 and the memory cell series M3 can be defined as the ground selection transistor 167. The series selection line SSL4 (such as the conductive strip 136) and the ground selection line GSL2 (such as the conductive strip 132) are electrically connected to opposite ends of the memory cell series M4. The series selection line SSL4 is electrically connected between the bit line BL and the memory cell series M4. The intersection of the series selection line SSL4 and the memory cell series M4 can be defined as the series selection transistor 164. The ground selection line GSL2 is electrically connected between the source line SL and the memory cell series M4. The intersection of the ground selection line GSL2 and the memory cell series M4 can be defined as the ground selection transistor 168.

When the memory device 10 shown in FIG. 1D is in a read operation, for example, a read operation is performed on a selected memory cell in the memory cell series M1, and the series selection of the series electrically connected to the memory cell series M1 is performed. A voltage is applied to line SSL1 to turn on the series selection transistor 161 electrically connected to the series selection line SSL1, and a voltage is applied to the ground selection line GSL1 electrically connected to the memory cell series M1 to turn on the ground selection line GSL1. The ground selector transistor 165. Since the memory cell series M1 and the memory cell series M2 are both electrically connected to the ground selection line GSL1, the ground selection transistor 166 electrically connected to the memory cell series M2 will also be turned on during this read operation.

In this read operation, the memory cell series M3 and the memory cell series M4 are not electrically connected to the ground selection line GSL1, and the memory cell series M3 and the memory cell series M4 are electrically connected to the ground selection transistor 167 and the ground selection line. The transistor 168 can remain turned off, and no capacitance is generated in the channel layer 122 electrically connecting the memory cell series M3 and the memory cell series M4. In one embodiment, the channel layer 122 electrically connecting the memory cell series M3 and the memory cell series M4 may be in an electrically floating state.

Please refer to Figure 2A and Figure 2B at the same time. Figure 2A is a schematic top view of the memory device 20 according to another embodiment of the present invention. Figure 2B is along the section line P2 in Figure 2A. A schematic cross-sectional view of the memory device 20. The difference between the memory device 20 and the memory device 10 is that the stacking structure S2 of the memory device 20 may be different from the stacking structure S of the memory device 10 , and the number and configuration of the isolation structures 205 under the memory device 20 are different from those under the memory device 10 Structure 105. The difference between the memory device 20 and the memory device 10 is described in detail as follows.

The memory device 20 may include a stack structure S2 disposed on the substrate 100 . The stacked structure S2 may include a plurality of insulating layers 101 and a plurality of conductive layers 102 staggeredly stacked along the first direction D1. The plurality of insulating layers 101 isolate the plurality of conductive layers 102 from each other. The stacked structure S2 may further include a conductive layer 202 disposed below the plurality of conductive layers 102 and located on the substrate 100 . An insulating layer 101 may be disposed between the conductive layer 202 and the conductive layer 102 . An insulating layer 101 may be disposed between the conductive layer 202 and the substrate 100 . For the sake of simplicity, FIG. 2B does not show all the layers of the stacked structure S2, and the number of layers in the stacked structure S2 can be adjusted according to needs.

The memory device 20 may include a plurality of lower isolation structures 205 arranged in the stack structure S2. The lower isolation structure 205 may extend along the first direction D1 and penetrate the conductive layer 202 in the stacked structure S2. For example, in the embodiment shown in Figure 2B, the lower isolation structure 205 can be disposed at the lower part of the stacked structure S2, and the upper surface 205u of the lower isolation structure 205 is located at the lower part of the stacked structure S2 and penetrates the lower part of the stacked structure S2. conductive layer 202. Specifically, the lower isolation structure 205 penetrates the conductive layer (for example, the conductive layer 202) closest to the substrate 100 in the stacked structure S2, and the plurality of lower isolation structures 205 causes the conductive layer 202 to be separated into conductive strips 231, 232, 233, 234. The conductive strips 231, 232, 233, 234 are electrically isolated from each other. The conductive strips 231 (eg, the first conductive strips) and the conductive strips 232 (eg, the second conductive strips) may be located on opposite sides of the lower isolation structure 205 respectively. The conductive strips 232 and 233 may be located on opposite sides of the lower isolation structure 205 respectively. The conductive strips 233 and 234 may be located on opposite sides of the lower isolation structure 205 respectively.

In one embodiment, the number of isolation structures 104 on the memory device 20 may be equal to the number of lower isolation structures 205 , and the configuration of the upper isolation structures 104 in the third direction D3 may be substantially similar to the configuration of the lower isolation structures 205 in the third direction D3 configuration on. The lower isolation structure 205 may be between the plurality of sub-blocks defined by the upper isolation structure 104 . In an embodiment, the plurality of upper isolation structures 104 may at least partially overlap with the plurality of lower isolation structures 205 in the first direction D1 respectively. In one embodiment, on a plane including the second direction D2 and the third direction D3, the position of the lower isolation structure 205 may be substantially aligned with the upper isolation structure 104 (for example, the upper isolation structure 104 and the upper isolation structure 104 are represented by dashed lines in FIG. 2A respectively substantially aligned lower isolation structures 205).

In the stacked structure S2, the conductive layer 102 (which can also be understood as the conductive layer that is not separated by the lower isolation structure 205) has a thickness T1 in the first direction D1. At least one conductive layer 202 close to the bottom of the stacked structure S2 (which can also be understood as a conductive layer serving as at least one ground selection line and separated by the lower isolation structure 205) has a thickness T2 in the first direction D1, and the thickness T2 can be greater than Thickness T1. In one embodiment, the thickness T2 is between 3-10 times the thickness T1. In one embodiment, the thickness T1 of the conductive layer 102 is approximately 200-350 angstrom; ). The thickness T2 of the at least one conductive layer 202 near the bottom of the stacked structure S2 is approximately 1000-2500 angstroms. The ratio of thickness T2 to thickness T1 (T2/T1) can be between 4 and 7. In an example, the conductive layer 202 may be made of a material different from the conductive layer 102 . Conductive layer 102 contains tungsten. Conductive layer 202 includes polysilicon.

The memory cell series M1 of the memory device 20 is electrically connected to the conductive strip 231 and the conductive strip 133 . The memory cell series M2 of the memory device 20 is electrically connected to the conductive strip 232 and the conductive strip 134 . The memory cell series M3 of the memory device 20 is electrically connected to the conductive strip 233 and the conductive strip 135 . The memory cell series M4 of the memory device 20 is electrically connected to the conductive strip 234 and the conductive strip 136 . The conductive strips 133, 134, 135, 136 can be used as series selection lines for the memory cell string, and are defined in the memory layer 121 at the intersection of the conductive strips 133, 134, 135, 136 and the channel layer 122 of the pillar element 103. The memory cells in it can be used as series selection transistors. The conductive strips 231, 232, 233, and 234 can be used as ground selection lines for the memory cell series and are defined in the memory layer 121 at the intersection of the conductive strips 231, 232, 233, and 234 and the channel layer 122 of the pillar element 103. The memory cell can be used as a ground selection transistor. Other conductive layers 102 in the memory device 20 (eg, conductive layers 102 that are not separated by the upper isolation structure 104) may serve as word lines. In the memory device 20, the series selection transistors electrically connected to the memory cell series M1, M2, M3, and M4 respectively can be independently controlled through different series selection lines; the series selection transistors electrically connected to the memory cell series M1, M2, M3 respectively , M4's ground selection transistor can be controlled independently through different ground selection lines.

Please refer to Figure 2C. FIG. 2C is an equivalent circuit diagram of the memory cell series M1 , M2 , M3 , and M4 in the memory device 20 shown in FIG. 2B . In Figure 2B, each memory cell series M1, M2, M3, and M4 is electrically connected to three series selection lines and one ground selection line. However, for the sake of simplicity, Figure 2C only shows that each memory cell series M1, M2, M3, and M4 is connected to a ground selection line. A series selection line and a ground selection line are provided at opposite ends of the memory cell string.

A plurality of word lines WL (for example, the conductive layer 102) are electrically connected to the memory cell series M1, M2, M3, and M4. The memory cell series M1, M2, M3, and M4 are electrically connected between the bit line BL (for example, the first upper conductive structure 107) and the source line SL.

The series selection line SSL1 (for example, the conductive strip 133) and the ground selection line GSL1 (for example, the conductive strip 231) are electrically connected to opposite ends of the memory cell series M1. The series selection line SSL1 is electrically connected between the bit line BL and the memory cell series M1. The intersection of the series selection line SSL1 and the memory cell series M1 can be defined as the series selection transistor 161. The ground selection line GSL1 is electrically connected between the source line SL and the memory cell series M1 . The intersection of the ground selection line GSL1 and the memory cell series M1 can be defined as the ground selection transistor 265 . The series selection line SSL2 (such as the conductive strip 134) and the ground selection line GSL2 (such as the conductive strip 232) are electrically connected to opposite ends of the memory cell series M2. The series selection line SSL2 is electrically connected between the bit line BL and the memory cell series M2. The intersection of the series selection line SSL2 and the memory cell series M2 can be defined as the series selection transistor 162. The ground selection line GSL2 is electrically connected between the source line SL and the memory cell series M2. The intersection of the ground selection line GSL2 and the memory cell series M2 can be defined as the ground selection transistor 266. The series selection line SSL3 (for example, the conductive strip 135) and the ground selection line GSL3 (for example, the conductive strip 233) are electrically connected to opposite ends of the memory cell series M3. The series selection line SSL3 is electrically connected between the bit line BL and the memory cell series M3. The intersection of the series selection line SSL3 and the memory cell series M3 can be defined as the series selection transistor 163. The ground selection line GSL3 is electrically connected between the source line SL and the memory cell series M3. The intersection of the ground selection line GSL3 and the memory cell series M3 can be defined as the ground selection transistor 267. The series selection line SSL4 (such as the conductive strip 136) and the ground selection line GSL4 (such as the conductive strip 234) are electrically connected to opposite ends of the memory cell series M4. The series selection line SSL4 is electrically connected between the bit line BL and the memory cell series M4. The intersection of the series selection line SSL4 and the memory cell series M4 can be defined as the series selection transistor 164. The ground selection line GSL4 is electrically connected between the source line SL and the memory cell series M4 . The intersection of the ground selection line GSL4 and the memory cell series M4 can be defined as the ground selection transistor 268 .

When the memory device 20 shown in FIG. 2C is in the reading operation, for example, the reading operation is performed on a selected memory cell in the memory cell series M1, and the series selection of the series electrically connected to the memory cell series M1 is performed. A voltage is applied to line SSL1 to turn on the series selection transistor 161 electrically connected to the series selection line SSL1, and a voltage is applied to the ground selection line GSL1 electrically connected to the memory cell series M1 to turn on the ground selection line GSL1. The ground selector transistor 265.

In this read operation, the memory cell series M2, the memory cell series M3, and the memory cell series M4 are not electrically connected to the ground selection line GSL1, and are electrically connected to the ground selection transistor 266 and the memory cell series M2 of the memory cell series M2. The ground selection transistor 267 connected to the memory cell series M3 and the ground selection transistor 268 electrically connected to the memory cell series M4 can remain closed, electrically connecting the memory cell series M2, the memory cell series M3 and the memory cell string. No capacitance is generated in the channel layer 122 of column M4. In one embodiment, the channel layer 122 electrically connected to the memory cell series M2, the memory cell series M3, and the memory cell series M4 may be in an electrically floating state.

In a comparative example, the memory device does not include a lower isolation structure, and the memory cell series M1, M2, M3, and M4 are all electrically connected to the same ground selection line. During the operation of the memory device, applying a voltage to the ground selection line will turn on all the ground selection transistors arranged at the intersection of the memory cell series M1, M2, M3, M4 and the ground selection line, so that the memory cell series M1, M2, Both M3 and M4 are affected by the voltage applied to the ground selection line, causing the channel layers electrically connected to the memory cell series M1, M2, M3, and M4 to generate capacitance, thereby causing the word line load to increase and read problems such as interference.

In one embodiment of the present invention, as shown in FIGS. 1A-1D , the lower isolation structure 105 separates at least one conductive layer 102 located at the lower part of the stacked structure S into conductive strips that are electrically isolated from each other and can serve as ground selection lines. The strips 131 (eg, first conductive strips) and conductive strips 132 (eg, second conductive strips), memory cell series electrically connected to different ground selection lines can be controlled respectively. Specifically, applying a voltage to one of the ground selection lines will turn on the ground selection transistors 165 and 166 electrically connected to the memory cell series M1 and M2 or the ground selection transistors 167 and 167 electrically connected to the memory cell series M3 and M4. 168, without causing capacitance to be generated in the channel layers electrically connected to the memory cell series M1, M2, M3, and M4. Therefore, compared with the comparative example, the word line load of this embodiment is reduced by 50%, and the problem of read interference can be reduced.

In another embodiment of the present invention, as shown in FIGS. 2A-2C , a plurality of lower isolation structures 205 separates the conductive layer 202 located at the lower part of the stacked structure S2 to be electrically isolated from each other and can be used as conductive ground selection lines. Strips 231 (eg, first conductive strips), conductive strips 232 (eg, second conductive strips), conductive strips 233 and 234, memory cell series electrically connected to different ground selection lines can be Control separately. Specifically, applying a voltage to one of the ground selection lines will turn on one of the ground selection transistors 265, 266, 267, and 268 electrically connected to the memory cell series M1, M2, M3, and M4 respectively, without causing The channel layers electrically connected to the memory cell series M1, M2, M3, and M4 all generate capacitance. Therefore, compared with the comparative example, the word line load of this embodiment is reduced by 75%, and the problem of read interference can be reduced.

Figures 3-10 illustrate a method for manufacturing a memory device according to an embodiment of the present invention.

Please refer to Figure 3. A substrate 100 is provided. Layer stack S3 is formed on substrate 100 . The layer stack S3 may include at least one insulating layer 101 and at least one dielectric layer 302 staggeredly stacked along the first direction D1. For example, the layer stack S3 can be formed by sequentially depositing the insulating layer 101 and the dielectric layer 302 . The substrate 100 may include doped or undoped semiconductor material, such as silicon. However, the present invention is not limited to this. The insulating layer 101 may include an oxide such as silicon oxide, or other suitable dielectric materials. Dielectric layer 302 may include nitride, such as silicon nitride, or other suitable dielectric materials. In one embodiment, the insulating layer 101 and the dielectric layer 302 include different materials.

Please refer to Figure 4. A lower isolation structure 105 is formed in layer stack S3. The lower isolation structure 105 may extend downwardly toward the substrate 100 . The lower isolation structure 105 may extend along the first direction D1 and the second direction D2, and separate at least one insulation layer 101 and at least one dielectric layer 302 in the layer stack S3 into two parts isolated from each other. For example, the layer stack S3 may be etched, such as wet etching or dry etching, to remove part of the layer stack S3 to form the trench 401; the trench 401 is formed along the Extends downward along the first direction D1 and stops on the upper surface 100u of the substrate 100; the trench 401 exposes the sidewalls of the layer stack S3 (also serving as the sidewalls of the trench 401), and exposes part of the upper surface 100u of the substrate 100 ( At the same time, it also serves as the bottom of the trench 401) is exposed; then, the lower isolation structure 105 is formed in the trench 401 through a deposition process. Lower isolation structure 105 may include a dielectric material, such as an oxide.

Please refer to Figure 5. An insulation stack structure S4 is formed on the layer stack S3. The insulation stack structure S4 may cover the upper surface 105u of the lower isolation structure 105 and the upper surface 501u of the layer stack S3. The lower isolation structure 105 and the layer stack S3 may be located under the insulation stack structure S4. The insulation stack structure S4 may include a plurality of insulation layers 101 and a plurality of dielectric layers 302 staggeredly stacked along the first direction D1. For example, the insulating stack structure S4 can be formed by sequentially depositing the insulating layer 101 and the dielectric layer 302 . In one embodiment, the number of layers in the insulation stack S4 may be greater than the number of layers in the layer stack S3.

Please refer to Figure 6. A plurality of pillar elements 103 are formed. The plurality of pillar elements 103 may be dispersedly configured in the insulation stack structure S4 and the layer stack S3. A plurality of pillar elements 103 may be disposed on opposite sides of the lower isolation structure 105 . The pillar element 103 may extend along the first direction D1 through the insulation stack structure S4 and the layer stack S3. In one embodiment, forming the pillar element 103 may include the following steps. The insulating stack structure S4 and the layer stack S3 are patterned to form a plurality of holes 601 that are isolated from each other. For example, the insulating stack structure S4 and the layer stack S3 can be patterned by a photolithography process. The hole 601 extends downward along the first direction D1 and stops at the substrate 100; the hole 601 exposes the sidewalls of the insulating stack structure S4 and the layer stack S3 (also serving as the sidewalls of the hole 601), and exposes the substrate 100 (also serves as the sidewall of the hole 601). The bottom of hole 601) is exposed. Then, the memory layer 121 can be lined in the hole 601 by a deposition process, and the bottom of the memory layer 121 can be removed by an etching process. The channel layer 122 may be deposited on the sidewalls of the memory layer 121 and contact the substrate 100 through the exposed bottom of the memory layer 121 . The insulating pillars 123 can fill the remaining space in the holes 601 through a deposition process. Then, part of the channel layer 122 and part of the insulating pillar 123 may be removed by etching back and/or chemical-mechanical planarization (CMP), and part of the memory layer 121 may be exposed. side walls. Next, the pads 124 can be formed on the channel layer 122 and the insulating pillar 123 through a deposition process. By performing the steps described above in FIG. 6 , the pillar element 103 can be formed in the insulation stack structure S4 and the layer stack S3 .

The memory layer 121 may include a multilayer structure. For example, the memory layer 121 may include a tunnel layer disposed on the outer wall of the channel layer 122, and a storage layer disposed on the outer wall of the tunnel layer. storage layer), and a blocking layer disposed on the outer wall of the storage layer. In one embodiment, the memory layer 121 may include a multi-layer structure known in the field of memory technology, such as an ONO (Oxide-Nitride-Oxide) structure, ONONO (Oxide-Nitride-Oxide-Nitride- oxide) structure, ONONONO (oxide-nitride-oxide-nitride-oxide-nitride-oxide) structure, SONOS (silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure, BE- SONOS (bandgap silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure, TANOS (tantalum nitride-aluminum oxide-silicon nitride-silicon oxide-silicon) structure, MA BE-SONOS (metal-high dielectric Electric constant material energy band gap silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure and its combination. Channel layer 122 may include a semiconductor material, such as a doped or undoped semiconductor material. In one embodiment, the channel layer 122 may include polysilicon, such as doped polysilicon or undoped polysilicon. Insulating pillars 123 may include oxides such as silicon oxide, or other suitable dielectric materials. The pad 124 may include a semiconductor material, such as a metal silicide, a doped semiconductor material, or an undoped semiconductor material. In one embodiment, the pads 124 may include polycrystalline silicon, such as doped polycrystalline silicon or undoped polycrystalline silicon.

Please refer to Figure 7. A plurality of slits 701 are formed in the insulation stack structure S4 and the layer stack S3. For example, the insulating stack structure S4 and the layer stack S3 may be etched to remove part of the insulating stack structure S4 and part of the layer stack S3 to form a slit 701 extending along the first direction D1; when the etching process is The etching is stopped when proceeding slightly beyond the lower surface 702b of layer stack S3. The slit 701 exposes the sidewalls of the insulation stack structure S4 and the layer stack S3 (also serving as the sidewalls of the slit 701 ), and exposes the substrate 100 (also serves as the bottom of the slit 701 ).

Please refer to Figure 8. The plurality of dielectric layers 302 in the insulating stack structure S4 and the layer stack S3 are replaced with conductive layers 102, and an isolation element 106 is formed in the slit 701. For example, an etching process may be performed through the slits 701 to remove the dielectric layers 302 in the insulation stack structure S4 and the layer stack S3 , thereby forming spaces between the insulation layers 101 . The etching process used to remove dielectric layer 302 does not remove lower isolation structure 105 . In order to ensure that the lower isolation structure 105 is not removed during this etching process, the etch selectivity of the material of the lower isolation structure 105 may be different from the etch selectivity of the material of the dielectric layer 302 , for example, in an etching process, the dielectric The etching rate of the material of the electrical layer 302 can be higher than the etching rate of the material of the lower isolation structure 105; by controlling the time during which the etching process is performed, the dielectric layer 302 can be removed and the lower isolation structure 105 can be retained.

In one embodiment, the lower isolation structure 105 separates the layer stack S3 into two parts that are isolated from each other. The layer stack S3 can be removed by etching through a plurality of slits 701 disposed on opposite sides of the lower isolation structure 105 . Dielectric layers 302 located on both sides of the lower isolation structure 105 .

Then, the spaces between the plurality of insulating layers 101 are filled with conductive material to form the conductive layer 102 between the plurality of insulating layers 101 . The dielectric layer 302 formed on the opposite sides of the lower isolation structure 105 (ie, the dielectric layer 302 in the layer stack S3) is replaced by a conductive material to form the conductive layer 102. The lower isolation structure 105 separates these conductive layers 102 to be electrically connected to each other. Sexually isolated conductive strips 131, 132. The conductive layer 102 may include conductive materials such as polysilicon or metal. In one embodiment, the conductive layer 102 may include tungsten (W). In one embodiment, at least part of the conductive layer 102 on the lower isolation structure 105 may serve as a gate. The above steps included in Figure 8 can be understood as a gate replacement process. After the conductive layer 102 is formed, a stacked structure S including a plurality of insulating layers 101 and a plurality of conductive layers 102 is formed.

After the conductive layer 102 is formed, the isolation film 141 is formed on the sidewall of the slit 701 , and the remaining space in the slit 701 is filled with the conductive film 142 . The isolation film 141 and the conductive film 142 may be formed by, for example, a deposition process. The isolation film 141 may include a dielectric material such as silicon dioxide. The conductive film 142 may include conductive materials such as polysilicon or metal. In one embodiment, the conductive film 142 may include tungsten.

Please refer to Figure 9. A plurality of upper isolation structures 104 are formed in the stacked structure S. The upper isolation structure 104 may be formed above the stacked structure S and passes through one or more insulating layers 101 and/or one or more conductive layers 102 in the stacked structure S along the first direction D1. For example, the stacked structure S may be etched to remove part of the stacked structure S to form a trench 901. The trench 901 extends downward along the first direction D1 and passes through one or more conductive layers 102 (for example, 3- 7 conductive layers 102) and then stop in the insulating layer 101; the trench 901 exposes part of the sidewalls of the stacked structure S (also serving as the sidewalls of the trench 901), and the insulating layer 101 (also serving as the bottom of the trench 901) ) is exposed; then, the upper isolation structure 104 is formed in the trench 901 through a deposition process. Upper isolation structure 104 may include oxide, or other suitable dielectric material.

Please refer to Figure 10. At least one first upper conductive structure 107 and at least one second upper conductive structure 108 are formed on the stacked structure S. The first upper conductive structure 107 and the second upper conductive structure 108 may extend along the third direction D3 and be staggered on the stacked structure S. The first upper conductive structure 107 and the second upper conductive structure 108 may include conductive materials such as metal.

In one embodiment, the manufacturing method may further include forming a plurality of tubular elements 109 . The formation of the tubular element 109 is illustrated below (not shown). More pillar elements 103 are formed in the step shown in Figure 6, some of which may be processed to form tubular elements 109 in the step shown in Figure 9. The post element 103 used to form the tubular element 109 may be formed where the upper isolation structure 104 is intended to be formed. In the step shown in FIG. 9 , the formation of the upper isolation structure 104 may include etching the pillar element 103 used to form the tubular element 109 to remove the upper part of the pillar element 103 to form the tubular element 109 ; and then by The deposition process forms upper isolation structure 104 on tubular element 109 . The memory layer 151 of the tubular element 109 may comprise similar materials as the memory layer 121 of the pillar element 103 . The dummy channel layer 152 of the tubular element 109 may comprise similar materials as the channel layer 122 of the column element 103 . The insulating posts 153 of the tubular element 109 may comprise similar materials as the insulating posts 123 of the post element 103 .

In one embodiment, the memory device 10 as shown in FIGS. 1A-1C can be obtained by performing the method illustrated in FIGS. 3-10.

Figures 11-18 illustrate a method for manufacturing a memory device according to another embodiment of the present invention.

Please refer to Figure 11. A substrate 100 is provided. Layer stack S6 is formed on substrate 100 . The layer stack S6 may include a plurality of insulating layers 101 and a conductive layer 202 between the plurality of insulating layers 101 . For example, the layer stack S6 can be formed by sequentially depositing the insulating layer 101 and the conductive layer 202 on the substrate 100 . Conductive layer 202 may include conductive material, such as metal or polysilicon.

Please refer to Figure 12. A plurality of lower isolation structures 205 are formed in layer stack S6. The plurality of lower isolation structures 205 may extend downwardly toward the substrate 100 . The plurality of lower isolation structures 205 may extend along the first direction D1 and the second direction D2, and separate the conductive layer 202 and the at least one insulating layer 101 into multiple parts isolated from each other. The lower isolation structure 205 can separate the conductive layer 202 into conductive strips 231, 232, 233, 234 that are electrically isolated from each other. For example, the layer stack S6 can be etched to remove a portion of the insulating layer 101 and a portion of the conductive layer 202 to form a trench 1201. The trench 1201 extends downward along the first direction D1 and stops on the substrate 100. On the surface 100u or stopping in the insulating layer 101 between the substrate 100 and the conductive layer 202. Next, the lower isolation structure 205 is formed in the trench 1201 through a deposition process. Lower isolation structure 205 may include a dielectric material, such as an oxide.

Please refer to Figure 13. An insulating stack structure S7 is formed on the layer stack S6. The insulation stack structure S7 may cover the upper surface 205u of the lower isolation structure 205 and the upper surface 1301u of the layer stack S6. The lower isolation structure 205 and the layer stack S6 may be located below the insulation stack structure S7. The insulation stack structure S7 may include a plurality of insulation layers 101 and a plurality of dielectric layers 302 staggeredly stacked along the first direction D1. For example, the insulating stack structure S7 can be formed by sequentially depositing the insulating layer 101 and the dielectric layer 302 .

Please refer to Figure 14. A plurality of pillar elements 103 are formed. The plurality of pillar elements 103 may be dispersedly configured in the insulation stack structure S7 and the layer stack S6. The pillar element 103 may extend along the first direction D1 through the insulation stack structure S7 and the layer stack S6. In one embodiment, forming the pillar element 103 may include the following steps. The insulating stack structure S7 and the layer stack S6 are patterned to form a plurality of holes 1401 that are isolated from each other. For example, the insulating stack structure S7 and the layer stack S6 can be patterned through a photolithography process. The hole 1401 extends downward along the first direction D1 and stops at the substrate 100; the hole 1401 exposes the sidewalls of the insulation stack structure S7 and the layer stack S6 (also serves as the sidewall of the hole 1401), and exposes the substrate 100 (also serves as the sidewall of the hole 1401). The bottom of hole 1401) is exposed. Then, the memory layer 121 can be lined in the hole 1401 through a deposition process, and the bottom of the memory layer 121 can be removed through an etching process. The channel layer 122 may be deposited on the sidewalls of the memory layer 121 and contact the substrate 100 through the exposed bottom of the memory layer 121 . The insulating pillars 123 fill the remaining space in the holes 1401 through the deposition process. Then, part of the channel layer 122 and part of the insulating pillar 123 may be removed through an etch back process and/or a chemical mechanical planarization process, and part of the sidewalls of the memory layer 121 may be exposed. Next, the contact pads 124 can be formed on the channel layer 122 and the insulating pillars 123 through a deposition process to form the pillar element 103 .

Please refer to Figure 15. A plurality of slits 1501 are formed in the insulation stack structure S7 and the layer stack S6. For example, the insulating stack structure S7 and the layer stack S6 may be etched to remove part of the insulating stack structure S7 and part of the layer stack S6 to form a slit 1501 extending along the first direction D1; when the etching process is The etching is stopped when it proceeds slightly beyond the lower surface 1502b of the layer stack S6; the slit 1501 exposes the sidewalls of the insulating stack structure S7 and the layer stack S6 (also serving as the sidewalls of the slit 1501), and exposes the substrate 100 (also serves as the slit). The bottom of seam 1501) is exposed.

Please refer to Figure 16. The plurality of dielectric layers 302 of the insulating stack structure S7 are replaced with conductive layers 102, and the isolation element 106 is formed in the slit 1501. For example, an etching process may be performed through the slits 1501 to remove the plurality of dielectric layers 302 in the insulation stack structure S7, thereby forming spaces between the plurality of insulation layers 101. Then, the spaces between the plurality of insulating layers 101 are filled with conductive material to form the conductive layer 102 between the plurality of insulating layers 101 . The etching process used to remove dielectric layer 302 does not remove conductive layer 202 and lower isolation structure 205 . In one embodiment, at least part of the conductive layer 102 may serve as a gate. The above steps included in Figure 16 can be understood as a gate replacement process. After the conductive layer 102 is formed, a stack structure S2 including a plurality of insulating layers 101 , a plurality of conductive layers 102 and a conductive layer 202 is formed.

After the conductive layer 102 is formed, the isolation film 141 is formed on the sidewall of the slit 1501 , and the remaining space in the slit 1501 is filled with the conductive film 142 . The isolation film 141 and the conductive film 142 may be formed by, for example, a deposition process.

Please refer to Figure 17. A plurality of upper isolation structures 104 are formed in the stacked structure S2. The upper isolation structure 104 may be formed on the upper part of the stacked structure S2 and pass through one or more insulating layers 101 and/or one or more conductive layers 102 in the stacked structure S2 along the first direction D1. For example, the stacked structure S2 may be etched to remove part of the stacked structure S2 to form a trench 1701. The trench 1701 extends downward along the first direction D1 and passes through one or more conductive layers 102 (for example, 3- 7 conductive layers 102) and then stop in the insulating layer 101; the trench 1701 exposes part of the sidewalls of the stacked structure S2 (also serving as the sidewalls of the trench 1701), and the insulating layer 101 (also serving as the bottom of the trench 901) ) is exposed; then, the upper isolation structure 104 is formed in the trench 1701 through a deposition process.

Please refer to Figure 18. At least one first upper conductive structure 107 and at least one second upper conductive structure 108 are formed on the stacked structure S2. The first upper conductive structure 107 and the second upper conductive structure 108 may extend along the third direction D3 and be staggered on the stacked structure S2.

In one embodiment, the manufacturing method may further include forming a plurality of tubular elements 109 . The formation of the tubular element 109 is illustrated below (not shown). More pillar elements 103 are formed in the step shown in Figure 14, some of which may be processed to form tubular elements 109 in the step shown in Figure 17. The post element 103 used to form the tubular element 109 may be formed where the upper isolation structure 104 is intended to be formed. In the steps shown in FIG. 17 , the formation of the upper isolation structure 104 may include etching the pillar element 103 used to form the tubular element 109 to remove the upper part of the pillar element 103 to form the tubular element 109 ; and then by The deposition process forms upper isolation structure 104 on tubular element 109 . The memory layer 151 of the tubular element 109 may comprise similar materials as the memory layer 121 of the pillar element 103 . The dummy channel layer 152 of the tubular element 109 may comprise similar materials as the channel layer 122 of the column element 103 . The insulating posts 153 of the tubular element 109 may comprise similar materials as the insulating posts 123 of the post element 103 .

In one embodiment, the memory device 20 as shown in FIGS. 2A-2B can be obtained by performing the methods illustrated in FIGS. 11-18. In the method of Figures 11-18, the conductive strips 231, 232, 233, and 234 are formed earlier than the conductive layer 102. The method of this embodiment can be applied to a memory device including multiple lower isolation structures.

As shown in Figures 1A, 1B, 2A and 2B, the memory device 10 includes three upper isolation structures 104 and one lower isolation structure 105 between two isolation elements 106. The memory device 20 includes There are three upper isolation structures 104 and three lower isolation structures 205 between the two isolation elements 106, but the present invention is not limited thereto. The technical solution provided by the present invention can be applied to devices including more or less upper isolation structures. The isolation structure and/or the memory device of the lower isolation structure and/or the column element. The following will be illustrated in Figures 19-20:

Please refer to Figure 19. Figure 19 is a schematic top view of a memory device 40 according to an embodiment of the present invention.

The memory device 40 may include a substrate (not shown), a stacked structure S8 disposed on the substrate, a plurality of pillar elements 103 extending through the stacked structure S8 along the first direction D1, and at least one of the upper portions of the stacked structure S8. The isolation structure 104, at least a lower isolation structure 1905 disposed at the lower part of the stacked structure S8, the tubular element 109 disposed below the upper isolation structure 104, a plurality of isolation elements 106, and a plurality of upper conductive structures (not shown). The stacked structure S8 may be similar to the stacked structure S of FIG. 1B, or may be similar to the stacked structure S2 of FIG. 2B. The lower isolation structure 1905 may be similar to the lower isolation structure 105 of Figure 1B, or may be similar to the lower isolation structure 205 of Figure 2B. On the plane including the second direction D2 and the third direction D3, the position of the isolation structure 1905 under the memory device 40 can be generally aligned with the upper isolation structure 104 (for example, the dotted line in FIG. 19 indicates that the position is generally aligned with the upper isolation structure 104 The lower isolation structure 1905). In this embodiment, the lower isolation structure 1905 separates at least one conductive layer in the stacked structure S8 into two conductive strips. The two conductive strips are electrically isolated from each other through the lower isolation structure 1905 and can serve as grounding respectively. Select the line.

In the memory device 40, the number of pillar elements 103 arranged between the two isolation elements 106 is less than the number of the pillar elements 103 between the two isolation elements 106 in the memory device 10 shown in FIG. 1A. In the memory device 40, the number of the upper isolation structures 104 disposed between the two isolation elements 106 is less than the number of the upper isolation structures 104 between the two isolation elements 106 in the memory device 10 shown in FIG. 1A. The manufacturing method and specific structure of the memory device 40 can be derived by analogy based on the foregoing description.

Please refer to Figure 20. Figure 20 is a schematic top view of a memory device 50 according to an embodiment of the present invention.

The memory device 50 may include a substrate (not shown), a stacked structure S9 disposed on the substrate, a plurality of pillar elements 103 extending through the stacked structure S9 along the first direction D1, and a plurality of upper columns disposed on the upper part of the stacked structure S9. The isolation structure 104, a plurality of lower isolation structures 2005 arranged at the lower part of the stacked structure S9, a tubular element 109 arranged below the upper isolation structure 104, a plurality of isolation elements 106, and a plurality of upper conductive structures (not shown). The stacked structure S9 may be similar to the stacked structure S2 of FIG. 2B. Lower isolation structure 2005 may be similar to lower isolation structure 205 of Figure 2B. On a plane including the second direction D2 and the third direction D3, the position of the lower isolation structure 2005 of the memory device 50 can be substantially aligned with the upper isolation structure 104 (for example, the dotted lines in Figure 20 and the upper isolation structure 104 are approximately aligned respectively. Aligned lower isolation structure 2005). In this embodiment, the plurality of lower isolation structures 2005 separates at least one conductive layer in the stacked structure S9 into five conductive strips. The five conductive strips are electrically isolated from each other through the lower isolation structures 2005 and can serve as grounding respectively. Select the line.

In the memory device 50, the number of pillar elements 103 arranged between the two isolation elements 106 is greater than the number of the pillar elements 103 between the two isolation elements 106 in the memory device 20 shown in FIG. 2A. In the memory device 50, the number of the upper isolation structures 104 disposed between the two isolation elements 106 is greater than the number of the upper isolation structures 104 between the two isolation elements 106 in the memory device 20 shown in FIG. 2A. The manufacturing method and specific structure of the memory device 50 can be derived by analogy based on the foregoing description.

The present invention provides a memory device including a lower isolation structure and a manufacturing method thereof. The lower isolation structure separates part of the conductive layer in the memory device into a plurality of conductive strips that are electrically isolated from each other. Through such a configuration, the number of memory cell strings controlled by a single conductive strip, such as a ground selection line, can be reduced. Specifically, the isolation structure provided by the present invention can be applied to a block of a memory device, so that the memory cell series in this block is controlled by a plurality of ground selection lines; during operation of the memory device, a voltage is applied to Electrically connected to one of the ground selection lines (hereinafter represented by the selected ground selection line) of the memory cell string containing the selected memory cell to turn on one or more ground selection transistors electrically connected to the selected ground selection line, this One or more ground selection transistors in the time block that are electrically connected to other ground selection lines (hereinafter represented by unselected ground selection lines) can remain turned off and are electrically connected to one or more memory cells with unselected ground selection lines. The series is not affected by voltages applied to selected ground select lines, and one or more channel layers electrically connected to unselected ground select lines do not develop capacitance. That is to say, in the memory device of the present invention, the number of memory cell strings affected by the operating voltage is reduced, which can effectively reduce the word line load and reduce the read disturb problem. In addition, in the manufacturing method provided by the present invention, the conductive layer separated by the lower isolation structure can be formed before the lower isolation structure, which helps to increase the number of lower isolation structures in the memory device and reduces the single grounding option in the block. Line-controlled memory cell string number to reduce word line load and read interference problems. The memory device of the present invention may further include tubular components, and configuring the tubular components can increase the process window.

In summary, although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the appended patent application scope.

10,20,40,50: memory device 100:Substrate 100u, 105u, 205u, 501u: upper surface 101:Insulation layer 102,202:Conductive layer 103: Column element 104: Upper isolation structure 105,205,1905,2005: Lower isolation structure 106:Isolation components 107: First upper conductive structure 108: Second upper conductive structure 109: Tubular components 121,151:Memory layer 122: Channel layer 123,153: Insulation column 124:pad 131,132,133,134,135,136,231,232,233,234: conductive strips 141:Isolation film 142:Conductive film 152: Dummy channel layer 161,162,163,164: Series selection transistor 165,166,167,168,265,266,267,268: Ground selection transistor 302: Dielectric layer 401,901,1201,1701:Trench 601,1401:hole 701,1501: slit 702b,1502b: Lower surface BL: bit line D1: first direction D2: second direction D3: Third direction GSL1, GSL2, GSL3, GSL4: Ground selection line M1, M2, M3, M4: memory cell series P1, P1-1, P2: Section line S, S2, S8, S9: stacked structure S3, S6: layer stacking S4, S7: Insulation stack structure SL: source line SSL1, SSL2, SSL3, SSL4: serial selection line T1, T2: thickness WL: word line

Figure 1A is a schematic top view of a memory device according to an embodiment of the present invention; Figure 1B is a schematic cross-sectional view of the memory device along the section line P1 in Figure 1A; Figure 1C is a schematic cross-sectional view of the memory device along the section line P1-1 in Figure 1A; Figure 1D is an equivalent circuit diagram of a memory device according to an embodiment of the present invention; Figure 2A is a schematic top view of a memory device according to another embodiment of the present invention; Figure 2B is a schematic cross-sectional view of the memory device along the section line P2 in Figure 2A; Figure 2C is an equivalent circuit diagram of a memory device according to another embodiment of the present invention; Figures 3-10 illustrate a method for manufacturing a memory device according to an embodiment of the present invention; Figures 11-18 illustrate a method for manufacturing a memory device according to another embodiment of the present invention; Figure 19 is a schematic top view of a memory device according to another embodiment of the present invention; and Figure 20 is a schematic top view of a memory device according to another embodiment of the present invention.

10:Memory device

103: Column element

104: Upper isolation structure

105:Lower isolation structure

106:Isolation components

107: First upper conductive structure

108: Second upper conductive structure

109: Tubular components

D1: first direction

D2: second direction

D3: Third direction

M1, M2, M3, M4: memory cell series

P1, P1-1: Section line

Claims (10)

A memory device containing: A stacked structure including multiple conductive layers; A lower isolation structure is arranged in the stacked structure and has an upper surface located at the lower part of the stacked structure. The lower isolation structure separates at least one of the conductive layers into a first conductive strip and a second A conductive strip, the first conductive strip and the second conductive strip are electrically isolated from each other; and Two memory cells are arranged in series in the stacked structure and are electrically connected to the first conductive strip and the second conductive strip respectively. The memory device according to claim 1, further comprising a first channel layer and a second channel layer, the first channel layer and the second channel layer being tubular and passing through the stacked structure, the first channel layer and The second channel layer is disposed on opposite sides of the lower isolation structure, and one of the memory cell series of the first conductive strip is electrically connected to the first channel layer, and is electrically connected to Another one of the memory cell series of the second conductive strip is electrically connected to the second channel layer. The memory device of claim 1, further comprising an upper isolation structure disposed in the stacked structure, wherein the upper isolation structure extends along a first direction and makes at least one conductive layer disposed on the upper part of the stacked structure Separately, the upper isolation structure and the lower isolation structure at least partially overlap in the first direction. The memory device of claim 1, further comprising at least one upper isolation structure disposed in the stack structure, wherein each of the at least one upper isolation structure extends along a first direction and is disposed in the stack At least one conductive layer on the upper portion of the structure is separated, and one of the at least one upper isolation structure and the lower isolation structure at least partially overlap in the first direction. The memory device of claim 3, further comprising more than one upper isolation structure disposed on the upper part of the stack structure, and more than one lower isolation structure disposed on the lower part of the stack structure, wherein the Each of the upper isolation structures and each of the lower isolation structures at least partially overlap in the first direction. The memory device of claim 1, wherein the lower isolation structure separates at least three of the conductive layers. The memory device of claim 1, wherein at least one conductive layer near a bottom of the stacked structure contains a different material from other conductive layers of the conductive layers. The memory device of claim 7, wherein the at least one conductive layer near the bottom of the stacked structure includes polysilicon. The memory device of claim 7, wherein a conductive layer among the conductive layers that is not separated by the lower isolation structure has a first thickness, and the at least one conductive layer close to the bottom of the stacked structure has a second thickness. Thickness, the second thickness is greater than the first thickness. The memory device of claim 9, wherein the ratio of the second thickness to the first thickness is between 4 and 7.

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