TW202339430A - Low propagation delay level shifter - Google Patents

Abstract

A level shifter includes a low-level adjustment circuit, a comparator circuit, and a high-level adjustment circuit. The low-level adjustment circuit pulls down a level of one of a first input node and a second input node to a first low supply voltage. The comparator outputs a one having higher level in the level of the first input level and a second low supply voltage to a first output node, in which the second low supply voltage is higher than the first low supply voltage. The high-level adjustment circuit selectively adjusts the level of the first output node according to the level of the first input node and the level of the second input node to generate the output signal.

Description

Level converter with low propagation delay

This case is about level converters, especially level converters that can quickly switch signal levels.

Electronic devices often contain several different circuit systems. In some applications, the circuit systems may operate at different voltage levels. In order to enable these circuit systems to transmit data or signals to each other, a level shifter can be provided between these circuit systems to ensure that the signal level matches the voltage level of the corresponding circuit system. In some related technologies, a level converter uses a plurality of cross-coupled inverters to perform level conversion. However, due to the influence of other clamping circuits and the operation delays of these inverters, a large transmission delay will occur during the signal level switching process. In this way, the switching process of the signal will be delayed, resulting in higher uncertainty at the transition edge of the signal.

In some implementations, one of the objectives of the present invention is to provide a level converter with low transmission delay to improve the shortcomings of the prior art.

In some implementations, the level converter includes a low level adjustment circuit, a first comparison circuit, and a high level adjustment circuit. The low level adjustment circuit selectively pulls down the level of one of a first input node and a second input node to a first low power supply voltage according to an input signal. The first comparison circuit outputs the higher one of the level of the first input node and a second low power supply voltage to a first output node, wherein the second low power supply voltage is higher than the first low power supply voltage. voltage. The high level adjustment circuit selectively adjusts the level of the first output node according to the level of the first input node and the level of the second input node to generate an output signal.

In some implementations, the level converter can provide an additional path to quickly adjust the level of the output node, thereby reducing the delay generated during the signal level switching process. In this way, the output signal generated by the level converter can have a fast switching transition edge, thereby reducing the uncertainty of the transition edge of the output signal.

Regarding the characteristics, implementation and functions of this case, the preferred embodiments are described in detail below with reference to the drawings.

All words used in this article have their ordinary meanings. The definitions of the above words in commonly used dictionaries, and the use examples of any of the words discussed here in the content of this case are only examples and should not limit the scope and meaning of this case. Likewise, this case is not limited to the various embodiments shown in this specification.

As used in this article, "coupling" or "connection" can refer to two or more components that are in direct physical or electrical contact with each other, or that are in indirect physical or electrical contact with each other. It can also refer to two or more components. Components interact or act with each other. As used herein, the term "circuit" may refer to a device consisting of at least one transistor and/or at least one active and passive component connected in a certain manner to process signals.

FIG. 1 is a schematic diagram of a level converter 100 according to some embodiments of the present invention. The level converter 100 can be used to convert the signal level to be suitable for voltage ranges of different power domains. For example, the level converter 100 may receive the input signal SIN from other digital circuits (not shown), where the level of the input signal SIN may range from a low power supply voltage VSSL to a high power supply voltage VDDL. The level converter 100 can generate an output signal VO according to the input signal SIN. The level of the output signal VO ranges from a low power supply voltage VSSH to a high power supply voltage VDDH. The high power supply voltage VDDH is higher than the low power supply voltage VSSH. The low power supply voltage VSSH It can be higher than or the same as the high supply voltage VDDL, and the high supply voltage VDDL is higher than the low supply voltage VSSL.

The level converter 100 includes a low level adjustment circuit 110 , a comparison circuit 120 , a comparison circuit 130 and a high level adjustment circuit 140 . The low level adjustment circuit 110 selectively pulls down the level of one of the input node I1 and the input node I2 to the high power supply voltage VDDL according to the input signal SIN. The comparison circuit 120 outputs the higher one of the level of the input node I1 and the low power supply voltage VSSH to the output node O1. The comparison circuit 130 outputs the higher one of the level of the input node I2 and the low power supply voltage VSSH to the output node O2. The high level adjustment circuit 140 selectively adjusts the level of the output node O1 and the level of the output node O2 according to the level of the input node I1 and the level of the input node I2, and generates the output signal VO according to the level of the output node O2.

In this example, the low level adjustment circuit 110 operates in the first power domain, which is defined by the low supply voltage VSSL and the high supply voltage VDDL. The low level adjustment circuit 110 can pull the amplitude of the input signal SIN up to the high power supply voltage VDDL or down to the low power supply voltage VSSL, and adjust the levels of the input node I1 and the level of the input node I2 accordingly. The high level adjustment circuit 140 operates in the second power domain, which is defined by the low supply voltage VSSH and the high supply voltage VDDH. The high level adjustment circuit 140 can further raise the level of the output node O1 (and the output node O2) to the high power supply voltage VDDH or the low power supply voltage VSSH according to the level of the input node I1 and the level of the input node I2, and generate a signal therefrom. Output signal VO.

As described later, the comparison circuit 120 can assist in accelerating the level of the output node O1 to be pulled down to the low power supply voltage VSSH, and the comparison circuit 130 can assist in accelerating the level of the output node O2 being pulled down to the low power supply voltage VSSH. In this way, the output signal VO can be quickly switched to the level of the low power supply voltage VSSH during the level conversion process, thereby reducing the transient delay and uncertainty of the falling edge of the output signal VO.

FIG. 2 is a schematic circuit diagram of the level converter 100 of FIG. 1 according to some embodiments of the present invention. In this example, the low level adjustment circuit 110 includes an inverter 112, an inverter 114, a transistor N1 and a transistor N2. The inverter 112 generates the signal S1 according to the input signal SIN. The inverter 114 generates the signal S2 based on the signal S1. The first terminal (for example, the drain) of the transistor N1 is coupled to the input node I2, the second terminal (for example, the source) of the transistor N1 receives the signal S1, and the control terminal (for example, the gate) of the transistor N1 Receives the high supply voltage VDDL. The first terminal of the transistor N2 is coupled to the input node I1, the second terminal of the transistor N2 receives the signal S2, and the control terminal of the transistor N2 receives the high power supply voltage VDDL.

Through the above arrangement, the transistor N1 and the transistor N2 can be biased by the high power supply voltage VDDL, the transistor N1 can selectively pull the level of the input node I2 down to the low power supply voltage VSSL according to the signal S1, and the transistor N2 can selectively pull down the level of the input node I1 to the low power supply voltage VSSL according to the signal S2. For example, when the input signal SIN is a logic value 0, the level of the signal S1 is the high power supply voltage VDDL, and the level of the signal S2 is the low power supply voltage VSSL. Under this condition, the transistor N1 is turned off and the transistor N2 is turned on to pull the level of the input node I1 down to the low supply voltage VSSL. Or, when the input signal SIN is a logic value 1, the level of the signal S1 is the low power supply voltage VSSL, and the level of the signal S2 is the high power supply voltage VDDL. Under this condition, transistor N2 is turned off and transistor N1 is turned on to pull the level of input node I2 down to the low supply voltage VSSL.

The high-level adjustment circuit 140 includes a plurality of transistors P1 to P4, a plurality of transistors N3 to N4, and a plurality of inverters 142 and 144. The first terminal of the transistor P1 (for example, the source) receives the high power supply voltage VDDH, the second terminal of the transistor P1 (for example, the drain) is coupled to the control node A, and the control terminal of the transistor P1 (for example, the gate pole) coupled to output node O2. The transistor P1 can selectively raise the level of the control node A to the high power supply voltage VDDH according to the level of the output node O2. The first terminal of the transistor P2 receives the high power supply voltage VDDH, the second terminal of the transistor P1 is coupled to the control node B, and the control terminal of the transistor P2 is coupled to the output node O1. The transistor P2 can selectively raise the level of the control node B to the high power supply voltage VDDH according to the level of the output node O1. The first terminal of the transistor N3 is coupled to the control node A, the second terminal of the transistor N3 receives the low power supply voltage VSSH, and the control terminal of the transistor N3 is coupled to the control node B. The transistor N3 can selectively pull down the level of the control node A to the low power supply voltage VSSH according to the level of the control node B. The first terminal of the transistor N4 is coupled to the control node B, the second terminal of the transistor N4 receives the low power supply voltage VSSH, and the control terminal of the transistor N4 is coupled to the control node A. The transistor N4 can selectively pull down the level of the control node B to the low power supply voltage VSSH according to the level of the control node A. The first terminal of the transistor P3 is coupled to the control node A, the second terminal of the transistor P3 is coupled to the input node I1, and the control terminal of the transistor P3 receives the low power supply voltage VSSH. The transistor P3 can be biased by the low supply voltage VSSH and selectively turned on according to the level of the control node A to adjust the level of the input node I1. The first terminal of the transistor P4 is coupled to the control node B, the second terminal of the transistor P4 is coupled to the input node I2, and the control terminal of the transistor P4 receives the low power supply voltage VSSH. The transistor P4 can be biased by the low supply voltage VSSH and selectively turned on according to the level of the control node B to adjust the level of the input node I2.

The plurality of inverters 142 and 144 are powered by the high power supply voltage VDDH and the low power supply voltage VSSL, and are coupled in series to operate as a buffer, which can generate the output signal VO according to the level of the output node O1.

The comparison circuit 120 includes a plurality of transistors P5 and P6. The first terminal of the transistor P5 is coupled to the output node O1, the second terminal of the transistor P5 receives the low power supply voltage VSSH, and the control terminal of the transistor P5 is coupled to the input node I1. The first terminal of the transistor P6 is coupled to the output node O1, the second terminal of the transistor P6 is coupled to the input node I1, and the control terminal of the transistor P6 receives the low power supply voltage VSSH. With the above arrangement, the transistor P5 can be selectively turned on according to the level of the input node I1 to transmit the low power supply voltage VSSH to the output node O1, and the transistor P6 can be selectively turned on according to the level of the input node I1 to connect. Input node I1 to output node O1. For example, when the low supply voltage VSSH is higher than the level of the input node I1, the transistor P5 is turned on and the transistor P6 is turned off to transmit the low supply voltage VSSH to the output node O1. Alternatively, when the level of the input node I1 is higher than the low power supply voltage VSSH, the transistor P6 is turned on and the transistor P5 is turned off to connect the input node I1 to the output node O1.

The comparison circuit 130 includes a plurality of transistors P7 and P8. The first terminal of the transistor P7 is coupled to the output node O2, the second terminal of the transistor P7 receives the low power supply voltage VSSH, and the control terminal of the transistor P7 is coupled to the input node I2. The first terminal of the transistor P8 is coupled to the output node O2, the second terminal of the transistor P8 is coupled to the input node I2, and the control terminal of the transistor P8 receives the low power supply voltage VSSH. With the above arrangement, the transistor P7 can be selectively turned on according to the level of the input node I2 to transmit the low power supply voltage VSSH to the output node O2, and the transistor P8 can be selectively turned on according to the level of the input node I2 to connect. Input node I2 to output node O2. For example, when the low supply voltage VSSH is higher than the level of the input node I2, the transistor P7 is turned on and the transistor P8 is turned off to transmit the low supply voltage VSSH to the output node O2. Alternatively, when the level of the input node I2 is higher than the low power supply voltage VSSH, the transistor P8 is turned on and the transistor P7 is turned off to connect the input node I2 to the output node O2.

It should be understood that the comparison circuit 120 and the comparison circuit 130 are equivalent to high voltage selection circuits, and this case is not limited to the above arrangement. Various comparison circuits that can output higher voltages are covered by this case.

FIG. 3A is a schematic diagram illustrating the operation of the level converter 100 when the input signal SIN in FIG. 2 has a low logic value according to some embodiments of the present invention. In the example of FIG. 3A , when the input signal SIN switches from a high level to a low level (ie, the input signal SIN has a low logic value), the signal S1 has a high level and the signal S2 has a low level. Under this condition, transistor N1 is turned off and transistor N2 is turned on to pull down the level of input node I1 to the low supply voltage VSSL. Since the low supply voltage VSSH is higher than the level of the input node I1 (equivalent to the low supply voltage VSSL), the transistor P6 is turned off and the transistor P5 is turned on to transmit the low supply voltage VSSH to the output node O1. In this way, the level of the output node O1 can be quickly pulled down to the low power supply voltage VSSH to generate the output signal VO with a corresponding low level.

In addition, since the output node O1 is at a low level, the transistor P2 is turned on to pull the level of the control node B to the high power supply voltage VDDH. Under this condition, transistor N4 is turned off, transistor N3 is turned on to pull down the level of control node A to the low supply voltage VSSH and thereby turns off transistor P3, and transistor P4 is turned on to connect control node B to the input node. I2. In this way, the level of the input node I2 can be pulled up to the high power supply voltage VDDH via the transistor P4 and the transistor P2. Since the level of the input node I2 is higher than the low supply voltage VSSH, the transistor P7 is turned off and the transistor P8 is turned on to connect the input node I2 to the output node O2, thereby turning off the transistor P1.

FIG. 3B is a schematic diagram illustrating the operation of the level converter 100 when the input signal SIN in FIG. 2 has a high logic value according to some embodiments of the present invention. In the example of FIG. 3B , when the input signal SIN switches from a low level to a high level (ie, the input signal SIN has a high logic value), the signal S2 has a high level and the signal S1 has a low level. Under this condition, transistor N2 is turned off and transistor N1 is turned on to pull down the level of input node I2 to the low supply voltage VSSL. Since the low supply voltage VSSH is higher than the level of the input node I2 (equivalent to the low supply voltage VSSL), the transistor P8 is turned off and the transistor P7 is turned on to transmit the low supply voltage VSSH to the output node O2. In this way, the level of the output node O2 can be quickly pulled down to the low power supply voltage VSSH.

In addition, since the output node O2 is at a low level, the transistor P1 is turned on to pull the level of the control node A to the high power supply voltage VDDH. Under this condition, transistor N3 is turned off, transistor N4 is turned on to pull down the level of control node B to the low supply voltage VSSH and thereby turns off transistor P4, and transistor P3 is turned on to connect control node A to the input node. I1. In this way, the level of the input node I1 can be pulled up to the high power supply voltage VDDH via the transistor P3 and the transistor P1. Since the level of the input node I1 is higher than the low supply voltage VSSH, the transistor P5 is turned off and the transistor P6 is turned on to connect the input node I1 to the output node O1, thereby turning off the transistor P2. In this way, the level of the input node I1 can be pulled up to the high power supply voltage VDDH to generate the output signal VO with a corresponding high level.

Based on the description of FIG. 3A and FIG. 3B , it should be understood that when the input signal SIN switches to a low level, the comparison circuit 120 can quickly pull down the level of the output node O1 to the low power supply voltage VSSH. In this way, when the input signal SIN switches from a high level to a low level, the output signal VO can have a low-latency level switching with a fast falling transition edge (i.e., a falling edge). Correspondingly, when the input signal SIN switches to a high level, the level of the input node I1 is raised through the cooperative operation of the comparison circuit 130 and the high level adjustment circuit 140, thereby raising the level of the output signal VO to the high power supply voltage VDDH. In some embodiments, in practical applications, the transient time of the output signal VO switching from a low level to a high level may be longer than the transient time of the output signal VO switching from a high level to a low level.

FIG. 4A is a schematic diagram of a level converter 400 according to some embodiments of the present invention. Compared with FIG. 2 , in this example, the level converter 400 further includes a selection circuit 410 , and the high level adjustment circuit 140 does not include a plurality of inverters 142 and 144 , and generates the output signal VO through the selection circuit 410 . As mentioned above, in the above example, the transient time of the output signal VO switching from the low level to the high level may be longer than the transient time of the output signal VO switching from the high level to the low level. In order to further ensure that the output signal VO can have a fast rising transition edge (ie, a rising edge), the selection circuit 410 can be used to further generate the output signal VO according to the level of the output node O2.

Specifically, the selection circuit 410 selects a corresponding node from the output node O1 and the output node O2 according to the level of the output node O1 and the level of the output node O2, and generates the output signal VO according to the level of the corresponding node. For example, the selection circuit 410 includes an inverter 411, an inverter 412, a logic gate 413, a logic gate 414, and a multiplexer 415. The inverter 411 generates the signal S3 according to the level of the output node O1. The inverter 412 generates the signal S4 according to the level of the output node O2. The logic gate 413 generates the signal S5 according to the signal S3 and the selection signal SEL. The logic gate 414 generates the selection signal SEL according to the signal S4 and the signal S5. In this example, the logic gate 413 and the logic gate 414 may be (but are not limited to) NAND gates and may operate as SR flip-flops. The multiplexer 415 outputs the signal S4 as the output signal VO according to the selection signal SEL, or generates the output signal VO according to the level of the output node O1.

Figure 4B is a waveform diagram of the relevant signals in Figure 4A according to some embodiments of the present case. When the input signal SIN has a high level, the output node O1 has a high level, and the output node O2 has a low level. Under this condition, the selection signal SEL has a low level, so the multiplexer 415 generates the output signal VO according to the level of the output node O1. When the input signal SIN switches from a high level to a low level, the level of the output node O1 is quickly pulled down to the low power supply voltage VSSL through the comparison circuit 120, so the multiplexer 415 can generate the corresponding output signal VO according to the level of the output node O1. . Then, when the level of the output node O2 is raised to the high power supply voltage VDDH (refer to FIG. 3A ) through the cooperative operation of the high level adjustment circuit 140 and the comparison circuit 130 , the selection signal SEL has a high level. Under this condition, the output signal S4 of the multiplexer 415 is the output signal VO. When the input signal SIN switches from a low level to a high level, the level of the output node O2 can be quickly pulled down to the low power supply voltage VSSL through the comparison circuit 130 (refer to FIG. 3B ), so that the signal S4 can have a fast rising transition edge. In this way, the multiplexer 415 can output the signal S4 as the output signal VO.

Equivalently speaking, the selection circuit 410 can select a corresponding node from the output node O1 and the output node O2 according to the level of the output node O1 and the level of the output node O2, wherein when the level of the corresponding node is from a high level (for example, When the high power supply voltage VDDH) switches to a low level (for example, the low power supply voltage VSSL), the selection circuit 410 generates the output signal VO according to the level of the corresponding node. In this way, it can be ensured that the selection circuit 410 generates the output signal VO according to the level with a fast falling level, thereby reducing the delay time of the level switching of the output signal VO.

Generally speaking, the operation speed of a circuit will gradually slow down the longer it is used. Since the selection circuit 410 can choose to generate the output signal VO through the output node O1 of the comparison circuit 120 or through the output node O2 of the comparison circuit 130, and the number of transistors used in the path of pulling down the output node O1 or the output node O2 is not large. , so the impact of usage time is relatively low. In other words, through the selection circuit 410, the durability of the level converter 400 can be further improved.

In the above embodiments, the plurality of transistors N1 to N4 are N-type transistors, and the plurality of transistors P1 to P8 are P-type transistors. Each of the above transistors can be implemented by a metal oxide field effect transistor (MOSFET), but this case is not limited to this. Various types or conductivity types of transistors that can perform similar operations are within the scope of this case.

FIG. 5 is a schematic diagram of an input-output driver 500 according to some embodiments of the present invention. The input-output driver 500 includes a level converter 510 , a delay matching circuit 520 , a non-overlapping circuit 530 and a protection circuit 540 . The level converter 510 may be implemented by the level converter 100 of FIG. 1 or FIG. 2 or the level converter 400 of FIG. 4 . The level converter 510 can generate the output signal VO according to the input signal SIN. The delay matching circuit 520 generates the output signal VO' according to the input signal SIN, wherein the delay time introduced by the delay matching circuit 520 to the input signal SIN is the same as (or close to) the delay time introduced by the level converter 510 to the input signal SIN. In other words, the non-overlapping circuit 530 receives the output signal VO and the output signal VO' at the same (or similar) time. In some embodiments, the delay matching circuit 520 may (but is not limited to) have a circuit structure similar to the level shifter 510 (but operates in a different power domain) to achieve similar delay times. The non-overlapping circuit 530 generates the control signal SC1 according to the output signal VO, and generates the control signal SC2 according to the output signal VO'. The non-overlapping circuit 530 can delay the output signal VO to generate the control signal SC1, and delay the output signal VO' to generate the control signal SC2, wherein there is a non-overlapping period between the control signal SC1 and the control signal SC2 (for example, for the conversion of the control signal SC1 The interval between the state edge and the transition edge of the control signal SC1).

The protection circuit 540 includes a plurality of transistors MP1, MP2, MN1 and a transistor MN2 as well as a plurality of diodes D1 and D2. A plurality of transistors MP1 - MP4 and a plurality of diodes D1 and D2 may operate a voltage protection circuit to provide basic voltage protection to the input and output pad 501 . The transistor MP1 receives the high power supply voltage VDDH and is selectively turned on according to the control signal SC1. Transistor MP2 is controlled by clamp signal VP and coupled to input-output pad 501 . Transistor MN2 is controlled by clamp signal VN and coupled to input-output pad 501 . The transistor MN1 receives the low power supply voltage VSS and is selectively turned on according to the control signal SC2.

By setting the non-overlapping period between the control signal SC1 and the control signal SC2, it can be ensured that the transistor MP1 and the transistor MN1 will not be turned on at the same time, thereby preventing the protection circuit 540 from generating a short-circuit current. As mentioned above, in some related technologies, there is an operation delay in the level converter, which causes higher uncertainty at the transition edge of the signal. If a level converter using these technologies is used to generate the output signal VO, uncertainty will also occur in the transition edge of the control signal SC1 generated by the non-overlapping circuit 530 (that is, the transition time point of the control signal SC1 cannot be accurately controlled. ). As a result, the non-overlapping period between the control signal SC1 and the control signal SC2 may be too long, thereby reducing the performance of the input-output driver 500 . Or, in some extreme cases, the transistor MP1 and the transistor MN1 may be turned on at the same time according to the control signal SC1 and the control signal SC2, thereby erroneously generating a short-circuit current. Compared with the above technology, using the level converter 100 or the level converter 400 provided in some embodiments of the present application, the non-overlapping circuit 530 can accurately control the transition time point of the control signal SC1 to ensure that the control signal SC1 and the control signal SC2 There is a certain non-overlapping period between them, and the non-overlapping period can be accurately controlled to have a short length to improve the performance of the input and output driver 500 .

In summary, the level converter in some embodiments of the present invention can provide an additional path to quickly adjust the level of the output node, thereby reducing the delay generated during the level switching process of the signal. In this way, the output signal generated by the level converter can have a fast switching transition edge, thereby reducing the uncertainty of the transition edge of the output signal.

Although the embodiments of this case are as described above, these embodiments are not intended to limit this case. Those with ordinary knowledge in the technical field can make changes to the technical features of this case based on the explicit or implicit contents of this case. All these changes All may fall within the scope of patent protection sought in this case. In other words, the scope of patent protection in this case must be determined by the scope of the patent application in this specification.

100:Level converter 110: Low level adjustment circuit 112, 114:Inverter 120, 130: Comparison circuit 140: High level adjustment circuit 142, 144:Inverter 400:Level converter 410: Select circuit 411, 412:Inverter 413, 414: Logic gate 415:Multiplexer 500: Input and output driver 501: Input and output pad 510:Level converter 520: Delay matching circuit 530: Non-overlapping circuit 540: Protection circuit A, B: control node D1, D2: Diode I1, I2: input nodes MN1, MN2, MP1, MP2, N1~N4, P1~P8: transistor O1, O2: output nodes S1~S5: signal SC1, SC2: control signal SEL: select signal SIN: input signal VDDH, VDDL: high supply voltage VN, VP: clamp signal VO, VO’: output signal VSS, VSSH, VSSL: low supply voltage

[Figure 1] is a schematic diagram of a level converter according to some embodiments of this case; [Figure 2] is a schematic circuit diagram of the level converter in Figure 1 according to some embodiments of this case; [Figure 3A] is a schematic diagram of the operation of the level converter when the input signal in Figure 2 has a low logic value according to some embodiments of this case; [Figure 3B] is a schematic diagram of the operation of the level converter when the input signal in Figure 2 has a high logic value according to some embodiments of this case; [Figure 4A] is a schematic diagram of a level converter according to some embodiments of this case; [Figure 4B] is a waveform diagram of the relevant signals in Figure 4A according to some embodiments of this case; and [Figure 5] is a schematic diagram of an input and output driver drawn according to some embodiments of this case.

100:Level converter

110: Low level adjustment circuit

120,130: Comparison circuit

140: High level adjustment circuit

I1,I2: input nodes

O1,O2: output nodes

SIN: input signal

VDDH, VDDL: high power supply voltage

VO: output signal

VSSH, VSSL: low supply voltage

Claims (10)

A level converter containing: a low level adjustment circuit that selectively pulls down the level of one of a first input node and a second input node to a first low power supply voltage according to an input signal; A first comparison circuit outputs a higher level of the first input node level and a second low power supply voltage to a first output node, wherein the second low power supply voltage is higher than the first Low supply voltage; and A high level adjustment circuit selectively adjusts the level of the first output node according to the level of the first input node and the level of the second input node to generate an output signal. The level converter of claim 1, wherein the low level adjustment circuit operates in a first power domain, the high level adjustment circuit operates in a second power domain, and the first power domain is composed of the first low power supply voltage and A first high power supply voltage is defined, the second power domain is defined by the second low power supply voltage and a second high power supply voltage, and the second high power supply voltage is higher than the first high power supply voltage. For example, the level converter of claim 1, wherein the low level adjustment circuit includes: a first inverter that generates a first signal based on the input signal; a second inverter that generates a second signal based on the first signal; A first transistor is biased by a high supply voltage and selectively pulls the level of the second input node down to the first low supply voltage according to the first signal; and A second transistor is biased by the high supply voltage and selectively pulls the level of the first input node down to the first low supply voltage according to the second signal. For example, the level converter of claim 1, wherein the high level adjustment circuit includes: a first transistor that selectively pulls up the level of a first control node to a high power supply voltage based on the level of a second output node; a second transistor that selectively pulls up the level of a second control node to the high power supply voltage based on the level of the first output node; a third transistor that selectively pulls down the level of the first control node to the second low supply voltage according to the level of the second control node; a fourth transistor that selectively pulls down the level of the second control node to the second low power supply voltage according to the level of the first control node; a fifth transistor biased by the second low supply voltage and selectively turned on according to the level of the first control node to adjust the level of the first input node; and A sixth transistor is biased by the second low power supply voltage and is selectively turned on according to the level of the second control node to adjust the level of the second input node. The level converter of claim 1, wherein the first comparison circuit includes: a first transistor selectively turned on according to the level of the first input node to transmit the second low supply voltage to the first output node; and A second transistor is selectively turned on according to the level of the first input node to connect the first input node to the first output node. For example, the level converter of claim 1 further includes: a second comparison circuit that outputs the higher level of the level of the second input node and the second low power supply voltage to a second output node, The high level adjustment circuit further selectively adjusts the level of the second output node according to the level of the first input node and the level of the second input node. For example, the level converter of claim 6 further includes: A selection circuit selects a corresponding node from the first output node and the second output node according to the level of the first output node and the level of the second output node, and generates the corresponding node according to the level of the corresponding node. output signal. The level converter of claim 7, wherein when the level of the corresponding node switches from a first level to a second level, the selection circuit generates the output signal according to the level of the corresponding node, and the third One level is higher than the second level. For example, the level converter of claim 7, wherein the selection circuit includes: a first inverter that generates a first signal according to the level of the first output node; a second inverter that generates a second signal according to the level of the second output node; a first logic gate that generates a third signal based on the first signal and a selection signal; a second logic gate that generates the selection signal based on the second signal and the third signal; and A multiplexer outputs a second signal as the output signal according to the selection signal or generates the output signal according to the level of the first output node. The level converter of claim 1, wherein when the input signal switches from a first level to a second level, the first comparison circuit is used to assist in accelerating the level of the first output node to be pulled down to The second low power supply voltage, and the first level is higher than the second level.

Images