TW202339404A - Power supply device with high output stability - Google Patents

Abstract

A power supply device with high output stability includes an input switch circuit, a transformer, a first capacitor, an output stage circuit, a PWM (Pulse Width Modulation) IC (Integrated Circuit), and a delay control circuit. The transformer includes a main coil, a first secondary coil, and a second secondary coil. A leakage inductor and a magnetizing inductor are built in the transformer. The first capacitor is coupled to the main coil. The delay control circuit includes a first resistor coupled to the output stage circuit. If it is detected that no current flows through the first resistor, the delay control circuit will temporarily disable the magnetizing inductor within a delay time period.

Description

High output stability power supply

The present invention relates to a power supply, and in particular to a power supply with high output stability.

In a traditional power supply, to increase its voltage gain, its switching frequency must be reduced. However, if the timing of adjusting the switching frequency is inappropriate, it may cause serious oscillations in the corresponding capacitor potential of the power supply, resulting in interruption of the energy supply of the power supply. In view of this, it is necessary to propose a new solution to overcome the difficulties faced by previous technologies.

In a preferred embodiment, the present invention proposes a power supply with high output stability, including: an input switching circuit that modulates the potential according to an input potential, a first pulse width, and a second pulse width. Modulating the potential to generate a switching potential; a transformer including a main coil, a first auxiliary coil, and a second auxiliary coil, wherein the transformer has a built-in leakage inductor and a magnetizing inductor, and the main coil The switching potential is received through the leakage inductor; a first capacitor is coupled to the main coil; an output stage circuit is coupled to the first secondary coil and the second secondary coil and is used to generate an output potential; a pulse width modulation integrated circuit that generates the first pulse width modulation potential and the second pulse width modulation potential; and a delay control circuit including a first pulse width modulation circuit coupled to the output stage circuit A resistor, if it is detected that no current flows through the first resistor, the delay control circuit will temporarily disable the exciting inductor within a delay time.

In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are listed below and described in detail with reference to the accompanying drawings.

Certain words are used in the specification and patent claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This specification and the patent application do not use differences in names as a way to distinguish components, but differences in functions of components as a criterion for distinction. The words "include" and "include" mentioned throughout the specification and the scope of the patent application are open-ended terms, and therefore should be interpreted as "include but not limited to." The term "approximately" means that within an acceptable error range, those skilled in the art can solve the technical problem and achieve the basic technical effect within a certain error range. In addition, the word "coupling" in this specification includes any direct and indirect electrical connection means. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device via other devices or connections. Two devices.

Figure 1 is a schematic diagram of a power supply 100 according to an embodiment of the present invention. For example, the power supply 100 can be applied to a desktop computer, a notebook computer, or an all-in-one computer. As shown in Figure 1, the power supply 100 includes: an input switching circuit 110, a transformer 120, a first capacitor C1, an output stage circuit 130, and a Pulse Width Modulation Integrated Circuit. , PWM IC) 140, and a delay control circuit 150. It should be noted that, although not shown in FIG. 1 , the power supply 100 may further include other components, such as a voltage regulator or/and a negative feedback circuit.

The input switching circuit 110 can generate a switching potential VW according to an input potential VIN, a first pulse width modulation potential VM1, and a second pulse width modulation potential VM2. The input potential VIN can come from an external input power supply, where the input potential VIN can be a DC potential with any level. For example, the potential level of the DC potential can be between 380V and 420V, but is not limited thereto. The transformer 120 includes a main coil 121, a first auxiliary coil 122, and a second auxiliary coil 123. The transformer 120 may further include a leakage inductor LR and a magnetizing inductor LM. The main coil 121 , the leakage inductor LR, and the exciting inductor LM may be located on the same side of the transformer 120 , while the first auxiliary coil 122 and the second auxiliary coil 123 may be located on opposite sides of the transformer 120 . The main coil 121 can receive the switching potential VW via the leakage inductor LR, and both the first auxiliary coil 122 and the second auxiliary coil 123 can operate in response to the switching potential VW. The first capacitor C1 is coupled to the main coil 121 . For example, the leakage inductor LR, the magnetizing inductor LM, and the first capacitor C1 may together form a resonant tank (Resonant Tank). The output stage circuit 130 is coupled to the first secondary coil 122 and the second secondary coil 123, and can be used to generate an output potential VOUT. For example, the output potential VOUT can be another DC potential, and its potential level can range from 18V to Between 20V, but not limited to this. The pulse width modulation integrated circuit 140 can be used to generate the first pulse width modulation potential VM1 and the second pulse width modulation potential VM2. The delay control circuit 150 includes a first resistor R1 coupled to the output stage circuit 130 . The delay control circuit 150 continuously monitors the operating status of its first resistor R1. If it is detected that no current flows through the first resistor R1, the delay control circuit 150 will temporarily disable the magnetizing inductor LM within a delay time TD. Under this design, the delay control circuit 150 can effectively prevent the capacitance potential VR of the first capacitor C1 from non-ideal oscillation by delaying the exciting inductor LM to participate in the resonance operation of the aforementioned resonance tank. According to actual measurement results, the design of the present invention can significantly improve the output stability of the power supply 100.

The following embodiments will introduce the detailed structure and operation of the power supply 100 . It must be understood that these drawings and descriptions are only examples and are not intended to limit the scope of the invention.

Figure 2 is a circuit diagram of a power supply 200 according to an embodiment of the present invention. In the embodiment of FIG. 2, the power supply 200 has an input node NIN and an output node NOUT, and includes: an input switching circuit 210, a transformer 220, a first capacitor C1, an output stage circuit 230, an Pulse width modulation integrated circuit 240, and a delay control circuit 250. The input node NIN of the power supply 200 can receive an input potential VIN from an external input power source, and the output node NOUT of the power supply 200 can be used to output an output potential VOUT to an electronic device (not shown).

The input switching circuit 210 includes a first transistor M1 and a second transistor M2. For example, the first transistor M1 and the second transistor M2 may each be an N-type Metal-Oxide-Semiconductor Field-Effect Transistor (NMOSFET). The first transistor M1 has a control terminal (for example: a gate), a first terminal (for example: a source), and a second terminal (for example: a drain), wherein the control terminal of the first transistor M1 The terminal is used to receive a first pulse width modulation potential VM1, the first terminal of the first transistor M1 is coupled to a first node N1 to output a switching potential VW, and the first terminal of the first transistor M1 The two terminals are coupled to the input node NIN. The second transistor M2 has a control terminal (for example, a gate), a first terminal (for example, a source), and a second terminal (for example, a drain), wherein the control terminal of the second transistor M2 The terminal is used to receive a second pulse width modulation potential VM2, the first terminal of the second transistor M2 is coupled to a ground potential VSS (for example: 0V), and the second terminal of the second transistor M2 is coupled to the first node N1.

The transformer 220 includes a main coil 221, a first auxiliary coil 222, and a second auxiliary coil 223. The transformer 220 further has a built-in leakage inductor LR and a magnetizing inductor LM. Both the leakage inductor LR and the magnetizing inductor LM may be inherent components produced when the transformer 220 is manufactured, and are not external independent components. The leakage inductor LR, the main coil 221, and the exciting inductor LM can all be located on the same side of the transformer 220 (for example, the primary side), while the first auxiliary coil 222 and the second auxiliary coil 223 can be located on opposite sides of the transformer 220. One side (for example: the secondary side, which can be isolated from the primary side). The leakage inductor LR has a first end and a second end, wherein the first end of the leakage inductor LR is coupled to the first node N1 to receive the switching potential VW, and the second end of the leakage inductor LR is coupled to to a second node N2. The main coil 221 has a first end and a second end, wherein the first end of the main coil 221 is coupled to the second node N2, and the second end of the main coil 221 is coupled to a third node N3. The exciting inductor LM has a first end and a second end, wherein the first end of the exciting inductor LM is coupled to the second node N2, and the second end of the exciting inductor LM is coupled to a fourth node. N4. The first capacitor C1 has a first terminal and a second terminal, wherein the first terminal of the first capacitor C1 is coupled to the third node N3, and the second terminal of the first capacitor C1 is coupled to the ground potential VSS. In some embodiments, the leakage inductor LR, the magnetizing inductor LM, and the first capacitor C1 can jointly form a resonant tank, which can be used to determine the resonant frequency and the corresponding gain value of the power supply 200 . In addition, a resonant current IR may flow through the leakage inductor LR, and a capacitive potential VR may be formed at the third node N3. The first secondary coil 222 has a first end and a second end, wherein the first end of the first secondary coil 222 is coupled to a fifth node N5, and the second end of the first secondary coil 222 is coupled to A common node NCM. For example, the common node NCM can be regarded as another ground potential, which can be the same as or different from the aforementioned ground potential VSS. The second secondary coil 223 has a first end and a second end, wherein the first end of the second secondary coil 223 is coupled to the common node NCM, and the second end of the second secondary coil 223 is coupled to a first end. Six nodes N6.

The output stage circuit 230 includes a first diode D1, a second diode D2, and a second capacitor C2. The first diode D1 has an anode and a cathode, wherein the anode of the first diode D1 is coupled to the fifth node N5, and the cathode of the first diode D1 is coupled to the output node NOUT. The second diode D2 has an anode and a cathode, wherein the anode of the second diode D2 is coupled to the sixth node N6, and the cathode of the second diode D2 is coupled to the output node NOUT. The second capacitor C2 has a first terminal and a second terminal, wherein the first terminal of the second capacitor C2 is coupled to the output node NOUT, and the second terminal of the second capacitor C2 is coupled to a seventh node N7 .

The pulse width modulation integrated circuit 240 can generate the first pulse width modulation potential VM1 and the second pulse width modulation potential VM2. The first pulse width modulation potential VM1 and the second pulse width modulation potential VM2 can be maintained at a fixed potential when the power supply 200 is initialized, and can provide a period after the power supply 200 enters the normal use stage. Sexual pulse waveform. In some embodiments, the first pulse width modulation potential VM1 and the second pulse width modulation potential VM2 may have complementary logic levels. In other embodiments, the first pulse width modulation potential VM1 and the second pulse width modulation potential VM2 may have the same waveform but there is a phase difference therebetween, so that both will not be at a high logic level at the same time. . It must be understood that the operating frequencies of the first pulse width modulation potential VM1 and the second pulse width modulation potential VM2 can be regarded as the switching frequency of the power supply 200 .

The delay control circuit 250 includes a subtractor 252, a timer 254, a third transistor M3, a fourth transistor M4, a first resistor R1, and a second resistor R2. For example, the third transistor M3 and the fourth transistor M4 may each be an N-type MOSFET.

The first resistor R1 has a first terminal and a second terminal, wherein the first terminal of the first resistor R1 is coupled to the common node NCM, and the second terminal of the first resistor R1 is coupled to the seventh Node N7. The subtractor 252 can obtain a first potential V1 at the seventh node N7 and a second potential V2 at the common node NCM, and can calculate a potential difference ΔV between the first potential V1 and the second potential V2 (for example: ,or ). It must be understood that this potential difference ΔV is equal to the voltage across the two ends of the first resistor R1. In some embodiments, if the potential difference ΔV is exactly equal to 0, it means that no current flows through the first resistor R1, and the subtractor 252 will output a first control potential VC1 with a high logic level. In other embodiments, if the potential difference ΔV is not equal to 0, the subtractor 252 may output the first control potential VC1 with a low logic level, or may not output the first control potential VC1 at all.

Timer 254 is coupled to subtractor 252 . When the timer 254 receives the first control potential VC1 with a high logic level from the subtractor 252, the timer 254 will provide a second control potential VC2 with a high logic level within a delay time TD. For example, the delay time TD can be between 460ns and 540ns, but is not limited thereto. On the contrary, outside the aforementioned delay time TD, the second control potential VC2 can be maintained at a low logic level.

The third transistor M3 has a control terminal (for example: a gate), a first terminal (for example: a source), and a second terminal (for example: a drain), wherein the control terminal of the third transistor M3 The terminal is coupled to an eighth node N8, the first terminal of the third transistor M3 is coupled to the third node N3, and the second terminal of the third transistor M3 is coupled to the fourth node N4. The fourth transistor M4 has a control terminal (for example: a gate), a first terminal (for example: a source), and a second terminal (for example: a drain), wherein the control terminal of the fourth transistor M4 The terminal is used to receive the second control potential VC2, the first terminal of the fourth transistor M4 is coupled to the ground potential VSS, and the second terminal of the fourth transistor M4 is coupled to the eighth node N8. The second resistor R2 has a first terminal and a second terminal, wherein the first terminal of the second resistor R2 is coupled to a driving node NE, and the second terminal of the second resistor R2 is coupled to the driving node NE. Eight nodes N8.

Initially, the pulse width modulation integrated circuit 240 can further generate a driving potential VE and a supply potential VDD, in which the driving potential VE with a high logic level can be output to the driving node NE, and the subtractor 252 can be supplied by The potential VDD is used for power supply. Then, in some embodiments, the power supply 200 will sequentially operate in a first phase T1, a second phase T2, a third phase T3, and a fourth phase T4. The operating principles are as follows: described.

Figure 3 shows a signal waveform diagram of the power supply 200 according to an embodiment of the present invention, in which the horizontal axis represents time and the vertical axis represents potential level or current value. First, during the first phase T1, the first transistor M1 is turned on and the second transistor M2 is turned off. At this time, only the leakage inductor LR resonates with the first capacitor C1. In addition, the first current I1 flowing through the first diode D1 first gradually becomes larger and then gradually becomes smaller.

During the second phase T2, the first transistor M1 is still turned on, and the second transistor M2 is still turned off. Since the first current I1 of the first diode D1 has dropped to 0 and no current flows through the first resistor R1, the timer 254 will be able to provide the second control potential with a high logic level within the delay time TD. VC2 to temporarily turn on the fourth transistor M4. That is, during the delay time TD, the third transistor M3 will be temporarily turned off, so that the exciting inductor LM cannot participate in the aforementioned resonance tank. Then, when the delay time TD has expired, the second control potential VC2 will switch from the high logic level back to the low logic level. At this time, the magnetizing inductor LM and the leakage inductor LR will resonate with the first capacitor C1 at the same time.

During the third phase T3, the first transistor M1 is turned off and the second transistor M2 is turned on. At this time, only the leakage inductor LR resonates with the first capacitor C1. In addition, the second current I2 flowing through the second diode D2 first gradually becomes larger, and then gradually becomes smaller.

During the fourth phase T4, the first transistor M1 is still turned off, and the second transistor M2 is still turned on. Since the second current I2 of the second diode D2 has dropped to 0 and no current flows through the first resistor R1, the timer 254 will be able to provide the second control potential with a high logic level within the delay time TD. VC2 to temporarily turn on the fourth transistor M4. That is, during the delay time TD, the third transistor M3 will be temporarily turned off, so that the exciting inductor LM cannot participate in the aforementioned resonance tank. Then, when the delay time TD has expired, the second control potential VC2 will switch from the high logic level back to the low logic level. At this time, the magnetizing inductor LM and the leakage inductor LR will resonate with the first capacitor C1 at the same time.

Figure 4 shows a signal waveform diagram of a traditional power supply, in which the horizontal axis represents time and the vertical axis represents potential level or current value. As shown in Figure 4, if the switching frequency of the traditional power supply is adjusted during the second stage T2, the corresponding resonant current IR may decline, and the corresponding capacitor potential VR may oscillate severely, which will have a negative impact on the traditional power supply. The output stability will have a greater negative impact.

Figure 5 shows a signal waveform diagram of the power supply 200 according to an embodiment of the present invention, in which the horizontal axis represents time and the vertical axis represents potential level or current value. According to the measurement results in Figure 5, if the magnetizing inductor LM participates in the resonance operation of the aforementioned resonance tank and is substantially delayed by a delay time TD, the decline of the resonance current IR and the non-ideal oscillation of the capacitor potential VR can be completely avoided. In other words, even if the power supply 200 adjusts the switching frequency during the second phase T2 or the fourth phase T4, the power supply 200 can still provide extremely high output stability as a whole, thus overcoming the major shortcomings of the traditional design.

The present invention proposes a novel power supply. According to the actual measurement results, the output stability of the power supply using the above-mentioned design can be greatly improved, so it is very suitable for use in various devices.

It is worth noting that the above-mentioned potential, current, resistance value, inductance value, capacitance value, and other component parameters are not limiting conditions of the present invention. Designers can adjust these settings according to different needs. The power supply of the present invention is not limited to the state shown in Figures 1-5. The present invention may only include any one or multiple features of any one or multiple embodiments of Figures 1-5. In other words, not all features shown in the figures need to be implemented in the power supply of the present invention at the same time. Although the embodiment of the present invention uses a metal oxide semi-field effect transistor as an example, the present invention is not limited thereto. Those skilled in the art can use other types of transistors, such as junction field effect transistors or fins. type field effect transistor, etc., without affecting the effect of the present invention.

The ordinal numbers in this specification and the scope of the patent application, such as "first", "second", "third", etc., have no sequential relationship with each other. They are only used to distinguish two items with the same Different components with names.

Although the present invention is disclosed above in terms of preferred embodiments, they are not intended to limit the scope of the present invention. Anyone skilled in the art can make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

100,200:Power supply 110,210: Input switching circuit 120,220:Transformer 121,221: Main coil 122,222: first secondary coil 123,223: Second secondary coil 130,230: Output stage circuit 140,240: Pulse width modulation integrated circuit 150,250: Delay control circuit 252:Subtractor 254: timer C1: first capacitor C2: Second capacitor D1: first diode D2: Second diode I1: first current I2: second current IR: resonant circuit LM: Magnetizing inductor LR: leakage inductor M1: the first transistor M2: Second transistor M3: The third transistor M4: The fourth transistor N1: first node N2: second node N3: The third node N4: fourth node N5: fifth node N6: The sixth node N7: The seventh node N8: The eighth node NCM: common node NIN: input node NE: driver node NOUT: output node R1: first resistor R2: second resistor T1: first stage T2: The second stage T3: The third stage T4: The fourth stage TD: delay time V1: first potential V2: second potential VC1: first control potential VC2: second control potential VDD: supply potential VE: drive potential VIN: input potential VM1: first pulse width modulation potential VM2: second pulse width modulation potential VOUT: output potential VR: capacitor potential VSS: ground potential VW: switching potential ΔV: potential difference

Figure 1 is a schematic diagram of a power supply according to an embodiment of the present invention. Figure 2 is a circuit diagram showing a power supply according to an embodiment of the present invention. Figure 3 shows a signal waveform diagram of a power supply according to an embodiment of the present invention. Figure 4 shows the signal waveform diagram of a traditional power supply. Figure 5 shows a signal waveform diagram of a power supply according to an embodiment of the present invention.

100:Power supply

110: Input switching circuit

120:Transformer

121: Main coil

122: First secondary coil

123: Second secondary coil

130:Output stage circuit

140: Pulse width modulation integrated circuit

150: Delay control circuit

C1: first capacitor

LM: Magnetizing inductor

LR: leakage inductor

R1: first resistor

TD: delay time

VIN: input potential

VM1: first pulse width modulation potential

VM2: second pulse width modulation potential

VOUT: output potential

VR: capacitor potential

VW: switching potential

Claims (10)

A power supply with high output stability, including: An input switching circuit generates a switching potential based on an input potential, a first pulse width modulation potential, and a second pulse width modulation potential; A transformer includes a primary coil, a first secondary coil, and a second secondary coil, wherein the transformer has a built-in leakage inductor and a magnetizing inductor, and the primary coil receives the switching potential through the leakage inductor. ; a first capacitor coupled to the main coil; an output stage circuit coupled to the first secondary coil and the second secondary coil and used to generate an output potential; a pulse width modulation integrated circuit that generates the first pulse width modulation potential and the second pulse width modulation potential; and A delay control circuit including a first resistor coupled to the output stage circuit, wherein if it is detected that no current flows through the first resistor, the delay control circuit will be temporarily disabled within a delay time the exciting inductor. The power supply of claim 1, wherein the input switching circuit includes: A first transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first transistor is used to receive the first pulse width modulation potential, and the first The first terminal of the transistor is coupled to a first node to output the switching potential, and the second terminal of the first transistor is coupled to an input node to receive the input potential; and A second transistor has a control end, a first end, and a second end, wherein the control end of the second transistor is used to receive the second pulse width modulation potential, and the second The first terminal of the transistor is coupled to a ground potential, and the second terminal of the second transistor is coupled to the first node. The power supply of claim 2, wherein the leakage inductor has a first terminal and a second terminal, the first terminal of the leakage inductor is coupled to the first node to receive the switching potential, the leakage inductor The second end of the device is coupled to a second node, the main coil has a first end and a second end, the first end of the main coil is coupled to the second node, and the main coil has a first end and a second end. The second terminal is coupled to a third node, the magnetizing inductor has a first terminal and a second terminal, the first terminal of the magnetizing inductor is coupled to the second node, and the magnetizing inductor has a first terminal and a second terminal. The second terminal is coupled to a fourth node, the first capacitor has a first terminal and a second terminal, the first terminal of the first capacitor is coupled to the third node, the first capacitor The second end is coupled to the ground potential, the first secondary coil has a first end and a second end, the first end of the first secondary coil is coupled to a fifth node, and the first secondary coil has a first end and a second end. The second end of the secondary coil is coupled to a common node, the second secondary coil has a first end and a second end, and the first end of the second secondary coil is coupled to the common node, The second end of the second secondary coil is coupled to a sixth node. The power supply of claim 3, wherein the output stage circuit includes: A first diode having an anode and a cathode, wherein the anode of the first diode is coupled to the fifth node, and the cathode of the first diode is coupled to an output node to output the output potential; a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to the sixth node, and the cathode of the second diode is coupled to the output node ;as well as a second capacitor having a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to the output node, and the second terminal of the second capacitor is coupled to a first Seven nodes. The power supply of claim 4, wherein the first resistor has a first terminal and a second terminal, the first terminal of the first resistor is coupled to the common node, and the first resistor The second terminal is coupled to the seventh node. The power supply of claim 4, wherein the delay control circuit further includes: A subtractor, obtains a first potential at the seventh node and a second potential at the common node, and calculates a potential difference between the first potential and the second potential, wherein if the potential difference is exactly equal to 0, the subtractor will output a first control potential. The power supply of claim 6, wherein the delay control circuit further includes: A timer, when the timer receives the first control potential from the subtractor, the timer will provide a second control potential with a high logic level within the delay time. The power supply of claim 7, wherein the delay control circuit further includes: A third transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third transistor is coupled to an eighth node, and the first terminal of the third transistor A terminal is coupled to the third node, and the second terminal of the third transistor is coupled to the fourth node; A fourth transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fourth transistor is used to receive the second control potential, and the third terminal of the fourth transistor One terminal is coupled to the ground potential, and the second terminal of the fourth transistor is coupled to the eighth node; and a second resistor having a first terminal and a second terminal, wherein the first terminal of the second resistor is coupled to a drive node, and the second terminal of the second resistor is coupled to to the eighth node. The power supply of claim 8, wherein the pulse width modulation integrated circuit further generates a driving potential and a supply potential, the driving potential is output to the driving node, and the subtractor is performed by the supply potential Power supply. For example, the power supply of claim 1, wherein the delay time is between 460ns and 540ns.

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