TW202338779A - Gate driver capable of selecting multiple channels simultaneously - Google Patents

Abstract

A gate driver including a channel decoder, a plurality of gate driving units and a plurality of level shifting units is disclosed. The channel decoder is configured to generate a plurality of turn-on signals according to a latch signal and a channel number signal. The plurality of gate driving units are coupled to the channel decoder, and configured to generate a plurality of gate output signals according to the plurality of turn-on signals, a selection signal and an input signal. The plurality of level shifting units are coupled to the plurality of gate driving units, and configured to perform voltage conversion according to the plurality of gate output signals. The channel number signal indicates a primary channel number, and the selection signal indicates at least one secondary channel number.

Description

Multiple channel gate drivers can be selected simultaneously

The present invention relates to a gate driver, in particular to a gate driver capable of selecting multiple channels simultaneously.

A liquid crystal display (LCD) includes a timing controller, a gate driver, a source driver, and a display panel. The display panel includes multiple pixel units arranged in a matrix. The gate driver is used to turn on multiple pixel units connected to a gate channel (Gate Channel) or scanning line (Scanning Line), while the source driver is used to turn on multiple pixel units connected to a source channel (Source Channel) or data line ( Data Line) multiple pixel units. The timing controller is used to control the gate driver and the source driver to sequentially open the gate channels and source channels to scan multiple pixel units arranged in a matrix to update the display image.

The traditional scanning operation of an LCD is performed in units of rows. The gate driver circuit opens one gate channel at a time, and the source driver provides pixel data for each column. The gate drive circuit can sequentially open the gate channels from top to bottom or bottom to top, for example, from the first row at the top of the display panel, the second row... to the last row at the bottom of the display panel, or from the last row. Go to the first line and scan in sequence.

However, new displays in the future will focus on requirements such as adjustable refresh rate (Refresh Rate), partial image updating, and low power consumption. Traditional scanning operations can no longer meet the above requirements. Therefore, how to provide a source driver that is different from the traditional method of turning on one gate channel at a time has become one of the emerging topics in this field.

One object of the present invention is to provide a gate driver that can select multiple channels simultaneously.

The invention discloses a gate driver, which includes a channel decoder, a plurality of gate driving units and a plurality of level conversion units. The channel decoder is used to generate multiple conduction signals based on a latch signal and a channel number signal. The plurality of gate driving units are coupled to the channel decoder and used to generate a plurality of gate output signals according to the plurality of conduction signals, a selection signal and an input signal. The plurality of level conversion units are coupled to the plurality of gate driving units and used to perform voltage conversion according to the plurality of gate output signals. The channel number signal indicates a primary channel number, and the selection signal indicates at least a secondary channel number.

Compared with the prior art, the gate driver of the present invention can randomly turn on any main gate channel and the related at least one secondary gate channel to achieve local picture updating (power saving) of the display, improve the update rate, and achieve corresponding Compatible with existing display gate scan operations.

FIG. 1 is a schematic diagram of a gate driver 1 according to an embodiment of the present invention. Structurally, the gate driver 1 includes a channel decoder 10 , a gate drive module 11 and a level conversion module 12 . The channel decoder 10 is used to generate a plurality of conduction signals ON[1]...ON[m] according to a latch signal LAT and a channel number signal NUM[10:0]. The gate drive module 11 includes a plurality of gate drive units GD[1]...GD[m], coupled to the channel decoder 10, for selecting a The signal SEL[3:1] and an input signal IN generate multiple gate output signals OUT[1]…OUT[m]. The level conversion module 12 includes a plurality of level conversion units LS[1]...LS[m], coupled to the gate driving module 11, for outputting signals OUT[1]...OUT[m] according to the plurality of gates. ], perform voltage conversion. The channel number signal NUM[10:0] indicates a primary channel number, and the selection signal SEL[3:1] indicates at least one secondary channel number.

Gate driver 1 is used for a display. The display includes a timing controller (Timing Controller) and a shift register (Level Shifter) (not shown in Figure 1). The timing controller is coupled to the gate driver 1 and used to generate the channel number signal NUM[10:0] and the selection signal SEL[3:1]. The shift register is coupled to the timing controller and the channel decoder 10 for generating the input signal IN and the latch signal LAT. In one embodiment, a plurality of gate driving units GD[1]...GD[m] are coupled to the timing controller and the shift register through the channel decoder 10 to indirectly receive the selection signals SEL[3:1] and Input signal IN. In one embodiment, a plurality of gate driving units GD[1]...GD[m] are coupled to the timing controller and the shift register to directly receive the selection signal SEL[3:1] and the input signal IN.

FIG. 2 is a signal timing diagram of the gate driver 1 according to the embodiment of the present invention. In this embodiment, the channel number signal NUM[10:0] includes but is not limited to 11 binary bits, and the channel decoder 10 is used to interpret (interpret) the decimal value corresponding to the channel number signal NUM[10:0]. , the three main channel numbers indicated by this channel number signal NUM[10:0] are represented by 11d'100, 11d'101 and 11d'105 respectively.

In this embodiment, the selection signal SEL[3:1] includes a bits, and the "at least one" minor channel number includes a minor channel numbers, and the a bits respectively correspond to a minor channel numbers. , and a is a positive integer greater than zero. The a minor channel numbers are respectively the sum of the major channel numbers and 1...a. In this embodiment, a is, for example but not limited to, an integer 3. The 3 bits correspond to 3 minor channel numbers respectively, and the 3 minor channel numbers are respectively the sum of the major channel number and the integers 1, 2 and 3. . When a b-th bit in the selection signal SEL[3:1] is a first logic state (for example, logic "1"), a b-th secondary channel corresponding to the b-th bit is in a conductive state ; And when the b-th bit in the selection signal SEL[3:1] is a second logic state (such as logic "0"), the b-th secondary channel corresponding to the b-th bit is in a closed state ;where 1≦b≦a.

In operation, when the channel decoder 10 detects the rising edge of the latch signal LAT, it generates a high voltage level according to the main channel number 11d'100 indicated by the channel number signal NUM[10:0]. The conduction signal ON[100] is used to turn on the gate drive unit GD[100] (not shown in Figure 2). The gate driving unit GD[100] is turned on to pass the input signal IN as the gate output signal OUT[100]. At the same time, the selection signal SEL[3:1] is represented by 3b’000, and the minor channel numbers related to the main channel number 11d’100 are decimal 101, 102 and 103, and they are all closed. Therefore, the gate driving units GD[101], GD[102] and GD[103] are turned off without passing the input signal IN, so that the gate output signals OUT[101], OUT[102] and OUT[103] have low voltage level.

In one embodiment, when the channel decoder 10 detects the rising edge of the latch signal LAT again, it generates a high voltage level according to the main channel number 11d'101 indicated by the channel number signal NUM[10:0]. The signal ON[101] is turned on to turn on the gate driving unit GD[101] (not shown in Figure 2). The gate driving unit GD[101] is turned on to pass the input signal IN as the gate output signal OUT[101]. At the same time, the selection signal SEL[3:1] is represented by 3b’111, and the secondary channel numbers related to the main channel number 11d’101 are 11d’102, 11d’103 and 11d’104, and they are all in the conducting state. Therefore, the gate driving units GD[102], GD[103] and GD[104] are turned on to pass the input signal IN, so that the gate output signals OUT[102], OUT[103] and OUT[104] have high voltages. Level.

In one embodiment, when the channel decoder 10 detects the rising edge of the latch signal LAT again, it generates a high voltage level according to the main channel number 11d'105 indicated by the channel number signal NUM[10:0]. The signal ON[105] is turned on to turn on the gate driving unit GD[105] (not shown in Figure 2). The gate driving unit GD[105] is turned on to pass the input signal IN as the gate output signal OUT[105]. At the same time, the selection signal SEL[3:1] is represented by 3b'010, then the secondary channel numbers related to the primary channel number 11d'105 are 11d'106, 11d'107 and 11d'108, and the secondary channel number is 11d '106 and 11d'108 are off, and minor channel number 11d'107 is on. Therefore, the gate driving units GD[106] and GD[108] are turned off without passing the input signal IN, and the gate driving unit GD[107] is turned on and passing the input signal IN, so that the gate output signal OUT[106] and OUT[108] have a low voltage level, and the gate output signal OUT[107] has a high voltage level.

As can be seen from the embodiment of Figure 2, the gate driver 1 of the present invention can randomly turn on any main gate channel and the associated at least one channel according to the channel number signal NUM[10:0] and the selection signal SEL[3:1]. A gate channel is required. It is worth noting that the gate driver 1 of the present invention is compatible with traditional display scanning operations; specifically, when the channel number signal NUM[10:0] is consecutive (consecutive) and the selection signal SEL[3: 1] When 3b'000, no secondary gate channel is opened, which is equivalent to a traditional display scan operation

Furthermore, the gate driver 1 of the present invention can realize partial picture updating of the display; specifically, when the selection signal SEL[3:1] is 3b'111, the gate driver 1 can open four adjacent gates at the same time. The gate channel is the main gate channel and three adjacent secondary gate channels. In other embodiments, when the selection signal SEL[3:1] includes a bits, the gate driver 1 can turn on at most 1+a adjacent gate channels at the same time. In practical applications, when the field of view (Field of View) provided by a large-size display exceeds the Region of Interest (ROI) focused by the human eye, the local image update function of the display can improve the local image of the display (i.e. the ROI). Area) smoothness (Smoothness). In addition, through partial picture updating, it is equivalent to not updating other partial pictures, which can also achieve the effect of power saving.

Furthermore, the gate driver 1 of the present invention can increase the refresh rate of the display by simultaneously opening multiple gate channels; specifically, when the selection signal SEL[3:1] is 3b'010, the gate driver 1 Two odd- or even-numbered gate channels can be opened at the same time. Compared with traditional displays that open one gate channel at a time, the gate driver 1 of the present invention can achieve more than twice the update rate to improve the dynamic smoothness of the overall display screen. Spend.

To put it simply, through the circuit structure of the gate driver 1 in Figure 1 of the present invention and the operation mode in Figure 2, any main gate channel and the associated at least one secondary gate channel can be randomly turned on to realize partial control of the display. Screen updates (power saving), improves update rate, and is compatible with existing monitor gate scanning operations.

FIG. 3 is a schematic equivalent circuit diagram of the gate driving units GD[n]_3A and GD[n]_3B according to the first embodiment of the present invention. The n-th gate driving unit GD[n] among the multiple gate driving units GD[1]...GD[m] in Figure 1 can be implemented by the gate driving unit GD[n]_3A or GD[n]_3B. Up to two gate channels can be opened at the same time. Assume that the selection signal SEL includes one bit (a=1), and the gate driving unit GD[n]_3A includes AND gates 31 and 32 and an OR gate 30 . The AND gate 31 is coupled to the channel decoder 10 (not shown in Figure 3), and is used to generate an n-th conduction signal ON[n] according to a plurality of conduction signals ON[1]...ON[m] and the input signal IN, An n-th relay signal P[n] is generated. The AND gate 32 is coupled to the AND gate 31 and used to generate an n-th relay signal P[n] to the n+1-th gate driving unit GD[n+1] according to the selection signal SEL (not shown in the figure). 3). The OR gate 30 is coupled to the AND gate 31 , a AND gate 32 and an n-th level conversion unit LS[n] among the plurality of level conversion units LS[1]...LS[m] (not shown in the figure). 3), used to generate an n-th gate among multiple gate output signals OUT[1]...OUT[m] based on the n-th relay signal P[n] and the n-1th relay signal. Output signal OUT[n].

On the other hand, the gate driving unit GD[n]_3B includes switches SW1, SW2 and SW31. The switch SW1 is coupled to the channel decoder 10 and the nth level conversion unit LS[n] among the plurality of level conversion units LS[1]...LS[m], and is used to determine according to the turn-on signal ON[n]. Whether to pass the input signal IN as the nth gate output signal OUT[n]. The switch SW2 is coupled to the switch SW1 and is used to determine whether to pass the input signal IN as the n-th relay signal P[n] according to the n-th conduction signal ON[n]. The switch SW31 is coupled to the switch SW2 and is used to determine whether to transmit the n-th relay signal P[n] to the n+1-th pole driving unit GD[n+1] according to the selection signal SEL.

FIG. 4 is a schematic equivalent circuit diagram of the gate driving units GD[n]_4A and GD[n]_4B according to the second embodiment of the present invention. The n-th gate driving unit GD[n] among the multiple gate driving units GD[1]...GD[m] in Figure 1 can be implemented by the gate driving unit GD[n]_4A or GD[n]_4B. Up to three gate channels can be opened at the same time. Assume that the selection signal SEL[2:1] includes two bits (a=2), and the gate driving unit GD[n]_4A includes AND gates 41, 42, 43 and an OR gate 40. The AND gate 41 is coupled to the channel decoder 10 (not shown in FIG. 4 ) and is used to generate the nth relay signal P[n] according to the conduction signal ON[n] and the input signal IN. The AND gate 42 is coupled to the AND gate 41 and is used to generate an n-th relay signal P1[n] to the n+1-th gate driving unit according to the bit [1] of the selection signal SEL[2:1]. GD[n+1] (not shown in Figure 4). The AND gate 43 is coupled to the AND gate 41 and is used to generate an n-th relay signal P2[n] to the n+2-th gate driving unit according to the bit [2] of the selection signal SEL[2:1]. GD[n+2]. The OR gate 40 is coupled to the AND gates 41, 42, 43 and an n-th level conversion unit LS[n] among the plurality of level conversion units LS[1]...LS[m] (not shown in Figure 4) , used to generate the nth gate output signal OUT[n] based on the relay signals P[n], P1[n-1] and P2[n-2]. The relay signal P2[n-1] is transmitted between the gate driving units GD[n-1] and GD[n+1].

On the other hand, the gate driving unit GD[n]_4B includes switches SW1, SW2, SW41 and SW42. The switch SW1 is coupled to the channel decoder 10 and the nth level conversion unit LS[n] among the plurality of level conversion units LS[1]...LS[m], and is used to conduct the nth signal ON[n according to the nth ], determine whether to pass the input signal IN as the nth gate output signal OUT[n]. The switch SW2 is coupled to the switch SW1 and is used to determine whether to pass the input signal IN as the n-th relay signal P[n] according to the n-th conduction signal ON[n]. The switch SW41 is coupled to the switch SW2 and is used to determine whether to transmit the relay signal P1[n] to the n+1th pole driving unit GD[n+1] based on the bit [1] of the selection signal SEL[2:1]. ]. The switch SW42 is coupled to the switch SW2 and is used to determine whether to transmit the relay signal P2[n] to the n+2-th pole driving unit GD[n+2 according to the bit [2] of the selection signal SEL[2:1]. ].

FIG. 5 is a schematic equivalent circuit diagram of the gate driving units GD[n]_5A and GD[n]_5B according to the third embodiment of the present invention. The n-th gate driving unit GD[n] among the multiple gate driving units GD[1]...GD[m] in Figure 1 can be implemented by the gate driving unit GD[n]_5A or GD[n]_5B. Up to four gate channels can be opened at the same time. Assume that the selection signal SEL[3:1] includes three bits (a=3), and the gate driving unit GD[n]_5A includes AND gates 51, 52, 53, 54 and an OR gate 50. The AND gate 51 is coupled to the channel decoder 10 (not shown in FIG. 5 ) and is used to generate the nth relay signal P[n] according to the conduction signal ON[n] and the input signal IN. The AND gate 52 is coupled to the AND gate 51 and is used to generate an n-th relay signal P1[n] to the n+1-th gate driving unit according to the bit [1] of the selection signal SEL[3:1]. GD[n+1] (not shown in Figure 5). The AND gate 53 is coupled to the AND gate 51 and is used to generate an n-th relay signal P2[n] to the n+1-th gate driving unit according to the bit [2] of the selection signal SEL[3:1]. GD[n+1]. The AND gate 54 is coupled to the AND gate 51 and is used to generate an n-th relay signal P3[n] to the n+1-th gate driving unit according to the bit [3] of the selection signal SEL[3:1]. GD[n+1]. The OR gate 50 is coupled to the AND gates 51, 52, 53, 54 and an n-th level conversion unit LS[n] among the plurality of level conversion units LS[1]...LS[m] (not shown in the figure). 5), used to generate the nth gate output signal OUT[n] based on the relay signals P[n], P1[n-1], P2[n-2] and P3[n-3]. The relay signal P2[n-1] is transmitted between the gate driving unit GD[n-1] and GD[n+1], and the relay signal P3[n-1] is transmitted between the gate driving unit GD[n- 1] and GD[n+2], and the relay signal P3[n-2] is transmitted between the gate driving units GD[n-2] and GD[n+1].

On the other hand, the gate driving unit GD[n]_5B includes switches SW1, SW2, SW51, SW52, and SW53. The switch SW1 is coupled to the channel decoder 10 and the nth level conversion unit LS[n] among the plurality of level conversion units LS[1]...LS[m], and is used to conduct the nth signal ON[n according to the nth ], determine whether to pass the input signal IN as the nth gate output signal OUT[n]. The switch SW2 is coupled to the switch SW1 and is used to determine whether to pass the input signal IN as the n-th relay signal P[n] according to the n-th conduction signal ON[n]. The switch SW51 is coupled to the switch SW2 and is used to determine whether to transmit the relay signal P1[n] to the n+1th pole driving unit GD[n+1] based on the bit [1] of the selection signal SEL[3:1]. ]. The switch SW52 is coupled to the switch SW2 and is used to determine whether to transmit the relay signal P2[n] to the n+2-th pole driving unit GD[n+2 according to the bit [2] of the selection signal SEL[3:1]. ]. The switch SW53 is coupled to the switch SW2 and is used to determine whether to transmit the relay signal P3[n] to the n+1th pole driving unit GD[n+3] according to the bit [3] of the selection signal SEL.

FIG. 6 is a schematic equivalent circuit diagram of the gate driving unit GD[n]_6 according to the fourth embodiment of the present invention. The n-th gate driving unit GD[n] among the multiple gate driving units GD[1]...GD[m] in Figure 1 can be realized by the gate driving unit GD[n]_6, which can turn on up to a at the same time. gate channel. Assume that the selection signal SEL[a:1] includes a bits, and the gate driving unit GD[n]_6 includes switches SW1, SW2 and a switches SW61...SW6a. The switch SW1 is coupled to the channel decoder 10 and the nth level conversion unit LS[n] among the plurality of level conversion units LS[1]...LS[m], and is used to conduct the nth signal ON[n according to the nth ], determine whether to pass the input signal IN as the nth gate output signal OUT[n]. The switch SW2 is coupled to the switch SW1 and is used to determine whether to pass the input signal IN as the n-th relay signal P[n] according to the n-th conduction signal ON[n]. A switches SW61...SW6a are coupled to the switch SW2, and are used to determine whether to pass a relay signal P1[n]...Pa[n] to a pole according to a bits of the selection signal SEL[a:1]. Drive units GD[n+1]…GD[n+a].

FIG. 7 is a schematic diagram of the circuit operation of the gate driving units GD[n]_3A and GD[n]_3B according to the first embodiment of the present invention. In the gate driving unit GD[n]_3A, when the conduction signal ON[n] is in the first logic state (for example, logic "1"), the AND gate 31 passes the input signal IN as the relay signal P[n], The AND gate 30 passes the relay signal P[n] as the n-th gate output signal OUT[n]; and when the conduction signal ON[n] is in the second logic state (for example, logic “0”), the AND gate 31 does not pass the input signal IN. When the selection signal SEL is in the first logic state (for example, logic “1”), the AND gate 32 transmits the relay signal P[n] to the OR gate 30 of the n+1th gate driving unit GD[n+1]. As the n+1th gate output signal OUT[n+1]; and when the selection signal SEL is in the second logic state (eg logic “0”), the AND gate 32 does not transmit the relay signal P[n]. Through the above operations, the gate driving unit GD[n]_3A can open up to two gate channels at the same time.

In the gate driving unit GD[n]_3B, when the n-th conduction signal ON[n] turns on the switch SW1, the switch SW1 passes the input signal IN as the n-th gate output signal OUT[n]; and when the n-th gate output signal OUT[n] is turned on, the switch SW1 When a conduction signal ON[n] turns off the switch SW1, the switch SW1 does not transmit the input signal IN. When the nth conduction signal ON[n] turns on the switch SW2, the switch SW2 passes the input signal IN as the nth relay signal P[n]; and when the nth conduction signal ON[n] turns off the switch SW2, the switch SW2 does not pass the input signal IN. When the selection signal SEL turns on the switch SW31, the switch SW31 transmits the n-th relay signal P[n] to the n+1 gate driving unit GD[n+1]; and when the selection signal SEL turns off the switch SW31, the switch SW31 does not transmit The nth relay signal P[n]. Through the above operations, the gate driving unit GD[n]_3B can open up to two gate channels at the same time.

FIG. 8 is a schematic diagram of the circuit operation of the gate driving unit GD[n]_4A according to the second embodiment of the present invention. When the conduction signal ON[n] is in the first logic state, the AND gate 41 passes the input signal IN as the relay signal P[n], and the OR gate 40 passes the relay signal P[n] as the nth gate. The output signal OUT[n]; and when the conduction signal ON[n] is in the second logic state, the AND gate 41 does not pass the input signal IN. When bit [1] of the selection signal SEL[2:1] is in the first logic state, the AND gate 42 transmits the relay signal P[n] to the n+1th gate driving unit GD[n+1]_4A The OR gate 40 is used as the n+1th gate output signal OUT[n+1]; and when the bit [1] of the selection signal SEL[2:1] is in the second logic state, the AND gate 42 does not pass Relay signal P[n]. When bit [2] of the selection signal SEL[2:1] is in the first logic state, the AND gate 43 transmits the relay signal P[n] to the n+2 gate driving unit GD[n+2]_4A The OR gate 40 is used as the n+2 gate output signal OUT[n+2]; and when the bit [2] of the selection signal SEL[2:1] is in the second logic state, the AND gate 43 does not pass Relay signal P[n]. Through the above operations, the gate drive unit GD[n]_4A can open up to three gate channels at the same time.

FIG. 9 is a schematic diagram of the circuit operation of the gate driving unit GD[n]_4B according to the second embodiment of the present invention. When the nth conduction signal ON[n] turns on the switch SW1, the switch SW1 passes the input signal IN as the nth gate output signal OUT[n]; and when the nth conduction signal ON[n] turns off the switch SW1, The switch SW1 does not pass the input signal IN. When the nth conduction signal ON[n] turns on the switch SW2, the switch SW2 passes the input signal IN as the nth relay signal P[n]; and when the nth conduction signal ON[n] turns off the switch SW2, the switch SW2 does not pass the input signal IN. When bit [1] of the selection signal SEL[2:1] turns on the switch SW41, the switch SW41 transmits the n-th relay signal P[n] to the n+1-th gate driving unit GD[n+1]_4B; And bit [1] of the selection signal SEL[2:1] turns off the switch SW41, and the switch SW41 does not transmit the nth relay signal P[n]. When bit [2] of the selection signal SEL[2:1] turns on the switch SW42, the switch SW42 transmits the n-th relay signal P[n] to the n+2-th gate driving unit GD[n+2]_4B; And bit [2] of the selection signal SEL[2:1] turns off the switch SW42, and the switch SW42 does not transmit the nth relay signal P[n]. Through the above operations, the gate driving unit GD[n]_4B can open up to three gate channels at the same time.

FIG. 10 is a schematic diagram of the circuit operation of the gate driving unit GD[n]_5A according to the third embodiment of the present invention. When the conduction signal ON[n] is in the first logic state, the AND gate 51 passes the input signal IN as the relay signal P[n], and the OR gate 50 passes the relay signal P[n] as the nth gate. The output signal OUT[n]; and when the conduction signal ON[n] is in the second logic state, the AND gate 51 does not pass the input signal IN. When bit [1] of the selection signal SEL[3:1] is in the first logic state, the AND gate 52 transmits the relay signal P[n] to the n+1th gate driving unit GD[n+1]_5A The OR gate 50 is used as the n+1th gate output signal OUT[n+1]; and when the bit [1] of the selection signal SEL[3:1] is in the second logic state, the AND gate 52 does not pass Relay signal P[n]. When the bit [2] of the selection signal SEL[3:1] is in the first logic state, the AND gate 53 transmits the relay signal P[n] to the n+2 gate driving unit GD[n+2]_5A The OR gate 50 is used as the n+2 gate output signal OUT[n+2]; and when the bit [2] of the selection signal SEL[3:1] is in the second logic state, the AND gate 53 does not pass Relay signal P[n]. When bit [3] of the selection signal SEL[3:1] is in the first logic state, the AND gate 54 transmits the relay signal P[n] to the n+3 gate driving unit GD[n+3]_5A The OR gate 50 is used as the n+3 gate output signal OUT[n+3]; and when the bit [3] of the selection signal SEL[3:1] is in the second logic state, the AND gate 54 does not pass Relay signal P[n]. Through the above operations, the gate drive unit GD[n]_5A can open up to four gate channels at the same time.

FIG. 11 is a schematic diagram of the circuit operation of the gate driving unit GD[n]_5B according to the third embodiment of the present invention. When the nth conduction signal ON[n] turns on the switch SW1, the switch SW1 passes the input signal IN as the nth gate output signal OUT[n]; and when the nth conduction signal ON[n] turns off the switch SW1, The switch SW1 does not pass the input signal IN. When the nth conduction signal ON[n] turns on the switch SW2, the switch SW2 passes the input signal IN as the nth relay signal P[n]; and when the nth conduction signal ON[n] turns off the switch SW2, the switch SW2 does not pass the input signal IN. When bit [1] of the selection signal SEL[3:1] turns on the switch SW51, the switch SW51 transmits the n-th relay signal P[n] to the n+1-th gate driving unit GD[n+1]_5B; And bit [1] of the selection signal SEL[3:1] turns off the switch SW51, and the switch SW51 does not transmit the nth relay signal P[n]. When bit [2] of the selection signal SEL[3:1] turns on the switch SW52, the switch SW52 transmits the n-th relay signal P[n] to the n+2-th gate driving unit GD[n+2]_5B; And bit [2] of the selection signal SEL[3:1] turns off the switch SW52, and the switch SW52 does not transmit the nth relay signal P[n]. When bit [3] of the selection signal SEL[3:1] turns on the switch SW53, the switch SW53 transmits the n-th relay signal P[n] to the n+3-th gate driving unit GD[n+3]_5B; And bit [3] of the selection signal SEL[3:1] turns off the switch SW53, and the switch SW53 does not transmit the nth relay signal P[n]. Through the above operations, the gate driving unit GD[n]_4B can open up to four gate channels at the same time.

In summary, through the circuit structure and operation mode of the gate driver according to the embodiment of the present invention, any main gate channel and the related at least one secondary gate channel can be randomly opened to achieve partial picture updating of the display (power saving). ), improves the update rate and is compatible with existing display gate scanning operations.

The present invention has been described by the above-mentioned relevant embodiments, but the above-mentioned embodiments are only examples of implementing the present invention. It must be pointed out that the disclosed embodiments do not limit the scope of the present invention. On the contrary, modifications and equivalent arrangements included in the spirit and scope of the claimed patent are included in the scope of the present invention.

1: Gate driver 10: Channel decoder 11: Gate drive module 12:Level conversion module 30, 40, 50: OR gate 31, 32, 41, 42, 43, 51, 52, 53, 54: and gate GD[1]…GD[n]…GD[m]: Gate drive unit GD[n]_3A, GD[n]_3B, GD[n+1]_3A, GD[n+1]_3B: Gate drive unit GD[n]_4A, GD[n]_4B, GD[n+1]_4A, GD[n+1]_4B: Gate drive unit GD[n+2]_4A, GD[n+2]_4B, GD[n]_5A, GD[n]_5B: Gate drive unit GD[n+1]_5A, GD[n+1]_5B, GD[n+2]_5A, GD[n+2]_5B: Gate drive unit GD[n+3]_5A, GD[n+3]_5B, GD[n]_6: Gate drive unit IN: input signal LAT: latch signal LS[1]…LS[n]…LS[m]: level conversion unit NUM[10:0]: channel number signal ON[1]…ON[n]…ON[m], ON[100], ON[101], ON[105]: ON signal OUT[1]…OUT[n]…OUT[m], OUT[100]…OUT[107]: Gate output signal P3[n-3], P3[n-2], P3[n-1], P3[n], P2[n-2], P2[n-1], P2[n]: relay signal P1[n-1], P1[n], P[n]: relay signal SEL, SEL[2:1], SEL[3:1]: select signal SW1, SW2, SW31, SW41, SW42: switch SW51, SW52, SW53, SW61…SW6a: switch [1]…[a]:bit

FIG. 1 is a schematic diagram of a gate driver according to an embodiment of the present invention. FIG. 2 is a signal timing diagram of a gate driver according to an embodiment of the present invention. FIG. 3 is a schematic equivalent circuit diagram of a gate driving unit according to the first embodiment of the present invention. FIG. 4 is a schematic equivalent circuit diagram of a gate driving unit according to the second embodiment of the present invention. FIG. 5 is a schematic equivalent circuit diagram of a gate driving unit according to the third embodiment of the present invention. FIG. 6 is a schematic equivalent circuit diagram of a gate driving unit according to the fourth embodiment of the present invention. FIG. 7 is a schematic diagram of the circuit operation of the gate driving unit according to the first embodiment of the present invention. FIG. 8 is a schematic diagram of the circuit operation of the gate driving unit according to the second embodiment of the present invention. FIG. 9 is a schematic diagram of the circuit operation of the gate driving unit according to the second embodiment of the present invention. FIG. 10 is a schematic diagram of the circuit operation of the gate driving unit according to the third embodiment of the present invention. FIG. 11 is a schematic diagram of the circuit operation of the gate driving unit according to the third embodiment of the present invention.

1: Gate driver

10: Channel decoder

11: Gate drive module

12:Level conversion module

GD[1]...GD[n]...GD[m]: Gate drive unit

IN: input signal

LAT: latch signal

LS[1]...LS[n]...LS[m]: level conversion unit

NUM[10:0]: channel number signal

ON[1]...ON[n]...ON[m]: ON signal

OUT[1]...OUT[n]...OUT[m]: gate output signal

SEL[3:1]: select signal

Claims (10)

A gate driver containing: A channel decoder is used to generate multiple conduction signals based on a latch signal and a channel number signal; A plurality of gate driving units coupled to the channel decoder for generating a plurality of gate output signals according to the plurality of conduction signals, a selection signal and an input signal; and A plurality of level conversion units coupled to the plurality of gate driving units for performing voltage conversion according to the plurality of gate output signals; The channel number signal indicates a primary channel number, and the selection signal indicates at least a secondary channel number. The gate driver of claim 1, wherein the selection signal includes a bit, the at least one minor channel number includes a minor channel number, and the a bits respectively correspond to the a minor channel number. , and a is a positive integer greater than zero. The gate driver as described in claim 2, wherein the a minor channel numbers are respectively the sum of the major channel number and 1...a. The gate driver as claimed in claim 2, wherein, When a b-th bit in the selection signal is a first logic state, a b-th secondary channel corresponding to the b-th bit is in a conductive state; and When the b-th bit in the selection signal is in a second logic state, the b-th secondary channel corresponding to the b-th bit is in a closed state; Among them 1≦b≦a. The gate driver as described in claim 2, wherein the main channel number is n, and the n-th gate driving unit in the plurality of gate driving units includes: a first AND gate, coupled to the channel decoder, for generating an n-th relay signal based on an n-th conduction signal of the plurality of conduction signals and the input signal; a second AND gate, coupled to the first AND gate, used to generate a the nth relay signal to the n+1th...n+ath according to the a bits of the selection signal gate drive units; and An OR gate, coupled to the first AND gate, the a second AND gate and an n-th level conversion unit among the plurality of level conversion units, used for controlling the n-th relay signal and The n-1th...n-ath relay signal generates an n-th gate output signal among the plurality of gate output signals. The gate driver of claim 5, wherein, When the nth conduction signal is in a first logic state, the first AND gate passes the input signal as the nth relay signal, and the OR gate passes the nth relay signal as the nth relay signal. n gate output signals; and when the n-th conduction signal is in a second logic state, the first AND gate does not pass the input signal; When at least one of the a bits of the selection signal is in the first logic state, at least one of the a second AND gates transmits the n-th relay signal to the n+1-th ...the OR gate of at least one of the n+a-th gate driving units; and when at least one of the a bits of the selection signal is in the second logic state, the a second AND gate The nth relay signal is not transmitted. The gate driver as described in claim 2, wherein the main channel number is n, and the n-th gate driving unit in the plurality of gate driving units includes: A first switch, coupled to the channel decoder and an n-th level conversion unit among the plurality of level conversion units, used to determine whether to transmit based on an n-th conduction signal of the plurality of conduction signals. The input signal serves as an n-th gate output signal among the plurality of gate output signals; a second switch, coupled to the first switch, used to determine whether to pass the input signal as an n-th relay signal based on the n-th conduction signal; and a third switch, coupled to the second switch, used to determine whether to transmit the nth relay signal to the n+1th...n+ath gate based on the a bits of the selection signal pole drive unit. The gate driver of claim 7, wherein, When the nth conduction signal turns on the first switch, the first switch transmits the input signal as the nth gate output signal; and when the nth conduction signal turns off the first switch, the first switch The switch does not pass this input signal; When the n-th turn-on signal turns on the second switch, the second switch passes the input signal as the n-th relay signal; and when the n-th turn-off signal turns on the second switch, the second switch Do not pass the input signal; When the a bit turns on the a third switch, the a third switch transmits the n-th relay signal to the n+1-th...n+a-th gate driving unit; and when the a-th gate driving unit The bit turns off the a third switch, and the a third switch does not transmit the n-th relay signal. The gate driver as described in claim 1, which is used for a display, including: a timing controller coupled to the gate driver for generating the channel number signal and the selection signal; and A shift register is coupled to the timing controller and the channel decoder and is used to generate the input signal and the latch signal. The gate driver of claim 9, wherein the plurality of gate driving units are coupled to the timing controller and the shift register through the channel decoder to indirectly receive the selection signal and the input signal; or , the plurality of gate driving units are coupled to the timing controller and the shift register to directly receive the selection signal and the input signal.

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