TW202336948A - 半導體封裝及層疊封裝 - Google Patents

半導體封裝及層疊封裝 Download PDF

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TW202336948A
TW202336948A TW112107735A TW112107735A TW202336948A TW 202336948 A TW202336948 A TW 202336948A TW 112107735 A TW112107735 A TW 112107735A TW 112107735 A TW112107735 A TW 112107735A TW 202336948 A TW202336948 A TW 202336948A
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substrate
semiconductor package
logic die
package
copper core
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TW112107735A
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于達人
林世欽
陳泰宇
楊柏俊
林秉燁
黃永成
許文松
馬伯豪
宋依庭
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聯發科技股份有限公司
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Abstract

本發明公開一種半導體封裝，包括：底部基板和頂部基板，該頂部基板與該底部基板間隔開，使得該底部基板和該頂部基板之間限定出間隙；邏輯晶粒，其中該邏輯晶粒的厚度為125-350微米； 複數個銅芯焊球，圍繞該邏輯晶粒設置於該底部基板與該頂部基板之間，以電性連接該底部基板與該頂部基板；以及密封樹脂，填充於該底部基板與該頂部基板之間的該間隙中，並將該邏輯晶粒與該複數個銅芯焊球密封於該間隙中。

Description

半導體封裝及層疊封裝
本發明涉及半導體技術領域，尤其涉及一種半導體封裝及層疊封裝。
層疊封裝 (Package-on-Package ，PoP) 是一種將垂直分立邏輯和記憶體球柵陣列 (ball grid array ，BGA) 封裝相結合的積體電路封裝方法。 兩個或複數個封裝安裝在彼此之上，即堆疊，並使用標準介面（standard interface）在它們之間路由訊號。 這允許在裝置（例如行動電話或數碼相機）中實現更高的組件密度。
PoP 解決方案通常用於手機中的基帶和應用處理器。 高端手機最快採用 PoP 封裝來滿足高 I/O （輸入/輸出，input/output）和性能要求。 堆疊（或層疊）PoP 的主要優點是裝置可以在組裝前單獨進行全面測試。
隨著半導體工業的發展，人們進行了許多研究以提高半導體封裝的可靠性和耐久性。改進 PoP 結構以提高散熱效率、應用處理器 (application processor ，AP) 性能和互連數量變得非常重要和勢在必行。
有鑑於此，本發明提供一種半導體封裝及層疊封裝，具有厚的邏輯晶粒以增強散熱性能，以解決上述問題。
根據本發明的第一方面，公開一種半導體封裝，包括：
底部基板和頂部基板，該頂部基板與該底部基板間隔開，使得該底部基板和該頂部基板之間限定出間隙；
邏輯晶粒，安裝在該底部基板的上表面上，其中該邏輯晶粒的厚度為125-350微米；
複數個銅芯焊球，圍繞該邏輯晶粒設置於該底部基板與該頂部基板之間，以電性連接該底部基板與該頂部基板；以及
密封樹脂，填充於該底部基板與該頂部基板之間的該間隙中，並將該邏輯晶粒與該複數個銅芯焊球密封於該間隙中。
根據本發明的第二方面，公開一種層疊封裝，包括：
如上所述的半導體封裝；以及
安裝在該半導體封裝上的記憶體封裝。
本發明的半導體封裝由於包括：底部基板和頂部基板，該頂部基板與該底部基板間隔開，使得該底部基板和該頂部基板之間限定出間隙；邏輯晶粒，安裝在該底部基板的上表面上，其中該邏輯晶粒的厚度為125-350微米； 複數個銅芯焊球，圍繞該邏輯晶粒設置於該底部基板與該頂部基板之間，以電性連接該底部基板與該頂部基板；以及密封樹脂，填充於該底部基板與該頂部基板之間的該間隙中，並將該邏輯晶粒與該複數個銅芯焊球密封於該間隙中。本發明中，由於邏輯晶粒的厚度較厚，使得邏輯晶粒的體積大幅增加，因此本發明中的晶粒的儲熱能力將大幅提升，這樣邏輯晶粒在運行過程中的升溫將會變得緩慢，可以讓邏輯晶粒在更長的時間內位於較低的溫度區間內運行，保證邏輯晶粒或半導體封裝的正常工作。因此本發明的上述方案將增強邏輯晶粒和半導體封裝的散熱性能，並且提高應用處理器的性能。
在下面對本發明的實施例的詳細描述中，參考了附圖，這些附圖構成了本發明的一部分，並且在附圖中透過圖示的方式示出了可以實踐本發明的特定的優選實施例。對這些實施例進行了足夠詳細的描述，以使所屬技術領域具有通常知識者能夠實踐它們，並且應當理解，在不脫離本發明的精神和範圍的情況下，可以利用其他實施例，並且可以進行機械，結構和程式上的改變。本發明。因此，以下詳細描述不應被理解為限制性的，並且本發明的實施例的範圍僅由所附申請專利範圍限定。
將理解的是，儘管術語“第一”、“第二”、“第三”、“主要”、“次要”等在本文中可用於描述各種元件、元件、區域、層和/或部分，但是這些元件、元件、區域、這些層和/或部分不應受到這些術語的限制。這些術語僅用於區分一個元件、元件、區域、層或部分與另一區域、層或部分。因此，在不脫離本發明構思的教導的情況下，下面討論的第一或主要元件、元件、區域、層或部分可以稱為第二或次要元件、元件、區域、層或部分。
此外，為了便於描述，本文中可以使用諸如“在...下方”、“在...之下”、“在...下”、“在...上方”、“在...之上”之類的空間相對術語，以便於描述一個元件或特徵與之的關係。如圖所示的另一元件或特徵。除了在圖中描述的方位之外，空間相對術語還意圖涵蓋裝置在使用或運行中的不同方位。該裝置可以以其他方式定向（旋轉90度或以其他定向），並且在此使用的空間相對描述語可以同樣地被相應地解釋。另外，還將理解的是，當“層”被稱為在兩層“之間”時，它可以是兩層之間的唯一層，或者也可以存在一個或複數個中間層。
術語“大約”、“大致”和“約”通常表示規定值的±20％、或所述規定值的±10％、或所述規定值的±5％、或所述規定值的±3％、或規定值的±2％、或規定值的±1％、或規定值的±0.5％的範圍內。本發明的規定值是近似值。當沒有具體描述時，所述規定值包括“大約”、“大致”和“約”的含義。本文所使用的術語僅出於描述特定實施例的目的，並不旨在限制本發明。如本文所使用的，單數術語“一”，“一個”和“該”也旨在包括複數形式，除非上下文另外明確指出。本文所使用的術語僅出於描述特定實施例的目的，並不旨在限制本發明構思。如本文所使用的，單數形式“一個”、“一種”和“該”也旨在包括複數形式，除非上下文另外明確指出。
將理解的是，當將“元件”或“層”稱為在另一元件或層“上”、“連接至”、“耦接至”或“鄰近”時，它可以直接在其他元件或層上、與其連接、耦接或相鄰、或者可以存在中間元件或層。相反，當元件稱為“直接在”另一元件或層“上”、“直接連接至”、“直接耦接至”或“緊鄰”另一元件或層時，則不存在中間元件或層。
注意：（i）在整個附圖中相同的特徵將由相同的附圖標記表示，並且不一定在它們出現的每個附圖中都進行詳細描述，並且（ii）一系列附圖可能顯示單個專案的不同方面，每個方面都與各種參考標籤相關聯，這些參考標籤可能會出現在整個序列中，或者可能只出現在序列的選定圖中。
圖1是示出根據本發明實施例的具有厚邏輯晶粒的示例性半導體封裝的示意性橫截面圖。 如圖1所示，半導體封裝10包括底部基板100，底部基板100具有上表面100a和相對的底表面100b。根據一個實施例，底部基板100可以是具有複數個導電互連結構110和至少一個絕緣層112的印刷線路板或封裝基板。根據一個實施例，例如，導電互連結構110可以包括複數個焊盤圖案（pad pattern）110a分佈於上表面100a，以及包括複數個焊盤圖案110b分佈於底表面100b。
根據一個實施例，邏輯晶粒50以倒裝晶片（flip-chip）方式安裝在底部基板100的上表面100a上。根據一個實施例，例如，邏輯晶粒50可以是應用處理器晶粒或基帶處理器晶粒，但不限於此。 根據一個實施例，例如，邏輯晶粒50的厚度t介於125-350微米之間（大於等於125微米並小於等於350微米），例如170微米，比用於高端行動裝置（比如高端手機）的普通邏輯晶粒(約80μm厚)更厚。因此，本發明實施例中的邏輯晶粒50的厚度比先前技術中的邏輯晶粒的厚度更厚，本發明實施例中的邏輯晶粒50也可以稱為厚的晶粒（厚的邏輯晶粒），或厚晶粒（厚的晶粒）。本發明實施例中，邏輯晶粒50的厚度t可以大於等於90微米，當然還是小於等於350微米。本發明實施例中，由於晶粒（邏輯晶粒）的厚度較厚（大於通常晶粒的厚度），使得晶粒的體積大幅增加，因此本發明實施例中的晶粒（例如邏輯晶粒50）的儲熱能力將大幅提升，這樣晶粒在運行過程中的升溫將會變得緩慢，可以讓晶粒在更長的時間內位於較低的溫度區間內運行，保證晶粒或半導體封裝的正常工作。因此本發明的上述方案將增強晶粒和半導體封裝的散熱性能，並且提高應用處理器 (application processor，AP) 的性能。
根據一個實施例，例如，邏輯晶粒50具有有源正表面50a和無源背表面50b。 根據一個實施例，例如，複數個輸入/輸出（input/output，I/O）焊盤501設置在有源正表面50a上。根據一個實施例，例如，邏輯晶粒50透過分別形成在複數個I/O焊盤501上的複數個導電元件502(例如焊料凸塊、金屬凸塊或柱)電連接至底部基板100。根據一個實施例，底部填充樹脂510可以被注入邏輯晶粒50和底部基板100的上表面100a之間的空間。根據一個實施例，導電元件502被底部填充樹脂510包圍。
根據一個實施例，邏輯晶粒50設置在底部基板100和頂部基板300之間。根據一個實施例，頂部基板300可以是具有複數個導電互連結構310和至少一個絕緣層312的印刷線路板或封裝基板。根據一個實施例，例如，導電互連結構310可以包括分佈在上表面300a上的複數個焊盤圖案（或焊盤、焊盤區域）310a和分佈在底表面300b上的複數個焊盤圖案（或焊盤、焊盤區域）310b。根據一個實施例，複數個銅芯焊球（copper cored solder ball）60或其他更具延展性的金屬連接件分別設置在分佈於頂部基板300的底表面300b上的焊盤圖案310b上。
根據一個實施例，底部基板100透過邏輯晶粒50周圍的銅芯焊球60與頂部基板300電連接。密封樹脂SM填充在底部基板100與頂部基板300之間的間隙高度h中。根據一個實施例，例如，在0.2-0.3mm的焊球間距範圍內，間隙高度h可以在160-450微米之間，但不限於此。在一個實施例中，例如，附著有銅芯焊球60的焊盤圖案110a的寬度w介於100-300微米之間，但不限於此。 根據一個實施例，例如，銅芯焊球60的縱橫比可以在1.1-2.0之間，例如1.44；其中，縱橫比可以是指高度與寬度之比，例如銅芯焊球60的高度與銅芯焊球60的寬度之比，其中銅芯焊球60的寬度可以是銅芯焊球60投影到上表面100a之後的寬度。在本發明一個實施例中，銅芯焊球60的縱橫比可以在1.2-1.5之間，以便於適用於不同厚度的晶粒（例如邏輯晶粒50）。根據一個實施例，例如，銅芯焊球60的球距P可以為0.2-0.3mm，以可以佈局更多數量的底部基板100與頂部基板300之間的電性連接結構。球距P可以是從一個銅芯焊球60的中心到相鄰的另一個銅芯焊球60的中心的距離。本發明實施例中，由於晶粒（例如邏輯晶粒50）的厚度增加，需要對底部基板100與頂部基板300的電性連接結構進行重新的設計。在本發明一個實施例中，採用了上述銅芯焊球60的電性連接結構，以適用於高度較高的晶粒（例如邏輯晶粒50）。本發明銅芯焊球60具有銅芯602和焊料層604，相比先前的連接結構具有更強的機械強度，從而加強支撐強度以及保證電性連接可靠性。
根據一個實施例，密封樹脂（sealing resin）SM圍繞銅芯焊球60並覆蓋邏輯晶粒50的無源背表面50b和側壁。根據一個實施例，密封樹脂SM與頂部基板300的底表面300b、底部填充樹脂510的側表面和底部基板100的上表面100a直接接觸。底部基板100和頂部基板300之間的間隙用密封樹脂SM密封。 邏輯晶粒50的無源背表面50b與頂部基板300的底表面300b之間的距離d可以等於或大於30微米。
根據一個實施例，每個銅芯焊球60可以包括直徑約10微米的銅芯602，銅芯602上覆蓋有焊料層604。銅芯焊球60連接底部基板100和頂部基板300。根據一個實施例，例如，銅芯602由銅或銅合金形成並且成形為實心球體。 根據一個實施例，例如，具有銅芯焊球60的頂部基板300可以透過熱壓接合(thermal compression bonding ，TCB) 方法安裝到底部基板100的上表面100a上。
根據一個實施例，諸如焊球或BGA球的外部連接端子120接合至底部基板100的底表面100b上的焊盤圖案110b，以進一步與主機板（mother board）或系統板連接。 根據一個實施例，諸如電容器或電阻器的表面安裝器件130可以安裝在底部基板100的底表面100b上。
圖2是示出根據本發明的實施例的具有厚邏輯晶粒的示例性堆疊（或層疊）封裝(PoP)的示意性橫截面圖，其中相似的層、區域或元件由相似的數字編號或標籤指定。 如圖2所示，諸如高頻寬PoP(HBPoP)的PoP裝置1可以包括如圖1所示的半導體封裝10和堆疊在半導體封裝10上的諸如LPDDR（Low Power Double Data Rate，低功耗雙倍資料速率） DRAM（Dynamic Random Access Memory，動態隨機存取記憶體）封裝的記憶體封裝20。根據一個實施例，例如，記憶體封裝20可以包括基板200、安裝在基板200上的記憶體晶粒210和封裝記憶體晶粒210的模塑料220。根據一個實施例，例如，記憶體封裝20可以透過諸如焊球或凸塊的複數個導電元件230電連接到半導體封裝10。在疊層（或層疊）封裝中，由於零部件密度更高，並且採用堆疊結構，因此在本領域的傳統做法中將會把裝置做的更薄，例如將晶粒的厚度做的更薄，以方便散熱並且適用於小型化應用。而本發明實施例的上述方案中，將晶粒（邏輯晶粒）的厚度做的更厚，顯然與本領域的傳統做法不同，例如本發明實施例中將晶粒（邏輯晶粒）設計為125-350微米，因此本發明的發明人打破常規思維，創造性的增厚晶粒厚度（提高晶粒厚度），在不明顯影響半導體封裝的高度或尺寸的情況下，顯著的提高晶粒或半導體封裝的熱性能。
儘管已經對本發明實施例及其優點進行了詳細說明，但應當理解的是，在不脫離本發明的精神以及申請專利範圍所定義的範圍內，可以對本發明進行各種改變、替換和變更。所描述的實施例在所有方面僅用於說明的目的而並非用於限制本發明。本發明的保護範圍當視所附的申請專利範圍所界定者為准。本領域技術人員皆在不脫離本發明之精神以及範圍內做些許更動與潤飾。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
10:半導體封裝 20:記憶體封裝 50:邏輯晶粒 50a:有源正表面 50b:無源背表面 60:銅芯焊球 100:底部基板 110,310:導電互連結構 110a ,110b, 310a,310b:焊盤圖案 100a,300a:上表面 100b, 300b:底表面 112,312:絕緣層 120:外部連接端子 130:表面安裝器件 200:基板 210:記憶體晶粒 220:模塑料 300:頂部基板 501:I/O焊盤 230,502:導電元件 510:底部填充樹脂 602:銅芯 604:焊料層
透過閱讀後續的詳細描述和實施例可以更全面地理解本發明，本實施例參照附圖給出，其中： 圖1是示出根據本發明實施例的具有厚邏輯晶粒的示例性半導體封裝的示意性橫截面圖； 以及 圖2是示出根據本發明實施例的具有厚邏輯晶粒的示例性堆疊（層疊）封裝(PoP)的示意性橫截面圖。
10:半導體封裝
50:邏輯晶粒
50a:有源正表面
50b:無源背表面
60:銅芯焊球
100:底部基板
110,310:導電互連結構
110a,110b,310a,310b:焊盤圖案
100a,300a:上表面
100b,300b:底表面
112,312:絕緣層
120:外部連接端子
130:表面安裝器件
300:頂部基板
501:I/O焊盤
502:導電元件
510:底部填充樹脂
602:銅芯
604:焊料層

Claims (13)

  1. 一種半導體封裝，包括： 底部基板和頂部基板，該頂部基板與該底部基板間隔開，使得該底部基板和該頂部基板之間限定出間隙； 邏輯晶粒，安裝在該底部基板的上表面上，其中該邏輯晶粒的厚度為125-350微米； 複數個銅芯焊球，圍繞該邏輯晶粒設置於該底部基板與該頂部基板之間，以電性連接該底部基板與該頂部基板；以及 密封樹脂，填充於該底部基板與該頂部基板之間的該間隙中，並將該邏輯晶粒與該複數個銅芯焊球密封於該間隙中。
  2. 如請求項1之半導體封裝，其中，該邏輯晶粒以倒裝晶片的方式安裝在該底部基板的該上表面上。
  3. 如請求項2之半導體封裝，其中，該邏輯晶粒包括有源正表面和無源背表面，該有源正表面上設置有複數個輸入/輸出焊盤。
  4. 如請求項3之半導體封裝，其中，該邏輯晶粒透過分別形成在該複數個I/O焊盤上的複數個導電元件電連接到該底部基板。
  5. 如請求項4之半導體封裝，其中，該邏輯晶粒與該底部基板的上表面之間設置有底部填充樹脂，該底部填充樹脂圍繞該複數個導電元件。
  6. 如請求項1之半導體封裝，其中，該底部基板和該頂部基板為印刷線路板或封裝基板。
  7. 如請求項1之半導體封裝，其中，該間隙的間隙高度範圍為160-450微米。
  8. 如請求項1之半導體封裝體，其中，該複數個銅芯焊球的縱橫比介於1.1-2.0之間。
  9. 如請求項1之半導體封裝，其中，該複數個銅芯焊球的球距為0.2-0.3mm。
  10. 如請求項1之半導體封裝體，其中，該複數個銅芯焊球中的每一個包括鍍有焊料層的銅芯。
  11. 如請求項1之半導體封裝，其中，外部連接端子設置在該底部基板的底表面上。
  12. 一種層疊封裝，包括： 如請求項1至11任意一項之半導體封裝；以及 安裝在該半導體封裝上的記憶體封裝。
  13. 如請求項12之層疊封裝，其中該記憶體封裝包括LPDDR DRAM封裝。
TW112107735A 2022-03-03 2023-03-03 半導體封裝及層疊封裝 TW202336948A (zh)

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