TW202335097A - 積體電路裝置的製造方法 - Google Patents

積體電路裝置的製造方法 Download PDF

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TW202335097A
TW202335097A TW111115091A TW111115091A TW202335097A TW 202335097 A TW202335097 A TW 202335097A TW 111115091 A TW111115091 A TW 111115091A TW 111115091 A TW111115091 A TW 111115091A TW 202335097 A TW202335097 A TW 202335097A
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Taiwan
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layer
metal
thin film
dielectric layer
film transistor
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TW111115091A
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English (en)
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邱日照
劉致為
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台灣積體電路製造股份有限公司
國立臺灣大學
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Publication of TW202335097A publication Critical patent/TW202335097A/zh

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Abstract

提供一種積體電路裝置的製造方法，該方法包含在半導體基板上形成一個場效電晶體；在場效電晶體上沉積一第一介電層；在第一介電層上沉積一第一含金屬介電層；以及在第一含金屬介電層上形成第一薄膜電晶體。

Description

積體電路裝置及其製造方法
由於各式電子組件（例如電晶體、二極體、電阻、電容等）整合密度的不斷提升，半導體產業歷經快速成長。整合密度的提升來自於將更多的電子組件（例如電晶體、二極體、電阻、電容等）整合在一個給定的面積內。
以下之揭露將提供多個不同的實施方式或實施例以實現所提供之專利標的之不同特徵。各個組件與安排將以特定實施例在以下說明，以簡化本揭露。當然這些實施例僅用於示例而非意旨於限制本揭露。舉例而言，敘述中之「第一特徵形成於第二特徵上」包含多種實施方式，其中涵蓋第一特徵與第二特徵直接接觸，亦涵蓋額外的特徵形成於第一特徵與第二特徵之間而使兩者不直接接觸。此外，於各式各樣的實施例中，本揭露可能會重複標號以及/或標示。此重複是為了簡化並清楚說明，而非意圖表明該處所討論的各種實施方式以及/或配置之間的關係。
更甚者，空間相對的詞彙，例如「下層的」、「低於」、「下方」、「高於」、「上方」等相關詞彙，於此用以簡單描述如圖所示之元件或特徵與另一元件或特徵的關係。這些空間相對的詞彙除了圖中所描繪的轉向之外，也涵蓋在使用或操作裝置時的不同的轉向。此外，當裝置可旋轉（旋轉90度或其他角度）時，在此使用之空間相對的描述語也可作對應的解讀。
為使得更多的組件能整合在一給定的面積內，而發展了各式各樣的堆疊技術。其中一種堆疊技術是電晶體堆疊，此堆疊技術將電晶體垂直堆疊，從而增加裝置密度。在部分實施例中，由於互補金屬氧化物半導體（complementary metal-oxide semiconductor；CMOS）裝置在磊晶上的困難，以及薄膜電晶體（thin film transistors；TFT）的低製程溫度，堆疊薄膜電晶體比堆疊互補金屬氧化物半導體裝置更容易。由於薄膜電晶體的半導體薄膜對氫以及/或濕氣敏感，堆疊式薄膜電晶體的閾值電壓（V T）可能不穩定。另一種堆疊技術是小晶片（chiplet）堆疊，將具有不同技術和應用的晶粒/晶片垂直堆疊，從而節省面積並降低能耗。
在本實施例部分實施例中，防潮隔離層設置於堆疊層之間，從而避免氫以及/或濕氣擴散至堆疊的薄膜電晶體，這會提高堆疊的薄膜電晶體的閾值電壓穩定性。防潮隔離層可包括陶瓷，其可以是含金屬的複合材料，例如氧化鋁（Al 2O 3）、氧化鋯（Zr 2O 3）、氧化鈦（TiO 2）、類似物或其組合。在本實施例的部分實施例中，防潮隔離層可設置在兩個堆疊的晶粒/晶片之間。在本揭露進一步的部分實施例中，防潮封裝層可用於封裝晶粒/晶片或堆疊的晶粒/晶片，從而避免氫以及/或濕氣擴散。
圖1A為根據本揭露部分實施例之積體電路裝置100A的示範剖視圖。積體電路裝置100A包含基板102和在基板102上方的後段（back-end-of-line；BEOL）內連接結構120。在部分實施例中，基板102可透過前段（front-end-of-line；FEOL）製程處理，並在上方形成採用實質單晶通道材料（例如矽）之裝置（例如互補金屬氧化物半導體場效電晶體）。後段內連接結構120可包含透過後段製程形成在基板102上方的多個薄膜電晶體基底內連接結構（或內連接層）122、124和126。在本實施例中，積體電路裝置100A包含位於基板102與薄膜電晶體基底內連接結構122之間的隔離層121、位於薄膜電晶體基底內連接結構122和124之間的隔離層123，以及位於薄膜電晶體基底內連接結構124和126之間的隔離層125。隔離層121、123和125可由提供化學以及電性隔離的合適材料製成。在部分實施例中，隔離層121、123和125可包括陶瓷。舉例而言，隔離層121、123和125可包括含金屬的化合物材料，例如氧化鋁（Al 2O 3）、氧化鋯（Zr 2O 3）、氧化鈦（TiO 2）、其他金屬氧化物、相似物或其組合。這些材料可具有比SiN x更低的水氣穿透率，進而實現化學隔離。舉例而言，隔離層121、123和125可作為氫擴散阻障。這些材料由於能隙大而也可以具有較小的漏電流，進而實現電性隔離。導電通孔V1至V3可分別延伸通過隔離層121、123和125，以在基板102和薄膜電晶體基底內連接結構122、124和126之間建立電性連接。導電通孔V1至V3可包含一個或多個阻障/附著層MB以及一個或多個被阻障/附著層MB包圍的導電材料FM。
圖1B為一示範剖視圖，表示圖1A的積體電路裝置100A之配置。在基板102上方形成一個或多個主動以及/或被動裝置104，在主動以及/或被動裝置104上形成前段層間介電質（interlayer dielectric；ILD）層110，並且在層間介電質層110中形成接觸插栓112，以連接主動以及/或被動裝置104。內連接結構120電性內連接一個或多個主動以及/或被動裝置104，以形成功能性電路。在本實施例中，內連接結構120的每一個薄膜電晶體基底內連接結構122、124和126包含一個或多個金屬化層。舉例而言，每一個薄膜電晶體基底內連接結構122、124和126可包含一個或多個介電層DI和介電層DI中的金屬化圖案MP。在部分實施例中，介電層DI可包含未摻雜的矽酸鹽玻璃（silicate glass；USG）、低k介電材料、極低k介電材料、SiO 2或其他合適的材料。介電層DI可稱為金屬間介電質（inter-metal dielectric；IMD）或層間介電質。金屬化圖案MP可包含一個或多個水平內連接以及垂直內連接，水平內連接例如導電線CL，分別在介電層DI中水平或橫向延伸，垂直內連接例如導電通孔CV，分別在介電層DI中垂直延伸。金屬化圖案MP的內連接（例如導電線CL和導電通孔CV)可由合適的導電材料製成，例如銅。在部分實施例中，金屬化圖案MP的導電通孔CV的部分可以延伸通過隔離層121、123和125，並且作為圖1A中隔離層121、123和125中的導電通孔V1至V3。
以圖1B中的單一電晶體來說明一個或多個主動以及/或被動裝置104。舉例而言，裝置104可包含閘極結構104 G和源極/汲極區104 SD，位於淺溝槽隔離（shallow trench isolation；STI）區105所環繞區域的上方。閘極結構104 G可包含閘極介電質104 GD和位於閘極介電質104 GD上方的閘極電極104 GM。間隔物104 SP可在閘極結構104 G的相對兩側上形成。在部分實施例中，源極/汲極區104 SD可以是在基板102中形成的摻雜區。在部分替代實施例中，源極/汲極區104 SD可以是在基板102上方形成的磊晶結構。一個或多個主動以及/或被動裝置104可包含各種N型金屬氧化物半導體（N-type metal-oxide semiconductor；NMOS）以及/或P型金屬氧化物半導體（P-type metal-oxide semiconductor；PMOS）裝置，例如電晶體、電容、電阻、二極體、光二極體、保險絲及類似物。應理解上述示例僅出於說明之目的而提供，並非意旨於以任何方式限制本揭露。在給定適合的應用情況下，亦可以形成其他電路。
接觸插栓112將上層內連接結構120電性耦合至下層裝置104。在圖1B的示例中，接觸插栓112建立了連接至鰭式場效電晶體（Fin Field-Effect Transistor；FinFET）裝置104的閘極結構104 G和源極/汲極區 104 SD的電性連接。
在本實施例中，薄膜電晶體基底內連接結構122、124和126可分別包含裝置122T、124T，和126T。裝置122T、124T，和126T包含薄膜電晶體。在部分實施例中，裝置可進一步包含非揮發性記憶體裝置（例如自旋轉移力矩式磁性隨機存取記憶體（spin-transfer-torque magnetoresistive random access memory；STT-MRAM））、揮發性記憶體裝置（例如嵌入式動態隨機存取記憶體（embedded dynamic random access memory；eDRAM））、類似物或其組合。在本揭露部分實施例中，裝置122T、124T和126T以薄膜電晶體來說明，並稱為薄膜電晶體，每一個薄膜電晶體可包含半導體層SL以及位在半導體層SL上的閘極結構GS。薄膜電晶體是一種場效電晶體，其通道材料（例如半導體層SL）為沉積薄膜而非單晶材料。薄膜電晶體的通道材料（例如半導體層SL）可使用各式半導體材料製成，例如矽、鍺、矽鍺、二維材料（MoS 2、石墨烯等）、多晶矽基薄膜電晶體以及各種氧化物半導體（亦稱為半導體氧化物），氧化物半導體包括如銦鎵鋅氧化物 （indium gallium zinc oxide；IGZO）等金屬氧化物。閘極結構GS可包含在半導體層SL上方的閘極介電質GI和在閘極介電質GI上方的閘極電極GE。半導體層SL可包含在閘極結構GS下方的通道區CR以及在通道區CR的相對兩側的源極/汲極區SDR。金屬化圖案MP（例如導電線CL和導電通路CV）可建立連接至半導體裝置104和薄膜電晶體 122T、124T和126T的電性連接。
在沒有隔離層121、123和125的情況下，可使用氧化矽層以及/和氮化矽層介入層間介電質層110和薄膜電晶體基底內連接結構122之間，並且可使用氧化矽層以及/或氮化矽層介入兩相鄰的薄膜電晶體基底內連接結構122、124和126之間。可使用含氫前驅物（例如矽烷SiH 4）形成氮化矽，舉例而言，透過電漿增強化學氣相沉積（plasma-enhance chemical vapor deposition；PECVD）製程，含氫前驅物作為大量的氫來源。氧化矽具有大的擴散長度，讓氫擴散。因此氧化矽層以及/或氮化矽層可能讓氫由介電層DI（SiO x）擴散至薄膜電晶體的通道區（例如銦鎵鋅氧化物）。氫擴散可能會減少有效通道的長度，並導致薄膜電晶體的閾值電壓（V T）發生變化。舉例而言，積體電路裝置的薄膜電晶體的閾值電壓（V T）可能會負向或正向偏移，導致積體電路裝置的閾值電壓不穩定。這可能會增強短通道效應，並且降低可擴縮性（scalability）。
在本揭露部分實施例中，藉由合適的沉積製程形成隔離層121、123和125，該沉積製程使用少量含氫前驅物或不使用含氫前驅物，因此形成之隔離層121、123和125具有比氮化矽層更低的氫濃度。舉例而言，可藉由物理氣相沉積（physical vapor deposition process；PVD）（例如射頻濺鍍（radio frequency sputter；RF sputter）沉積）製程、原子層沉積（atomic layer deposition；ALD）製程、電漿增強化學氣相沉積製程、其他合適的沉積製程或其組合，形成隔離層121、123和125。因此，隔離層121、123和125可能無法像氮化矽層一樣作為大量氫來源。在部分示例中，藉由原子層沉積形成的隔離層121、123和125可具有介於大約1%至大約2%的範圍內的氫濃度，且藉由電漿增強化學氣相沉積形成的氮化矽層可具有介於大約10%至大約20%範圍內的氫濃度。在部分示例中，藉由物理氣相沉積製程（例如濺鍍沉積）形成的隔離層121、123和125可具有小於1%的氫濃度。透過該配置，減少至薄膜電晶體122T至126T的通道區CR的氫擴散，進而提升堆疊式薄膜電晶體的閾值電壓（V T）的穩定性。
圖2A為根據本揭露部分實施例之積體電路裝置100B的示範剖視圖。圖2B為一示範剖視圖，表示圖2A的積體電路裝置100B之配置。本實施例的細節與圖1A和圖1B的細節相似。與圖1A和圖1B不同的是，積體電路裝置100B更包含封裝層130，封裝層130封裝基板102和後段內連接結構120，從而減緩濕氣從環境（側面隔離）擴散至薄膜電晶體122T、124T和126T中。
封裝層130可由提供化學以及電性隔離的合適材料製成。在部分實施例中，封裝層130可包括陶瓷。舉例而言，封裝層130可由含金屬的化合物材料製成，例如氧化鋁（Al 2O 3）、氧化鋯（Zr 2O 3）、氧化鈦（TiO 2）、相似物或其組合。這些材料可具有比SiN x更低的水氣穿透率，進而實現化學隔離。舉例而言，封裝層130可作為氫擴散阻障。這些材料也由於能隙大而可具有較小的漏電流，進而實現電性隔離。在部分實施例中，隔離層121、123和125以及封裝層130可以包括相同的材料，例如氧化鋁。在部分其他實施例中，隔離層121、123和125以及封裝層130中的至少兩項可包括不同的材料。在部分替代實施例中，當封裝層130封裝基板102和後段內連接結構120時，可省略部分或全部的隔離層121、123和125。
在本揭露部分實施例中，藉由合適的沉積製程形成封裝層130，該沉積製程使用少量含氫前驅物或不使用含氫前驅物，因此，形成之封裝層130具有比氮化矽層更低的氫濃度。舉例而言，可藉由物理氣相沉積（例如射頻濺鍍沉積）製程、原子層沉積製程、電漿增強化學氣相沉積製程、其他合適的沉積製程或其組合，形成封裝層130。因此，封裝層130可能無法像氮化矽層一樣作為大量氫源。在部分示例中，藉由原子層沉積形成的封裝層130可具有介於大約1%至大約2%的範圍內的氫濃度，且藉由電漿增強化學氣相沉積形成的氮化矽層可具有介於大約10%至大約20%範圍內的氫濃度。在部分示例中，藉由濺鍍沉積形成的封裝層130可具有小於1%的氫濃度。透過該配置，減少至薄膜電晶體122T至126T的通道區CR的氫擴散，進而提升堆疊式薄膜電晶體的閾值電壓（V T）的穩定性。
圖3為根據本揭露部分實施例之積體電路裝置100C的示範剖視圖。本實施例的細節與圖1A和圖1B的細節相似。與圖1A和圖1B不同的是，積體電路裝置100C包含多個以小晶片堆疊垂直堆疊的晶片100A1至100A3、設置於晶片100A1至100A3之相鄰兩者之間的隔離層142和144以及用來封裝晶片100A1至100A3的封裝層130’。隔離層142和144可以減緩晶片之間的濕氣擴散，且封裝層130’可以減緩濕氣從環境（側面隔離）擴散到晶片100A1至100A3中的薄膜電晶體122T、124T和126T中。
積體電路裝置100C可包含晶片100A1至100A3。每一個晶片100A1至100A3可包含基板和位於基板上的內連接結構，作為積體電路裝置100A的配置。晶片100A1至100A3可具有不同的功能，例如輸入/輸出（I/O）介面、記憶體、處理器、相似物或其組合。舉例而言，在部分實施例中，晶片100A1至100A3分別為輸入/輸出晶片、微處理器核心晶片和記憶體晶片。
隔離層142和144以及封裝層130’可由提供化學以及電性隔離的合適材料製成。隔離層142和144的細節與隔離層121、123和125的細節可相似（參考圖1A至圖2B），故不在此重複敘述。在部分實施例中，裝置100A的配置如圖1A所示，部分或全部的晶片 100A1至100A3可包含設置在兩相鄰內連接結構/層之間的隔離層121、123和125。
在部分實施例中，將導電連接器BP1設置在晶片100A1至100A3之相鄰兩者之間，延伸通過隔離層142和144，以提供兩相鄰晶片之間之電性連接。導電連接器BP可包括導電材料，如焊錫、銅、鋁、金、鎳、銀、鈀、錫、類似物或其組合。在部分實施例中，可在晶片100A1與晶片100A2相對的一側上，設置錫球BP2。可透過蒸鍍、電鍍、印刷、焊錫轉移、植球（ball placement）、類似方法，形成錫球BP2。
可以在晶片100A1至100A3周圍形成封裝層130’。封裝層130’可由提供化學以及電性隔離的合適材料製成。隔離層142和144的細節與隔離層121、123和125的細節可相似（參考圖1A至圖2B），故不在此重複敘述。在部分實施例中，隔離層121、123和125以及封裝層130’可包括相同的材料。在部分其他實施例中，隔離層121、123和125以及封裝層130中的至少兩項可包括不同的材料。本實施例之其他細節與前述相似，故不在此重複敘述。
圖4至圖15說明根據本揭露部分實施例，製造積體電路裝置之方法的各個中間階段。應理解到，可以在圖4至圖15所示的操作之前、期間和之後提供額外的操作，並且對該方法的額外實施例，以下描述的部分操作可以被替換或刪除。其操作/製程的順序可以互換。
參照圖4所示，在部分實施例中，提供基板102。基板102可包括實質單晶材料，例如塊矽。在部分實施例中，基板102可包含另一種元素半導體，例如鍺；一種化合物半導體，包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦和/或銻化銦；一種合金半導體，包括矽鍺、磷化砷鎵、砷化銦鋁、砷化鎵鋁、砷化銦鎵、磷化銦鎵以及/或磷砷化鎵銦；或其組合。在部分實施例中，基板102包括絕緣體上半導體（semiconductor -on-insulator；SOI）基板的主動層。絕緣體上半導體基板包含在絕緣層上形成的半導體材料層，例如矽。絕緣層可為例如掩埋氧化物（buried oxide；BOX）層或氧化矽層。在基板例如矽或玻璃基板上設置絕緣層。亦可使用其他基板，例如多層或梯度基板。為了清楚說明，將基板102描繪為包含多個晶片區CH1以及圍繞晶片區CH1的切割路徑區SR。在部分實施例中，切割路徑區SR可包含切割道區或切割區。
在部分實施例中，在基板102的晶片區CH1上形成一個或多個主動以及/或被動裝置104。在所描繪之實施例中，裝置104為鰭式場效電晶體，鰭式場效電晶體是在半導體突起的鰭狀條中形成的三維金屬氧化物半導體場效電晶體（Metal Oxide Semiconductor Field Effect Transistor；MOSFET）結構，該鰭狀條又稱為鰭片103。圖4中所示的剖面是沿著鰭片103的縱軸，在與源極/汲極區104 SD間的電流方向平行的方向上所擷取。可以藉由光刻微影和蝕刻技術，圖案化基板102以形成鰭片103。舉例而言，可採用間隔圖像轉移（spacer image transfer；SIT）圖案化技術。在該方法中，在基板上方形成犧牲層，並使用合適的光刻微影和蝕刻製程圖案化，以形成心軸。使用自對準製程在心軸旁邊形成間隔物。接著透過適當的選擇性蝕刻製程去除犧牲層。然後，可將每個剩餘的間隔物作為硬遮罩，以藉由例如反應離子蝕刻（reactive ion etching；RIE）將溝槽蝕刻至基板102中，來圖案化對應的鰭片103。圖4僅繪示了單一鰭片103，但基板102可包含任意數量的鰭片。在部分其他實施例中，裝置104可為平面電晶體或閘極環繞（gate-all-around；GAA)電晶體。閘極環繞電晶體可以藉由通道堆疊技術製造，且堆疊奈米片（nanosheet；NS）可以在固定的元件面積下增強電流（I on）。
如圖4所示，在鰭片103的相對兩側形成的淺溝槽隔離區105。可藉由沉積一種或多種介電材料（例如氧化矽）完全填充鰭周圍的溝槽，而後使介電材料的頂表面凹陷以形成淺溝槽隔離區105。可使用高密度電漿化學氣相沉積（high density plasma chemical vapor deposition；HDP-CVD）、低壓化學氣相沉積（low-pressure chemical vapor deposition；LPCVD）、次常壓（sub-atmospheric chemical vapor deposition；SACVD）、可流動式化學氣相沉積（flowable chemical vapor deposition；FCVD）、旋轉塗佈、以及/或相似物或其組合，來沉積淺溝槽隔離區105的介電材料。在沉積之後，可以執行退火製程或固化製程。在部分情況下，淺溝槽隔離區105可包含襯層，例如藉由氧化矽表面而生長的熱氧化物襯層。凹槽製程可使用如平坦化製程（例如化學機械拋光（chemical mechanical polish；CMP）），接著採用選擇性蝕刻製程（例如濕式蝕刻或乾式蝕刻或其組合），使得在淺溝槽隔離區105中的介電材料的頂表面凹陷，令鰭片103的上部分突出於周圍的絕緣淺溝槽隔離區105。在部分情況下，也可以藉由平坦化製程，去除用來形成鰭片103的圖案化硬遮罩。
在部分實施例中，圖4所示之鰭式場效電晶體104的閘極結構104 G為高k金屬閘極（high-k metal gate;HKMG）結構，可以使用後閘極製程流程形成此高k金屬閘極結構。在後閘極製程流程中，在形成淺溝槽隔離區105之後，形成犧牲虛設閘極結構（未示於圖中）。虛設閘極結構可包含虛設閘極介電質、虛設閘極電極和硬遮罩。首先，可沉積虛設閘極介電材料（例如氧化矽、氮化矽或類似物）。接著，可以在虛設閘極介電質上沉積虛設閘極材料（例如非晶矽、多晶矽或相似物），然後進行平坦化（例如藉由化學機械拋光）。在虛設閘極材料上方可形成硬遮罩層（例如氮化矽、碳化矽或相似物）。而後藉由圖案化硬遮罩並使用合適的光刻微影及蝕刻技術，將該圖案轉移到虛設閘極介電質和虛設閘極材料，來形成虛設閘極結構。虛設閘極結構可以沿著突出鰭片的多個側面延伸，以及在淺溝槽隔離區105的表面上方的鰭片之間延伸。如以下更詳細的描述，高k金屬閘極結構104 G可以取代虛設閘極結構，如圖4中所示。可以使用任一合適的方法，來沉積用來形成虛設閘極結構和硬遮罩的材料，例如化學氣相沉積、電漿增強化學氣相沉積、原子層沉積、電漿增強原子層沉積（plasma-enhanced ALD；PEALD）或相似物，或者藉由半導體表面的熱氧化或其組合。
在圖4中，舉例而言，自對準虛設閘極結構，形成電晶體裝置104的源極/汲極區104 SD和間隔物104 SP。可藉由在虛設閘極圖案化完成之後執行間隔物介電層的沉積和非等向性蝕刻來形成間隔物104 SP。間隔介電層可包括一種或多種介電質，例如氧化矽、氮化矽、氮氧化矽、碳化矽、碳氮化矽、類似物或其組合。非等向性蝕刻製程從虛設閘極結構的頂部移除間隔物介電層，在沿著虛設閘極結構的側壁橫向延伸到鰭片103的一部分表面上留下間隔物104 SP。
源極/汲極區104 SD是與半導體鰭片103直接接觸的半導體區。在部分實施例中，源極/汲極區104 SD可包含重摻雜區和相對輕摻雜的汲極延伸（又稱lightly-doped drain；LDD）區。一般而言，透過使用間隔物104 SP，將重摻雜區與虛設閘極結構分隔開來，而汲極延伸區可以在形成間隔物104 SP之前形成，並因此汲極延伸區在間隔物104 SP下方延伸，且在部分實施例中，汲極延伸區可進一步延伸至虛設閘極結構下方的半導體鰭片103的一部分。可以藉由例如離子佈植製程來植入摻雜劑（例如砷、磷、硼、銦或相似物），以形成汲極延伸區。
源極/汲極區104 SD可包含磊晶生長區。舉例而言，在形成汲極延伸區之後，可以形成間隔物104 SP，隨後，形成與間隔物104 SP自對準的重摻雜源極和汲極區，間隔物104 SP的形成可以藉由先蝕刻鰭片以形成凹槽，接著，可藉由選擇性磊晶生長（selective epitaxial growth；SEG）製程在凹槽中沉積晶體半導體材料，用以填充凹槽並且進一步延伸超出鰭片103的原始表面，形成凸起的源極/汲極磊晶結構。晶體半導體材料可為元素（例如矽或鍺或類似物）或合金（例如矽碳（Si 1-xC x）或矽鍺（Si 1-xGe x）或類似物）。選擇性磊晶生長製程可以採用任一合適的磊晶生長方法，例如氣相/固相/液相磊晶（vapor phase epitaxy；VPE、solid phase epitaxy；SPE、liquid phase epitaxy；LPE）或金屬有機化學氣相沉積（metal-organic chemical vapor deposition；MOCVD）或分子束磊晶（molecular beam epitaxy；MBE）或相似方法。可以在選擇性磊晶生長期間、或藉由在選擇性磊晶生長之後執行離子佈植製程或藉由兩者之組合，將高劑量（例如大約從10 14cm -2到10 16cm -2）的摻雜劑原位引入重摻雜源極/汲極區104 SD。
一旦形成源極/汲極區104 SD，在源極/汲極區104 SD上方沉積第一層間介電質層（例如層間介電質層110的下部分）。在部分實施例中，可在沉積層間介電質材料之前沉積合適的介電質（例如氮化矽、碳化矽、或相似物或其組合）的接觸蝕刻停止層（contact etch stop layer；CESL）（未示於圖中）。可以執行平坦化製程（例如化學機械拋光）以從虛設閘極上方去除多餘的層間介電質材料和任何剩餘的硬遮罩材料，進而形成頂表面，其中虛設閘極材料的頂表面被曝露並與第一層間介電質層的頂表面可實質共平面。可以藉由先使用一種或多種蝕刻技術去除虛設閘極結構，以形成如圖4中所示的高k金屬閘極結構104 G，從而在各個間隔物104 SP之間產生凹槽。接著，沉積包括一個或多個介電質的替代閘極介電層104 GD，隨後沉積包括一個或多個金屬的替代閘極金屬層104 GM，以完全填充凹槽。可以使用例如化學機械拋光製程，從第一層間介電質的頂表面上方去除閘極介電層104 GD和閘極金屬層104 GM多餘的部分。如圖4所示，所得到的結構可包含閘極介電層104 GD和閘極金屬層104 GM的剩餘部分，這些部分嵌入相對應的間隔物104 SP之間。
閘極介電層104 GD包括，舉例而言，高k介電材料如金屬的氧化物以及/或矽酸鹽（例如鉿、鋁、鋯、鑭、鎂、鋇、鈦和其他金屬的氧化物以及/或矽酸鹽）、氮化矽、氧化矽、相似物或其組合，或者其多層組合。在部分實施例中，閘極金屬層104 GM可為多層金屬閘極疊層，包含在閘極介電層104 GD上方接續形成的阻障層、功函數層以及閘極填充層。阻障層的示例性材料包括氮化鈦、氮化鉭、鈦、鉭、或相似物或其多層組合。功函數層可包括用於p型場效電晶體的氮化鈦、氮化鉭、釕、鉬、鋁，以及用於n型場效電晶體的鈦、銀、鋁化鉭、碳化鋁鉭、氮化鋁鈦、碳化鉭、碳氮化鉭、矽氮化鉭、錳、鋯。亦可使用其他合適的功函數材料或組合，或其多層。用來填充凹槽的剩餘部分的閘極填充層可包括金屬，例如銅、鋁、鎢、鈷、釕、或相似物或其組合，或其多層。可以藉由任何合適的方法沉積用來形成閘極結構的材料，例如化學氣相沉積、電漿增強化學氣相沉積、物理氣相沉積、原子層沉積、電漿增強原子層沉積、電化學鍍膜（electrochemical plating；ECP）、化學鍍膜以及/或類似方法。
在形成高k金屬閘極結構104 G之後，在第一層間介電質層上方沉積第二層間介電質層，並且將這些層間介電質層合稱為層間介電質層110，如圖4所示。在部分實施例中，用來形成第一層間介電質層和第二層間介電質層的絕緣材料可包括氧化矽、磷矽酸鹽玻璃（phosphosilicate glass；PSG）、硼矽酸鹽玻璃（borosilicate glass；BSG）、摻硼磷矽酸鹽玻璃（boron-doped phosphosilicate glass；BPSG）、未摻雜矽酸鹽玻璃、低介電常數（low-k）介電質例如氟矽酸鹽玻璃（fluorosilicate glass；FSG）、碳氧化矽（silicon oxycarbide；SiOCH）、碳摻雜氧化物（carbon-doped oxide；CDO）、可流動氧化物或多孔氧化物（例如乾凝膠/氣凝膠）、類似物或其組合。可以使用任何合適的方法沉積用來形成第一層間介電質層和第二層間介電質層的介電材料，例如化學氣相沉積、物理氣相沉積、原子層沉積、電漿增強原子層沉積、電漿增強化學氣相沉積、次常壓化學氣相沉積、可流動性化學氣相沉積、旋轉塗佈以及/或相似物或其組合。
可以使用光刻微影、蝕刻和沉積技術，在層間介電質層110中形成接觸插栓112。舉例而言，可以在層間介電質層110上方，形成圖案化遮罩，並且圖案化遮罩用於蝕刻延伸穿過層間介電質層110的一開口，以曝露閘極結構104 G和源極/汲極區104 SD。隨後，可以在層間介電質層110中的開口內，形成導電襯層。接著，以導電填充材料填充開口。襯層包括阻障金屬，該阻障金屬用於減少導電材料從接觸插栓112向外擴散至周圍介電材料中。在部分實施例中，襯層可包含兩個阻障金屬層。第一阻障金屬與源極/汲極區104 SD中的半導體材料接觸，隨後可與源極/汲極區104 SD中的重摻雜半導體發生化學反應，以形成低電阻歐姆接觸，其後未反應的金屬可被移除。舉例而言，若源極/汲極區104 SD中的重摻雜半導體是矽或矽鍺合金半導體，則第一阻障金屬可包括鈦、鎳、鉑、鈷、其他合適的金屬或其合金，並且可以與源極/汲極區104 SD形成矽化物。導電襯層的第二阻障金屬層可以額外包括其他金屬（例如氮化鈦、氮化鉭、鉭或其他合適的金屬或其合金）。可在導電襯層上沉積導電填充材料（例如鎢、鋁、銅、釕、鎳、鈷、其合金、其組合及相似物），以藉由任何可接受的沉積技術（例如化學氣相沉積、原子層沉積、電漿增強原子層沉積、電漿增強化學氣相沉積、物理氣相沉積、電化學鍍膜、化學鍍膜、相似物或其任何組合）來填充接觸開口。接著，可以使用平坦化製程（例如化學機械拋光）從層間介電質層 110的表面上去除所有導電材料的多餘部分。所得之導電插栓延伸至層間介電質層110中並構成接觸插栓112，接觸插栓112建立連接至電子裝置的電極的物理和電性連接，其中電子裝置例如為圖4中所示之三閘極鰭式場效電晶體裝置104。
在層間介電質層110上沉積隔離層121。隔離層121可包括合適的材料以提供化學及電性隔離。在部分實施例中，隔離層121包括陶瓷。舉例而言，隔離層121可包括含金屬化合物材料，例如氧化鋁、氧化鋯、氧化鈦、相似物或其組合。在形成隔離層121之後，可選擇性執行化學機械拋光製程，以平坦化隔離層121的頂表面。
如前所述，在本實施例中，可以藉由合適的沉積製程形成隔離層121，並使用比氮化矽沉積製程更少的含氫前驅物或不使用含氫前驅物，從而獲得比氮化矽層低的氫濃度。舉例而言，可以藉由物理氣相沉積（例如射頻濺鍍）製程、原子層沉積製程、電漿增強化學氣相沉積製程、其他合適的沉積製程或其組合，以形成隔離層121。在部分實施例中，可以在不使用含氫前驅物的情況下執行物理氣相沉積（例如射頻濺鍍）製程。因此，藉由濺鍍形成的隔離層121可獲得小於1%的氫濃度。在部分實施例中，可以使用含氫前驅物（例如三甲基鋁（trimethylaluminum；TMA））執行原子層沉積製程，原子層沉積製程中含氫前驅物所提供的氫含量低於用來形成氮化矽的含氫前驅物（例如矽烷）。因此，藉由原子層沉積製程形成的隔離層121可具有在大約1%至大約2%的範圍內的氫濃度。隔離層121可為單層、多層堆疊或複合結構。對於具有複合結構的隔離層121，執行具有兩種或多種靶（或源）材的共濺鍍製程，以產生金屬合金或非金屬複合物（如陶瓷）的組合薄膜。
在部分實施例中，隔離層121具有從大約1奈米至大約1000奈米的範圍內的厚度。若隔離層121的厚度小於大約1奈米，隔離層121可能具有較差的薄膜均勻性，且前段層間介電質層 110中的裝置104可能會因為形成導電通孔的蝕刻製程而損壞。若隔離層121的厚度大於大約1000奈米，則難以在隔離層121中形成導電通孔。隔離層121的沉積溫度可在大約100K至大約1000K的範圍內。若隔離層121的沉積溫度低於大約100K或高於大約1000K，則難以形成隔離層121。
在部分實施例中，原子層沉積氧化鋁（Al 2O 3）具有比射頻濺鍍氧化鋁更低的水氣穿透率以及比射頻濺鍍氧化鋁更薄的薄膜厚度。舉例而言，原子層沉積氧化鋁的水氣穿透率可落在大約 10 -5g　m -2day -1至大約10 -7g　m -2day -1的範圍內，且薄膜厚度在大約 1 奈米至大約20奈米。射頻濺鍍氧化鋁的水氣穿透率可落在大約0.1g　m -2day -1至大約2 g　m -2day -1的範圍內，薄膜厚度則在大約20奈米至大約1微米的範圍內。由於原子層沉積製程可使用含氫前驅物（例如三甲基鋁），因此原子層沉積氧化鋁的氫濃度可以比射頻濺鍍氧化鋁的氫濃度更高。依據裝置的需求，可以選擇原子層沉積和物理氣相沉積（例如濺鍍沉積）製程之一，以形成具有合適的水氣穿透率、合適的薄膜厚度以及合適的氫濃度的隔離層（例如氧化鋁）。
參考圖5所示。在圖4的結構上方形成光罩210，並曝露出部分的隔離層121。光罩210可包括感光材料。可藉由合適的光刻微影製程形成光罩210，且光罩210具有開口（或溝槽）210O於其中。光刻微影製程可包含塗佈光阻層、將光阻曝光於圖案、執行後曝烘烤製程以及顯影抗蝕劑以形成包含抗蝕劑的圖案化遮罩。在部分替代實施例中，光罩可以是三層光阻。舉例而言，光罩210包含底層、位於底層上方的中間層以及位於中間層上方的光阻層。底層可包括有機或無機材料。中間層可包括氮化矽、氮氧化矽或相似物。光阻層可包括感光材料。
參考圖6所示。圖案化隔離層121以獲得開口121O，開口121O曝露下層導電特徵，例如接觸插栓112。在部分實施例中，透過光罩210的開口210O（如圖5所示），蝕刻隔離層121，從而在其中形成開口121O。圖案化可包含一個或多個蝕刻製程。蝕刻製程可包含乾式蝕刻製程、濕式蝕刻製程或其組合。在蝕刻製程期間，光罩210可作為蝕刻遮罩。在蝕刻製程後，可藉由合適的灰化製程剝離光罩210。
參考圖7A所示。在隔離層121的開口121O中形成導電通孔V1，以連接接觸插栓112。圖7B為示範剖視圖，表示在隔離層121的開口121O中的導電通孔V1之配置。參考圖7A及圖7B所示。形成導電通孔V1可包含以一個或多個導電材料FM填充開口121O，接著藉由化學機械拋光移除多餘的導電材料FM。在部分實施例中，一個或多個導電材料FM可包括銅、鎢、鋁、鈦、氮化鈦、氮化鉭、相似物或其組合。在部分實施例中，可以在沉積一個或多個導電材料FM之前，沉積一個或多個阻障/附著層MB至開口121O中。一個或多個阻障/附著層MB可包括鈦、氮化鈦、鉭、氮化鉭、相似物或其組合，並可藉由物理氣相沉積、化學氣相沉積、原子層沉積或相似方法來形成。
參考圖8所示。可在隔離層121上方形成薄膜電晶體基底內連接結構122。薄膜電晶體基底內連接結構122可包含使用合適的方法例如單鑲嵌製程、雙鑲嵌製程或相似方法，分別在介電層DI 11至DI 13中形成的多個內連接階層。內連接階層可包含一個或多個水平內連接以及垂直內連接，其中水平內連接分別在介電層DI 11和DI 13中水平或橫向延伸，例如導電線CL，其中垂直內連接在介電層DI 12中垂直延伸，例如導電通孔CV。這些在介電層DI 11至DI 13中的導電線CL和導電通孔CV的組合，可被稱為金屬化圖案MP1。
在部分實施例中，介電層DI 11至DI 13可包括在導電特徵之間設置的低k介電材料，這些低k介電材料具有例如低於大約4.0或甚至低於大約2.0的k值。在部分實施例中，介電層DI 11至DI 13可由例如磷矽玻璃、硼磷矽玻璃、氟矽玻璃、碳氧化矽（SiO xC y）、旋轉塗佈玻璃、旋轉塗佈聚合物、氧化矽、氮氧化矽、其組合或相似物製成，並可藉由任何合適之方法，如旋轉塗佈、化學氣相沉積、電漿增強化學氣相沉積、或相似物來形成。
導電線CL和導電通孔CV可包括導電材料，例如銅、鋁、鎢、其組合或相似物。在部分實施例中，導電線CL和導電通孔CV可進一步包含一個或多個阻障/附著層（未表示於圖中），以保護相對應的介電層DI 11至DI 13免於金屬擴散（例如銅擴散）和金屬汙染。一個或多個阻障/附著層可包括鈦、氮化鈦、鉭、氮化鉭、或相似物，並且可藉由物理氣相沉積、化學氣相沉積、原子層沉積或相似方式形成。
在部分實施例中，薄膜電晶體基底內連接結構122可進一步包含被介電層DI 12環繞的薄膜電晶體122T。在薄膜電晶體基底內連接結構122的金屬化層（例如介電層DI 11以及介電層DI 11中的導電線CL）上方，形成額外的介電層DI 1A。介電層DI 1A作為支撐薄膜電晶體122T（例如半導體層SL）的基礎介電層。介電層DI 1A可包括低k介電材料。在部分實施例中，介電層DI 1A可由例如磷矽玻璃、硼磷矽玻璃、氟矽玻璃、碳氧化矽（SiO xC y）、旋轉塗佈玻璃、旋轉塗佈聚合物、氧化矽、氮氧化矽、其組合或相似物製成，並可藉由例如旋轉塗佈、化學氣相沉積、電漿增強化學氣相沉積或相似方式形成。由於介電層DI 1A與介電層DI 11和DI 13的作用不同，因此介電層DI 1A可具有與介電層DI 11和DI 13不同的厚度以及/或材料。舉例而言，介電層DI 1A可以比一個或多個介電層DI 11和DI 13更薄或更厚。又或者，介電層DI 1A可以具有與一個或多個介電層DI 11和DI 13相同的厚度以及/或材料。
薄膜電晶體122T的製程可包含在介電層DI 1A上沉積半導體層SL。藉由微影和蝕刻製程，圖案化半導體層SL，以獲得合適的圖形。然後在一部分的半導體層SL上形成閘極結構GS。形成閘極結構GS包含沉積閘極介電層、沉積閘極電極層、圖案化閘極介電層以及閘極電極層成為閘極介電質GI和閘極電極GE中。在部分實施例中，在閘極結構GS下方的部分的半導體層SL作為薄膜電晶體的通道區CR，而SL位在通道區CR的相對兩側上的其餘部分的半導體層可摻雜並作為薄膜電晶體的源極/汲極區SDR。在本揭露的部分實施例中，薄膜電晶體122T的製程可以在低於前段製程的溫度下執行，例如在低於大約400 °C下執行，從而避免金屬化圖案的金屬擴散以利電晶體堆疊。舉例而言，形成半導體層SL（例如沉積以及退火半導體層SL）的溫度可低於在前段製程中形成磊晶源極/汲極區104 SD（例如沉積以及退火磊晶源極/汲極區104 SD）的溫度。
在部分實施例中，半導體層SL可為沉積薄膜而非單晶材料。舉例而言，半導體層SL可為非晶相（亦即無結構排列）、或多晶相（亦即具有微米尺寸至奈米尺寸之晶粒）。在部分實施例中，半導體層SL可包括非晶相半導體（例如非晶矽）或非晶相金屬氧化物半導體（例如非晶銦鎵鋅氧化物），非晶相材料具有無晶界以及高度均勻性之優勢。在部分實施例中，半導體層SL可包括多晶相材料（例如多晶矽），多晶相材料具有高遷移率之優勢。在這些實施例中，在半導體層SL內部，可以是本徵的或非有意地摻雜通道區CR，並可將源極/汲極區SDR摻雜為具有導電性。在部分其他實施例中，半導體層SL可包括具有超高遷移率的優勢之二維材料（2D material），例如過渡金屬二硫屬化物（transition-metal dichalcogenide；TMD）（例如MoS 2）或石墨烯。在這些實施例中，半導體層SL亦可以稱為二維材料層。
在部分實施例中，在如圖8所示的薄膜電晶體基底內連接結構122的製程中，首先在隔離層121上，沉積介電層DI 11，接著在隔離層121上的介電層DI 11中，形成導電線CL。接下來，可在介電層DI 11和導電線CL之上沉積介電層DI 1A，並且可在介電層DI 1A上形成薄膜電晶體122T。所形成的薄膜電晶體122T位於隔離層121上方，並至少部分藉由隔離層121與裝置104分隔開。然後可以在薄膜電晶體122T上沉積介電層DI 12，並在介電層DI 1A與DI 12中形成導電通孔。可以在介電層DI 12上沉積介電層DI 13，然後可以在介電層DI 13中形成導電線CL。在本實施例中，薄膜電晶體基底內連接結構122示例於圖8中。在部分替代實施例中，薄膜電晶體基底內連接結構122可具有其他配置。
參考圖9所示。在薄膜電晶體基底內連接結構122上沉積隔離層123。隔離層123可包括合適的材料以提供化學及電性隔離。在部分實施例中，隔離層123可包括陶瓷。舉例而言，隔離層123可包括含金屬化合物材料，例如氧化鋁、氧化鋯、氧化鈦、相似物或其組合。在本實施例中，如前所述，可以藉由合適之沉積製程，形成隔離層123，其中合適之沉積製程不使用含氫前驅物或使用比氮化矽的沉積製程少量的含氫前驅物，從而獲得比氮化矽層低的氫濃度。舉例而言，可藉由物理氣相沉積製程（例如濺鍍沉積）、原子層沉積製程、電漿增強化學氣相沉積製程、其他合適的沉積製程或其組合，形成隔離層123。在部分實施例中，可以在不使用含氫前驅物的情況下執行物理氣相沉積製程（例如濺鍍沉積）。因此，藉由濺射形成的隔離層123可具有小於1%的氫濃度。在部分實施例中，可以使用含氫前驅物（例如三甲基鋁）執行原子層沉積製程，該含氫前驅物所提供的氫含量少於用來形成氮化矽的含氫前驅物（例如矽烷）。因此，藉由原子層沉積製程形成的隔離層123具有大約1%至大約2%範圍內的氫濃度。隔離層123的細節可與隔離層121相似。在部分實施例中，隔離層121與隔離層123可包括相同的材料。在部分實施例中，隔離層121與隔離層123可包括不同的材料。在形成隔離層123之後，可選擇性執行化學機械拋光製程，以平坦化隔離層123的頂表面。
參考圖10所示。在圖4之結構上形成光罩220，並曝露部分的隔離層123。光罩220可包括感光材料。可藉由合適的光刻微影製程形成光罩220，且在光罩220中具有開口（或凹槽）220O。光刻微影製程可包含塗佈光阻層（未示於圖中）、將光阻曝光於圖案、執行後曝烘烤製程以及顯影抗蝕劑，以形成包含抗蝕劑的圖案化遮罩。在部分替代實施例中，光罩可以是三層光阻。舉例而言，光罩220包含底層、位於底層上方的中間層，以及位於中間層上方的光阻層。底層可包括有機或無機材料。中間層可包括氮化矽、氮氧化矽、碳氧化矽或相似物。光阻層可包括感光材料。
參考圖11所示。圖案化隔離層123以獲得開口123O，開口123O曝露下層導電特徵，例如導電線CL。在部分實施例中，透過光罩220的開口220O（如圖10所示），蝕刻隔離層123，從而在其中形成開口123O。開口123O可延伸通過介電層DI 13，從而達到導電線CL。圖案化可包含一個或多個蝕刻製程。蝕刻製程可包含乾式蝕刻製程、濕式蝕刻製程或其組合。在蝕刻製程期間，光罩220可作為蝕刻遮罩。在蝕刻製程後，可藉由合適的灰化製程剝離光罩220。
參考圖12所示。在隔離層123的開口123O中形成導電通孔V2，以連接導電線CL。形成導電通孔V2可包含以一個或多個導電材料，填充開口123O，接著藉由化學機械拋光，移除多餘的導電材料。在部分實施例中，一個或多個導電材料可包括銅、鎢、鋁、鈦、氮化鈦以及/或氮化鉭。在部分實施例中，可在沉積一個或多個導電材料之前，沉積一個或多個阻障/附著層至開口123O中。一個或多個阻障/附著層可包括鈦、氮化鈦、鉭、氮化鉭或相似物，並可藉由物理氣相沉積、化學氣相沉積、原子層沉積或相似方法來形成。
參考圖13所示。可在隔離層123上方形成薄膜電晶體基底內連接結構124。薄膜電晶體基底內連接結構124可包含使用任何合適的方法（例如單鑲嵌製程、雙鑲嵌製程或相似方法），分別在介電層DI 21至DI 23中形成的多個內連接階層。內連接階層可包含一個或多個水平內連接以及垂直內連接，水平內連接分別在介電層DI 21和DI 23中水平或橫向延伸，例如導電線CL，垂直內連接在介電層DI 22中垂直延伸，例如導電通孔CV。這些在介電層DI 21至DI 23中的導電線CL和導電通孔CV的組合，可稱為金屬化圖案MP2。
在部分實施例中，薄膜電晶體基底內連接結構124可進一步包含被介電層DI 22環繞的薄膜電晶體124T。在薄膜電晶體基底內連接結構124的金屬化層（例如介電層DI 21以及介電層DI 21中的導電線CL）上方，形成額外的介電層DI 2A。介電層DI 2A作為支撐薄膜電晶體124T（例如半導體層SL）的基礎介電層。薄膜電晶體124T的製程可包含在介電層DI 2A上沉積半導體層SL、圖案化半導體層SL以獲得合適的圖形、在半導體層SL上形成閘極結構GS以及選擇性摻雜半導體層SL，以形成源極/汲極區SDR。所形成之薄膜電晶體124T位於隔離層123上方，並且至少部分藉由隔離層123與薄膜電晶體122T分隔開。薄膜電晶體基底內連接結構124和薄膜電晶體124T在材料及製程方面的細節，與薄膜電晶體基底內連接結構122和薄膜電晶體122T的細節相似，故不在此重複敘述。
在圖8至圖14中，進行後段製程，以在層間介電質層110的上方形成後段內連接結構120，其中後段內連接結構120可包含各種薄膜電晶體基底內連接結構122和124。在後段製程之後，可進行晶圓切割製程，以在切割路徑區域SR上分割晶片區域CH1，從而產生如圖14中所示之晶粒/晶片。晶圓切割製程可包含用來將基板102切割成晶粒/晶片的合適方法。例如，晶圓切割製程涉及切割和斷裂、機械切割、雷射切割或相似方法。
參考圖15所示。在晶圓切割製程之後，可以將各個晶粒/晶片封裝，以適用於構建電子裝置，例如電腦等。在圖14所示的晶粒/晶片周圍，形成封裝層130。封裝層130可包括合適材料的材料，以提供化學和電性隔離。在部分實施例中，封裝層130可包括陶瓷。舉例而言，封裝層130可包括含金屬的化合物材料，例如氧化鋁、氧化鋯、氧化鈦、相似物或其組合。在部分實施例中，封裝層130和隔離層121/123可包括相同的材料。在部分其他實施例中，封裝層130和隔離層121/123可包括不同的材料。
在本實施例中，可藉由合適的沉積製程形成封裝層130，並使用比氮化矽沉積製程更少的含氫前驅物或不使用含氫前驅物，從而獲得比氮化矽層低的氫濃度。舉例而言，可以藉由物理氣相沉積（例如濺鍍沉積）製程、原子層沉積製程、電漿增強化學氣相沉積製程、其他合適的沉積製程或其組合來形成封裝層130。在部分實施例中，可以在不使用含氫前驅物的情況下執行物理氣相沉積（例如濺鍍沉積）製程。因此，藉由濺射形成的封裝層130可獲得小於1%的氫濃度。在部分實施例中，可以使用含氫前驅物（例如三甲基鋁）執行原子層沉積製程，該含氫前驅物所提供的氫含量低於用來形成氮化矽的含氫前驅物（例如矽烷）。因此，藉由原子層沉積製程形成的封裝層130可具有在大約1%至大約2%的範圍內的氫濃度。封裝層130可為單層、多層堆疊或複合結構。對於具有複合結構的封裝層130，可執行濺射兩種或多種靶（或源）材的共濺鍍製程，以產生組合薄膜（例如如金屬合金）或者非金屬複合物（如陶瓷）。
在部分實施例中，封裝層130的厚度可以在從大約1奈米至大約1000奈米的範圍內。若封裝層130的厚度小於大約1奈米，封裝層130可能具有較差的薄膜均勻性。若封裝層130的厚度大於大約1000奈米，則增加非必要的製程時間及成本。封裝層130的沉積溫度可在大約100K至大約1000K的範圍內。若封裝層130的沉積溫度低於大約100K或高於大約1000K，則難以形成封裝層130。其他封裝層130的細節可與隔離層121/123相似，故不在此重複敘述。
在沒有封裝層130的情況下，濕氣可能會通過切割缺陷擴散到裝置中，導致高寄生電容。此外，由於金屬間介電質/層間介電質中的濕氣，金屬間介電質/層間介電質的崩潰電壓（V BD）降低，進而降低了積體電路裝置的可靠性。
在本揭露部分實施例中，在晶粒/晶片的側壁及頂表面上形成封裝層130，從而封裝裝置（例如裝置104、薄膜電晶體122T和124T）。在晶圓切割之後，封裝層130可以減緩濕氣從環境（側面隔離）擴散至裝置中。透過此配置，以避免金屬間介電質/層間介電質受濕氣，進而免於降低金屬間介電質/層間介電質的崩潰電壓（V BD），故可改善積體電路裝置之可靠度。
根據本揭露部分實施例，圖16所示為氧化鋁及氮化矽的水氣穿透率圖。在本實施例中，藉由原子層沉積製程形成厚氧化鋁及薄氧化鋁，且厚氧化鋁之厚度可大於薄氧化鋁但小於氮化矽。在圖中，薄氧化鋁的水氣穿透率與厚氧化鋁的水氣穿透率相當。將厚/薄氧化鋁與氮化矽比較，厚/薄氧化鋁具有比氮化矽更高的水氣穿透率。因此，厚/薄氧化鋁可以做為防潮隔離層（例如圖1A中的隔離層121、123和125）和防潮封裝層（例如圖2A和圖3中的封裝層130和130’。
根據本揭露部分實施例，圖17及圖18說明在不同階段中，製造積體電路的方法。本實施例之細節與圖4 至圖15的細節相似，差別在於在隔離層121和123上方形成額外的介電層DI 10和DI 20，進而將導電線CL與隔離層121和123分隔開。
參考圖17所示。執行後段製程，以在層間介電質層110上方形成後段內連接結構120，此後段內連接結構120可包含各種薄膜電晶體基底內連接結構122及124。在本實施例中，對於薄膜電晶體基底內連接結構122，可以在沉積介電層DI 11之前，先在隔離層121的頂表面上沉積介電層DI 10，並且形成通過介電層DI 11和隔離層121的導電通孔V1。在本實施例中，對於薄膜電晶體基底內連接結構124，可以在沉積介電層DI 21之前，先在隔離層123的頂表面上沉積介電層DI 20，並且形成通過介電層DI 20和隔離層123的導電通孔V2。在部分實施例中，介電層DI 10至DI 20可包括低k介電材料，設置於這樣的導電特徵之間，且這些低k介電材料具有例如低於大約4.0或甚至低於大約2.0的k值。在部分實施例中，介電層DI 10和DI 20可由例如磷矽玻璃、硼磷矽玻璃、氟矽玻璃、碳氧化矽（SiO xC y）、旋轉塗佈玻璃、旋轉塗佈聚合物、氧化矽、氮氧化矽、其組合或相似物製成，並藉由任何合適之方法例如旋轉塗佈、化學氣相沉積、電漿增強化學氣相沉積、或相似的方法形成。透過該配置，將介電層DI 11和DI 21中的導電線CL與隔離層121和123間隔開。在後段製程之後，可執行晶圓切割製程（例如使用切割、雷射或其他裝置），以分割晶片區域，從而產生如圖17所示之各別晶粒/晶片。
參考圖18所示。在如圖17所示之晶粒/晶片周圍形成封裝層130，以提供化學及電性隔離。本實施例的其餘細節與圖4至圖15中的細節相似，故不在此重複敘述。
圖19至圖21為根據本揭露部分實施例的積體電路裝置的示範剖視圖。應理解到，可以在圖19至圖21所示的操作之前、期間和之後提供額外的操作，並且對該方法的額外實施例，以下描述的部分操作可以被替換或刪除。其操作/製程的順序可以互換。
參考圖19所示，提供晶圓WA1及WA2。在部分實施例中，每一個晶圓WA1及WA2可包含基板102、在基板102上的內連接結構120以及在內連接結構120上的介電層190。每一個晶圓WA1及WA2可包含一個或多個晶片區CH1以及圍繞晶片區CH1的切割路徑區SR。晶圓WA1和WA2中的基板102和內連接結構120的細節可與前述之基板及後段內連接結構（例如圖13的基板102及內連接結構120）相似，故不在此重複敘述。
在部分實施例中，介電層190為氧化層，氧化層可包括氧化矽。在其他實施例中，介電層190包括其他含矽以及/或含氧的材料例如氮氧化矽、氮化矽或相似物。在介電層190中可形成導電連接器BP11和BP12，且可藉由合適的導電特徵（例如通孔），將導電連接器BP11和BP12電性耦合至內連接結構120的金屬化圖案。舉例而言，晶圓WA2包含通孔TV，通孔TV延伸通過整個內連接結構120，並將導電連接器BP12連接至內連接結構120。導電連接器BP11和BP12可由銅、鋁、鎳、鎢或其合金製成。在部分實施例中，導電連接器BP11和BP12可接合焊墊、金屬柱、相似物或其組合。對於晶圓WA2，介電層190可稱為接合介電層，且介電層190的頂表面與導電連接器BP12的頂表面可相互對齊，這是透過在形成導電連接器BP12的期間，進行平坦化所達成。平坦化可包含化學機械拋光製程。
在本實施例中，晶圓WA1可進一步包含在介電層190上方的隔離層142以及導電連接器BP11，導電連接器BP11形成於介電層190和覆蓋在介電層190上方的隔離層142中。隔離層142可稱為接合隔離層。隔離層142的材料及形成可與隔離層121及123相似（參考圖4至圖12所示），故不在此重複敘述。導電連接器BP11的形成可包含在隔離層142和隔離層142下方的介電層190中，蝕刻開口142O，並且以導電材料例如焊料、銅、鋁、金、鎳、銀、鈀、錫、相似物或其組合，填充開口142O。可執行化學機械拋光製程，以從開口142O中去除一部分導電材料。對於晶圓WA1，可以藉由化學機械拋光製程，將隔離層142的頂表面與導電連接器BP11的頂表面相互對齊。
參考圖20所示，藉由例如晶圓堆疊技術（wafer-on-wafer；WoW），將晶圓WA2垂直堆疊在晶圓WA1上。在部分實施例中，執行混合鍵合（hybrid bonding）製程，以接合晶圓WA1與晶圓WA2。混合鍵合製程可包含表面活化、熱壓縮和其他合適的製程。在部分實施例中，混合鍵合製程涉及至少兩種類型的鍵結，包括金屬間（例如銅與銅）鍵結和介電質間鍵結。舉例而言，晶圓WA2的導電連接器BP12透過金屬間鍵結，接合晶圓WA1的導電連接器BP11，且晶圓WA2的接合介電層190透過介電質間鍵結，接合至晶圓WA1的接合隔離層142。經過鍵合製程後，導電連接器BP11和BP12的組合可稱為導電連接器BP1。導電連接器BP1可以將晶圓WA2的內連接結構120的金屬化圖案與晶圓WA1的內連接結構120的金屬化圖案連接。
參考圖21，在鍵合製程之後，可沿著切割路徑區SR （參考圖20所示）切割堆疊的晶圓WA1和WA2，執行晶圓切割製程，以分割晶片區CHl （參考圖20所示），從而產生個別的堆疊的晶粒/晶片100A1和100A2。晶圓切割製程可包含合適方法，用來將堆疊晶圓WA1和WA2切割成堆疊的晶片100A1和100A2。
在晶圓切割製程之後，可以在堆疊的晶片100A1和100A2周圍形成封裝層130’。如前所述，封裝層130’可由合適的材料製成，以提供化學及電性隔離。在部分實施例中，封裝層130’可包括陶瓷。舉例而言，封裝層130’可由含金屬之化合物材料，例如氧化鋁、氧化鋯、氧化鈦、相似物或其組合製成。可以藉由物理氣相沉積製程（例如射頻濺鍍）、原子層沉積製程、電漿增強化學氣相沉積製程、其他合適的沉積製程或其組合，形成封裝層130’。在形成封裝層130’之後，可以在晶片100A2未被封裝層130’覆蓋的一側，設置錫球BP2。錫球BP2可與通孔TV接觸。可以藉由蒸鍍、電鍍、印刷、焊料轉移、植球或相似方法，形成錫球BP2。本實施例的其他細節與上述相似，故不在此重複敘述。
圖22至圖24是根據本揭露部分實施例的積體電路裝置的示範剖視圖。本實施例之細節與圖19至圖21之說明相似，差別在於採用晶片堆疊晶圓（chip-on-wafer；CoW）技術，形成積體電路裝置。應理解到，可以在圖19至圖21所示的操作之前、期間和之後提供額外的操作，並且對該方法的額外實施例，以下描述的部分操作可以被替換或刪除。其操作/製程的順序可以互換。
參考圖22所示，提供晶圓WA1、晶片100A2以及晶片100A3。晶圓WA1可包含基板102、基板102上方的內連接結構120、內連接結構120上方的介電層190、介電層190上方的隔離層142以及導電連接器BP11。可以在介電層190和隔離層142上方形成導電連接器BP11。晶圓WA1可包含一個或多個晶片區CH1以及圍繞在晶片區CH1周圍的切割路徑區SR。晶圓WA1的細節與前述圖19中之晶圓WA1相似，故不在此重複敘述。
合適的晶圓可以透過晶圓切割製程，形成晶片100A2和晶片100A3。在部分實施例中，每一個晶片100A2和晶片100A3可包含基板102、基板102上方的內連接結構120以及內連接結構120上方的介電層190。基板102和內連接結構120的細節與前述相似，故不在此重複敘述。在介電層190中可形成導電連接器BP12，且導電連接器BP12可電性耦合至內連接結構120的金屬化圖案。
參考圖23所示，晶片100A2和晶片100A3藉由例如晶片堆疊晶圓技術，在晶圓WA1上垂直堆疊。在部分實施例中，執行一個或多個混合鍵合製程，以將晶片100A2和晶片100A3接合至晶圓WA1。在部分實施例中，混合鍵合製程涉及至少兩種類型的鍵結，包括金屬間（例如銅與銅）鍵結和介電質間鍵結。舉例而言，晶片100A2/100A3的導電連接器BP12透過金屬間鍵結，與晶圓WA1的導電連接器BP11接合，且晶片100A2/100A3的接合介電層190透過介電質間鍵結，接合至晶圓WA1的接合隔離層142。經過鍵合製程後，導電連接器BP11和BP12的組合可稱為導電連接器BP1。導電連接器BP1可以將晶片100A2/100A3的內連接結構120的金屬化圖案與晶圓WA1的內連接結構120的金屬化圖案連接。
參考圖24所示，在鍵合製程之後可執行晶圓切割製程，沿著切割路徑區SR（參考圖23所示）切割晶圓WA1，以分割晶片區CH1（參考圖23所示），從而形成個別晶粒/晶片100A1，並有晶片100A2和晶片100A3堆疊在晶粒/晶片100A1上。晶圓切割製程可包含合適的方法，用來將晶圓WA1切割為晶片100A1。在晶圓切割製程之後，可在晶片100A2和100A3周圍，形成底部填充物UF。底部填充物UF可以提供積體電路裝置結構支撐。在部分實施例中，底部填充物UF可以是分布在晶片100A2至100A3之間的液態環氧樹脂，然後藉由例如熱固化製程固化以硬化。在固化之後，底部填充物UF成為固體。在部分實施例中，底部填充物UF包括有填料分散在其中的環氧樹脂。填料可包括纖維、顆粒、其他合適的元素、其組合或相似物。在形成底部填充物UF之後，可接著在晶片100A1至100A3周圍形成封裝層130’，並可以在未被封裝層130’覆蓋的晶片100A2和100A3的側面上，設置錫球BP2。本實施例的其他細節與前述相似，故不在此重複敘述。
基於上述討論，可以看出以上揭露提供光子封裝裝置優勢。然而，應當理解到，其他實施例可提供額外的優勢，並非所有優勢都必須在此揭露，且沒有所有實施例都需要的特定優勢。其中一個優勢是由於薄膜電晶體的製程溫度低，薄膜電晶體能很容易地堆疊在互補金屬氧化物半導體裝置上。另一個優勢是在堆疊層之間設置防潮隔離層，從而避免氫以及/或濕氣擴散至堆疊的薄膜電晶體。還有另一個優勢是可以在堆疊晶粒周圍設置防潮封裝層，從而避免氫以及/或濕氣擴散。
根據本揭露之部分實施例，提供製造積體電路裝置之方法。方法包含在半導體基板上形成場效電晶體；在場效電晶體上沉積第一介電層；在第一介電層上沉積第一含金屬介電層；以及在第一含金屬介電層上形成第一薄膜電晶體。
根據本揭露之部分實施例，提供製造積體電路裝置之方法。更包含形成一導電特徵，該導電特徵延伸通過該第一含金屬介電層，其中該導電特徵電性連接至該場效電晶體。
根據本揭露之部分實施例，提供製造積體電路裝置之方法。其中形成該導電特徵包含在該第一含金屬介電層中，蝕刻一開口；以及以一導電材料填充該開口。
根據本揭露之部分實施例，提供製造積體電路裝置之方法。更包含在該第一薄膜電晶體上，沉積一第二介電層；在該第二介電層上，沉積一第二含金屬介電層；以及在該第二含金屬介電層上，形成一第二薄膜電晶體。
根據本揭露之部分實施例，提供製造積體電路裝置之方法。更包含形成一導電特徵，該導電特徵延伸通過該第二含金屬介電層，其中該導電特徵電性連接至該第一薄膜電晶體。
根據本揭露之部分實施例，提供製造積體電路裝置之方法。其中形成該場效電晶體包含形成一閘極介電質，該閘極介電質接觸該半導體基板的一頂表面；以及在該閘極介電質上，形成一閘極電極。
根據本揭露之部分實施例，提供製造積體電路裝置之方法。更包含在形成該第一薄膜電晶體之前，在該第一含金屬介電層上，沉積一基底介電層，其中形成該第一薄膜電晶體包含形成一閘極介電質以及一閘極電極，該閘極介電質接觸該基底介電層的一頂表面，且該閘極電極在該閘極介電質上。
根據本揭露之部分實施例，提供製造積體電路裝置之方法。其中沉積該第一含金屬介電層是使用一濺鍍沉積製程或一原子層沉積製程進行的。
根據本揭露之部分實施例，提供製造積體電路裝置之方法。更包含切割該半導體基板成為至少一晶片；以及形成一封裝層，該封裝層封裝該晶片，其中該封裝層包含一含金屬介電材料。
根據本揭露之部分實施例，提供製造積體電路裝置之方法。其中該封裝層之該含金屬介電材料與該第一含金屬介電層之一材料相同。
根據本揭露之部分實施例，提供製造積體電路裝置之方法。方法包含在半導體基板上形成第一電晶體；在第一電晶體上沉積第一氧化鋁層；在第一氧化鋁層中形成第一通孔；以及在第一氧化鋁層中形成第一通孔之後，在第一氧化鋁層上方形成第二電晶體。
根據本揭露之部分實施例，提供製造積體電路裝置之方法。其中該第一氧化鋁層是藉由一射頻濺鍍沉積製程沉積，該射頻濺鍍沉積製程不使用一含氫前驅物。
根據本揭露之部分實施例，提供製造積體電路裝置之方法。其中該第一氧化鋁層是藉由一原子層沉積製程沉積。
根據本揭露之部分實施例，提供製造積體電路裝置之方法。更包含在該第二電晶體上，沉積一第二氧化鋁層；在該第二氧化鋁層中，形成複數個第二通孔；以及在該第二氧化鋁層中形成該些第二通孔之後，在該第二氧化鋁層上，形成一第三電晶體。
根據本揭露之部分實施例，提供製造積體電路裝置之方法。更包含將該第一、該第二以及該第三電晶體封裝在一第三氧化層中。
根據本揭露之部分實施例，積體電路裝置包含半導體基板、場效電晶體、第一金屬氧化層、第一金屬通孔、第一薄膜電晶體。場效電晶體位於半導體基板上。第一金屬氧化層位於場效電晶體上方。第一金屬通孔延伸通過第一金屬氧化層。薄膜電晶體位於第一金屬氧化層上方，並且與場效電晶體至少部份藉由該第一金屬氧化層分隔開來。
根據本揭露之部分實施例，積體電路裝置更包含一封裝層，該封裝層封裝該場效電晶體以及該第一薄膜電晶體。
根據本揭露之部分實施例，積體電路裝置其中該封裝層由相同於該第一金屬氧化層之一材料組成。
根據本揭露之部分實施例，積體電路裝置其中該封裝層由氧化鋁組成。
根據本揭露之部分實施例，積體電路裝置更包含一第二金屬氧化層，位於該第一薄膜電晶體上；複數個第二金屬通孔，延伸通過該第二金屬氧化層；以及一第二薄膜電晶體，位於該第二金屬氧化層上，該第二薄膜電晶體與該第一薄膜電晶體至少部分藉由該第二金屬氧化層分隔開來。
以上概述了幾個實施例的特徵，以令本領域技術人員能更佳地理解本揭露之各個面向。本領域技術人員應當理解，他們可以輕易地使用本揭露作為設計或修改其他製程和結構的基礎，以實現與本文所介紹的實施例相同的優點以及/ 或執行相同的目的。本領域技術人員也應意識到，該同等結構並不背離本揭露的精神及範圍，且可在不背離本揭露的精神及範圍的情況下對本文進行各種改動、替換及變更。
100A、100B、100C:積體電路裝置 100A1~100A3:晶片 102:基板 103:鰭片 104:主動以及/或被動裝置 104 G、GS:閘極結構 104 SD、SDR:源極/汲極區 104 GD:閘極介電層 104 GM:閘極金屬層 104 SP:間隔物 105:淺溝槽隔離區 110:層間介電質層 112:接觸插栓 120:內連接結構 121、123、125、142、144:隔離層 121O、123O、142O、210O、220O:開口 122、124、126:薄膜電晶體基底內連接結構 122T、124T、126T:裝置（薄膜電晶體） 130、130’:封裝層 210、220:光罩 BP1、BP11、BP12:導電連接器 BP2:錫球 CL:導電線 CV:導電通孔 CR:通道區 CH1:晶片區 DI、DI 1A、DI 10、DI 11、DI 12、DI 13、DI 2A、DI 20、DI 21、DI 22、DI 23、190:介電層 FM:導電材料 GI:閘極介電質 GE:閘極電極 MB:阻障/附著層 MP、MP1、MP2:金屬化圖案 SL:半導體層 SR:切割路徑區 TV:通孔 UF:填充物 V1~V3:導電通孔 WA1、WA2:晶圓
從以下詳細敘述並搭配圖式檢閱，可理解本揭露的態樣。應注意，多種特徵並未以產業上實務標準的比例繪製。事實上，為了討論上的清楚易懂，各種特徵的尺寸可以任意地增加或減少。 圖1A為根據本揭露部分實施例之積體電路裝置之示範剖視圖。 圖1B為一示範剖視圖，表示圖1A的積體電路裝置之組成。 圖2A為根據本揭露部分實施例之積體電路裝置之示範剖視圖。 圖2B為一示範剖視圖，表示圖2A的積體電路裝置之組成。 圖3為根據本揭露部分實施例之積體電路裝置之示範剖視圖。 圖4至圖15說明根據本揭露部分實施例，製造積體電路裝置之方法的各個中間階段。 圖16為根據本揭露部分實施例之氧化鋁（Al 2O 3）以及氮化矽的水氣穿透率（water vapor transmission rates; WVTR）圖。 圖17和圖18說明根據本揭露部分實施例，製造積體電路裝置之方法的各個中間階段。 圖19至圖21為根據本揭露部分實施例之積體電路裝置之示範剖視圖。 圖22至圖24為根據本揭露部分實施例之積體電路裝置之示範剖視圖。
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無
100B:積體電路裝置
102:基板
104:主動以及/或被動裝置
104G、GS:閘極結構
104SD、SDR:源極/汲極區
104GD:閘極介電層
104GM:閘極金屬層
105:淺溝槽隔離區
110:層間介電質層
112:接觸插栓
120:後段內連接結構
121、123、125:隔離層
122、124、126:薄膜電晶體基底內連接結構
122T、124T、126T:裝置(薄膜電晶體)
130:封裝層
CL:導電線
CV:導電通孔
CR:通道區
DI:介電層
GI:閘極介電質
GE:閘極電極
MP:金屬化圖案
SL:半導體層
V1~V3:導電通孔

Claims (20)

  1. 一種製造積體電路裝置的方法，包含： 在一半導體基板上，形成一場效電晶體； 在該場效電晶體上，沉積一第一介電層； 在該第一介電層上，沉積一第一含金屬介電層；以及 在該第一含金屬介電層上，形成一第一薄膜電晶體。
  2. 如請求項1所述的方法，更包含： 形成一導電特徵，該導電特徵延伸通過該第一含金屬介電層，其中該導電特徵電性連接至該場效電晶體。
  3. 如請求項2所述的方法，其中形成該導電特徵包含： 在該第一含金屬介電層中，蝕刻一開口；以及 以一導電材料填充該開口。
  4. 如請求項1所述的方法，更包含： 在該第一薄膜電晶體上，沉積一第二介電層； 在該第二介電層上，沉積一第二含金屬介電層；以及 在該第二含金屬介電層上，形成一第二薄膜電晶體。
  5. 如請求項4所述的方法，更包含： 形成一導電特徵，該導電特徵延伸通過該第二含金屬介電層，其中該導電特徵電性連接至該第一薄膜電晶體。
  6. 如請求項1所述的方法，其中形成該場效電晶體包含： 形成一閘極介電質，該閘極介電質接觸該半導體基板的一頂表面，；以及 在該閘極介電質上，形成一閘極電極。
  7. 如請求項1所述的方法，更包含： 在形成該第一薄膜電晶體之前，在該第一含金屬介電層上，沉積一基底介電層，其中形成該第一薄膜電晶體包含形成一閘極介電質以及一閘極電極，該閘極介電質接觸該基底介電層的一頂表面，且該閘極電極在該閘極介電質上。
  8. 如請求項1所述的方法，其中沉積該第一含金屬介電層是使用一濺鍍沉積製程或一原子層沉積製程進行的。
  9. 如請求項1所述的方法，更包含： 切割該半導體基板成為至少一晶片；以及 形成一封裝層，該封裝層封裝該晶片，其中該封裝層包含一含金屬介電材料。
  10. 如請求項9所述的方法，其中該封裝層之該含金屬介電材料與該第一含金屬介電層之一材料相同。
  11. 一種製造積體電路裝置的方法，包含： 在一半導體基板上，形成一第一電晶體； 在該第一電晶體上，沉積一第一氧化鋁層； 在該第一氧化鋁層中，形成複數個第一通孔；以及 在該第一氧化鋁層中形成該些第一通孔之後，在該第一氧化鋁層上，形成一第二電晶體。
  12. 如請求項11所述的方法，其中該第一氧化鋁層是藉由一射頻濺鍍沉積製程沉積，該射頻濺鍍沉積製程不使用一含氫前驅物。
  13. 如請求項11所述的方法，其中該第一氧化鋁層是藉由一原子層沉積製程沉積。
  14. 如請求項11所述的方法，更包含： 在該第二電晶體上，沉積一第二氧化鋁層； 在該第二氧化鋁層中，形成複數個第二通孔；以及 在該第二氧化鋁層中形成該些第二通孔之後，在該第二氧化鋁層上，形成一第三電晶體。
  15. 如請求項14所述的方法，更包含： 將該第一、該第二以及該第三電晶體封裝在一第三氧化層中。
  16. 一種積體電路裝置，包含： 一半導體基板； 一場效電晶體，位於該半導體基板上； 一第一金屬氧化層，位於該場效電晶體上； 複數個第一金屬通孔，延伸通過該第一金屬氧化層；以及 一第一薄膜電晶體，位於該第一金屬氧化層上，其中該第一薄膜電晶體與該場效電晶體至少部分藉由該第一金屬氧化層分隔開來。
  17. 如請求項16所述之積體電路裝置，更包含： 一封裝層，該封裝層封裝該場效電晶體以及該第一薄膜電晶體。
  18. 如請求項17所述之積體電路裝置，其中該封裝層由相同於該第一金屬氧化層之一材料組成。
  19. 如請求項17所述之積體電路裝置，其中該封裝層由氧化鋁組成。
  20. 如請求項16所述之積體電路裝置，更包含： 一第二金屬氧化層，位於該第一薄膜電晶體上； 複數個第二金屬通孔，延伸通過該第二金屬氧化層；以及 一第二薄膜電晶體，位於該第二金屬氧化層上，該第二薄膜電晶體與該第一薄膜電晶體至少部分藉由該第二金屬氧化層分隔開來。
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