TW202331820A - Fabrication method of semiconductor substrate and micro-electro-mechanical system (mems) device - Google Patents

Abstract

A method of fabricating a semiconductor substrate includes the following steps. A first wafer is provided and a first surface of the first wafer is etched to form a plurality of cavities. A second wafer is formed on the first surface, where forming the second wafer includes the following steps: providing a core substrate; forming a first insulating layer on the core substrate; and depositing a polysilicon layer on the first insulating layer and the core substrate. In addition, the polysilicon layer is bonded with the first wafer to cover the cavities, where the polysilicon layer is disposed between the first insulating layer and the first wafer. In addition, a MEMS device using the semiconductor substrate is also provided.

Description

Fabrication method of semiconductor substrate and microelectromechanical (MEMS) device

The present disclosure generally relates to a semiconductor substrate, and more particularly to a method of fabricating a semiconductor substrate including a polysilicon layer disposed on a wafer with a cavity, and to a microelectromechanical device using the semiconductor substrate.

In recent years, micro-electro-mechanical systems (MEMS) devices have been gaining increasing attention from various industries as an enabling technology. A MEMS device may include movable parts and at least one other element, such as a pressure sensor, actuator or resonator, using a micromechanical process to selectively etch portions of a wafer. Thus, the wafer may contain additional structural layers and may be composed of a semiconductor material such as silicon.

Silicon-on-insulator (SOI) wafers can be used as substrates for MEMS devices. A silicon-on-insulator wafer includes a silicon layer, a carrier wafer, and a buried oxide layer. The buried oxide layer is sandwiched by the silicon layer and the carrier wafer for physically separating and electrically isolating the silicon layer and the carrier wafer. For MEMS devices using a silicon-on-insulator wafer as a substrate, the silicon layer of the silicon-on-insulator wafer can be processed to form movable components of the MEMS device, such as cantilever structures or suspended membranes. Alternatively, MEMS devices can use bonded wafers instead of silicon-on-insulator wafers as substrates. The bonding wafer may be a stacked structure including a component wafer and a carrier wafer, and the component wafer may be thinned by performing a grinding process on the component wafer until the thinned component wafer reaches the desired level. Thickness is required. The thinned device wafer can be further processed to form movable parts of the MEMS device, such as cantilever structures or suspended membranes.

However, it is difficult to precisely control the thickness of the silicon layer of the SOI wafer or precisely control the thickness of the thinned device wafer, which negatively affects the electrical performance of the individual MEMS devices across the entire wafer. In addition, the cost of the SOI wafer is high, and the manufacturing process of the SOI wafer is quite time-consuming. Therefore, there is a need for a semiconductor substrate for MEMS devices to overcome the above-mentioned problems.

In view of this, the semiconductor substrate of the present disclosure provides a polysilicon device layer with precise thickness and resistivity control. Furthermore, a method of fabricating a semiconductor substrate is provided which is less time consuming and has greater fabrication flexibility compared to SOI wafers. In addition, the present disclosure provides a MEMS device using the semiconductor substrate, which has better device performance due to the precise thickness and resistivity control of the polysilicon device layer.

According to an embodiment of the present disclosure, a method for manufacturing a semiconductor substrate is provided, including the following steps. A first wafer is provided, and a first surface of the first wafer is etched to form a plurality of cavities. Forming a second wafer on the first surface, wherein forming the second wafer includes the following steps: providing a core substrate; forming a first insulating layer on the core substrate; A polysilicon layer is deposited on the core substrate. In addition, bonding the polysilicon layer and the first wafer to cover the cavities, wherein the polysilicon layer is disposed between the first insulating layer and the first wafer.

According to an embodiment of the present disclosure, a MEMS device is provided, including a support substrate, an adhesive layer, a polysilicon device layer, and a MEMS structure. The support base has a cavity on an upper surface, wherein the cavity does not penetrate the support base. The adhesive layer is conformally disposed on the upper surface of the support substrate and the sidewalls and bottom surface of the cavity. The polysilicon element layer is disposed on the upper surface of the support base to cover the cavity. The MEMS structure is disposed on the polysilicon element layer.

The present disclosure provides several different embodiments, which can be used to realize different features of the present disclosure. For simplicity of illustration, the present disclosure also describes examples of certain components and arrangements. These examples are provided for the purpose of illustration only, without any limitation. For example, the description of "the first component is formed on or over the second component" in this disclosure may refer to "the first component is in direct contact with the second component" or "the first component is in direct contact with the second component." There are other parts between the two parts", so that the first part is not in direct contact with the second part. In addition, various embodiments in the present disclosure may use repeated reference numerals and/or textual notations. The use of these repeated reference numerals and text notations is used to make the description more concise and clear, rather than to indicate the relationship between different embodiments and/or configurations.

In addition, for the space-related descriptive words mentioned in this disclosure, for example: "below", "above", "low", "high", "below", "above ”, “below”, “above”, “bottom”, “top” and similar terms, for the sake of description, are used to describe the relationship between one part or feature and another part (or more) in the drawings. The relative relationship of features. In addition to the orientations shown in the drawings, these space-related terms are also used to describe possible orientations of semiconductor devices during fabrication, use, and operation. For example, when a semiconductor device is rotated by 180 degrees, a component that was originally positioned "above" other components becomes positioned "below" the other components. Therefore, as the swing direction of the semiconductor device is changed (rotated by 90 degrees or other angles), the space-related description used to describe its swing direction should also be interpreted in a corresponding manner.

Although the present disclosure uses terms such as first, second, third, etc. to describe various elements, components, regions, layers, and/or sections, it should be understood that these elements, components, regions, layers, and/or blocks should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and/or block from another element, component, region, layer, and/or block, and do not imply or represent the element The presence of any preceding ordinal number does not imply an order of arrangement of one element over another, or an order in method of manufacture. Therefore, without departing from the scope of the specific embodiments of the present disclosure, the first element, component, region, layer, or block discussed below may also be referred to as the second element, component, region, layer, or block Of.

The terms "about" or "substantially" mentioned in this disclosure usually mean within 20%, preferably within 10%, and more preferably within 5%, of a given value or range Within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the description are approximate quantities, that is, the meaning of "about" or "substantial" may still be implied if "about" or "substantial" is not specified.

The present disclosure relates to semiconductor substrates, methods of manufacturing the same, and microelectromechanical (MEMS) devices using semiconductor substrates. The semiconductor element includes a first wafer having a plurality of cavities and a second wafer bonded to the first wafer to cover the cavities. The second wafer includes a polysilicon layer wrapping the core substrate and a first insulating layer disposed between the core substrate and the polysilicon layer. The polysilicon layer of the second wafer has precise thickness and resistivity control. Therefore, the MEMS device using the semiconductor substrate of the present disclosure has better device performance than the MEMS device using the SOI wafer. In addition, compared with semiconductor substrates fabricated using SOI wafers, the semiconductor substrates fabricated according to the embodiments of the present disclosure require less time, lower costs, better control of fabrication parameters, and greater fabrication flexibility.

According to some embodiments of the present disclosure, methods of fabricating a semiconductor substrate are provided. FIG. 1 is a schematic cross-sectional view of several stages of a method for fabricating a semiconductor substrate 100 and processing the semiconductor substrate 100 for MEMS devices to form a substrate 201 according to an embodiment of the present disclosure. Referring to FIG. 1 , firstly, in step S101 , a first wafer 101 is provided, such as a silicon wafer or other suitable semiconductor materials. The first wafer 101 includes a single crystal semiconductor material, such as silicon, sapphire or other suitable semiconductor materials, for example, elemental semiconductors (such as germanium), compound semiconductors (such as gallium nitride, silicon carbide, gallium arsenide, phosphide gallium, indium phosphide, indium arsenide and/or indium antimonide), alloy semiconductors (such as silicon germanium, gallium arsenide, aluminum gallium arsenide, aluminum nitride, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide , gallium arsenic indium phosphide), or a combination of the foregoing. Next, at the stage of step S102 , the first wafer 101 is etched to form a plurality of cavities 103 on the upper surface thereof. The bottom surface of the cavity 103 is higher than the bottom surface of the first wafer 101, which means that the cavity does not penetrate through the supporting substrate. In one embodiment, the cavity 103 may have a right angle, which means that the angle between the sidewall and the bottom surface of the cavity 103 is about 90°. In some embodiments, each cavity 103 has a cross-sectional shape, such as a rectangle, a trapezoid, an inverted trapezoid, or other suitable shapes. The elements using the semiconductor substrate 100 can adjust the depth of the cavity 103 based on actual needs. In addition, the number of cavities 103 shown in FIG. 1 is only for illustration purposes, and the actual number of cavities 103 in the first wafer 101 may exceed 100 according to actual needs. The cavity 103 can be removed by using a patterned mask disposed on the first wafer 101 as an etching mask and performing an etching process to remove the portion of the first wafer 101 exposed by the openings of the patterned mask. form. The etching process can be a dry etching or a wet etching process. Based on the requirements of the MEMS device, the shape and size of the cavity 103 can be adjusted by parameters of the etching process and the patterning mask. For example, each cavity 103 may be circular or polygonal with a diameter or a diagonal length of about 50 µm to 2 mm, but is not limited thereto.

Next, at the stage of step S103 , the core substrate 105 of the second wafer 102 is provided. The core substrate 105 may be a semiconductor substrate, such as a silicon wafer, a silicon-containing substrate, or other suitable semiconductor substrates. In some embodiments, the material of the core substrate 105 may be the same as that of the first wafer 101 , but is not limited thereto. Subsequently, a first insulating layer 107 is formed on one surface of the core substrate 105 . The first insulating layer 107 may be a silicon oxide layer formed by thermal oxidation or deposition process. Thereafter, a polysilicon layer 108 is deposited on the first insulating layer 107 and the core substrate 105 . The polysilicon layer 108 can be formed by chemical vapor deposition (chemical vapor deposition, CVD) process, such as atmospheric pressure chemical vapor deposition process (atmospheric pressure chemical vapor deposition, APCVD), low-pressure chemical vapor deposition (low-pressure chemical vapor deposition) , LPCVD) process or other suitable process. In some embodiments, the thickness of the deposited polysilicon layer 108 can be well controlled by adjusting process parameters and conditions, and can be from about 2 µm to about 15 µm or thicker. According to different requirements, the first insulating layer 107 and the polysilicon layer 108 can be sequentially formed in different processes or in the same process. For example, the first insulating layer 107 may be formed on the core substrate 105 at the initial stage of forming the polysilicon layer 108 .

Subsequently, in step S104, the deposited polysilicon layer 108 is processed by a polishing process to obtain a mirror-polished polysilicon layer 109. The polishing process is, for example, a wet polishing process, a chemical mechanical polishing (CMP) process, etc., but not limited thereto. In some embodiments, the mirror polished polysilicon layer 109 may have a thickness from about 1 µm to about 10 µm. At the stage of step S104 , in some embodiments, the second wafer 102 includes a core substrate 105 , a first insulating layer 107 and a mirror-polished polysilicon layer 109 . The first insulating layer 107 and the mirror-polished polysilicon layer 109 are formed on the same surface of the core substrate 105 . The polishing process can adjust the surface roughness of the mirror-polished polysilicon layer 109 and provide better film quality for the component layers of the MEMS device. Even though the deposited polysilicon layer 108 is processed by a polishing process, the average thickness of the mirror polished polysilicon layer 109 may be the same as or slightly smaller than the average thickness of the deposited polysilicon layer 108 (eg, the thickness difference is less than 5%).

Next, at the stage of step S105, the second wafer 102 is bonded to the first wafer 101 to cover the cavity 103, thereby obtaining the semiconductor substrate 100, wherein the mirror polished polysilicon layer 109 is disposed on the first insulating layer 107 and the first between wafers 101. Subsequently, at the stage of step S106 , the semiconductor substrate 100 is processed to completely remove the core substrate 105 and the first insulating layer 107 . In some embodiments, the core substrate 105 and the first insulating layer 107 may be removed by back grinding (BG) or chemical mechanical polishing. Therefore, the mirror-polished polysilicon layer 109 extending across the entire first wafer 101 will remain on the first wafer 101, becoming the polysilicon element layer 110 covering the cavity 103, and then obtaining the substrate 201 for fabricating MEMS devices. .

According to some embodiments of the present disclosure, the polysilicon device layer 110 for MEMS devices is formed by depositing and polishing the polysilicon layer to precisely control the thickness of the polysilicon device layer 110 . In addition, during or after the deposition process for forming the polysilicon layer 108 , the resistivity of the polysilicon device layer 110 can be precisely controlled by adjusting the doping level of the polysilicon layer. Therefore, the mechanical or electrical performance of the MEMS device formed by the polysilicon element layer 110 can be improved.

Furthermore, according to some embodiments of the present disclosure, the semiconductor substrate for the MEMS device is fabricated without using an SOI wafer, thus reducing the fabrication cost and cycle time of the semiconductor substrate. In addition, the manufacturing flexibility and process parameter control of the disclosed semiconductor substrate will also be improved.

In the following paragraphs of the description, methods for fabricating a semiconductor substrate of alternative embodiments of the present disclosure are disclosed.

FIG. 2 is a schematic cross-sectional view of several stages of a method for fabricating a semiconductor substrate 100A and processing the semiconductor substrate 100A for MEMS devices to form a substrate 201 according to another embodiment of the present disclosure. In the embodiment of the present disclosure, the details of the first wafer 101 and the formation of multiple cavities 103 in step S201 and step S202 in FIG. 2 may be the same as those corresponding to the descriptions in step S101 and step S102 in FIG. 1 , and will not be repeated here.

At the stage of step S203, in some embodiments, a core substrate 105 such as a silicon wafer or a silicon-containing wafer is provided, and then a first insulating layer 107 is formed on the front surface, rear surface and sidewalls of the core substrate 105 to cover core substrate 105 . The first insulating layer 107 may be a silicon oxide layer formed by thermal oxidation or deposition process. Thereafter, a polysilicon layer 108 is deposited on the first insulating layer 107 and on the front surface, rear surface and sidewalls of the core substrate 105 . The polysilicon layer 108 surrounds the first insulating layer 107 and the core substrate 105 . The polysilicon layer 108 can be formed by a chemical vapor deposition process, such as an atmospheric pressure chemical vapor deposition process, a low pressure chemical vapor deposition process, or other suitable processes. In some embodiments, the deposited polysilicon layer 108 may have a thickness from about 2 µm to about 15 µm or more.

Afterwards, in step S204 , the deposited polysilicon layer 108 is processed by a polishing process to obtain a mirror-polished polysilicon layer 109 , wherein the mirror-polished polysilicon layer 109 covers the first insulating layer 107 and the core substrate 105 . In some embodiments, the mirror polished polysilicon layer 109 may have a thickness from about 1 µm to about 10 µm. At the stage of step S204 , in some embodiments, the second wafer 102 includes a core substrate 105 , a first insulating layer 107 and a mirror-polished polysilicon layer 109 . The first insulating layer 107 and the mirror polished polysilicon layer 109 cover the core substrate 105 . The polishing process can adjust the surface roughness of the mirror-polished polysilicon layer 109 and provide better film quality for the component layers of the MEMS device.

Next, at the stage of step S205, the second wafer 102 will be bonded to the first wafer 101 to cover the plurality of cavities 103 to obtain the semiconductor substrate 100A, wherein the mirror polished polysilicon layer 109 will be disposed on the first insulating layer 107 and the first wafer 101. The semiconductor substrate 100A includes a first wafer 101, and the first wafer 101 includes a plurality of cavities 103 disposed on an upper surface thereof.

The semiconductor substrate 100A further includes a second wafer 102 bonded to the first wafer 101 to cover the plurality of cavities 103 . In one embodiment, the second wafer 102 includes a core substrate 105 , a polysilicon layer 109 covering the core substrate 105 , and a first insulating layer 107 disposed between the core substrate 105 and the polysilicon layer 109 . The first insulating layer 107 covers the core substrate 105 and may be composed of silicon oxide, silicon nitride, silicon oxynitride or a combination thereof. In some embodiments, the first insulating layer 107 is a silicon oxide layer formed by thermally oxidizing the core substrate 105 . A first insulating layer 107 is formed to cover the front surface, rear surface and sidewalls of the core substrate 105 . In addition, in some embodiments of the present disclosure, the polysilicon layer 109 is also called a mirror polished polysilicon layer, and covers the first insulating layer 107 and the core substrate 105 . Compared with the deposited polysilicon layer (ie, the polysilicon layer 108 ), the mirror-polished polysilicon layer 109 has a lower surface roughness, thereby providing a component layer with better film quality for MEMS devices. In some embodiments, the mirror polished polysilicon layer 109 may have a thickness from about 1 µm to about 10 µm. A polysilicon layer 109 is formed on the first insulating layer 107 to cover the front surface, rear surface and sidewalls of the core substrate 105 .

Afterwards, in step S206 , the semiconductor substrate 100A is processed to remove some portions of the second wafer 102 . At this process stage, part of the core substrate 105 , part of the first insulating layer 107 and part of the mirror-polished polysilicon layer 109 are left on the first wafer 101 as the intermediate structure 112 . Subsequently, in step S207 , the intermediate structure 112 is processed to completely remove the core substrate 105 and the first insulating layer 107 . In some embodiments, the core substrate 105 , the first insulating layer 107 and the mirror polished polysilicon layer 109 may be removed by a back grinding process or a chemical mechanical polishing process. Therefore, the lower portion of the mirror-polished polysilicon layer 109 remains on the first wafer 101 to become the polysilicon device layer 110 covering the cavities 103 to obtain the substrate 201 for fabricating MEMS devices.

FIG. 3 is a schematic cross-sectional view of several stages of a method for fabricating a semiconductor substrate 100B and processing the semiconductor substrate 100B for MEMS devices to form a substrate 202 according to another embodiment of the present disclosure. Details of the first wafer 101 and the cavity 103 formed in step S301 and step S302 in FIG. 3 may be the same as the corresponding descriptions of step S101 and step S102 in FIG. 1 , and will not be repeated here. Details of the core substrate 105 , the first insulating layer 107 and the deposited polysilicon layer 108 in step S303 in FIG. 3 may be the same as those corresponding to step S203 in FIG. 2 , and will not be repeated here.

Next, in step S304 , the deposited polysilicon layer 108 is polished to obtain a mirror-polished polysilicon layer 109 , wherein the mirror-polished polysilicon layer 109 covers the first insulating layer 107 and the core substrate 105 . In some embodiments, the mirror polished polysilicon layer 109 may have a thickness from about 1 µm to about 10 µm. Afterwards, a second insulating layer 111 is formed on the mirror-polished polysilicon layer 109 to cover the mirror-polished polysilicon layer 109 , the first insulating layer 107 and the core substrate 105 . At the stage of step S304 , in some embodiments, the second wafer 102 includes the core substrate 105 , the first insulating layer 107 , the mirror-polished polysilicon layer 109 and the second insulating layer 111 .

Afterwards, in step S305, the second wafer 102 is bonded to the first wafer 101 to cover a plurality of cavities 103 to obtain a semiconductor substrate 100B, wherein the mirror polished polysilicon layer 109 is disposed on the first insulating layer 107 and the second insulating layer 107. Between one wafer 101. In addition, the second insulating layer 111 is disposed between the mirror-polished polysilicon layer 109 and the first wafer 101 . The semiconductor substrate 100B includes a first wafer 101, and the first wafer 101 includes a plurality of cavities 103 disposed on an upper surface thereof. In addition, the semiconductor substrate 100B further includes a second wafer 102 bonded to the first wafer 101 to cover the plurality of cavities 103 . The difference between the semiconductor substrate 100B in step S305 in FIG. 3 and the semiconductor substrate 100A in step S205 in FIG. The second insulating layer 111 between the wafer 101 and the polysilicon layer 109 . The second insulating layer 111 may be composed of silicon oxide, silicon nitride, silicon oxynitride or a combination thereof. In some embodiments, the second insulating layer 111 is a silicon oxide layer formed by thermally oxidizing the polysilicon layer 109 . The second insulating layer 111 is formed on the polysilicon layer 109 to cover the front surface, the rear surface and the sidewall of the core substrate 105 . In addition, the second insulating layer 111 may also cover the cavities 103 of the first wafer 101 . For other details of the semiconductor substrate 100B, reference may be made to the foregoing description of the semiconductor substrate 100A, and will not be repeated here.

Next, in step S306 , the semiconductor substrate 100B is processed to remove some portions of the second wafer 102 . At this process stage, part of the core substrate 105 , part of the first insulating layer 107 , part of the mirror-polished polysilicon layer 109 and part of the second insulating layer 111 will remain on the first wafer 101 as an intermediate structure 112 .

Subsequently, in step S307 , the intermediate structure 112 is processed to completely remove the core substrate 105 and the first insulating layer 107 . In some embodiments, the core substrate 105 , the first insulating layer 107 , the mirror-polished polysilicon layer 109 and the second insulating layer 111 may be removed by a back grinding process or a chemical mechanical polishing process. Therefore, the lower portion of the mirror-polished polysilicon layer 109 and the lower portion of the second insulating layer 111 are left on the first wafer 101 to cover the plurality of cavities 103 to obtain the substrate 202 for fabricating MEMS devices. The remaining portion of the mirror-polished polysilicon layer 109 on the first wafer 101 is used as the polysilicon device layer 110 of the MEMS device. The rest of the second insulating layer 111 is disposed between the polysilicon device layer 110 and the first wafer 101 .

FIG. 4 is a schematic cross-sectional view of several stages of a method for fabricating a semiconductor substrate 100C and processing the semiconductor substrate 100C for MEMS devices to form a substrate 203 according to another embodiment of the present disclosure. The details of the first wafer 101 and the formation of multiple cavities 103 in step S401 and step S402 in FIG. 4 may be the same as those corresponding to step S101 and step S102 in FIG. 1 , and will not be repeated here.

Subsequently, at the stage of step S403, in some embodiments, an adhesive layer 113 is formed to cover the first wafer 101, and the adhesive layer 113 is also conformally formed on the sidewalls and bottom surfaces of the plurality of cavities 103 . The adhesive layer 113 may be a silicon oxide layer formed by thermal oxidation or deposition process.

Next, at the stage of step S404 , in some embodiments, a core substrate 105 such as a silicon wafer or a silicon-containing wafer is provided. Subsequently, a first insulating layer 107 is formed on the front surface, rear surface and sidewalls of the core substrate 105 to cover the core substrate 105 . The first insulating layer 107 may be a silicon oxide layer formed by thermal oxidation or deposition process. Thereafter, a polysilicon layer is deposited on the first insulating layer 107 to cover the first insulating layer 107 and the core substrate 105 . Then, the deposited polysilicon layer is processed by a polishing process to obtain a mirror-polished polysilicon layer 109 , wherein the mirror-polished polysilicon layer 109 covers the first insulating layer 107 and the core substrate 105 . In some embodiments, the mirror polished polysilicon layer 109 may have a thickness from about 1 µm to about 10 µm. At the stage of step S404 , in some embodiments, the second wafer 102 includes a core substrate 105 , a first insulating layer 107 and a mirror-polished polysilicon layer 109 . Both the first insulating layer 107 and the mirror polished polysilicon layer 109 cover the core substrate 105 . The mirror polishing process can adjust the surface roughness of the mirror polished polysilicon layer 109 and provide better film quality for the element layer of the MEMS device.

Thereafter, at the stage of step S405, the second wafer 102 will be bonded to the first wafer 101 to cover the plurality of cavities 103 to obtain the semiconductor substrate 100C, wherein the mirror polished polysilicon layer 109 will be disposed on the first insulating layer 107 and the first wafer 101. In addition, a mirror-polished polysilicon layer 109 is disposed between the first insulating layer 107 and the adhesive layer 113 . Fusion bonding occurs at the interface between the adhesive layer 113 and the plurality of cavities 103 , and also at the interface between the adhesive layer 113 and the mirror-polished polysilicon layer 109 , which enhances the adhesion of the mirror-polished polysilicon layer 109 .

The semiconductor substrate 100C includes a first wafer 101, and the first wafer 101 includes a plurality of cavities 103 disposed on an upper surface thereof. In addition, the semiconductor substrate 100C further includes a second wafer 102 bonded to the first wafer 101 to cover the plurality of cavities 103 . The difference between the semiconductor substrate 100C of step S405 in FIG. 4 and the semiconductor substrate 100A of step S205 in FIG. Adhesive layer 113 on the sidewall and bottom surface of cavity 103 . The adhesive layer 113 may be composed of silicon oxide, silicon nitride, silicon oxynitride or a combination thereof. In some embodiments, the adhesive layer 113 is a silicon oxide layer formed by thermally oxidizing the first wafer 101 . The adhesive layer 113 is formed on the upper surface, the bottom surface and the sidewall of the first wafer 101 , and is formed on the sidewall and the bottom surface of each cavity 103 . For other details of the semiconductor substrate 100C, reference may be made to the foregoing description of the semiconductor substrate 100A, and will not be repeated here.

Next, in step S406 , the semiconductor substrate 100C is processed to remove part of the second wafer 102 . At this process stage, part of the core substrate 105 , part of the first insulating layer 107 and part of the mirror-polished polysilicon layer 109 are left on the first wafer 101 as the intermediate structure 112 .

Subsequently, in step S407 , the intermediate structure 112 is processed to completely remove the core substrate 105 and the first insulating layer 107 . In some embodiments, the core substrate 105 , the first insulating layer 107 and the mirror polished polysilicon layer 109 may be removed by a back grinding process or a chemical mechanical polishing process. Therefore, the lower portion of the mirror-polished polysilicon layer 109 remains on the first wafer 101 to become the polysilicon device layer 110 , thereby obtaining the substrate 203 for fabricating MEMS devices. The base 203 includes a polysilicon device layer 110 , an adhesive layer 113 and a first wafer 101 . The polysilicon device layer 110 covers the cavities 103 of the first wafer 101 . The adhesive layer 113 is disposed between the polysilicon device layer 110 and the first wafer 101 , and is conformally disposed on the sidewalls and bottom surfaces of the plurality of cavities 103 , and also covers the first wafer 101 .

FIG. 5 is a schematic cross-sectional view of several stages of a method for fabricating a semiconductor substrate 100D and processing the semiconductor substrate 100D for MEMS devices to form a substrate 204 according to another embodiment of the present disclosure. Details of the first wafer 101 and the cavity 103 formed in step S501 and step S502 in FIG. 5 may be the same as those corresponding to step S101 and step S102 in FIG. 1 , and will not be repeated here. In addition, the details of forming the adhesive layer 113 in step S503 in FIG. 5 may be the same as the description corresponding to step S403 in FIG. 4 , and will not be repeated here.

Next, at the stage of step S504 , in some embodiments, a core substrate 105 such as a silicon wafer or a silicon-containing wafer is provided. Subsequently, a first insulating layer 107 is formed on the front surface, rear surface and sidewalls of the core substrate 105 to cover the core substrate 105 . The first insulating layer 107 may be a silicon oxide layer formed by thermal oxidation or deposition process. Thereafter, a polysilicon layer is deposited on the first insulating layer 107 to cover the first insulating layer 107 and the core substrate 105 . Then, the deposited polysilicon layer is processed by a polishing process to obtain a mirror-polished polysilicon layer 109 , wherein the mirror-polished polysilicon layer 109 covers the first insulating layer 107 and the core substrate 105 . In some embodiments, the mirror polished polysilicon layer 109 may have a thickness from about 1 µm to about 10 µm. Subsequently, a second insulating layer 111 is formed on the mirror-polished polysilicon layer 109 to cover the mirror-polished polysilicon layer 109 , the first insulating layer 107 and the core substrate 105 . At the stage of step S504 , in some embodiments, the second wafer 102 includes the core substrate 105 , the first insulating layer 107 , the mirror-polished polysilicon layer 109 and the second insulating layer 111 . The mirror polishing process can adjust the surface roughness of the mirror polished polysilicon layer 109 and provide better film quality for the component layers of the MEMS device.

Thereafter, at the stage of step S505, the second wafer 102 will be bonded to the first wafer 101 to cover the plurality of cavities 103 to obtain the semiconductor substrate 100D, wherein the mirror polished polysilicon layer 109 will be disposed on the first insulating layer 107 and the first wafer 101. In addition, a mirror-polished polysilicon layer 109 is disposed between the first insulating layer 107 and the second insulating layer 111 . In addition, the second insulating layer 111 is disposed between the mirror-polished polysilicon layer 109 and the adhesive layer 113 .

The semiconductor substrate 100D includes a first wafer 101, and the first wafer 101 includes a plurality of cavities 103 disposed on an upper surface thereof. In addition, the semiconductor substrate 100D further includes a second wafer 102 bonded to the first wafer 101 to cover the plurality of cavities 103 . The difference between the semiconductor substrate 100D in step S505 in FIG. 5 and the semiconductor substrate 100C in step S405 in FIG. 111 covers the polysilicon layer 109 and is disposed between the first wafer 101 and the polysilicon layer 109 . The second insulating layer 111 is also disposed between the polysilicon layer 109 and the adhesive layer 113 . For other details of the semiconductor substrate 100D, reference may be made to the foregoing descriptions of the semiconductor substrate 100B and the semiconductor substrate 100A, and will not be repeated here.

Afterwards, in step S506 , the semiconductor substrate 100D is processed to remove some portions of the second wafer 102 . At this process stage, part of the core substrate 105 , part of the first insulating layer 107 , part of the mirror-polished polysilicon layer 109 and part of the second insulating layer 111 will remain on the first wafer 101 as an intermediate structure 112 .

Next, in step S507 , the intermediate structure 112 is processed to completely remove the core substrate 105 and the first insulating layer 107 . In some embodiments, the core substrate 105 , the first insulating layer 107 , the mirror-polished polysilicon layer 109 and the second insulating layer 111 may be removed by a back grinding process or a chemical mechanical polishing process. As a result, the lower portion of the mirror-polished polysilicon layer 109 and the lower portion of the second insulating layer 111 remain on the first wafer 101 to cover the plurality of cavities 103 to obtain a substrate 204 for fabricating MEMS devices. The remaining portion of the mirror-polished polysilicon layer 109 on the first wafer 101 is used as the polysilicon device layer 110 of the MEMS device. The rest of the second insulating layer 111 is disposed between the polysilicon device layer 110 and the adhesive layer 113 on the first wafer 101 . The base 204 includes a polysilicon device layer 110 , a second insulating layer 111 , an adhesive layer 113 and the first wafer 101 . The polysilicon device layer 110 and the second insulating layer 111 cover the cavity 103 of the first wafer 101 . The adhesive layer 113 is disposed between the second insulating layer 111 and the first wafer 101 , and is conformally disposed on the sidewall and bottom surface of the cavity 103 , and also surrounds the first wafer 101 .

According to some embodiments of the present disclosure, microelectromechanical devices using some of the aforementioned semiconductor substrates are provided. 6 to 8 are schematic cross-sectional views of a MEMS device 200 according to some embodiments of the present disclosure.

Referring to FIG. 6, FIG. 6 provides a MEMS device 200 fabricated by using the substrate 201 in step S106 in FIG. 1 or the substrate 201 in step S207 in FIG. 2 . As described above, the substrate 301 of the MEMS device 200 may be formed from the semiconductor substrate 100 in step S105 in FIG. 1 or the semiconductor substrate 100A in step S205 in FIG. 2 . As shown in FIG. 6 , the MEMS device 200 includes a singulated wafer 401 , a polysilicon device layer 110 and a MEMS structure 211 . The diced wafer 401 is a part of the first wafer 101 which can be obtained by performing a separation process on the first wafer 101 . The diced wafer 401 is also referred to as a supporting substrate of the MEMS device 200 . The diced wafer 401 has cavities 103 on its front surface. The polysilicon device layer 110 is disposed on the front surface of the diced wafer 401 to cover the cavity 103 . The MEMS structure 211 is disposed on the polysilicon device layer 110 . In this embodiment, the MEMS structure 211 is a piezoelectric micro-machined ultrasonic transducer (piezoelectric micro-machined ultrasonic transducer, PMUT), which includes a piezoelectric material layer disposed between the upper electrode layer 222 and the lower electrode layer 224 220. In addition, the MEMS structure 211 further includes a dielectric layer 226 disposed on the piezoelectric material layer 220 , the upper electrode layer 222 and the lower electrode layer 224 . The dielectric layer 226 has a plurality of openings 228 to expose a portion of the lower electrode layer 224 and a portion of the upper electrode layer 222, and these electrode layers are electrically connected to an external circuit (not shown in FIG. 6 ) via wires 230 . During operation of the MEMS device 200 , the membrane suspended above the cavity 103 may vibrate at a predetermined frequency, which is affected in part by the thickness and elasticity of the polysilicon device layer 110 .

Referring to FIG. 7 , FIG. 7 provides the MEMS device 200 fabricated by using the substrate 202 of step S307 in FIG. 3 . As mentioned above, the substrate 302 of the MEMS device 200 can be formed from the semiconductor substrate 100B in step S305 in FIG. 3 . As shown in FIG. 7 , the MEMS device 200 includes a diced wafer 401 , a polysilicon element layer 110 , a second insulating layer 111 and a MEMS structure 212 . The diced wafer 401 has a plurality of cavities 103 on its front surface. Although two cavities 103 are shown in FIG. 7 , the as-diced wafer 401 may have one or more than two cavities 103 . The second insulating layer 111 is disposed between the polysilicon device layer 110 and the diced wafer 401 . The MEMS structure 212 is disposed on the polysilicon device layer 110 . In this embodiment, the MEMS structure 212 includes a MEMS resonator and a plurality of filters. The microelectromechanical structure 212 also includes a piezoelectric material layer 220 disposed between an upper electrode layer 222 and a lower electrode layer 224 . The piezoelectric material layer 220 has an opening 225 to expose a portion of the lower electrode layer 224 . Wires 230 are conformally disposed on the sidewalls and bottom surface of the opening 225 for electrically connecting the lower electrode layer 224 to an external circuit (not shown in FIG. 7 ). The passivation layer 227 is disposed on the upper electrode layer 222 and has an opening exposing a portion of the upper electrode layer 222 . Another wire 230 is disposed on part of the upper electrode layer 222 for electrical connection to an external circuit (not shown in FIG. 7 ). In addition, the MEMS structure 212 , the polysilicon device layer 110 and the second insulating layer 111 may be patterned together to form a plurality of vias 232 connected to the cavities 103 of the diced wafer 401 . During operation of the MEMS device 200 , the membrane suspended above the cavity 103 can vibrate at a predetermined resonant frequency, which is affected in part by the thickness and elasticity of the polysilicon device layer 110 .

Referring to FIG. 8 , FIG. 8 provides the MEMS device 200 fabricated by using the substrate 203 of step S407 in FIG. 4 . As described above, the substrate 303 of the MEMS device 200 may be formed from the semiconductor substrate 100C in step S405 in FIG. 4 . As shown in FIG. 8, the MEMS device 200 includes a diced wafer 401, a polysilicon element layer 110, an adhesive layer 113, and a MEMS structure 213, wherein the MEMS structure 213 is formed by the polysilicon element layer 110, and the diced wafer 401 It has a plurality of cavities 103 on its front surface. After the MEMS structure 213 is formed, the substrate 203 in step S407 in FIG. 4 is thinned and then cut into several pieces. Therefore, as shown in FIG. 8 , the adhesive layer 113 is conformally disposed on the front surface of the diced wafer 401 and the sidewalls and bottom surfaces of the plurality of cavities 103 . The polysilicon device layer 110 is disposed on the adhesive layer 113 . In this embodiment, the microelectromechanical structure 213 is a microelectromechanical accelerometer and/or gyroscope, which is formed by patterning the polysilicon element layer 110 to form a plurality of protrusions 207 and a plurality of through holes 205, and a plurality of The vias 205 are connected to the plurality of cavities 103 of the diced wafer 401 . In addition, the MEMS structure 213 further includes a plurality of wires 206 formed on the plurality of protrusions 207 of the patterned polysilicon device layer 110 . In the case where the MEMS device 200 is an accelerometer or a gyroscope, the portion of the polysilicon device layer 110 suspended above the cavity 103 may serve as a movable proof mass. During operation of the MEMS device 200, when an external force is applied to the MEMS device 200, the movable proof mass may be displaced from its original position. The degree of displacement of the movable proof mass formed by the polysilicon device layer 110 is affected in part by the mass of the movable proof mass.

The MEMS structure and the substrate of the MEMS device 200 of this application may be the embodiments shown in FIG. 6 to FIG. 8 , but are not limited thereto. The MEMS structure of the MEMS device 200 includes a MEMS resonator (resonator) and a filter, a capacitive micro-machined ultrasonic transducer (CMUT), a piezoelectric micro-machined ultrasonic transducer (piezoelectric micro- machined ultrasonic transducer, PMUT), MEMS accelerometers, MEMS gyroscopes, inertial sensors, pressure sensors, microfluidic components, other micro components or combinations thereof. In addition, the substrate of the MEMS device 200 can be taken from any semiconductor substrate of the disclosed embodiments.

According to an embodiment of the present disclosure, the second wafer of semiconductor substrate provides a layer of polysilicon devices for fabricating MEMS devices. The polysilicon element layer of the MEMS device is formed by performing a deposition process and a mirror polishing process on the polysilicon layer, so that the thickness of the polysilicon element layer can be precisely controlled to improve the performance of the MEMS device. In addition, the resistivity of the polysilicon device layer can be precisely controlled by adjusting the doping level of the polysilicon layer. Therefore, the electrical performance of the MEMS device using the polysilicon device layer is also enhanced.

Furthermore, according to embodiments of the present disclosure, semiconductor substrates for MEMS devices are fabricated without using SOI wafers. Therefore, compared with conventional MEMS device substrates fabricated by using SOI wafers, the fabrication process of the semiconductor substrate of the present disclosure has the effect of less time-consuming and lower cost.

In addition, according to the embodiments of the present disclosure, in the process of manufacturing the semiconductor substrate, the thickness of the polysilicon device layer and the size of the cavity can be adjusted based on the requirements of the MEMS device. Therefore, compared with conventional MEMS device substrates manufactured by using SOI wafers, the semiconductor substrate manufacturing process of the present disclosure can better control process parameters and have greater manufacturing flexibility. The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: Semiconductor substrate 101:First Wafer 102:Second wafer 103: cavity 105: core substrate 107: The first insulating layer 108: polysilicon layer 109:Mirror polished polysilicon layer 110: Polysilicon component layer 111: second insulating layer 112: Intermediate structure 113: Adhesive layer 200: MEMS devices 205: through hole 206: conductive line 207: protrusion 211, 212, 213: MEMS structures 220: piezoelectric material layer 222: Upper electrode layer 224: Lower electrode layer 225, 228: opening 226: dielectric layer 227: protective layer 230: conductive line 232: Through hole 303: Base 401: Wafer after dicing S101~S106: steps S201~S207: steps S301~S307: steps S401~S407: steps S501~S507: steps

In order to make the following easier to understand, you can refer to the drawings and their detailed descriptions at the same time when reading this disclosure. Through the specific embodiments herein and referring to the corresponding drawings, the specific embodiments of the present disclosure are explained in detail, and the working principle of the specific embodiments of the present disclosure is explained. FIG. 1 is a schematic cross-sectional view of several stages of a method for fabricating a semiconductor substrate and processing a semiconductor substrate for a MEMS device according to an embodiment of the present disclosure. FIG. 2 is a schematic cross-sectional view of several stages of a method for fabricating a semiconductor substrate and processing the semiconductor substrate for MEMS devices according to another embodiment of the present disclosure. FIG. 3 is a schematic cross-sectional view of several stages of a method for fabricating a semiconductor substrate and processing the semiconductor substrate for MEMS devices according to another embodiment of the present disclosure. FIG. 4 is a schematic cross-sectional view of several stages of a method for fabricating a semiconductor substrate and processing the semiconductor substrate for MEMS devices according to another embodiment of the present disclosure. FIG. 5 is a schematic cross-sectional view of several stages of a method for fabricating a semiconductor substrate and processing the semiconductor substrate for MEMS devices according to another embodiment of the present disclosure. FIG. 6 is a schematic cross-sectional view of a MEMS device according to an embodiment of the present disclosure. FIG. 7 is a schematic cross-sectional view of a MEMS device according to another embodiment of the present disclosure. FIG. 8 is a schematic cross-sectional view of a MEMS device according to another embodiment of the present disclosure.

100: Semiconductor substrate

101:First Wafer

102:Second wafer

103: cavity

105: core substrate

107: The first insulating layer

108: polysilicon layer

109:Mirror polished polysilicon layer

110: Polysilicon component layer

S101: step

S102: step

S103: step

S104: step

S105: step

S106: step

Claims (13)

A method of manufacturing a semiconductor substrate, comprising: providing a first wafer; etching a first surface of the first wafer to form cavities; forming a second wafer on the first surface, wherein forming the second wafer includes: provide a core base; forming a first insulating layer on the core substrate; depositing a polysilicon layer on the first insulating layer and the core substrate; and Bonding the polysilicon layer and the first wafer to cover the cavities, wherein the polysilicon layer is disposed between the first insulating layer and the first wafer. The method for manufacturing a semiconductor substrate as claimed in claim 1, wherein when the first insulating layer is formed on the core substrate, the first insulating layer covers the core substrate. The method for manufacturing a semiconductor substrate as claimed in claim 1, wherein when the polysilicon layer is deposited on the first insulating layer and the core substrate, the polysilicon layer covers the core substrate. The method for manufacturing a semiconductor substrate as claimed in claim 1, wherein forming the second wafer further includes polishing the polysilicon layer to form a mirror polished polysilicon layer. The method for manufacturing a semiconductor substrate as claimed in claim 4, wherein forming the second wafer further includes forming a second insulating layer to cover the mirror-polished polysilicon layer. The manufacturing method of the semiconductor substrate according to claim 1, before bonding the polysilicon layer and the first wafer, further includes forming an adhesive layer to cover the first wafer and conformally form in the cavities side walls and bottom surface of the cavity. The method for manufacturing a semiconductor substrate as claimed in claim 6, wherein the first wafer and the core substrate comprise silicon, and forming the first insulating layer, forming the second insulating layer, and forming the adhesive layer include a thermal oxidation process . The manufacturing method of the semiconductor substrate according to claim 1, before bonding the polysilicon layer and the first wafer, further includes forming an adhesive layer to cover the first wafer and conformally form in the cavities side walls and bottom surface of the cavity. The manufacturing method of the semiconductor substrate according to claim 1, after bonding the polysilicon layer and the first wafer, further includes removing the core substrate and the first insulating layer to expose the polysilicon layer, wherein the polysilicon layer It is a polysilicon element layer, and the polysilicon element layer is arranged on the first wafer and covers the cavities. The method of manufacturing a semiconductor substrate as claimed in claim 9, wherein removing the core substrate and the first insulating layer comprises a back grinding process or a chemical mechanical polishing process. A microelectromechanical device comprising: a support base having a cavity on an upper surface and the cavity does not penetrate through the support base; an adhesive layer conformally disposed on the upper surface of the support substrate, and on the sidewalls and bottom surface of the cavity; a polysilicon element layer disposed on the upper surface of the support base to cover the cavity; and A MEMS structure is arranged on the polysilicon element layer. The MEMS device as claimed in claim 11 further includes an insulating layer disposed between the polysilicon element layer and the adhesive layer. The MEMS device as claimed in claim 11, wherein the MEMS structure includes a MEMS resonator and a plurality of filters, a capacitive MEMS ultrasonic transducer, a piezoelectric MEMS ultrasonic transducer, a micro An electromechanical accelerometer, a microelectromechanical gyroscope or a combination thereof.

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