CN117069051A

CN117069051A - Microelectromechanical device and method of manufacturing the same

Info

Publication number: CN117069051A
Application number: CN202210499744.7A
Authority: CN
Inventors: 拉奇许·昌德; 苏素轩; 穆尼安迪·顺穆甘; 拉玛奇德拉玛尔斯·彼拉迪·叶蕾哈卡
Original assignee: Vanguard International Semiconductor Corp
Current assignee: Vanguard International Semiconductor Corp
Priority date: 2022-05-09
Filing date: 2022-05-09
Publication date: 2023-11-17

Abstract

The invention discloses a micro-electromechanical device and a manufacturing method thereof, wherein the micro-electromechanical device comprises: a supporting substrate; a cavity arranged in the support substrate; a stopping member disposed between the support substrate and the cavity, and having an inner sidewall contacting the cavity; wherein the stop member comprises a filler material surrounding the perimeter of the cavity and a liner surrounding the filler material; and a microelectromechanical structure disposed over the cavity and attached to the stop member and the support substrate.

Description

Microelectromechanical device and method of manufacturing the same

Technical Field

The present invention relates to microelectromechanical (MEMS) devices, and in particular to microelectromechanical devices that include cavities and methods of manufacturing the same.

Background

In recent years, microelectromechanical (micro-electro-mechanical systems, MEMS) devices have been a technology that can be implemented, and have also received increasing attention in various industries. The MEMS device includes a movable portion and at least one other element, such as a pressure sensor, actuator or resonator, that is formed using a micromachining process to selectively etch away portions of a wafer that may include additional structural layers and may be made of a semiconductor material such as silicon.

Most MEMS devices have a membrane layer composed of an elastic material, electrodes, and a piezoelectric material disposed over the cavity, thereby releasing the device and improving the performance of the MEMS device. Generally, cavities below the membrane layer may be formed by bonding with a silicon-on-insulator (SOI) wafer using a cavity wafer, etching the back side of the wafer, or etching away a sacrificial material buried in the wafer. However, the existing method of forming the cavity is difficult to control the size of the cavity, and furthermore, the cost of the SOI wafer is high, and the manufacturing process of bonding the SOI wafer and the cavity wafer is time-consuming. Accordingly, there is a need in the art for improved MEMS devices and methods of fabricating the same that overcome the above-described problems.

Disclosure of Invention

Accordingly, one of the objectives of the present invention is to provide an improved microelectromechanical (MEMS) device and method of manufacturing the same, which has precisely controlled cavity dimensions, thereby improving the performance of the MEMS device, increasing the yield, increasing the flexibility of product tuning, and saving the cycle time and cost of manufacturing the MEMS device.

According to an embodiment of the present invention, there is provided a microelectromechanical device including: a supporting substrate; a cavity arranged in the support substrate; a stopping member disposed between the support substrate and the cavity, and having an inner sidewall contacting the cavity; wherein the stop member comprises a filler material surrounding the perimeter of the cavity and a liner surrounding the filler material; and a microelectromechanical structure disposed over the cavity and attached to the stop member and the support substrate.

According to another embodiment of the present invention, there is provided a method of manufacturing a microelectromechanical device, including: providing a supporting substrate; etching the support substrate to form a trench, wherein the trench surrounds a portion of the support substrate; forming a liner within the trench; filling the trench with a filling material to form a stop member, wherein the stop member comprises the liner layer and the filling material; forming a microelectromechanical structure on the stop member and the support substrate, wherein the microelectromechanical structure includes a through-hole; and etching the portion of the support substrate by providing an etchant through the through-hole to form a cavity, wherein the stopping member is in contact with the cavity.

Compared with the existing manufacturing method, the manufacturing method of the MEMS device provided by the embodiment of the invention has the advantages of less time consumption, lower manufacturing cost, high manufacturing yield, accurate size control of the cavity and more flexibility in depth adjustment of the cavity.

Drawings

Fig. 1A and 1B are schematic cross-sectional and top views of some stages of a method of fabricating a MEMS device according to an embodiment of the invention.

Fig. 2A and 2B are schematic cross-sectional views of some stages of a method of fabricating a MEMS device according to another embodiment of the invention.

Fig. 3A and 3B are schematic cross-sectional views of some stages of a method of fabricating a MEMS device according to another embodiment of the invention.

FIG. 4 is a schematic cross-sectional view of some stages of a method of fabricating a MEMS device according to another embodiment of the invention.

FIG. 5 is a schematic cross-sectional view of a MEMS device according to an embodiment of the invention.

FIG. 6 is a schematic cross-sectional view of a MEMS device according to another embodiment of the invention.

FIG. 7 is a schematic cross-sectional view of a MEMS device according to another embodiment of the invention.

Reference numerals illustrate:

100. 200, 300, 400, … MEMS device

101. 201, 301, 401, … support substrate

102 … core substrate

103. 207, 307, 407 … grooves

104. 203, 208, 240, 303, 308, 408, … dielectric layers

105. 209, 309, 409 … lining

106. 210, 310, 410, … filler material layer

107. 211, 311, 411 and … filling material

109. 213, 313, 413, … stopping member

110C, 130C … section state

110T, 130T … top view

111 … MEMS structure

112 … through-holes

113. 215, 315, 415 … cavities

120. 220, 322 … device layers

121 … projection

122. 228, 334, … conductor

205. 305, 403, … semiconductor layer

222. 326 … upper electrode layer

224. 328 … bottom electrode layer

226 … contact guide hole

230. 324 … piezoelectric material layer

320. 402 … insulating layer

330 … protective layer

332 … opening

Steps S110, S120, S130, S140, S210, S220, S230, S240, S250, S260, S310, S320, S330, S340, S350, S360, S410, S420, S430, S440 …

Detailed Description

In order to make the features of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

The invention provides several different embodiments that can be used to implement different features of the invention. For simplicity of explanation, the invention also describes examples of specific components and arrangements. These examples are provided for the purpose of illustration only and are not intended to be limiting in any way. For example, the following description of a first feature being formed on or over a second feature may refer to the first feature being in direct contact with the second feature, or may refer to other features being present between the first and second features, such that the first and second features are not in direct contact. Furthermore, various embodiments of the present invention may use repeated reference characters and/or textual notations. These repeated reference characters and notations are used to make the description more concise and clear, rather than to indicate a relationship between different embodiments and/or configurations.

In addition, for the spatially related narrative terms mentioned in the present invention, for example: when "under", "low", "lower", "upper", "top", "bottom" and the like, for purposes of description, the terms used herein are used to describe one element or feature in the drawings relative to another element(s) or feature. In addition to the orientation shown in the drawings, these spatially dependent terms are also used to describe possible orientations of the semiconductor device in use and operation. With respect to the orientation of the semiconductor device (rotated 90 degrees or other orientations), the spatially relative descriptors describing the orientation should also be interpreted in a similar manner.

Although the invention has been described in the language of first, second, third, etc., to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section, which does not itself imply any preceding ordinal number or order of arrangement or method of manufacture of the element. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the scope of the embodiments of the present invention.

The terms "about" or "substantially" as referred to herein generally mean within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the amounts provided in the specification are about amounts, i.e., without a specific recitation of "about" or "substantially," the meaning of "about" or "substantially" may still be implied.

While the following is directed to embodiments of the present invention, the present invention is not limited to the embodiments described above, but may be practiced in other embodiments. Furthermore, specific details are omitted so as not to obscure the spirit of the present invention, and such omitted details are within the knowledge of those skilled in the art.

The present invention relates to a microelectromechanical (MEMS) device and a method of manufacturing the same, which can precisely control the size of a cavity formed by etching a predetermined portion of a support substrate, the predetermined portion being surrounded and defined by a stop member (or etch stop member) comprising a filler material and a liner layer surrounding the sidewalls and bottom surface of the filler material. Since the etching selectivity of the liner layer of the stop member to the support substrate is less than 1 (e.g., 0.8, 0.5, 0.1, 0.01, or any intermediate value therebetween), the portion of the support substrate covered by the stop member is not removed during the process of etching the support substrate to form the cavity, thereby precisely controlling the size of the cavity and further improving the device performance of the MEMS device of the present invention. In addition, compared with the existing manufacturing method, the manufacturing method of the MEMS device provided by the embodiment of the invention has the advantages of less time consumption, lower manufacturing cost, high manufacturing yield, accurate size control of the cavity and more flexibility in depth adjustment of the cavity.

According to some embodiments of the present invention, methods of manufacturing a MEMS device are provided. Fig. 1A-1B are schematic cross-sectional and top-view illustrations of some stages of a method of fabricating a MEMS device 100 according to an embodiment of the invention. Referring to fig. 1A, first, a support substrate 101 is provided, and the support substrate 101 may be a silicon wafer or other suitable semiconductor wafer. The material of the support substrate 101 comprises a single crystal semiconductor material, such as silicon (Si), sapphire, or other suitable semiconductor material, for example, the material of the support substrate 101 comprises an elemental semiconductor, such as Ge; the material of the support substrate 101 may also include a compound semiconductor, such as GaN, siC, gaAs, gaP, inP, inAs and/or InSb; the material of the support substrate 101 also includes an alloy semiconductor, for example SiGe, gaAsP, alInAs, alN, alGaAs, gaInAs, gaInP, gaInAsP; or the material of the support substrate 101 may comprise a combination of the foregoing. Next, in step S110, the support substrate 101 is etched to form a plurality of trenches 103 on its upper surface, as in a cross-sectional state 110C and a top-view state 110T shown in fig. 1A. In some embodiments, the groove 103 may have a continuous or discontinuous annular shape in a top view. Further, the groove 103 may be any shape, such as a circle, a ring, a square, an ellipse, a polygon, or the like, when viewed from a top view, but is not limited to these shapes. The trench 103 surrounds a predetermined portion of the support substrate 101, which is used to define the location and depth of a cavity manufactured in a subsequent process. Then, in step S120, a dielectric layer 104, such as a silicon oxide layer, is formed on the support substrate 101 and in the trench 103 in a conformal manner, for example, by a thermal growth process (such as a thermal oxidation process or a thermal nitridation process), or by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process using tetraethoxysilane (tetraethoxy silane, TEOS), and the dielectric layer 104 in the trench 103 serves as a liner. The thermal growth process has a better trench filling capability than the PECVD process when forming the liner in the trench 103, so that the sidewalls and bottom of the trench 103 can be completely covered by the liner when forming the liner by the thermal growth process. Thus, even if the aspect ratio (or the ratio of the trench depth to the trench width) of the trench 103 is greater than 15 and the trench depth is greater than 150 μm, the liner layer formed by the thermal growth process can still completely cover the sidewall and the bottom surface of the trench 103. In addition, for liners formed via thermal growth processes, the liner may be considered a reaction product between the support substrate 101 and a gaseous reactant, such as oxygen, nitrogen, or a combination of the foregoing, or other reactant capable of reacting with the support substrate 101.

As shown in fig. 1A, a dielectric layer 104 may be formed to encapsulate the support substrate 101. Then, a filling material layer 106 is formed on the dielectric layer 104 through a deposition process, such as a Physical Vapor Deposition (PVD) process, and fills the trench 103. As shown in fig. 1A, the filling material layer 106 may be formed on the upper surface of the support substrate 101, or further encapsulate the support substrate 101 (not shown). The filler material layer 106 comprises polysilicon or a dielectric material, such as silicon oxide, silicon nitride, or a combination thereof. Since the filler material layer 106 is formed by a deposition process, the portion of the filler material deposited within the trench 103 may include voids (void) at the bottom and/or middle portions of the trench 103 based on the limited trench filling capability of the deposition process.

Subsequently, referring to fig. 1B, in step S130, the filling material layer 106 and the dielectric layer 104 are planarized to form a stop member 109 as shown in a cross-sectional state 130C and a top-down state 130T of fig. 1B, wherein the stop member 109 comprises the liner layer 105 and the filling material 107. The fill material layer 106 and the dielectric layer 104 may be planarized by a chemical-mechanical planarization (CMP) process until the top surfaces of the stop features 109 are flush with the top surface of the support substrate 101. The stopping member 109 may have a continuous or discontinuous annular shape in a top view, and the stopping member 109 surrounds a predetermined portion of the support substrate 101, which is used to form a cavity. Further, the aspect ratio of the stop feature 109 may be 10 to 20, and the height of the stop feature 109 may be in the range of about 20 micrometers (μm) to about 300 μm. In some embodiments, the height of the stop feature 109, the depth of the trench 103, and the depth of the cavity may be in the range of about 20 μm to about 300 μm, such as about 150 μm or about 250 μm, the thickness of the liner 105 may be in the range of about 0.1 μm to about 3.0 μm, and the thickness of the filler material 107 may be in the range of about 7 μm to about 15 μm, although the invention is not limited to the above ranges.

Next, in step S140, another wafer (not shown) is attached to the stop member 109 and the support substrate 101. The attached wafer is then patterned to form a MEMS structure 111, the MEMS structure 111 comprising a plurality of through-holes 112. Such MEMS structures 111 may include MEMS resonators and filters (filters), capacitive micro-Ultrasonic Sensors (CMUTs), piezoelectric micro-mechanical ultrasonic sensors (piezoelectric micro-machined ultrasonic transducer, PMUTs), MEMS accelerometers (acelerometers), MEMS gyroscopes (gyroscillopes), inertial sensors (inertial sensors), pressure sensors, microfluidic elements, other micro-elements, or combinations of the foregoing. Then, a predetermined portion of the support substrate 101 surrounded by the stopping member 109 is etched by supplying an etchant through the through-hole 112 to form a cavity 113. The stop feature 109 is used as an etch stop feature during etching to precisely define the lateral dimension (e.g., diameter) of the cavity 113. Furthermore, even if the liner 105 of the stop member 109 is a thin layer having a thickness of less than 3 μm (e.g., 1.0, 1.5, 2.0, 2.5, or any intermediate value between these values), since the present invention uses the filler material 107 to enhance the mechanical strength of the stop member 109, the stop member 109 as a whole can have high mechanical strength and no fracture occurs during etching.

Thereafter, the support substrate 101 and the MEMS structure 111 may be patterned by an etching process to form the MEMS device 100. After the etching process, the dielectric layer 104 and the filling material layer 106 on the sidewalls and the bottom surface of the support substrate 101 are removed. In the MEMS device 100, the MEMS structure 111 is disposed over the cavity 113, and the stop member 109 is disposed between the support substrate 101 and the cavity 103. Further, the stopping member 109 is provided along the inner sidewall of the support substrate 101, and the inner sidewall of the stopping member 109 is in contact with the cavity 113. The stop member 109 comprises a filler material 107 and a liner 105, wherein the filler material 107 surrounds the perimeter of the cavity 113 when viewed from above, and the liner 105 wraps around at least the sidewalls and bottom surface of the filler material 107. Further, a liner 105 is provided between the cavity 103 and the support substrate 101, the liner 105 extending from a first region at the bottom of the filler material 107 to a second region between the side wall of the filler material 107 and the support substrate 101, and to a third region between the other side wall of the filler material 107 and the cavity 113. In addition, the liner 105 is a thin layer and the slit surrounded and defined by the liner 105 is filled with a filler material 107.

According to an embodiment of the present invention, the depth of the cavity 113 is substantially the same as the height of the stop member 109, and dimensions such as width, length and diameter of the cavity 113 can be precisely controlled by the stop member 109, because the etch selectivity of the liner 105 of the stop member 109 to the support substrate 101 is less than 1 (e.g., 0.8, 0.5, 0.1, 0.01 or any intermediate value therebetween), and thus the etching of the support substrate 101 is stopped on the liner 105 of the stop member 109. In the present embodiment, the bottom surface of the cavity 113 may have a concave portion corresponding to the position of the through-hole 112 of the MEMS structure 111.

Fig. 2A-2B are schematic cross-sectional views of some stages of a method of fabricating a MEMS device 200 according to another embodiment of the invention. Referring to fig. 2A, first, a core substrate 102 is provided. The core substrate 102 is, for example, a silicon wafer or other suitable semiconductor wafer, and the material of the core substrate 102 may be referred to as the description of the support substrate 101 in fig. 1A. Next, in step S210, a dielectric layer 203 is formed on the core substrate 102. The dielectric layer 203 may be a silicon oxide layer formed by a thermal oxidation process, a PECVD process using Tetraethoxysilane (TEOS), or a Physical Vapor Deposition (PVD) process. In some embodiments, the dielectric layer 203 is deposited on the upper surface of the core substrate 102. In other embodiments, the dielectric layer 203 may be formed in a straightforward manner to encapsulate the core substrate 102. According to embodiments of the invention, the dielectric layer 203 may serve as a bottom stop, and may be referred to hereafter as a bottom stop 203.

Next, in step S220, a semiconductor layer 205 is deposited to encapsulate the bottom stop 203 and the core substrate 102, thereby forming a support substrate 201. The semiconductor layer 205 comprises polysilicon or other suitable semiconductor material. In the present embodiment, the support substrate 201 includes the core substrate 102, the bottom stop member 203, and the semiconductor layer 205.

Thereafter, in step 230, the semiconductor layer 205 is etched to form a plurality of trenches 207 therein. According to an embodiment of the present invention, etching of the semiconductor layer 205 may stop on the bottom stop 203. The trench 207 and the bottom stop 203 define a predetermined portion of the semiconductor layer 205 for forming a cavity.

Next, referring to fig. 2B, in step S240, a dielectric layer 208, such as a silicon oxide layer, is formed on the semiconductor layer 205 of the support substrate 201 and in the trench 207 in a straightforward manner by a thermal oxidation process or a PECVD process using Tetraethoxysilane (TEOS), and the dielectric layer 208 in the trench 207 is used as a liner. The thermal oxidation process has better trench filling capability than the PECVD process for forming the liner within the trench 207. Then, a fill material layer 210 is formed on the dielectric layer 208 and fills the trench 207 by a deposition process, such as a CVD or PVD process. The fill material layer 210 comprises polysilicon or dielectric material and includes voids in the fill material deposited at the bottom and/or middle portions of the trench 207. Additional details of dielectric layer 208 and fill material layer 210 may be found in the previous description of dielectric layer 104 and fill material layer 106 of fig. 1A.

Next, in step S250, the filling material layer 210 and the dielectric layer 208 are planarized to form a stop feature 213, the stop feature 213 comprising the liner 209 and the filling material 211. The fill material layer 210 and the dielectric layer 208 may be planarized by a CMP process until the top surface of the stop feature 213 is flush with the top surface of the semiconductor layer 205 of the support substrate 201. After the CMP process, the dielectric layer 208 and the filling material layer 210 may remain on the sidewalls and bottom surface of the semiconductor layer 205 of the support substrate 201. The stop member 213 may have a continuous or discontinuous annular shape in a top view, and the stop member 213 surrounds a predetermined portion of the semiconductor layer 205 for forming the cavity. Further, the aspect ratio of the stop feature 213 may be 10 to 20, and the height of the stop feature 213 may be in the range of about 20 μm to about 300 μm, such as about 150 μm or about 250 μm. The thickness of the liner 209 may be in the range of about 0.1 μm to about 3.0 μm, and the thickness of the filler 211 may be in the range of about 7 μm to about 15 μm, but the present invention is not limited to the above range.

Then, in step S260, another wafer (not shown) is attached to the stop member 213 and the support substrate 201. The attached wafer is then patterned to form the MEMS structure 111, wherein the MEMS structure 111 comprises a plurality of through holes 112. Then, an etchant is supplied through the through-holes 112 of the MEMS structure 111, so that the etchant etches a predetermined portion of the semiconductor layer 205 surrounded by the stop member 213 to form the cavity 215, and then the MEMS device 200 is formed. Thereafter, the support substrate 201 and the MEMS structure 111 may be patterned by an etching process, and the dielectric layer 208 and the filling material layer 210 on the sidewalls and bottom surface of the support substrate 201 are removed. In the MEMS device 200, the MEMS structure 111 is disposed over the cavity 215, and the stop member 213 is disposed between the semiconductor layer 205 of the support substrate 201 and the cavity 215. Further, the stopper 213 is provided along the inner sidewall of the semiconductor layer 205, and both the inner sidewall of the stopper 213 and a part of the surface of the bottom stopper 203 are in contact with the cavity 215.

According to an embodiment of the invention, the depth of the cavity 215 is substantially the same as the height of the stop member 213. In addition, the dimensions of the cavity 215, such as width, length, diameter, and depth, can be precisely controlled by the stop feature 213 and the bottom stop feature 203 because the etch selectivity of the liner 209 of the stop feature 213 and the bottom stop feature 203 to the semiconductor layer 205 is less than 1 (e.g., 0.8, 0.5, 0.1, 0.01, or any value in between these values) such that the etching of the semiconductor layer 205 will stop on the stop feature 213 and the bottom stop feature 203. In the present embodiment, the bottom surface of the cavity 215 is the upper surface of the bottom stop member 203.

Fig. 3A-3B are schematic cross-sectional views of some stages of a method of manufacturing a MEMS device 300 according to another embodiment of the invention. Referring to fig. 3A, first, a core substrate 102 is provided. The core substrate 102 is, for example, a silicon wafer or other suitable semiconductor wafer, and the material of the core substrate 102 may be referred to as the description of the support substrate 101 in fig. 1A. Next, in step S310, a dielectric layer 303 is formed to encapsulate the core substrate 102, wherein the dielectric layer 303 may be a silicon oxide layer formed by a thermal oxidation process or a PECVD process using Tetraethoxysilane (TEOS). According to an embodiment of the present invention, an upper portion of the dielectric layer 303 is used as a bottom stop, and may be referred to as a bottom stop 303 hereafter.

Next, in step S320, a semiconductor layer 305 is deposited on the bottom stop 303 to form a support substrate 301. The semiconductor layer 305 comprises amorphous silicon or other suitable semiconductor material, and the semiconductor layer 305 may be deposited on the upper surface of the bottom stop member 303 by a PVD process. In the present embodiment, the support substrate 301 includes the core substrate 102, the bottom stop member 303, and the semiconductor layer 305.

Thereafter, in step 330, the semiconductor layer 305 is etched to form a plurality of trenches 307 therein. According to an embodiment of the present invention, etching of the semiconductor layer 305 is stopped on the bottom stop member 303. The trench 307 and the bottom stop 303 define a predetermined portion of the semiconductor layer 305 for forming a cavity.

Next, referring to fig. 3B, in step S340, a dielectric layer 308, such as a silicon oxide layer or a silicon nitride layer, is formed on the support substrate 301 and in the trench 307. A dielectric layer 308 may be formed on the upper surface and sidewalls of the semiconductor layer 305, and on the sidewalls and bottom surface of the dielectric layer 303 to encapsulate the support substrate 301. The dielectric layer 308 may be formed by a thermal growth process, such as a thermal oxidation process or a thermal nitridation process, or a PECVD process using Tetraethoxysilane (TEOS), the dielectric layer 308 within the trench 307 being a liner, the thermal growth process having a better trench filling capability than the PECVD process for forming the liner within the trench 307. Then, a filling material layer 310 is formed on the dielectric layer 308, and the trench 307 is filled. The fill material layer 310 comprises polysilicon or a dielectric material, such as silicon oxide, silicon nitride, or other suitable dielectric material. The filling material layer 310 may be formed on the upper surface of the semiconductor layer 305 by a PVD process, or the filling material layer 310 may be formed to encapsulate the support substrate 301 by a CVD process. Furthermore, voids may be included in the fill material deposited at the bottom and/or middle portions of trench 307.

Next, in step S350, the filling material layer 310 and the dielectric layer 308 are planarized to form a stop feature 313, wherein the stop feature 313 includes the liner 309 and the filling material 311. The fill material layer 310 and the dielectric layer 308 may be planarized by a CMP process until the top surface of the stop feature 313 is flush with the top surface of the semiconductor layer 305 of the support substrate 301. After the CMP process, the dielectric layer 308 and the filling material layer 310 may remain on the sidewalls and bottom surface of the support substrate 301. In this embodiment, details of the top-view shape, the aspect ratio, the height, the thickness of the liner 309 and the filling material 311, and the like of the stop member 313 may be referred to the foregoing description of the stop member 213 in fig. 2B, and the stop member 313 surrounds a predetermined portion of the semiconductor layer 305 for forming the cavity.

Then, in step S360, another wafer (not shown) is attached to the stopping member 313 and the supporting substrate 301. The attached wafer is then patterned to form the MEMS structure 111, wherein the MEMS structure 111 comprises a plurality of through holes 112. Then, a predetermined portion of the semiconductor layer 305 surrounded by the stopping member 313 is etched by supplying an etchant through the through-hole 112 to form a cavity 315, and then the MEMS device 300 is formed. Thereafter, the support substrate 301 and the MEMS structure 111 may be patterned by an etching process. After the etching process, the dielectric layer 308 and the filling material layer 310 on the sidewalls and bottom surface of the support substrate 301 may be removed. In addition, lower portions and sidewall portions of the dielectric layer 303 located on the bottom surface and sidewalls of the core substrate 102 may be further removed. In MEMS device 300, MEMS structure 111 is disposed over cavity 315, and stop feature 313 is disposed between semiconductor layer 305 and cavity 315. In addition, the stopping member 313 is disposed along an inner sidewall of the semiconductor layer 305, and both the inner sidewall of the stopping member 315 and an upper surface of the bottom stopping member 303 are in contact with the cavity 315.

According to an embodiment of the invention, the depth of the cavity 315 is substantially the same as the height of the stop member 313. In addition, the dimensions of the cavity 315, such as width, length, diameter and depth, may be precisely controlled by the stop member 315 and the bottom stop member 303. This is because the etch selectivity of liner 309 and bottom stop 303 of stop 313 to semiconductor layer 305 is less than 1 (e.g., 0.8, 0.5, 0.1, 0.01, or any intermediate value therebetween) such that the etching of semiconductor layer 305 stops on stop 313 and bottom stop 303.

FIG. 4 is a schematic cross-sectional view of some stages of a method of manufacturing a MEMS device 400 in accordance with another embodiment of the invention. Referring to fig. 4, first, a support substrate 401 is provided. The support substrate 401 includes a semiconductor substrate 104, an insulating layer 402 over the semiconductor substrate 104, and a semiconductor layer 403 over the insulating layer 402. The semiconductor substrate 104 is, for example, a silicon wafer or other suitable semiconductor wafer. The material of the semiconductor substrate 104 may be referred to in the foregoing description of the support substrate 101 in fig. 1A. The insulating layer 402 may be a buried oxide layer and act as a bottom stop, which may be referred to hereinafter as a bottom stop 402. Semiconductor layer 403 comprises monocrystalline silicon or other suitable semiconductor material. In this embodiment, the thickness of the semiconductor layer 403 may be between about 20 microns to about 200 microns. In an embodiment of the present invention, the support substrate 401 may be a semiconductor-on-insulator (SOI) wafer, which may be used to form a shallow cavity of a MEMS device.

Next, in step S410, the semiconductor layer 403 is etched to form a plurality of trenches 407 therein. According to an embodiment of the present invention, etching of the semiconductor layer 403 is stopped on the bottom stop 402. Trench 407 and bottom stop feature 402 define a predetermined portion of semiconductor layer 403 for forming a cavity.

Thereafter, in step S420, a dielectric layer 408, such as a silicon oxide layer or a silicon nitride layer, is formed on the support substrate 401 and in the trench 407. The dielectric layer 408 may be further formed on the upper surface and sidewalls of the semiconductor layer 403, on the sidewalls of the bottom stop member 402, and on the sidewalls and bottom surface of the semiconductor substrate 104. The dielectric layer 408 may be formed by a thermal growth process, such as a thermal oxidation process or a thermal nitridation process, or the dielectric layer 408 may be formed by a PECVD process using Tetraethoxysilane (TEOS), with the dielectric layer 408 within the trench 407 lining. The thermal growth process has better trench filling capability than the PECVD process for forming the liner within trench 407. Then, a fill material layer 410 is formed over the dielectric layer 408 and fills the trench 407, the fill material layer 410 comprising polysilicon or a dielectric material. The filling material layer 410 may be formed on the upper surface of the support substrate 401 by a PVD process, or the filling material layer 410 may be formed to wrap the support substrate 401 by a CVD process. In addition, voids may be included in the fill material deposited at the bottom and/or middle portions of trench 407.

Next, in step S430, the fill material layer 410 and the dielectric layer 408 are planarized to form a stop member 413, wherein the stop member 413 comprises the liner 409 and the fill material 411. The fill material layer 410 and the dielectric layer 408 may be planarized by a CMP process until the top surface of the stop member 413 is flush with the top surface of the semiconductor layer 403 of the support substrate 401. After the CMP process, the dielectric layer 408 and the filler material layer 410 may remain on the sidewalls and bottom surface of the support substrate 401. The stopping member 413 may have a continuous or discontinuous annular shape in a top view to surround a predetermined portion of the semiconductor layer 403 for forming the cavity. Further, the aspect ratio of the stop feature 413 may be 10 to 20, and the height of the stop feature 213 may be in the range of about 20 μm to about 300 μm, such as about 50 μm or about 100 μm. The thickness of the liner 409 may be in the range of about 0.1 μm to about 3.0 μm, and the thickness of the filling material 411 may be in the range of about 7 μm to about 15 μm, but the present invention is not limited to the above range.

Thereafter, in step S440, another wafer (not shown) is attached to the stopping member 413 and the support substrate 401. The attached wafer is then patterned to form the MEMS structure 111, wherein the MEMS structure 111 comprises a plurality of through holes 112. Then, a predetermined portion of the semiconductor layer 403 is etched by supplying an etchant through the through-hole 112 to form a cavity 415, and then the MEMS device 400 is formed. Thereafter, the support substrate 401 and the MEMS structure 111 may be patterned by an etching process. After the etching process, the dielectric layer 408 and the filling material layer 410 on the sidewalls and bottom surface of the support substrate 401 may be removed. In MEMS device 400, MEMS structure 111 is disposed over cavity 415, and stop 413 is disposed between semiconductor layer 403 and cavity 415. Further, a stopper 413 is provided along an inner sidewall of the semiconductor layer 403, and both the inner sidewall of the stopper 413 and an upper surface of the bottom stopper 402 are in contact with the cavity 415.

According to an embodiment of the invention, the depth of the cavity 415 is substantially the same as the height of the stop member 413. In some embodiments, the height of the stop feature 413 may be determined by the thickness of the semiconductor layer 403 of the SOI wafer, thereby allowing the depth of the cavity 415 to be shallow. In addition, since the etching selectivity of the liner 409 and the bottom stop 402 of the stop 413 to the semiconductor layer 403 is less than 1 (e.g., 0.8, 0.5, 0.1, 0.01, or any intermediate value therebetween), the etching of the semiconductor layer 403 may stop on the stop 413 and the bottom stop 402, and thus the dimensions, e.g., width, length, diameter, and depth, of the cavity 315 may be precisely controlled by the stop 413 and the bottom stop 402.

FIG. 5 is a schematic cross-sectional view of a MEMS device 100 according to an embodiment of the invention, as shown in FIG. 5, in an embodiment, the MEMS device 100 comprises a support substrate 101, a stop member 109, a cavity 113, and a MEMS structure 111. Details of the support substrate 101, the stop member 109, and the cavity 113 may be referred to in the foregoing description with respect to fig. 1B. In this embodiment, the MEMS structure 111 may be a MEMS accelerometer and/or gyroscope formed by patterning the device layer 120 to form a plurality of protrusions 121 and a plurality of through-holes 112, wherein the through-holes 112 interconnect with the cavities 113 of the support substrate 101, and the device layer 120 comprises polysilicon or other suitable semiconductor material. In addition, the MEMS structure 111 further includes a plurality of wires 122 formed on the protruding portion 121. Where MEMS device 100 is an accelerometer or gyroscope, the portion of device layer 120 that is suspended over cavity 113 may act as a movable mass. During operation of MEMS device 100, when MEMS device 100 is subjected to an external force, the movable mass may be displaced from its original position, and the extent of displacement of this movable mass may be affected in part by the mass of the movable mass and the size of cavity 113. In other embodiments, the support substrate 101 under the MEMS structure 111 of the MEMS device 100 may be replaced with the support substrate 201 of fig. 2B, the support substrate 301 of fig. 3B, or the support substrate 401 of fig. 4.

FIG. 6 is a schematic cross-sectional view of a MEMS device 200 according to another embodiment of the invention. As shown in FIG. 6, in one embodiment, MEMS device 200 includes a support substrate 201, a stop feature 213, a cavity 215, and a MEMS structure 111. Details of the support substrate 201, the stop member 213, and the cavity 215 are described with reference to fig. 2B. In this embodiment, the MEMS structure 111 is a piezoelectric micromachined ultrasonic sensor (PMUT) that includes a device layer 220 disposed on a support substrate 201 and over a cavity 215, and a layer 230 of piezoelectric material disposed between an upper electrode layer 222 and a lower electrode layer 224, the device layer 220 comprising polysilicon or other suitable semiconductor material. In addition, the MEMS structure 111 further includes a dielectric layer 240 disposed over the piezoelectric material layer 230, the upper electrode layer 222, and the lower electrode layer 224. The dielectric layer 240 has at least two contact vias 226 to electrically connect to a portion of the lower electrode layer 224 and a portion of the upper electrode layer 222, respectively. For example, the conductive line 228 connected to the electrode may be electrically connected to an external circuit (not shown in fig. 6) through the contact via 226. During operation of MEMS device 200, the membrane layer suspended over cavity 215 may vibrate at a predetermined frequency that may be affected in part by the thickness and elasticity of device layer 220 and the size of cavity 215. In addition, as shown in fig. 2B, the through-holes 112 of the MEMS structure 111 may be filled with a passivation layer after the cavity 215 is formed, or some of the through-holes 112 may remain in the MEMS structure 111 (not shown in fig. 6). In other embodiments, the support substrate 201 under the MEMS structure 111 of the MEMS device 200 may be replaced with the support substrate 101 of fig. 1B, the support substrate 301 of fig. 3B, or the support substrate 401 of fig. 4.

FIG. 7 is a schematic cross-sectional view of a MEMS device 300 according to another embodiment of the invention. As shown in FIG. 7, in one embodiment, MEMS device 300 includes a support substrate 301, stop feature 313, cavity 315, and MEMS structure 111. Details of the support substrate 301, the stop member 313, and the cavity 315 may be as described above with reference to fig. 3B. In addition, the support substrate 301 shown in fig. 7 is patterned after the etching process. In this embodiment, the MEMS structure 111 is a MEMS resonator and/or filter, and the MEMS structure 111 includes an insulating layer 320 and a device layer 322 disposed on the support substrate 301 and over the cavity 315 in sequence, and a piezoelectric material layer 324 disposed between an upper electrode layer 326 and a lower electrode layer 328. The piezoelectric material layer 324 has an opening 332 to expose a portion of the lower electrode layer 328, and conductive lines 334 are disposed on the sidewalls and bottom of the opening 332 in a conformal manner for electrically connecting the lower electrode layer 328 to an external circuit (not shown in fig. 7). The protection layer 330 is disposed on the upper electrode layer 326 and has an opening to expose a portion of the upper electrode layer 326, and another conductive line 334 is disposed on the portion of the upper electrode layer 326 to be electrically connected to an external circuit (not shown in fig. 7). In addition, the through-hole 112 of the MEMS structure 111 is in contact with and connected to the cavity 315 of the support substrate 301. During operation of MEMS device 300, the membrane layer suspended over cavity 315 may vibrate at a predetermined resonant frequency, which may be affected in part by the thickness and elasticity of device layer 322 and the size of cavity 315. In other embodiments, the support substrate 301 under the MEMS structure 111 of the MEMS device 300 may be replaced with the support substrate 101 of fig. 1B, the support substrate 201 of fig. 2B, or the support substrate 401 of fig. 4.

The MEMS structure 111 and the support substrates 101, 201, and 301 of the MEMS devices 100, 200, and 300 depicted in fig. 5, 6, and 7 are examples, but the present invention is not limited thereto. The MEMS structure 111 of the MEMS devices 100, 200, and 300 may include MEMS resonators and/or filters, capacitive Micromachined Ultrasonic Sensors (CMUTs), piezoelectric Micromachined Ultrasonic Sensors (PMUTs), MEMS accelerometers, MEMS gyroscopes, inertial sensors, pressure sensors, microfluidic elements, other microelements, or combinations of the foregoing. In addition, the support substrates 101, 201, and 301 of the MEMS devices 100, 200, and 300 may be taken from any of the support substrates of the embodiments of the present invention.

According to the embodiment of the invention, the etching selectivity ratio of the lining of the stopping component to the semiconductor material of the supporting substrate is less than 1, and the lining of the stopping component has good groove filling capability to the deep groove. Thus, the stop member may prevent lateral undercut etching of the support substrate to achieve precise control of the dimensions of the cavity. In addition, by employing the stop member, the etching of the support substrate in depth can be easily controlled to provide flexibility in the depth of the cavity. Thus, the dimensions of the cavity, such as width, length, diameter and depth, can be precisely controlled by the stop member. Furthermore, in some embodiments, the etching of the semiconductor material of the support substrate may stop on the bottom stop such that the depth of the cavity is further precisely controlled by the bottom stop. Thus, the performance of the MEMS device of the present invention can be improved due to the precise dimensions of the cavity.

In addition, according to the embodiment of the present invention, a thermal growth process (e.g., a thermal oxidation process or a thermal nitridation process) for forming the liner of the stopper has a good trench filling capability for the trench having a high aspect ratio and a deep depth, and thus, by using the stopper of the embodiment of the present invention, a deep cavity can be easily formed, by which a large-sized and sinking MEMS structure can be prevented from contacting the bottom of the cavity. In addition, the process of forming the cavity therein according to the embodiments of the present invention also helps to prevent scratches on the support substrate caused by the existing method of forming the cavity by back etching. Therefore, the production yield of the MEMS device is improved.

Furthermore, according to some embodiments of the present invention, the support substrate of the MEMS device is fabricated without using an SOI wafer. Thus, the MEMS device of the present invention is more time-efficient and less costly to manufacture than prior MEMS devices fabricated using SOI wafers.

The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several equivalent substitutions and obvious modifications can be made without departing from the spirit of the invention, and the same should be considered to be within the scope of the invention.

Claims

1. A microelectromechanical device, comprising:

a supporting substrate;

a cavity arranged in the support substrate;

a stopping member disposed between the support substrate and the cavity, and having an inner sidewall contacting the cavity; wherein the stop member comprises a filler material surrounding the perimeter of the cavity and a liner surrounding the filler material; and

a microelectromechanical structure is disposed over the cavity and attached to the stop member and the support substrate.

2. The microelectromechanical device of claim 1, wherein the support substrate comprises a core substrate, a bottom stop member on the core substrate, and a semiconductor layer on the bottom stop member, and wherein the stop member is disposed along an inner sidewall of the semiconductor layer.

3. The microelectromechanical device of claim 2, wherein the bottom stop is disposed below the stop, and the bottom stop contacts the stop and the cavity.

4. The microelectromechanical device of claim 2, wherein the semiconductor layer comprises a polysilicon layer and encapsulates the core substrate and the bottom stop feature.

5. The microelectromechanical device of claim 2, wherein the semiconductor layer comprises an amorphous silicon layer or a single crystal silicon layer.

6. The microelectromechanical device of claim 1, wherein the liner layer comprises a silicon oxide layer, the filler material comprises polysilicon or a dielectric material, and a portion of the filler material comprises voids.

7. The microelectromechanical device of claim 1, wherein the depth of the cavity is the same as the height of the stop member.

8. The microelectromechanical device of claim 1, wherein the stop feature has an aspect ratio between 10 and 20, and the cavity has a depth between 20 and 300 microns.

9. The microelectromechanical device of claim 1, wherein the microelectromechanical structure comprises a through hole in contact with the cavity.

10. The microelectromechanical device of claim 1, wherein the liner extends from a first region at the bottom of the filler material to a second region between a sidewall of the filler material and the support substrate, and to a third region between another sidewall of the filler material and the cavity.

11. A method of manufacturing a microelectromechanical device, comprising:

providing a supporting substrate;

etching the support substrate to form a trench, wherein the trench surrounds a portion of the support substrate;

forming a liner within the trench;

filling the trench with a filling material to form a stop member, wherein the stop member comprises the liner layer and the filling material;

forming a microelectromechanical structure on the stop member and the support substrate, wherein the microelectromechanical structure includes a through-hole; and

an etchant is provided through the through-hole to etch the portion of the support substrate to form a cavity, wherein the stop member is in contact with the cavity.

12. The method of claim 11, wherein forming the liner layer comprises a thermal growth process or a plasma enhanced chemical vapor deposition process using tetraethoxysilane to form a dielectric layer on the support substrate and in the trench in a straightforward manner.

13. The method of manufacturing a microelectromechanical device of claim 12, wherein filling the trench with the filler material to form the stop feature comprises: depositing a layer of filler material on the dielectric layer and planarizing the layer of filler material and the dielectric layer until a top surface of the stop feature is level with a top surface of the support substrate, wherein the layer of filler material comprises polysilicon or dielectric material and a portion of the filler material in the trench comprises voids.

14. The method of claim 11, wherein the support substrate includes a core substrate and a semiconductor layer on a surface of the core substrate before etching the portion of the support substrate to form the cavity, and the stop feature is formed in the semiconductor layer.

15. The method of claim 14, wherein the support substrate further comprises a bottom stop between the semiconductor layer and the core substrate, and etching the portion of the support substrate to form the cavity stops on the bottom stop.

16. The method of claim 15, wherein forming the bottom stop feature comprises depositing a dielectric layer on the surface of the core substrate.

17. The method of claim 16, wherein forming the semiconductor layer comprises depositing a polysilicon layer to encapsulate the core substrate and the bottom stop feature.

18. The method of claim 15, wherein forming the bottom stop feature comprises a thermal oxidation process to form an oxide layer around the core substrate.

19. The method of claim 18, wherein forming the semiconductor layer comprises depositing an amorphous silicon layer on the bottom stop feature.

20. The method of claim 11, wherein the support substrate comprises a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor layer on the insulating layer; wherein the stop feature is formed in the semiconductor layer prior to etching the portion of the support substrate to form the cavity, and the insulating layer is a bottom stop feature located below the stop feature.