TW202331711A - Resistive memory apparatus - Google Patents

Abstract

A resistive memory apparatus including a plurality of bit lines, a plurality of word lines, a memory array, a plurality of bypass paths, a plurality of select circuits and a switch circuit is provided. The word lines respectively cross the bit lines. The memory array includes a plurality of memory elements. One end of each memory element is coupled to the corresponding word line, and the other end of each memory element is coupled between a first node and a second node on the corresponding bit line. Each bypass path is connected in parallel with the corresponding bit line between the first node point and the second node. Each select circuit is coupled to the corresponding bit line and the corresponding bypass path, and configured to select the coupled bit line or the coupled bypass path. The switch circuit is coupled to the word lines, and configured to select one of the word lines.

Description

resistive memory device

The present invention relates to a memory device, and more particularly to a resistive memory device.

Resistive random access memory (RRAM) is a non-volatile memory that is actively developed in the industry. In a 1-transistor-1-resistor (1T1R) architecture, the transistor controls the current through the resistive memory cell. In this type of architecture, the area of the transistors used to control the current is relatively large. Trying to shrink the transistor will complicate the manufacturing process and reduce the current provided. Therefore, a 1-selector-1-resistor (1S1R) architecture in which the transistor is replaced by a selector is gradually used by the industry.

However, in the current 1-selector-1-resistor architecture, even unselected memory elements will generate sneak current, which not only easily causes errors in read operations, but also sometimes causes adjacent The memory element transitions improperly. For example, FIG. 1A and FIG. 1B show a schematic diagram of sneak current on a conventional resistive memory device. Please refer to FIGS. 1A and 1B . In FIG. 1A , since the memory element MT is selected to operate, the switch element SW is turned on to write data into or read data from the memory element MT. However, as shown in FIG. 1A , the unselected memory element MN1 may also generate a sneak current SC1 along the path P1 , thereby affecting the operation. Similarly, as shown in FIG. 1B , the unselected memory elements MN2 and MN3 may also generate a sneak current SC2 along the path P2, thereby affecting the operation.

The more cells connected in the manner shown in FIG. 1A and FIG. 1B , the greater the impact of the sneak current. Therefore, how to manage the sneak current is a major issue for designers in the field.

The invention provides a resistive memory device, which can manage the sneak current and reduce the influence caused by the sneak current.

The resistive memory device of the present invention includes a plurality of bit lines, a plurality of word lines, a memory array, a plurality of bypass paths, a plurality of selection circuits and a switch circuit. The word lines cross the bit lines respectively. A memory array includes a plurality of memory elements. One end of each memory element is coupled to the corresponding word line, and the other end of each memory element is coupled between the first terminal and the second terminal on the corresponding bit line. Each bypass path is connected in parallel with the corresponding bit line between the first terminal and the second terminal. Each selection circuit is coupled to a corresponding bit line and a bypass path, configured to select the coupled bit line or bypass path. The switch circuit is coupled to the word lines and is configured to select one of the word lines.

In an embodiment of the present invention, when one of the above-mentioned plurality of memory elements is selected as the selected memory element, the selection circuit coupled to the selected memory element through the bit line selects the coupled bit element lines, and other selection circuits select the coupled bypass paths.

Based on the above, in the resistive memory device of the present invention, when one of the plurality of memory elements is selected, except for the bit line required to operate the selected memory element, other bit lines The conduction path of the line can be replaced by a bypass path. Thereby, the resistive memory device of the present invention can reduce the paths that generate sneak current, even in a structure with a large area, it can indeed reduce the influence caused by sneak current.

FIG. 2 is a schematic block diagram of a resistive memory device according to an embodiment of the invention. FIG. 3 is a schematic circuit diagram of a resistive memory device according to an embodiment of the invention. Please refer to FIG. 2 and FIG. 3 at the same time. The resistive memory device 100 includes bit lines BL0~BL3, word lines WL0~WL3, bypass paths BP0~BP3, memory array 110, selection circuits 120_0~120_3 and switches. circuit 130. As shown in FIG. 3 , the word lines WL0 ˜ WL3 are arranged to intersect with the bit lines BL0 ˜ BL3 respectively, and the intersecting angle is, for example, about 90 degrees, but the present invention is not limited thereto. The resistive memory device 100 is, for example, a subset of a larger memory array.

The memory array 110 includes memory elements M00-M33, one end of the memory elements M00-M03 is coupled to the word line WL0, one end of the memory elements M10-M13 is coupled to the word line WL1, and the memory elements M20-M23 One end of the memory elements M30-M33 is coupled to the word line WL2, and one end of the memory elements M30-M33 is coupled to the word line WL3. The other ends of the memory elements M00 , M10 , M20 , M30 are coupled between the first terminal ND1_0 and the second terminal ND2_0 on the bit line BL0 . The other ends of the memory elements M01 , M11 , M21 , M31 are coupled between the first terminal ND1_1 and the second terminal ND2_1 on the bit line BL1 . The other ends of the memory elements M02 , M12 , M22 , M32 are coupled between the first terminal ND1_2 and the second terminal ND2_2 on the bit line BL2 . The other ends of the memory elements M03 , M13 , M23 , M33 are coupled between the first terminal ND1_3 and the second terminal ND2_3 on the bit line BL3 .

The following uses the memory device M00 as an example to illustrate the internal structure of the memory device in this embodiment, and the internal structures of the other memory devices M01-M33 are the same as the memory device M00. FIG. 4 is a schematic block diagram of a memory device according to an embodiment of the invention. Referring to FIG. 4 , the memory element M00 includes a resistive memory cell 200 and a selector 210 . The resistive memory cell 200 can provide a single bit of storage data. The selector 210 may be a bidirectional threshold switch (ovonic threshold switch, OTS), which is a two-terminal symmetrical voltage sensitive switching element. For example, when an applied voltage less than the threshold voltage is applied on the selector 210 , the selector 210 remains in an off state (eg, a non-conductive state). On the other hand, when an applied voltage greater than the threshold voltage is applied in either direction of the selector 210 , the selector 210 will become a conduction state (eg, conduction state). That is to say, the selector 210 can allow bidirectional switching, and since there is no need to control the conduction of the terminal (such as the metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) gate or bidirectional The base of the polar junction transistor (bipolar junction transistor, BJT), has the advantage of small area. Also, the selector 210 may be based on field-enhanced emission or tunneling.

It should be noted that the arrangement order of the resistive memory cell 200 and the selector 210 in the memory element M00 is not limited in the present invention, as long as one memory element M00 is configured with one resistive memory cell 200 and one selector The configuration of the device 210 is enough. In an embodiment, the selector 210 can also be integrated into the resistive memory cell 200 .

Returning to FIG. 2 and FIG. 3 , the bypass paths BP0 - BP3 are respectively connected in parallel with the bit lines BL0 - BL3 . As shown in FIG. 3 , the bypass path BP0 is connected in parallel with the bit line BL0 between the first terminal ND1_0 and the second terminal ND2_0 . The bypass path BP1 is connected in parallel with the bit line BL1 between the first terminal ND1_1 and the second terminal ND2_1 . The bypass path BP2 is connected in parallel with the bit line BL2 between the first terminal ND1_2 and the second terminal ND2_2 . The bypass path BP3 is connected in parallel with the bit line BL3 between the first terminal ND1_3 and the second terminal ND2_3 .

The selection circuits 120_0 - 120_3 are respectively coupled to the bit lines BL0 - BL3 and the bypass paths BP0 - BP3 . The selection circuit 120_0 is coupled to the bit line BL0 and the bypass path BP0, and is configured to select the coupled bit line BL0 or the bypass path BP0 to conduct voltage or current. The selection circuit 120_1 is coupled to the bit line BL1 and the bypass path BP1, and is configured to select the coupled bit line BL1 or the bypass path BP1 to conduct voltage or current. The selection circuit 120_2 is coupled to the bit line BL2 and the bypass path BP2, and is configured to select the coupled bit line BL2 or the bypass path BP2 to conduct voltage or current. The selection circuit 120_3 is coupled to the bit line BL3 and the bypass path BP3, and is configured to select the coupled bit line BL3 or the bypass path BP3 to conduct voltage or current.

The switch circuit 130 is coupled to the word lines WL0 ˜ WL3 . The switch circuit 130 is configured to select one of the word lines WL0 ˜ WL3 to conduct voltage or current.

In this embodiment, both the selection circuits 120_0 - 120_3 and the switch circuit 130 can realize the selection operation by operating the switch elements. The switching element may, for example, consist of a transistor. As shown in FIG. 3 , the selection circuit 120_0 includes a first switch element SW1_0 and a second switch element SW2_0, the selection circuit 120_1 includes a first switch element SW1_1 and a second switch element SW2_1, and the selection circuit 120_2 includes a first switch element SW1_2 and a second switch element. The switching element SW2_2 and the selection circuit 120_3 include a first switching element SW1_3 and a second switching element SW2_3. The switch circuit 130 includes third switch elements SW3_0 - SW3_3 .

The first switch elements SW1_0 - SW1_3 are respectively controlled by the control signals SBL0 - SBL3 to be turned on or off. The second switch elements SW2_0 - SW2_3 are respectively controlled by the control signals SBP0 - SBP3 to be turned on or off. The third switch elements SW3_0 - SW3_3 are respectively controlled by the control signals SWL0 - SWL3 to be turned on or off. The control signals SBL0 ˜ SBL3 , SBP0 ˜ SBP3 , and SWL0 ˜ SWL3 may come from a memory controller outside the resistive memory device 100 , for example.

The internal circuits of the selection circuits 120_0~120_3 are configured in a similar manner. Taking the selection circuit 120_0 as an example, the first switch element SW1_0 is arranged on the bit line BL0, the second switch element SW2_0 is arranged on the bypass path BP0, and the first switch One end of the element SW1_0 and one end of the second switch element SW2_0 are commonly coupled to ND2_0 on the bit line BL0. In the switch circuit 130 , one ends of the third switch elements SW3_0 ˜ SW3_3 are respectively coupled to the word lines WL0 ˜ WL3 , and the other ends of the third switch elements SW3_0 ˜ SW3_3 are coupled to the source line SL.

In this embodiment, when one of the memory elements M00-M33 is selected as the selected memory element MS, the selection circuit coupled to the selected memory element MS through the bit line will select the coupled bit The other selection circuit selects the coupled bypass path for voltage or current conduction. The selected memory element MS is, for example, selected to perform a write operation or a read operation. The following takes the memory device M10 as an example to describe the operation when the memory device M10 is selected as the memory device MS.

Specifically, FIG. 5A and FIG. 5B are examples of the operation method of the selection circuit according to an embodiment of the present invention. When the selected memory element MS (memory element M10 ) is selected, the selection circuit 120_0 selects the bit line BL0 to conduct voltage or current. As shown in FIG. 5A , the first switch element SW1_0 disposed on the bit line BL0 corresponding to the selected memory element MS is turned on based on the control signal SBL0 of the turn-on level VP to generate the current I1 . The second switch element SW2_0 disposed on the bypass path BP0 parallel to the bit line BL0 is turned off based on the control signal SBP0 of the turn-off level V0.

On the other hand, when the selected memory element MS (memory element M10 ) is selected, the selection circuits 120_1 - 120_3 respectively select the bypass paths BP1 - BP3 to conduct voltage or current. The first switching elements SW1_1~SW1_3 arranged on the bit lines BL1~BL3 corresponding to other memory elements are turned off, and are arranged in bypasses connected in parallel with the bit lines BL1~BL3 corresponding to other memory elements The second switch elements SW2_1 - SW2_3 on the paths BP1 - BP3 are turned on. Taking the selection circuit 120_1 as an example, as shown in FIG. 5B , the first switch element SW1_1 disposed on the bit line BL1 will be turned off based on the control signal SBL1 of the off level V0, and the first switch element SW1_1 disposed in parallel with the bit line BL1 will be turned off. The second switch element SW2_1 on the bypass path BP1 is turned on based on the control signal SBP1 of the turn-on level VP to generate the current I2.

Moreover, when the selected memory element MS (memory element M10) is selected, the third switch element SW3_1 coupled to the word line WL1 corresponding to the selected memory element MS is also based on the control signal SWL1 of the conduction level VP. And turn on.

Through the above method, when the selected memory element MS is selected to perform a write operation or a read operation, only the bit line coupled to the selected memory element MS will remain conductive, and the conduction paths of other bit lines are all turned on. will be replaced by a bypass path. In this way, by limiting to a sufficiently small subset of the memory array, the amount of possible sneak current is reduced, thereby reducing the impact of the sneak current.

It should be noted that, in the embodiment of the present invention, a 4x4 memory array 110 including 16 memory elements M00-M33 is used for illustration, but the present invention is not limited thereto, as long as it conforms to the teaching of the present invention. As for the circuit structure of the paths, those skilled in the art can analogize the number of memory elements used to more according to the actual needs according to the teaching of the present invention. In addition, those skilled in the art can properly arrange a plurality of resistive memory devices taught by the present invention, for example, in the extending direction of the bit lines, to expand into a larger memory array.

To sum up, in the resistive memory device of the present invention, multiple bypass paths are configured. When one of the plurality of memory elements is selected, except for the bit line required to operate the selected memory element, the conduction paths of other bit lines can be replaced by bypass paths. Thereby, the resistive memory device of the present invention can reduce the paths that generate sneak current, even in a structure with a large area, it can indeed reduce the influence caused by sneak current.

100: resistive memory device 110: memory array 120_0~120_3: select circuit 130: switch circuit 200: resistive memory cell 210: selector BL0~BL3: bit line BP0~BP3: Bypass path I1, I2: current M00~M33, MN1, MN2, MN3, MT: memory components ND1_0~ND1_3: the first endpoint ND2_0~ND2_3: the second endpoint P1, P2: path SBL0~SBL3, SBP0~SBP3, SWL0~SWL3: control signal SC1, SC2: sneak current SL: source line SW: switching element SW1_0~SW1_3: the first switching element SW2_0~SW2_3: the second switching element SW3_0~SW3_3: the third switching element V0: Disconnect level VP: conduction level WL0~WL3: character line

1A and 1B are schematic diagrams showing sneak currents on a conventional resistive memory device. FIG. 2 is a schematic block diagram of a resistive memory device according to an embodiment of the invention. FIG. 3 is a schematic circuit diagram of a resistive memory device according to an embodiment of the invention. FIG. 4 is a schematic block diagram of a memory device according to an embodiment of the invention. 5A and 5B are examples of the operation method of the selection circuit according to an embodiment of the present invention.

100: resistive memory device

110: memory array

120_0~120_3: select circuit

130: switch circuit

BL0~BL3: bit line

BP0~BP3: Bypass path

WL0~WL3: character line

Claims (12)

A resistive memory device comprising: multiple bit lines; A plurality of word lines are configured to cross the bit lines respectively; A memory array, including a plurality of memory elements, one end of each of the memory elements is coupled to the corresponding word line, and the other end of each of the memory elements is coupled to one of the corresponding bit lines between a first endpoint and a second endpoint; a plurality of bypass paths, each of the bypass paths is connected in parallel with the corresponding bit line between the first terminal and the second terminal; a plurality of selection circuits, each of which is coupled to the corresponding bit line and the bypass path and configured to select the coupled bit line or the bypass path; and A switch circuit, coupled to the word lines, is configured to select one of the word lines. The resistive memory device as claimed in claim 1, wherein when one of the memory elements is selected as a selected memory element, the selected memory element coupled to the selected memory element through the bit line A circuit selects the coupled bit line, and other selection circuits select the coupled bypass path. The resistive memory device as described in claim 2, wherein each of the selection circuits includes a first switch element and a second switch element, the first switch element is arranged on the corresponding bit line, and the second switch The element is arranged on the corresponding bypass path, and one end of the first switch element and one end of the second switch element are jointly coupled to the second terminal on the corresponding bit line. The resistive memory device as claimed in claim 3, wherein when the selected memory element is selected, the first switch element disposed on the bit line corresponding to the selected memory element is turned on, and is disposed on the bit line corresponding to the selected memory element. The second switch element on the bypass path connected in parallel with the bit line corresponding to the selected memory element is turned off. The resistive memory device according to claim 3, wherein when the selected memory element is selected, the first switch element set on the bit line corresponding to the other memory elements is turned off, and is set on The second switch element on the bypass path parallel to the bit line corresponding to the other memory elements is turned on. The resistive memory device as claimed in item 2, wherein the switch circuit includes a plurality of third switch elements, one ends of the third switch elements are respectively coupled to the word lines, and the other ends of the third switch elements One end is coupled to a source line, When the selected memory element is selected, the third switch element coupled to the word line corresponding to the selected memory element is turned on. The resistive memory device as claimed in claim 1, wherein each of the memory elements includes a resistive memory cell and a selector. The resistive memory device as claimed in claim 7, wherein the selector is a bidirectional threshold switch, which is a two-terminal symmetrical voltage sensitive switching element. The resistive memory device as claimed in claim 7, wherein the selector is based on field enhanced emission and tunneling. The resistive memory device as claimed in claim 7, wherein the selector is integrated into the resistive memory cell. The resistive memory device according to claim 7, wherein when an applied voltage less than a threshold voltage is applied to the selector, the selector remains in an off state, and when a voltage greater than the threshold voltage is applied in either direction of the selector When the voltage is applied, the selector becomes conductive. The resistive memory device as claimed in claim 7, wherein the selector allows bidirectional switching.

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